1 | /* sun3lance.c: Ethernet driver for SUN3 Lance chip */ |
2 | /* |
3 | |
4 | Sun3 Lance ethernet driver, by Sam Creasey (sammy@users.qual.net). |
5 | This driver is a part of the linux kernel, and is thus distributed |
6 | under the GNU General Public License. |
7 | |
8 | The values used in LANCE_OBIO and LANCE_IRQ seem to be empirically |
9 | true for the correct IRQ and address of the lance registers. They |
10 | have not been widely tested, however. What we probably need is a |
11 | "proper" way to search for a device in the sun3's prom, but, alas, |
12 | linux has no such thing. |
13 | |
14 | This driver is largely based on atarilance.c, by Roman Hodek. Other |
15 | sources of inspiration were the NetBSD sun3 am7990 driver, and the |
16 | linux sparc lance driver (sunlance.c). |
17 | |
18 | There are more assumptions made throughout this driver, it almost |
19 | certainly still needs work, but it does work at least for RARP/BOOTP and |
20 | mounting the root NFS filesystem. |
21 | |
22 | */ |
23 | |
24 | static const char version[] = |
25 | "sun3lance.c: v1.2 1/12/2001 Sam Creasey (sammy@sammy.net)\n" ; |
26 | |
27 | #include <linux/module.h> |
28 | #include <linux/stddef.h> |
29 | #include <linux/kernel.h> |
30 | #include <linux/string.h> |
31 | #include <linux/errno.h> |
32 | #include <linux/interrupt.h> |
33 | #include <linux/init.h> |
34 | #include <linux/ioport.h> |
35 | #include <linux/delay.h> |
36 | #include <linux/netdevice.h> |
37 | #include <linux/etherdevice.h> |
38 | #include <linux/skbuff.h> |
39 | #include <linux/bitops.h> |
40 | #include <linux/pgtable.h> |
41 | |
42 | #include <asm/cacheflush.h> |
43 | #include <asm/setup.h> |
44 | #include <asm/irq.h> |
45 | #include <asm/io.h> |
46 | #include <asm/dvma.h> |
47 | #include <asm/idprom.h> |
48 | #include <asm/machines.h> |
49 | |
50 | #ifdef CONFIG_SUN3 |
51 | #include <asm/sun3mmu.h> |
52 | #else |
53 | #include <asm/sun3xprom.h> |
54 | #endif |
55 | |
56 | /* sun3/60 addr/irq for the lance chip. If your sun is different, |
57 | change this. */ |
58 | #define LANCE_OBIO 0x120000 |
59 | #define LANCE_IRQ IRQ_AUTO_3 |
60 | |
61 | /* Debug level: |
62 | * 0 = silent, print only serious errors |
63 | * 1 = normal, print error messages |
64 | * 2 = debug, print debug infos |
65 | * 3 = debug, print even more debug infos (packet data) |
66 | */ |
67 | |
68 | #define LANCE_DEBUG 0 |
69 | |
70 | #ifdef LANCE_DEBUG |
71 | static int lance_debug = LANCE_DEBUG; |
72 | #else |
73 | static int lance_debug = 1; |
74 | #endif |
75 | module_param(lance_debug, int, 0); |
76 | MODULE_PARM_DESC(lance_debug, "SUN3 Lance debug level (0-3)" ); |
77 | MODULE_LICENSE("GPL" ); |
78 | |
79 | #define DPRINTK(n,a) \ |
80 | do { \ |
81 | if (lance_debug >= n) \ |
82 | printk a; \ |
83 | } while( 0 ) |
84 | |
85 | |
86 | /* we're only using 32k of memory, so we use 4 TX |
87 | buffers and 16 RX buffers. These values are expressed as log2. */ |
88 | |
89 | #define TX_LOG_RING_SIZE 3 |
90 | #define RX_LOG_RING_SIZE 5 |
91 | |
92 | /* These are the derived values */ |
93 | |
94 | #define TX_RING_SIZE (1 << TX_LOG_RING_SIZE) |
95 | #define TX_RING_LEN_BITS (TX_LOG_RING_SIZE << 5) |
96 | #define TX_RING_MOD_MASK (TX_RING_SIZE - 1) |
97 | |
98 | #define RX_RING_SIZE (1 << RX_LOG_RING_SIZE) |
99 | #define RX_RING_LEN_BITS (RX_LOG_RING_SIZE << 5) |
100 | #define RX_RING_MOD_MASK (RX_RING_SIZE - 1) |
101 | |
102 | /* Definitions for packet buffer access: */ |
103 | #define PKT_BUF_SZ 1544 |
104 | |
105 | /* Get the address of a packet buffer corresponding to a given buffer head */ |
106 | #define PKTBUF_ADDR(head) (void *)((unsigned long)(MEM) | (head)->base) |
107 | |
108 | |
109 | /* The LANCE Rx and Tx ring descriptors. */ |
110 | struct lance_rx_head { |
111 | unsigned short base; /* Low word of base addr */ |
112 | volatile unsigned char flag; |
113 | unsigned char base_hi; /* High word of base addr (unused) */ |
114 | short buf_length; /* This length is 2s complement! */ |
115 | volatile short msg_length; /* This length is "normal". */ |
116 | }; |
117 | |
118 | struct lance_tx_head { |
119 | unsigned short base; /* Low word of base addr */ |
120 | volatile unsigned char flag; |
121 | unsigned char base_hi; /* High word of base addr (unused) */ |
122 | short length; /* Length is 2s complement! */ |
123 | volatile short misc; |
124 | }; |
125 | |
126 | /* The LANCE initialization block, described in databook. */ |
127 | struct lance_init_block { |
128 | unsigned short mode; /* Pre-set mode */ |
129 | unsigned char hwaddr[6]; /* Physical ethernet address */ |
130 | unsigned int filter[2]; /* Multicast filter (unused). */ |
131 | /* Receive and transmit ring base, along with length bits. */ |
132 | unsigned short rdra; |
133 | unsigned short rlen; |
134 | unsigned short tdra; |
135 | unsigned short tlen; |
136 | unsigned short pad[4]; /* is thie needed? */ |
137 | }; |
138 | |
139 | /* The whole layout of the Lance shared memory */ |
140 | struct lance_memory { |
141 | struct lance_init_block init; |
142 | struct lance_tx_head tx_head[TX_RING_SIZE]; |
143 | struct lance_rx_head rx_head[RX_RING_SIZE]; |
144 | char rx_data[RX_RING_SIZE][PKT_BUF_SZ]; |
145 | char tx_data[TX_RING_SIZE][PKT_BUF_SZ]; |
146 | }; |
147 | |
148 | /* The driver's private device structure */ |
149 | |
150 | struct lance_private { |
151 | volatile unsigned short *iobase; |
152 | struct lance_memory *mem; |
153 | int new_rx, new_tx; /* The next free ring entry */ |
154 | int old_tx, old_rx; /* ring entry to be processed */ |
155 | /* These two must be longs for set_bit() */ |
156 | long tx_full; |
157 | long lock; |
158 | }; |
159 | |
160 | /* I/O register access macros */ |
161 | |
162 | #define MEM lp->mem |
163 | #define DREG lp->iobase[0] |
164 | #define AREG lp->iobase[1] |
165 | #define REGA(a) (*( AREG = (a), &DREG )) |
166 | |
167 | /* Definitions for the Lance */ |
168 | |
169 | /* tx_head flags */ |
170 | #define TMD1_ENP 0x01 /* end of packet */ |
171 | #define TMD1_STP 0x02 /* start of packet */ |
172 | #define TMD1_DEF 0x04 /* deferred */ |
173 | #define TMD1_ONE 0x08 /* one retry needed */ |
174 | #define TMD1_MORE 0x10 /* more than one retry needed */ |
175 | #define TMD1_ERR 0x40 /* error summary */ |
176 | #define TMD1_OWN 0x80 /* ownership (set: chip owns) */ |
177 | |
178 | #define TMD1_OWN_CHIP TMD1_OWN |
179 | #define TMD1_OWN_HOST 0 |
180 | |
181 | /* tx_head misc field */ |
182 | #define TMD3_TDR 0x03FF /* Time Domain Reflectometry counter */ |
183 | #define TMD3_RTRY 0x0400 /* failed after 16 retries */ |
184 | #define TMD3_LCAR 0x0800 /* carrier lost */ |
185 | #define TMD3_LCOL 0x1000 /* late collision */ |
186 | #define TMD3_UFLO 0x4000 /* underflow (late memory) */ |
187 | #define TMD3_BUFF 0x8000 /* buffering error (no ENP) */ |
188 | |
189 | /* rx_head flags */ |
190 | #define RMD1_ENP 0x01 /* end of packet */ |
191 | #define RMD1_STP 0x02 /* start of packet */ |
192 | #define RMD1_BUFF 0x04 /* buffer error */ |
193 | #define RMD1_CRC 0x08 /* CRC error */ |
194 | #define RMD1_OFLO 0x10 /* overflow */ |
195 | #define RMD1_FRAM 0x20 /* framing error */ |
196 | #define RMD1_ERR 0x40 /* error summary */ |
197 | #define RMD1_OWN 0x80 /* ownership (set: ship owns) */ |
198 | |
199 | #define RMD1_OWN_CHIP RMD1_OWN |
200 | #define RMD1_OWN_HOST 0 |
201 | |
202 | /* register names */ |
203 | #define CSR0 0 /* mode/status */ |
204 | #define CSR1 1 /* init block addr (low) */ |
205 | #define CSR2 2 /* init block addr (high) */ |
206 | #define CSR3 3 /* misc */ |
207 | #define CSR8 8 /* address filter */ |
208 | #define CSR15 15 /* promiscuous mode */ |
209 | |
210 | /* CSR0 */ |
211 | /* (R=readable, W=writeable, S=set on write, C=clear on write) */ |
212 | #define CSR0_INIT 0x0001 /* initialize (RS) */ |
213 | #define CSR0_STRT 0x0002 /* start (RS) */ |
214 | #define CSR0_STOP 0x0004 /* stop (RS) */ |
215 | #define CSR0_TDMD 0x0008 /* transmit demand (RS) */ |
216 | #define CSR0_TXON 0x0010 /* transmitter on (R) */ |
217 | #define CSR0_RXON 0x0020 /* receiver on (R) */ |
218 | #define CSR0_INEA 0x0040 /* interrupt enable (RW) */ |
219 | #define CSR0_INTR 0x0080 /* interrupt active (R) */ |
220 | #define CSR0_IDON 0x0100 /* initialization done (RC) */ |
221 | #define CSR0_TINT 0x0200 /* transmitter interrupt (RC) */ |
222 | #define CSR0_RINT 0x0400 /* receiver interrupt (RC) */ |
223 | #define CSR0_MERR 0x0800 /* memory error (RC) */ |
224 | #define CSR0_MISS 0x1000 /* missed frame (RC) */ |
225 | #define CSR0_CERR 0x2000 /* carrier error (no heartbeat :-) (RC) */ |
226 | #define CSR0_BABL 0x4000 /* babble: tx-ed too many bits (RC) */ |
227 | #define CSR0_ERR 0x8000 /* error (RC) */ |
228 | |
229 | /* CSR3 */ |
230 | #define CSR3_BCON 0x0001 /* byte control */ |
231 | #define CSR3_ACON 0x0002 /* ALE control */ |
232 | #define CSR3_BSWP 0x0004 /* byte swap (1=big endian) */ |
233 | |
234 | /***************************** Prototypes *****************************/ |
235 | |
236 | static int lance_probe( struct net_device *dev); |
237 | static int lance_open( struct net_device *dev ); |
238 | static void lance_init_ring( struct net_device *dev ); |
239 | static netdev_tx_t lance_start_xmit(struct sk_buff *skb, |
240 | struct net_device *dev); |
241 | static irqreturn_t lance_interrupt( int irq, void *dev_id); |
242 | static int lance_rx( struct net_device *dev ); |
243 | static int lance_close( struct net_device *dev ); |
244 | static void set_multicast_list( struct net_device *dev ); |
245 | |
246 | /************************* End of Prototypes **************************/ |
247 | |
248 | static struct net_device * __init sun3lance_probe(void) |
249 | { |
250 | struct net_device *dev; |
251 | static int found; |
252 | int err = -ENODEV; |
253 | |
254 | if (!MACH_IS_SUN3 && !MACH_IS_SUN3X) |
255 | return ERR_PTR(error: -ENODEV); |
256 | |
257 | /* check that this machine has an onboard lance */ |
258 | switch(idprom->id_machtype) { |
259 | case SM_SUN3|SM_3_50: |
260 | case SM_SUN3|SM_3_60: |
261 | case SM_SUN3X|SM_3_80: |
262 | /* these machines have lance */ |
263 | break; |
264 | |
265 | default: |
266 | return ERR_PTR(error: -ENODEV); |
267 | } |
268 | |
269 | if (found) |
270 | return ERR_PTR(error: -ENODEV); |
271 | |
272 | dev = alloc_etherdev(sizeof(struct lance_private)); |
273 | if (!dev) |
274 | return ERR_PTR(error: -ENOMEM); |
275 | |
276 | if (!lance_probe(dev)) |
277 | goto out; |
278 | |
279 | err = register_netdev(dev); |
280 | if (err) |
281 | goto out1; |
282 | found = 1; |
283 | return dev; |
284 | |
285 | out1: |
286 | #ifdef CONFIG_SUN3 |
287 | iounmap((void __iomem *)dev->base_addr); |
288 | #endif |
289 | out: |
290 | free_netdev(dev); |
291 | return ERR_PTR(error: err); |
292 | } |
293 | |
294 | static const struct net_device_ops lance_netdev_ops = { |
295 | .ndo_open = lance_open, |
296 | .ndo_stop = lance_close, |
297 | .ndo_start_xmit = lance_start_xmit, |
298 | .ndo_set_rx_mode = set_multicast_list, |
299 | .ndo_set_mac_address = NULL, |
300 | .ndo_validate_addr = eth_validate_addr, |
301 | }; |
302 | |
303 | static int __init lance_probe( struct net_device *dev) |
304 | { |
305 | unsigned long ioaddr; |
306 | |
307 | struct lance_private *lp; |
308 | static int did_version; |
309 | volatile unsigned short *ioaddr_probe; |
310 | unsigned short tmp1, tmp2; |
311 | |
312 | #ifdef CONFIG_SUN3 |
313 | ioaddr = (unsigned long)ioremap(LANCE_OBIO, PAGE_SIZE); |
314 | if (!ioaddr) |
315 | return 0; |
316 | #else |
317 | ioaddr = SUN3X_LANCE; |
318 | #endif |
319 | |
320 | /* test to see if there's really a lance here */ |
321 | /* (CSRO_INIT shouldn't be readable) */ |
322 | |
323 | ioaddr_probe = (volatile unsigned short *)ioaddr; |
324 | tmp1 = ioaddr_probe[0]; |
325 | tmp2 = ioaddr_probe[1]; |
326 | |
327 | ioaddr_probe[1] = CSR0; |
328 | ioaddr_probe[0] = CSR0_INIT | CSR0_STOP; |
329 | |
330 | if(ioaddr_probe[0] != CSR0_STOP) { |
331 | ioaddr_probe[0] = tmp1; |
332 | ioaddr_probe[1] = tmp2; |
333 | |
334 | #ifdef CONFIG_SUN3 |
335 | iounmap((void __iomem *)ioaddr); |
336 | #endif |
337 | return 0; |
338 | } |
339 | |
340 | lp = netdev_priv(dev); |
341 | |
342 | /* XXX - leak? */ |
343 | MEM = dvma_malloc_align(sizeof(struct lance_memory), 0x10000); |
344 | if (!MEM) { |
345 | #ifdef CONFIG_SUN3 |
346 | iounmap((void __iomem *)ioaddr); |
347 | #endif |
348 | printk(KERN_WARNING "SUN3 Lance couldn't allocate DVMA memory\n" ); |
349 | return 0; |
350 | } |
351 | |
352 | lp->iobase = (volatile unsigned short *)ioaddr; |
353 | dev->base_addr = (unsigned long)ioaddr; /* informational only */ |
354 | |
355 | REGA(CSR0) = CSR0_STOP; |
356 | |
357 | if (request_irq(LANCE_IRQ, handler: lance_interrupt, flags: 0, name: "SUN3 Lance" , dev) < 0) { |
358 | #ifdef CONFIG_SUN3 |
359 | iounmap((void __iomem *)ioaddr); |
360 | #endif |
361 | dvma_free((void *)MEM); |
362 | printk(KERN_WARNING "SUN3 Lance unable to allocate IRQ\n" ); |
363 | return 0; |
364 | } |
365 | dev->irq = (unsigned short)LANCE_IRQ; |
366 | |
367 | |
368 | printk("%s: SUN3 Lance at io %#lx, mem %#lx, irq %d, hwaddr " , |
369 | dev->name, |
370 | (unsigned long)ioaddr, |
371 | (unsigned long)MEM, |
372 | dev->irq); |
373 | |
374 | /* copy in the ethernet address from the prom */ |
375 | eth_hw_addr_set(dev, addr: idprom->id_ethaddr); |
376 | |
377 | /* tell the card it's ether address, bytes swapped */ |
378 | MEM->init.hwaddr[0] = dev->dev_addr[1]; |
379 | MEM->init.hwaddr[1] = dev->dev_addr[0]; |
380 | MEM->init.hwaddr[2] = dev->dev_addr[3]; |
381 | MEM->init.hwaddr[3] = dev->dev_addr[2]; |
382 | MEM->init.hwaddr[4] = dev->dev_addr[5]; |
383 | MEM->init.hwaddr[5] = dev->dev_addr[4]; |
384 | |
385 | printk("%pM\n" , dev->dev_addr); |
386 | |
387 | MEM->init.mode = 0x0000; |
388 | MEM->init.filter[0] = 0x00000000; |
389 | MEM->init.filter[1] = 0x00000000; |
390 | MEM->init.rdra = dvma_vtob(MEM->rx_head); |
391 | MEM->init.rlen = (RX_LOG_RING_SIZE << 13) | |
392 | (dvma_vtob(MEM->rx_head) >> 16); |
393 | MEM->init.tdra = dvma_vtob(MEM->tx_head); |
394 | MEM->init.tlen = (TX_LOG_RING_SIZE << 13) | |
395 | (dvma_vtob(MEM->tx_head) >> 16); |
396 | |
397 | DPRINTK(2, ("initaddr: %08lx rx_ring: %08lx tx_ring: %08lx\n" , |
398 | dvma_vtob(&(MEM->init)), dvma_vtob(MEM->rx_head), |
399 | (dvma_vtob(MEM->tx_head)))); |
400 | |
401 | if (did_version++ == 0) |
402 | printk( version ); |
403 | |
404 | dev->netdev_ops = &lance_netdev_ops; |
405 | // KLUDGE -- REMOVE ME |
406 | set_bit(nr: __LINK_STATE_PRESENT, addr: &dev->state); |
407 | |
408 | |
409 | return 1; |
410 | } |
411 | |
412 | static int lance_open( struct net_device *dev ) |
413 | { |
414 | struct lance_private *lp = netdev_priv(dev); |
415 | int i; |
416 | |
417 | DPRINTK( 2, ( "%s: lance_open()\n" , dev->name )); |
418 | |
419 | REGA(CSR0) = CSR0_STOP; |
420 | |
421 | lance_init_ring(dev); |
422 | |
423 | /* From now on, AREG is kept to point to CSR0 */ |
424 | REGA(CSR0) = CSR0_INIT; |
425 | |
426 | i = 1000000; |
427 | while (--i > 0) |
428 | if (DREG & CSR0_IDON) |
429 | break; |
430 | if (i <= 0 || (DREG & CSR0_ERR)) { |
431 | DPRINTK( 2, ( "lance_open(): opening %s failed, i=%d, csr0=%04x\n" , |
432 | dev->name, i, DREG )); |
433 | DREG = CSR0_STOP; |
434 | return -EIO; |
435 | } |
436 | |
437 | DREG = CSR0_IDON | CSR0_STRT | CSR0_INEA; |
438 | |
439 | netif_start_queue(dev); |
440 | |
441 | DPRINTK( 2, ( "%s: LANCE is open, csr0 %04x\n" , dev->name, DREG )); |
442 | |
443 | return 0; |
444 | } |
445 | |
446 | |
447 | /* Initialize the LANCE Rx and Tx rings. */ |
448 | |
449 | static void lance_init_ring( struct net_device *dev ) |
450 | { |
451 | struct lance_private *lp = netdev_priv(dev); |
452 | int i; |
453 | |
454 | lp->lock = 0; |
455 | lp->tx_full = 0; |
456 | lp->new_rx = lp->new_tx = 0; |
457 | lp->old_rx = lp->old_tx = 0; |
458 | |
459 | for( i = 0; i < TX_RING_SIZE; i++ ) { |
460 | MEM->tx_head[i].base = dvma_vtob(MEM->tx_data[i]); |
461 | MEM->tx_head[i].flag = 0; |
462 | MEM->tx_head[i].base_hi = |
463 | (dvma_vtob(MEM->tx_data[i])) >>16; |
464 | MEM->tx_head[i].length = 0; |
465 | MEM->tx_head[i].misc = 0; |
466 | } |
467 | |
468 | for( i = 0; i < RX_RING_SIZE; i++ ) { |
469 | MEM->rx_head[i].base = dvma_vtob(MEM->rx_data[i]); |
470 | MEM->rx_head[i].flag = RMD1_OWN_CHIP; |
471 | MEM->rx_head[i].base_hi = |
472 | (dvma_vtob(MEM->rx_data[i])) >> 16; |
473 | MEM->rx_head[i].buf_length = -PKT_BUF_SZ | 0xf000; |
474 | MEM->rx_head[i].msg_length = 0; |
475 | } |
476 | |
477 | /* tell the card it's ether address, bytes swapped */ |
478 | MEM->init.hwaddr[0] = dev->dev_addr[1]; |
479 | MEM->init.hwaddr[1] = dev->dev_addr[0]; |
480 | MEM->init.hwaddr[2] = dev->dev_addr[3]; |
481 | MEM->init.hwaddr[3] = dev->dev_addr[2]; |
482 | MEM->init.hwaddr[4] = dev->dev_addr[5]; |
483 | MEM->init.hwaddr[5] = dev->dev_addr[4]; |
484 | |
485 | MEM->init.mode = 0x0000; |
486 | MEM->init.filter[0] = 0x00000000; |
487 | MEM->init.filter[1] = 0x00000000; |
488 | MEM->init.rdra = dvma_vtob(MEM->rx_head); |
489 | MEM->init.rlen = (RX_LOG_RING_SIZE << 13) | |
490 | (dvma_vtob(MEM->rx_head) >> 16); |
491 | MEM->init.tdra = dvma_vtob(MEM->tx_head); |
492 | MEM->init.tlen = (TX_LOG_RING_SIZE << 13) | |
493 | (dvma_vtob(MEM->tx_head) >> 16); |
494 | |
495 | |
496 | /* tell the lance the address of its init block */ |
497 | REGA(CSR1) = dvma_vtob(&(MEM->init)); |
498 | REGA(CSR2) = dvma_vtob(&(MEM->init)) >> 16; |
499 | |
500 | #ifdef CONFIG_SUN3X |
501 | REGA(CSR3) = CSR3_BSWP | CSR3_ACON | CSR3_BCON; |
502 | #else |
503 | REGA(CSR3) = CSR3_BSWP; |
504 | #endif |
505 | |
506 | } |
507 | |
508 | |
509 | static netdev_tx_t |
510 | lance_start_xmit(struct sk_buff *skb, struct net_device *dev) |
511 | { |
512 | struct lance_private *lp = netdev_priv(dev); |
513 | int entry, len; |
514 | struct lance_tx_head *head; |
515 | unsigned long flags; |
516 | |
517 | DPRINTK( 1, ( "%s: transmit start.\n" , |
518 | dev->name)); |
519 | |
520 | /* Transmitter timeout, serious problems. */ |
521 | if (netif_queue_stopped(dev)) { |
522 | int tickssofar = jiffies - dev_trans_start(dev); |
523 | if (tickssofar < HZ/5) |
524 | return NETDEV_TX_BUSY; |
525 | |
526 | DPRINTK( 1, ( "%s: transmit timed out, status %04x, resetting.\n" , |
527 | dev->name, DREG )); |
528 | DREG = CSR0_STOP; |
529 | /* |
530 | * Always set BSWP after a STOP as STOP puts it back into |
531 | * little endian mode. |
532 | */ |
533 | REGA(CSR3) = CSR3_BSWP; |
534 | dev->stats.tx_errors++; |
535 | |
536 | if(lance_debug >= 2) { |
537 | int i; |
538 | printk("Ring data: old_tx %d new_tx %d%s new_rx %d\n" , |
539 | lp->old_tx, lp->new_tx, |
540 | lp->tx_full ? " (full)" : "" , |
541 | lp->new_rx ); |
542 | for( i = 0 ; i < RX_RING_SIZE; i++ ) |
543 | printk( "rx #%d: base=%04x blen=%04x mlen=%04x\n" , |
544 | i, MEM->rx_head[i].base, |
545 | -MEM->rx_head[i].buf_length, |
546 | MEM->rx_head[i].msg_length); |
547 | for( i = 0 ; i < TX_RING_SIZE; i++ ) |
548 | printk("tx #%d: base=%04x len=%04x misc=%04x\n" , |
549 | i, MEM->tx_head[i].base, |
550 | -MEM->tx_head[i].length, |
551 | MEM->tx_head[i].misc ); |
552 | } |
553 | |
554 | lance_init_ring(dev); |
555 | REGA( CSR0 ) = CSR0_INEA | CSR0_INIT | CSR0_STRT; |
556 | |
557 | netif_start_queue(dev); |
558 | |
559 | return NETDEV_TX_OK; |
560 | } |
561 | |
562 | |
563 | /* Block a timer-based transmit from overlapping. This could better be |
564 | done with atomic_swap(1, dev->tbusy), but set_bit() works as well. */ |
565 | |
566 | /* Block a timer-based transmit from overlapping with us by |
567 | stopping the queue for a bit... */ |
568 | |
569 | netif_stop_queue(dev); |
570 | |
571 | if (test_and_set_bit( nr: 0, addr: (void*)&lp->lock ) != 0) { |
572 | printk( "%s: tx queue lock!.\n" , dev->name); |
573 | /* don't clear dev->tbusy flag. */ |
574 | return NETDEV_TX_BUSY; |
575 | } |
576 | |
577 | AREG = CSR0; |
578 | DPRINTK( 2, ( "%s: lance_start_xmit() called, csr0 %4.4x.\n" , |
579 | dev->name, DREG )); |
580 | |
581 | #ifdef CONFIG_SUN3X |
582 | /* this weirdness doesn't appear on sun3... */ |
583 | if(!(DREG & CSR0_INIT)) { |
584 | DPRINTK( 1, ("INIT not set, reinitializing...\n" )); |
585 | REGA( CSR0 ) = CSR0_STOP; |
586 | lance_init_ring(dev); |
587 | REGA( CSR0 ) = CSR0_INIT | CSR0_STRT; |
588 | } |
589 | #endif |
590 | |
591 | /* Fill in a Tx ring entry */ |
592 | #if 0 |
593 | if (lance_debug >= 2) { |
594 | printk( "%s: TX pkt %d type 0x%04x" |
595 | " from %s to %s" |
596 | " data at 0x%08x len %d\n" , |
597 | dev->name, lp->new_tx, ((u_short *)skb->data)[6], |
598 | DEV_ADDR(&skb->data[6]), DEV_ADDR(skb->data), |
599 | (int)skb->data, (int)skb->len ); |
600 | } |
601 | #endif |
602 | /* We're not prepared for the int until the last flags are set/reset. |
603 | * And the int may happen already after setting the OWN_CHIP... */ |
604 | local_irq_save(flags); |
605 | |
606 | /* Mask to ring buffer boundary. */ |
607 | entry = lp->new_tx; |
608 | head = &(MEM->tx_head[entry]); |
609 | |
610 | /* Caution: the write order is important here, set the "ownership" bits |
611 | * last. |
612 | */ |
613 | |
614 | /* the sun3's lance needs it's buffer padded to the minimum |
615 | size */ |
616 | len = (ETH_ZLEN < skb->len) ? skb->len : ETH_ZLEN; |
617 | |
618 | // head->length = -len; |
619 | head->length = (-len) | 0xf000; |
620 | head->misc = 0; |
621 | |
622 | skb_copy_from_linear_data(skb, PKTBUF_ADDR(head), len: skb->len); |
623 | if (len != skb->len) |
624 | memset(PKTBUF_ADDR(head) + skb->len, 0, len-skb->len); |
625 | |
626 | head->flag = TMD1_OWN_CHIP | TMD1_ENP | TMD1_STP; |
627 | lp->new_tx = (lp->new_tx + 1) & TX_RING_MOD_MASK; |
628 | dev->stats.tx_bytes += skb->len; |
629 | |
630 | /* Trigger an immediate send poll. */ |
631 | REGA(CSR0) = CSR0_INEA | CSR0_TDMD | CSR0_STRT; |
632 | AREG = CSR0; |
633 | DPRINTK( 2, ( "%s: lance_start_xmit() exiting, csr0 %4.4x.\n" , |
634 | dev->name, DREG )); |
635 | dev_kfree_skb(skb); |
636 | |
637 | lp->lock = 0; |
638 | if ((MEM->tx_head[(entry+1) & TX_RING_MOD_MASK].flag & TMD1_OWN) == |
639 | TMD1_OWN_HOST) |
640 | netif_start_queue(dev); |
641 | |
642 | local_irq_restore(flags); |
643 | |
644 | return NETDEV_TX_OK; |
645 | } |
646 | |
647 | /* The LANCE interrupt handler. */ |
648 | |
649 | static irqreturn_t lance_interrupt( int irq, void *dev_id) |
650 | { |
651 | struct net_device *dev = dev_id; |
652 | struct lance_private *lp = netdev_priv(dev); |
653 | int csr0; |
654 | |
655 | still_more: |
656 | flush_cache_all(); |
657 | |
658 | AREG = CSR0; |
659 | csr0 = DREG; |
660 | |
661 | /* ack interrupts */ |
662 | DREG = csr0 & (CSR0_TINT | CSR0_RINT | CSR0_IDON); |
663 | |
664 | /* clear errors */ |
665 | if(csr0 & CSR0_ERR) |
666 | DREG = CSR0_BABL | CSR0_MERR | CSR0_CERR | CSR0_MISS; |
667 | |
668 | |
669 | DPRINTK( 2, ( "%s: interrupt csr0=%04x new csr=%04x.\n" , |
670 | dev->name, csr0, DREG )); |
671 | |
672 | if (csr0 & CSR0_TINT) { /* Tx-done interrupt */ |
673 | int old_tx = lp->old_tx; |
674 | |
675 | // if(lance_debug >= 3) { |
676 | // int i; |
677 | // |
678 | // printk("%s: tx int\n", dev->name); |
679 | // |
680 | // for(i = 0; i < TX_RING_SIZE; i++) |
681 | // printk("ring %d flag=%04x\n", i, |
682 | // MEM->tx_head[i].flag); |
683 | // } |
684 | |
685 | while( old_tx != lp->new_tx) { |
686 | struct lance_tx_head *head = &(MEM->tx_head[old_tx]); |
687 | |
688 | DPRINTK(3, ("on tx_ring %d\n" , old_tx)); |
689 | |
690 | if (head->flag & TMD1_OWN_CHIP) |
691 | break; /* It still hasn't been Txed */ |
692 | |
693 | if (head->flag & TMD1_ERR) { |
694 | int status = head->misc; |
695 | dev->stats.tx_errors++; |
696 | if (status & TMD3_RTRY) dev->stats.tx_aborted_errors++; |
697 | if (status & TMD3_LCAR) dev->stats.tx_carrier_errors++; |
698 | if (status & TMD3_LCOL) dev->stats.tx_window_errors++; |
699 | if (status & (TMD3_UFLO | TMD3_BUFF)) { |
700 | dev->stats.tx_fifo_errors++; |
701 | printk("%s: Tx FIFO error\n" , |
702 | dev->name); |
703 | REGA(CSR0) = CSR0_STOP; |
704 | REGA(CSR3) = CSR3_BSWP; |
705 | lance_init_ring(dev); |
706 | REGA(CSR0) = CSR0_STRT | CSR0_INEA; |
707 | return IRQ_HANDLED; |
708 | } |
709 | } else if(head->flag & (TMD1_ENP | TMD1_STP)) { |
710 | |
711 | head->flag &= ~(TMD1_ENP | TMD1_STP); |
712 | if(head->flag & (TMD1_ONE | TMD1_MORE)) |
713 | dev->stats.collisions++; |
714 | |
715 | dev->stats.tx_packets++; |
716 | DPRINTK(3, ("cleared tx ring %d\n" , old_tx)); |
717 | } |
718 | old_tx = (old_tx +1) & TX_RING_MOD_MASK; |
719 | } |
720 | |
721 | lp->old_tx = old_tx; |
722 | } |
723 | |
724 | |
725 | if (netif_queue_stopped(dev)) { |
726 | /* The ring is no longer full, clear tbusy. */ |
727 | netif_start_queue(dev); |
728 | netif_wake_queue(dev); |
729 | } |
730 | |
731 | if (csr0 & CSR0_RINT) /* Rx interrupt */ |
732 | lance_rx( dev ); |
733 | |
734 | /* Log misc errors. */ |
735 | if (csr0 & CSR0_BABL) dev->stats.tx_errors++; /* Tx babble. */ |
736 | if (csr0 & CSR0_MISS) dev->stats.rx_errors++; /* Missed a Rx frame. */ |
737 | if (csr0 & CSR0_MERR) { |
738 | DPRINTK( 1, ( "%s: Bus master arbitration failure (?!?), " |
739 | "status %04x.\n" , dev->name, csr0 )); |
740 | /* Restart the chip. */ |
741 | REGA(CSR0) = CSR0_STOP; |
742 | REGA(CSR3) = CSR3_BSWP; |
743 | lance_init_ring(dev); |
744 | REGA(CSR0) = CSR0_STRT | CSR0_INEA; |
745 | } |
746 | |
747 | |
748 | /* Clear any other interrupt, and set interrupt enable. */ |
749 | // DREG = CSR0_BABL | CSR0_CERR | CSR0_MISS | CSR0_MERR | |
750 | // CSR0_IDON | CSR0_INEA; |
751 | |
752 | REGA(CSR0) = CSR0_INEA; |
753 | |
754 | if(DREG & (CSR0_RINT | CSR0_TINT)) { |
755 | DPRINTK(2, ("restarting interrupt, csr0=%#04x\n" , DREG)); |
756 | goto still_more; |
757 | } |
758 | |
759 | DPRINTK( 2, ( "%s: exiting interrupt, csr0=%#04x.\n" , |
760 | dev->name, DREG )); |
761 | return IRQ_HANDLED; |
762 | } |
763 | |
764 | /* get packet, toss into skbuff */ |
765 | static int lance_rx( struct net_device *dev ) |
766 | { |
767 | struct lance_private *lp = netdev_priv(dev); |
768 | int entry = lp->new_rx; |
769 | |
770 | /* If we own the next entry, it's a new packet. Send it up. */ |
771 | while( (MEM->rx_head[entry].flag & RMD1_OWN) == RMD1_OWN_HOST ) { |
772 | struct lance_rx_head *head = &(MEM->rx_head[entry]); |
773 | int status = head->flag; |
774 | |
775 | if (status != (RMD1_ENP|RMD1_STP)) { /* There was an error. */ |
776 | /* There is a tricky error noted by John Murphy, |
777 | <murf@perftech.com> to Russ Nelson: Even with |
778 | full-sized buffers it's possible for a jabber packet to use two |
779 | buffers, with only the last correctly noting the error. */ |
780 | if (status & RMD1_ENP) /* Only count a general error at the */ |
781 | dev->stats.rx_errors++; /* end of a packet.*/ |
782 | if (status & RMD1_FRAM) dev->stats.rx_frame_errors++; |
783 | if (status & RMD1_OFLO) dev->stats.rx_over_errors++; |
784 | if (status & RMD1_CRC) dev->stats.rx_crc_errors++; |
785 | if (status & RMD1_BUFF) dev->stats.rx_fifo_errors++; |
786 | head->flag &= (RMD1_ENP|RMD1_STP); |
787 | } else { |
788 | /* Malloc up new buffer, compatible with net-3. */ |
789 | // short pkt_len = head->msg_length;// & 0xfff; |
790 | short pkt_len = (head->msg_length & 0xfff) - 4; |
791 | struct sk_buff *skb; |
792 | |
793 | if (pkt_len < 60) { |
794 | printk( "%s: Runt packet!\n" , dev->name ); |
795 | dev->stats.rx_errors++; |
796 | } |
797 | else { |
798 | skb = netdev_alloc_skb(dev, length: pkt_len + 2); |
799 | if (!skb) { |
800 | dev->stats.rx_dropped++; |
801 | head->msg_length = 0; |
802 | head->flag |= RMD1_OWN_CHIP; |
803 | lp->new_rx = (lp->new_rx+1) & |
804 | RX_RING_MOD_MASK; |
805 | } |
806 | |
807 | #if 0 |
808 | if (lance_debug >= 3) { |
809 | u_char *data = PKTBUF_ADDR(head); |
810 | printk("%s: RX pkt %d type 0x%04x" |
811 | " from %pM to %pM" , |
812 | dev->name, lp->new_tx, ((u_short *)data)[6], |
813 | &data[6], data); |
814 | |
815 | printk(" data %02x %02x %02x %02x %02x %02x %02x %02x " |
816 | "len %d at %08x\n" , |
817 | data[15], data[16], data[17], data[18], |
818 | data[19], data[20], data[21], data[22], |
819 | pkt_len, data); |
820 | } |
821 | #endif |
822 | if (lance_debug >= 3) { |
823 | u_char *data = PKTBUF_ADDR(head); |
824 | printk( "%s: RX pkt %d type 0x%04x len %d\n " , dev->name, entry, ((u_short *)data)[6], pkt_len); |
825 | } |
826 | |
827 | |
828 | skb_reserve( skb, len: 2 ); /* 16 byte align */ |
829 | skb_put( skb, len: pkt_len ); /* Make room */ |
830 | skb_copy_to_linear_data(skb, |
831 | PKTBUF_ADDR(head), |
832 | len: pkt_len); |
833 | |
834 | skb->protocol = eth_type_trans( skb, dev ); |
835 | netif_rx( skb ); |
836 | dev->stats.rx_packets++; |
837 | dev->stats.rx_bytes += pkt_len; |
838 | } |
839 | } |
840 | |
841 | // head->buf_length = -PKT_BUF_SZ | 0xf000; |
842 | head->msg_length = 0; |
843 | head->flag = RMD1_OWN_CHIP; |
844 | |
845 | entry = lp->new_rx = (lp->new_rx +1) & RX_RING_MOD_MASK; |
846 | } |
847 | |
848 | /* From lance.c (Donald Becker): */ |
849 | /* We should check that at least two ring entries are free. |
850 | If not, we should free one and mark stats->rx_dropped++. */ |
851 | |
852 | return 0; |
853 | } |
854 | |
855 | |
856 | static int lance_close( struct net_device *dev ) |
857 | { |
858 | struct lance_private *lp = netdev_priv(dev); |
859 | |
860 | netif_stop_queue(dev); |
861 | |
862 | AREG = CSR0; |
863 | |
864 | DPRINTK( 2, ( "%s: Shutting down ethercard, status was %2.2x.\n" , |
865 | dev->name, DREG )); |
866 | |
867 | /* We stop the LANCE here -- it occasionally polls |
868 | memory if we don't. */ |
869 | DREG = CSR0_STOP; |
870 | return 0; |
871 | } |
872 | |
873 | |
874 | /* Set or clear the multicast filter for this adaptor. |
875 | num_addrs == -1 Promiscuous mode, receive all packets |
876 | num_addrs == 0 Normal mode, clear multicast list |
877 | num_addrs > 0 Multicast mode, receive normal and MC packets, and do |
878 | best-effort filtering. |
879 | */ |
880 | |
881 | /* completely untested on a sun3 */ |
882 | static void set_multicast_list( struct net_device *dev ) |
883 | { |
884 | struct lance_private *lp = netdev_priv(dev); |
885 | |
886 | if(netif_queue_stopped(dev)) |
887 | /* Only possible if board is already started */ |
888 | return; |
889 | |
890 | /* We take the simple way out and always enable promiscuous mode. */ |
891 | DREG = CSR0_STOP; /* Temporarily stop the lance. */ |
892 | |
893 | if (dev->flags & IFF_PROMISC) { |
894 | /* Log any net taps. */ |
895 | DPRINTK( 3, ( "%s: Promiscuous mode enabled.\n" , dev->name )); |
896 | REGA( CSR15 ) = 0x8000; /* Set promiscuous mode */ |
897 | } else { |
898 | short multicast_table[4]; |
899 | int num_addrs = netdev_mc_count(dev); |
900 | int i; |
901 | /* We don't use the multicast table, but rely on upper-layer |
902 | * filtering. */ |
903 | memset( multicast_table, (num_addrs == 0) ? 0 : -1, |
904 | sizeof(multicast_table) ); |
905 | for( i = 0; i < 4; i++ ) |
906 | REGA( CSR8+i ) = multicast_table[i]; |
907 | REGA( CSR15 ) = 0; /* Unset promiscuous mode */ |
908 | } |
909 | |
910 | /* |
911 | * Always set BSWP after a STOP as STOP puts it back into |
912 | * little endian mode. |
913 | */ |
914 | REGA( CSR3 ) = CSR3_BSWP; |
915 | |
916 | /* Resume normal operation and reset AREG to CSR0 */ |
917 | REGA( CSR0 ) = CSR0_IDON | CSR0_INEA | CSR0_STRT; |
918 | } |
919 | |
920 | |
921 | static struct net_device *sun3lance_dev; |
922 | |
923 | static int __init sun3lance_init(void) |
924 | { |
925 | sun3lance_dev = sun3lance_probe(); |
926 | return PTR_ERR_OR_ZERO(ptr: sun3lance_dev); |
927 | } |
928 | module_init(sun3lance_init); |
929 | |
930 | static void __exit sun3lance_cleanup(void) |
931 | { |
932 | unregister_netdev(dev: sun3lance_dev); |
933 | #ifdef CONFIG_SUN3 |
934 | iounmap((void __iomem *)sun3lance_dev->base_addr); |
935 | #endif |
936 | free_netdev(dev: sun3lance_dev); |
937 | } |
938 | module_exit(sun3lance_cleanup); |
939 | |