1/* Broadcom NetXtreme-C/E network driver.
2 *
3 * Copyright (c) 2014-2016 Broadcom Corporation
4 * Copyright (c) 2016-2018 Broadcom Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.
9 */
10
11#ifndef BNXT_H
12#define BNXT_H
13
14#define DRV_MODULE_NAME "bnxt_en"
15
16/* DO NOT CHANGE DRV_VER_* defines
17 * FIXME: Delete them
18 */
19#define DRV_VER_MAJ 1
20#define DRV_VER_MIN 10
21#define DRV_VER_UPD 2
22
23#include <linux/ethtool.h>
24#include <linux/interrupt.h>
25#include <linux/rhashtable.h>
26#include <linux/crash_dump.h>
27#include <linux/auxiliary_bus.h>
28#include <net/devlink.h>
29#include <net/dst_metadata.h>
30#include <net/xdp.h>
31#include <linux/dim.h>
32#include <linux/io-64-nonatomic-lo-hi.h>
33#ifdef CONFIG_TEE_BNXT_FW
34#include <linux/firmware/broadcom/tee_bnxt_fw.h>
35#endif
36
37extern struct list_head bnxt_block_cb_list;
38
39struct page_pool;
40
41struct tx_bd {
42 __le32 tx_bd_len_flags_type;
43 #define TX_BD_TYPE (0x3f << 0)
44 #define TX_BD_TYPE_SHORT_TX_BD (0x00 << 0)
45 #define TX_BD_TYPE_LONG_TX_BD (0x10 << 0)
46 #define TX_BD_FLAGS_PACKET_END (1 << 6)
47 #define TX_BD_FLAGS_NO_CMPL (1 << 7)
48 #define TX_BD_FLAGS_BD_CNT (0x1f << 8)
49 #define TX_BD_FLAGS_BD_CNT_SHIFT 8
50 #define TX_BD_FLAGS_LHINT (3 << 13)
51 #define TX_BD_FLAGS_LHINT_SHIFT 13
52 #define TX_BD_FLAGS_LHINT_512_AND_SMALLER (0 << 13)
53 #define TX_BD_FLAGS_LHINT_512_TO_1023 (1 << 13)
54 #define TX_BD_FLAGS_LHINT_1024_TO_2047 (2 << 13)
55 #define TX_BD_FLAGS_LHINT_2048_AND_LARGER (3 << 13)
56 #define TX_BD_FLAGS_COAL_NOW (1 << 15)
57 #define TX_BD_LEN (0xffff << 16)
58 #define TX_BD_LEN_SHIFT 16
59
60 u32 tx_bd_opaque;
61 __le64 tx_bd_haddr;
62} __packed;
63
64struct tx_bd_ext {
65 __le32 tx_bd_hsize_lflags;
66 #define TX_BD_FLAGS_TCP_UDP_CHKSUM (1 << 0)
67 #define TX_BD_FLAGS_IP_CKSUM (1 << 1)
68 #define TX_BD_FLAGS_NO_CRC (1 << 2)
69 #define TX_BD_FLAGS_STAMP (1 << 3)
70 #define TX_BD_FLAGS_T_IP_CHKSUM (1 << 4)
71 #define TX_BD_FLAGS_LSO (1 << 5)
72 #define TX_BD_FLAGS_IPID_FMT (1 << 6)
73 #define TX_BD_FLAGS_T_IPID (1 << 7)
74 #define TX_BD_HSIZE (0xff << 16)
75 #define TX_BD_HSIZE_SHIFT 16
76
77 __le32 tx_bd_mss;
78 __le32 tx_bd_cfa_action;
79 #define TX_BD_CFA_ACTION (0xffff << 16)
80 #define TX_BD_CFA_ACTION_SHIFT 16
81
82 __le32 tx_bd_cfa_meta;
83 #define TX_BD_CFA_META_MASK 0xfffffff
84 #define TX_BD_CFA_META_VID_MASK 0xfff
85 #define TX_BD_CFA_META_PRI_MASK (0xf << 12)
86 #define TX_BD_CFA_META_PRI_SHIFT 12
87 #define TX_BD_CFA_META_TPID_MASK (3 << 16)
88 #define TX_BD_CFA_META_TPID_SHIFT 16
89 #define TX_BD_CFA_META_KEY (0xf << 28)
90 #define TX_BD_CFA_META_KEY_SHIFT 28
91 #define TX_BD_CFA_META_KEY_VLAN (1 << 28)
92};
93
94#define BNXT_TX_PTP_IS_SET(lflags) ((lflags) & cpu_to_le32(TX_BD_FLAGS_STAMP))
95
96struct rx_bd {
97 __le32 rx_bd_len_flags_type;
98 #define RX_BD_TYPE (0x3f << 0)
99 #define RX_BD_TYPE_RX_PACKET_BD 0x4
100 #define RX_BD_TYPE_RX_BUFFER_BD 0x5
101 #define RX_BD_TYPE_RX_AGG_BD 0x6
102 #define RX_BD_TYPE_16B_BD_SIZE (0 << 4)
103 #define RX_BD_TYPE_32B_BD_SIZE (1 << 4)
104 #define RX_BD_TYPE_48B_BD_SIZE (2 << 4)
105 #define RX_BD_TYPE_64B_BD_SIZE (3 << 4)
106 #define RX_BD_FLAGS_SOP (1 << 6)
107 #define RX_BD_FLAGS_EOP (1 << 7)
108 #define RX_BD_FLAGS_BUFFERS (3 << 8)
109 #define RX_BD_FLAGS_1_BUFFER_PACKET (0 << 8)
110 #define RX_BD_FLAGS_2_BUFFER_PACKET (1 << 8)
111 #define RX_BD_FLAGS_3_BUFFER_PACKET (2 << 8)
112 #define RX_BD_FLAGS_4_BUFFER_PACKET (3 << 8)
113 #define RX_BD_LEN (0xffff << 16)
114 #define RX_BD_LEN_SHIFT 16
115
116 u32 rx_bd_opaque;
117 __le64 rx_bd_haddr;
118};
119
120struct tx_cmp {
121 __le32 tx_cmp_flags_type;
122 #define CMP_TYPE (0x3f << 0)
123 #define CMP_TYPE_TX_L2_CMP 0
124 #define CMP_TYPE_RX_L2_CMP 17
125 #define CMP_TYPE_RX_AGG_CMP 18
126 #define CMP_TYPE_RX_L2_TPA_START_CMP 19
127 #define CMP_TYPE_RX_L2_TPA_END_CMP 21
128 #define CMP_TYPE_RX_TPA_AGG_CMP 22
129 #define CMP_TYPE_STATUS_CMP 32
130 #define CMP_TYPE_REMOTE_DRIVER_REQ 34
131 #define CMP_TYPE_REMOTE_DRIVER_RESP 36
132 #define CMP_TYPE_ERROR_STATUS 48
133 #define CMPL_BASE_TYPE_STAT_EJECT 0x1aUL
134 #define CMPL_BASE_TYPE_HWRM_DONE 0x20UL
135 #define CMPL_BASE_TYPE_HWRM_FWD_REQ 0x22UL
136 #define CMPL_BASE_TYPE_HWRM_FWD_RESP 0x24UL
137 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
138
139 #define TX_CMP_FLAGS_ERROR (1 << 6)
140 #define TX_CMP_FLAGS_PUSH (1 << 7)
141
142 u32 tx_cmp_opaque;
143 __le32 tx_cmp_errors_v;
144 #define TX_CMP_V (1 << 0)
145 #define TX_CMP_ERRORS_BUFFER_ERROR (7 << 1)
146 #define TX_CMP_ERRORS_BUFFER_ERROR_NO_ERROR 0
147 #define TX_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT 2
148 #define TX_CMP_ERRORS_BUFFER_ERROR_INVALID_STAG 4
149 #define TX_CMP_ERRORS_BUFFER_ERROR_STAG_BOUNDS 5
150 #define TX_CMP_ERRORS_ZERO_LENGTH_PKT (1 << 4)
151 #define TX_CMP_ERRORS_EXCESSIVE_BD_LEN (1 << 5)
152 #define TX_CMP_ERRORS_DMA_ERROR (1 << 6)
153 #define TX_CMP_ERRORS_HINT_TOO_SHORT (1 << 7)
154
155 __le32 tx_cmp_unsed_3;
156};
157
158struct rx_cmp {
159 __le32 rx_cmp_len_flags_type;
160 #define RX_CMP_CMP_TYPE (0x3f << 0)
161 #define RX_CMP_FLAGS_ERROR (1 << 6)
162 #define RX_CMP_FLAGS_PLACEMENT (7 << 7)
163 #define RX_CMP_FLAGS_RSS_VALID (1 << 10)
164 #define RX_CMP_FLAGS_UNUSED (1 << 11)
165 #define RX_CMP_FLAGS_ITYPES_SHIFT 12
166 #define RX_CMP_FLAGS_ITYPES_MASK 0xf000
167 #define RX_CMP_FLAGS_ITYPE_UNKNOWN (0 << 12)
168 #define RX_CMP_FLAGS_ITYPE_IP (1 << 12)
169 #define RX_CMP_FLAGS_ITYPE_TCP (2 << 12)
170 #define RX_CMP_FLAGS_ITYPE_UDP (3 << 12)
171 #define RX_CMP_FLAGS_ITYPE_FCOE (4 << 12)
172 #define RX_CMP_FLAGS_ITYPE_ROCE (5 << 12)
173 #define RX_CMP_FLAGS_ITYPE_PTP_WO_TS (8 << 12)
174 #define RX_CMP_FLAGS_ITYPE_PTP_W_TS (9 << 12)
175 #define RX_CMP_LEN (0xffff << 16)
176 #define RX_CMP_LEN_SHIFT 16
177
178 u32 rx_cmp_opaque;
179 __le32 rx_cmp_misc_v1;
180 #define RX_CMP_V1 (1 << 0)
181 #define RX_CMP_AGG_BUFS (0x1f << 1)
182 #define RX_CMP_AGG_BUFS_SHIFT 1
183 #define RX_CMP_RSS_HASH_TYPE (0x7f << 9)
184 #define RX_CMP_RSS_HASH_TYPE_SHIFT 9
185 #define RX_CMP_PAYLOAD_OFFSET (0xff << 16)
186 #define RX_CMP_PAYLOAD_OFFSET_SHIFT 16
187
188 __le32 rx_cmp_rss_hash;
189};
190
191#define RX_CMP_HASH_VALID(rxcmp) \
192 ((rxcmp)->rx_cmp_len_flags_type & cpu_to_le32(RX_CMP_FLAGS_RSS_VALID))
193
194#define RSS_PROFILE_ID_MASK 0x1f
195
196#define RX_CMP_HASH_TYPE(rxcmp) \
197 (((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_RSS_HASH_TYPE) >>\
198 RX_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
199
200struct rx_cmp_ext {
201 __le32 rx_cmp_flags2;
202 #define RX_CMP_FLAGS2_IP_CS_CALC 0x1
203 #define RX_CMP_FLAGS2_L4_CS_CALC (0x1 << 1)
204 #define RX_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2)
205 #define RX_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3)
206 #define RX_CMP_FLAGS2_META_FORMAT_VLAN (0x1 << 4)
207 __le32 rx_cmp_meta_data;
208 #define RX_CMP_FLAGS2_METADATA_TCI_MASK 0xffff
209 #define RX_CMP_FLAGS2_METADATA_VID_MASK 0xfff
210 #define RX_CMP_FLAGS2_METADATA_TPID_MASK 0xffff0000
211 #define RX_CMP_FLAGS2_METADATA_TPID_SFT 16
212 __le32 rx_cmp_cfa_code_errors_v2;
213 #define RX_CMP_V (1 << 0)
214 #define RX_CMPL_ERRORS_MASK (0x7fff << 1)
215 #define RX_CMPL_ERRORS_SFT 1
216 #define RX_CMPL_ERRORS_BUFFER_ERROR_MASK (0x7 << 1)
217 #define RX_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)
218 #define RX_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1 << 1)
219 #define RX_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2 << 1)
220 #define RX_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
221 #define RX_CMPL_ERRORS_IP_CS_ERROR (0x1 << 4)
222 #define RX_CMPL_ERRORS_L4_CS_ERROR (0x1 << 5)
223 #define RX_CMPL_ERRORS_T_IP_CS_ERROR (0x1 << 6)
224 #define RX_CMPL_ERRORS_T_L4_CS_ERROR (0x1 << 7)
225 #define RX_CMPL_ERRORS_CRC_ERROR (0x1 << 8)
226 #define RX_CMPL_ERRORS_T_PKT_ERROR_MASK (0x7 << 9)
227 #define RX_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR (0x0 << 9)
228 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1 << 9)
229 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2 << 9)
230 #define RX_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (0x3 << 9)
231 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x4 << 9)
232 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x5 << 9)
233 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x6 << 9)
234 #define RX_CMPL_ERRORS_PKT_ERROR_MASK (0xf << 12)
235 #define RX_CMPL_ERRORS_PKT_ERROR_NO_ERROR (0x0 << 12)
236 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1 << 12)
237 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2 << 12)
238 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3 << 12)
239 #define RX_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4 << 12)
240 #define RX_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5 << 12)
241 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6 << 12)
242 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7 << 12)
243 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (0x8 << 12)
244
245 #define RX_CMPL_CFA_CODE_MASK (0xffff << 16)
246 #define RX_CMPL_CFA_CODE_SFT 16
247
248 __le32 rx_cmp_timestamp;
249};
250
251#define RX_CMP_L2_ERRORS \
252 cpu_to_le32(RX_CMPL_ERRORS_BUFFER_ERROR_MASK | RX_CMPL_ERRORS_CRC_ERROR)
253
254#define RX_CMP_L4_CS_BITS \
255 (cpu_to_le32(RX_CMP_FLAGS2_L4_CS_CALC | RX_CMP_FLAGS2_T_L4_CS_CALC))
256
257#define RX_CMP_L4_CS_ERR_BITS \
258 (cpu_to_le32(RX_CMPL_ERRORS_L4_CS_ERROR | RX_CMPL_ERRORS_T_L4_CS_ERROR))
259
260#define RX_CMP_L4_CS_OK(rxcmp1) \
261 (((rxcmp1)->rx_cmp_flags2 & RX_CMP_L4_CS_BITS) && \
262 !((rxcmp1)->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS))
263
264#define RX_CMP_ENCAP(rxcmp1) \
265 ((le32_to_cpu((rxcmp1)->rx_cmp_flags2) & \
266 RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3)
267
268#define RX_CMP_CFA_CODE(rxcmpl1) \
269 ((le32_to_cpu((rxcmpl1)->rx_cmp_cfa_code_errors_v2) & \
270 RX_CMPL_CFA_CODE_MASK) >> RX_CMPL_CFA_CODE_SFT)
271
272struct rx_agg_cmp {
273 __le32 rx_agg_cmp_len_flags_type;
274 #define RX_AGG_CMP_TYPE (0x3f << 0)
275 #define RX_AGG_CMP_LEN (0xffff << 16)
276 #define RX_AGG_CMP_LEN_SHIFT 16
277 u32 rx_agg_cmp_opaque;
278 __le32 rx_agg_cmp_v;
279 #define RX_AGG_CMP_V (1 << 0)
280 #define RX_AGG_CMP_AGG_ID (0xffff << 16)
281 #define RX_AGG_CMP_AGG_ID_SHIFT 16
282 __le32 rx_agg_cmp_unused;
283};
284
285#define TPA_AGG_AGG_ID(rx_agg) \
286 ((le32_to_cpu((rx_agg)->rx_agg_cmp_v) & \
287 RX_AGG_CMP_AGG_ID) >> RX_AGG_CMP_AGG_ID_SHIFT)
288
289struct rx_tpa_start_cmp {
290 __le32 rx_tpa_start_cmp_len_flags_type;
291 #define RX_TPA_START_CMP_TYPE (0x3f << 0)
292 #define RX_TPA_START_CMP_FLAGS (0x3ff << 6)
293 #define RX_TPA_START_CMP_FLAGS_SHIFT 6
294 #define RX_TPA_START_CMP_FLAGS_ERROR (0x1 << 6)
295 #define RX_TPA_START_CMP_FLAGS_PLACEMENT (0x7 << 7)
296 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_SHIFT 7
297 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7)
298 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7)
299 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7)
300 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7)
301 #define RX_TPA_START_CMP_FLAGS_RSS_VALID (0x1 << 10)
302 #define RX_TPA_START_CMP_FLAGS_TIMESTAMP (0x1 << 11)
303 #define RX_TPA_START_CMP_FLAGS_ITYPES (0xf << 12)
304 #define RX_TPA_START_CMP_FLAGS_ITYPES_SHIFT 12
305 #define RX_TPA_START_CMP_FLAGS_ITYPE_TCP (0x2 << 12)
306 #define RX_TPA_START_CMP_LEN (0xffff << 16)
307 #define RX_TPA_START_CMP_LEN_SHIFT 16
308
309 u32 rx_tpa_start_cmp_opaque;
310 __le32 rx_tpa_start_cmp_misc_v1;
311 #define RX_TPA_START_CMP_V1 (0x1 << 0)
312 #define RX_TPA_START_CMP_RSS_HASH_TYPE (0x7f << 9)
313 #define RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT 9
314 #define RX_TPA_START_CMP_AGG_ID (0x7f << 25)
315 #define RX_TPA_START_CMP_AGG_ID_SHIFT 25
316 #define RX_TPA_START_CMP_AGG_ID_P5 (0xffff << 16)
317 #define RX_TPA_START_CMP_AGG_ID_SHIFT_P5 16
318
319 __le32 rx_tpa_start_cmp_rss_hash;
320};
321
322#define TPA_START_HASH_VALID(rx_tpa_start) \
323 ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type & \
324 cpu_to_le32(RX_TPA_START_CMP_FLAGS_RSS_VALID))
325
326#define TPA_START_HASH_TYPE(rx_tpa_start) \
327 (((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
328 RX_TPA_START_CMP_RSS_HASH_TYPE) >> \
329 RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
330
331#define TPA_START_AGG_ID(rx_tpa_start) \
332 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
333 RX_TPA_START_CMP_AGG_ID) >> RX_TPA_START_CMP_AGG_ID_SHIFT)
334
335#define TPA_START_AGG_ID_P5(rx_tpa_start) \
336 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
337 RX_TPA_START_CMP_AGG_ID_P5) >> RX_TPA_START_CMP_AGG_ID_SHIFT_P5)
338
339#define TPA_START_ERROR(rx_tpa_start) \
340 ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type & \
341 cpu_to_le32(RX_TPA_START_CMP_FLAGS_ERROR))
342
343struct rx_tpa_start_cmp_ext {
344 __le32 rx_tpa_start_cmp_flags2;
345 #define RX_TPA_START_CMP_FLAGS2_IP_CS_CALC (0x1 << 0)
346 #define RX_TPA_START_CMP_FLAGS2_L4_CS_CALC (0x1 << 1)
347 #define RX_TPA_START_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2)
348 #define RX_TPA_START_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3)
349 #define RX_TPA_START_CMP_FLAGS2_IP_TYPE (0x1 << 8)
350 #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_VALID (0x1 << 9)
351 #define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT (0x3 << 10)
352 #define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT_SHIFT 10
353 #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL (0xffff << 16)
354 #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_SHIFT 16
355
356 __le32 rx_tpa_start_cmp_metadata;
357 __le32 rx_tpa_start_cmp_cfa_code_v2;
358 #define RX_TPA_START_CMP_V2 (0x1 << 0)
359 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK (0x7 << 1)
360 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT 1
361 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)
362 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
363 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_FLUSH (0x5 << 1)
364 #define RX_TPA_START_CMP_CFA_CODE (0xffff << 16)
365 #define RX_TPA_START_CMPL_CFA_CODE_SHIFT 16
366 __le32 rx_tpa_start_cmp_hdr_info;
367};
368
369#define TPA_START_CFA_CODE(rx_tpa_start) \
370 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) & \
371 RX_TPA_START_CMP_CFA_CODE) >> RX_TPA_START_CMPL_CFA_CODE_SHIFT)
372
373#define TPA_START_IS_IPV6(rx_tpa_start) \
374 (!!((rx_tpa_start)->rx_tpa_start_cmp_flags2 & \
375 cpu_to_le32(RX_TPA_START_CMP_FLAGS2_IP_TYPE)))
376
377#define TPA_START_ERROR_CODE(rx_tpa_start) \
378 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) & \
379 RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK) >> \
380 RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT)
381
382struct rx_tpa_end_cmp {
383 __le32 rx_tpa_end_cmp_len_flags_type;
384 #define RX_TPA_END_CMP_TYPE (0x3f << 0)
385 #define RX_TPA_END_CMP_FLAGS (0x3ff << 6)
386 #define RX_TPA_END_CMP_FLAGS_SHIFT 6
387 #define RX_TPA_END_CMP_FLAGS_PLACEMENT (0x7 << 7)
388 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_SHIFT 7
389 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7)
390 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7)
391 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7)
392 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7)
393 #define RX_TPA_END_CMP_FLAGS_RSS_VALID (0x1 << 10)
394 #define RX_TPA_END_CMP_FLAGS_ITYPES (0xf << 12)
395 #define RX_TPA_END_CMP_FLAGS_ITYPES_SHIFT 12
396 #define RX_TPA_END_CMP_FLAGS_ITYPE_TCP (0x2 << 12)
397 #define RX_TPA_END_CMP_LEN (0xffff << 16)
398 #define RX_TPA_END_CMP_LEN_SHIFT 16
399
400 u32 rx_tpa_end_cmp_opaque;
401 __le32 rx_tpa_end_cmp_misc_v1;
402 #define RX_TPA_END_CMP_V1 (0x1 << 0)
403 #define RX_TPA_END_CMP_AGG_BUFS (0x3f << 1)
404 #define RX_TPA_END_CMP_AGG_BUFS_SHIFT 1
405 #define RX_TPA_END_CMP_TPA_SEGS (0xff << 8)
406 #define RX_TPA_END_CMP_TPA_SEGS_SHIFT 8
407 #define RX_TPA_END_CMP_PAYLOAD_OFFSET (0xff << 16)
408 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT 16
409 #define RX_TPA_END_CMP_AGG_ID (0x7f << 25)
410 #define RX_TPA_END_CMP_AGG_ID_SHIFT 25
411 #define RX_TPA_END_CMP_AGG_ID_P5 (0xffff << 16)
412 #define RX_TPA_END_CMP_AGG_ID_SHIFT_P5 16
413
414 __le32 rx_tpa_end_cmp_tsdelta;
415 #define RX_TPA_END_GRO_TS (0x1 << 31)
416};
417
418#define TPA_END_AGG_ID(rx_tpa_end) \
419 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
420 RX_TPA_END_CMP_AGG_ID) >> RX_TPA_END_CMP_AGG_ID_SHIFT)
421
422#define TPA_END_AGG_ID_P5(rx_tpa_end) \
423 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
424 RX_TPA_END_CMP_AGG_ID_P5) >> RX_TPA_END_CMP_AGG_ID_SHIFT_P5)
425
426#define TPA_END_PAYLOAD_OFF(rx_tpa_end) \
427 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
428 RX_TPA_END_CMP_PAYLOAD_OFFSET) >> RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT)
429
430#define TPA_END_AGG_BUFS(rx_tpa_end) \
431 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
432 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT)
433
434#define TPA_END_TPA_SEGS(rx_tpa_end) \
435 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
436 RX_TPA_END_CMP_TPA_SEGS) >> RX_TPA_END_CMP_TPA_SEGS_SHIFT)
437
438#define RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO \
439 cpu_to_le32(RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO & \
440 RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS)
441
442#define TPA_END_GRO(rx_tpa_end) \
443 ((rx_tpa_end)->rx_tpa_end_cmp_len_flags_type & \
444 RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO)
445
446#define TPA_END_GRO_TS(rx_tpa_end) \
447 (!!((rx_tpa_end)->rx_tpa_end_cmp_tsdelta & \
448 cpu_to_le32(RX_TPA_END_GRO_TS)))
449
450struct rx_tpa_end_cmp_ext {
451 __le32 rx_tpa_end_cmp_dup_acks;
452 #define RX_TPA_END_CMP_TPA_DUP_ACKS (0xf << 0)
453 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_P5 (0xff << 16)
454 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5 16
455 #define RX_TPA_END_CMP_AGG_BUFS_P5 (0xff << 24)
456 #define RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5 24
457
458 __le32 rx_tpa_end_cmp_seg_len;
459 #define RX_TPA_END_CMP_TPA_SEG_LEN (0xffff << 0)
460
461 __le32 rx_tpa_end_cmp_errors_v2;
462 #define RX_TPA_END_CMP_V2 (0x1 << 0)
463 #define RX_TPA_END_CMP_ERRORS (0x3 << 1)
464 #define RX_TPA_END_CMP_ERRORS_P5 (0x7 << 1)
465 #define RX_TPA_END_CMPL_ERRORS_SHIFT 1
466 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)
467 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2 << 1)
468 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
469 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_RSV_ERROR (0x4 << 1)
470 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_FLUSH (0x5 << 1)
471
472 u32 rx_tpa_end_cmp_start_opaque;
473};
474
475#define TPA_END_ERRORS(rx_tpa_end_ext) \
476 ((rx_tpa_end_ext)->rx_tpa_end_cmp_errors_v2 & \
477 cpu_to_le32(RX_TPA_END_CMP_ERRORS))
478
479#define TPA_END_PAYLOAD_OFF_P5(rx_tpa_end_ext) \
480 ((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) & \
481 RX_TPA_END_CMP_PAYLOAD_OFFSET_P5) >> \
482 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5)
483
484#define TPA_END_AGG_BUFS_P5(rx_tpa_end_ext) \
485 ((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) & \
486 RX_TPA_END_CMP_AGG_BUFS_P5) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5)
487
488#define EVENT_DATA1_RESET_NOTIFY_FATAL(data1) \
489 (((data1) & \
490 ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK) ==\
491 ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL)
492
493#define EVENT_DATA1_RESET_NOTIFY_FW_ACTIVATION(data1) \
494 (((data1) & \
495 ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK) ==\
496 ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION)
497
498#define EVENT_DATA2_RESET_NOTIFY_FW_STATUS_CODE(data2) \
499 ((data2) & \
500 ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK)
501
502#define EVENT_DATA1_RECOVERY_MASTER_FUNC(data1) \
503 !!((data1) & \
504 ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC)
505
506#define EVENT_DATA1_RECOVERY_ENABLED(data1) \
507 !!((data1) & \
508 ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED)
509
510#define BNXT_EVENT_ERROR_REPORT_TYPE(data1) \
511 (((data1) & \
512 ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK) >>\
513 ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT)
514
515#define BNXT_EVENT_INVALID_SIGNAL_DATA(data2) \
516 (((data2) & \
517 ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_MASK) >>\
518 ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_SFT)
519
520struct nqe_cn {
521 __le16 type;
522 #define NQ_CN_TYPE_MASK 0x3fUL
523 #define NQ_CN_TYPE_SFT 0
524 #define NQ_CN_TYPE_CQ_NOTIFICATION 0x30UL
525 #define NQ_CN_TYPE_LAST NQ_CN_TYPE_CQ_NOTIFICATION
526 __le16 reserved16;
527 __le32 cq_handle_low;
528 __le32 v;
529 #define NQ_CN_V 0x1UL
530 __le32 cq_handle_high;
531};
532
533#define DB_IDX_MASK 0xffffff
534#define DB_IDX_VALID (0x1 << 26)
535#define DB_IRQ_DIS (0x1 << 27)
536#define DB_KEY_TX (0x0 << 28)
537#define DB_KEY_RX (0x1 << 28)
538#define DB_KEY_CP (0x2 << 28)
539#define DB_KEY_ST (0x3 << 28)
540#define DB_KEY_TX_PUSH (0x4 << 28)
541#define DB_LONG_TX_PUSH (0x2 << 24)
542
543#define BNXT_MIN_ROCE_CP_RINGS 2
544#define BNXT_MIN_ROCE_STAT_CTXS 1
545
546/* 64-bit doorbell */
547#define DBR_INDEX_MASK 0x0000000000ffffffULL
548#define DBR_XID_MASK 0x000fffff00000000ULL
549#define DBR_XID_SFT 32
550#define DBR_PATH_L2 (0x1ULL << 56)
551#define DBR_TYPE_SQ (0x0ULL << 60)
552#define DBR_TYPE_RQ (0x1ULL << 60)
553#define DBR_TYPE_SRQ (0x2ULL << 60)
554#define DBR_TYPE_SRQ_ARM (0x3ULL << 60)
555#define DBR_TYPE_CQ (0x4ULL << 60)
556#define DBR_TYPE_CQ_ARMSE (0x5ULL << 60)
557#define DBR_TYPE_CQ_ARMALL (0x6ULL << 60)
558#define DBR_TYPE_CQ_ARMENA (0x7ULL << 60)
559#define DBR_TYPE_SRQ_ARMENA (0x8ULL << 60)
560#define DBR_TYPE_CQ_CUTOFF_ACK (0x9ULL << 60)
561#define DBR_TYPE_NQ (0xaULL << 60)
562#define DBR_TYPE_NQ_ARM (0xbULL << 60)
563#define DBR_TYPE_NULL (0xfULL << 60)
564
565#define DB_PF_OFFSET_P5 0x10000
566#define DB_VF_OFFSET_P5 0x4000
567
568#define INVALID_HW_RING_ID ((u16)-1)
569
570/* The hardware supports certain page sizes. Use the supported page sizes
571 * to allocate the rings.
572 */
573#if (PAGE_SHIFT < 12)
574#define BNXT_PAGE_SHIFT 12
575#elif (PAGE_SHIFT <= 13)
576#define BNXT_PAGE_SHIFT PAGE_SHIFT
577#elif (PAGE_SHIFT < 16)
578#define BNXT_PAGE_SHIFT 13
579#else
580#define BNXT_PAGE_SHIFT 16
581#endif
582
583#define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHIFT)
584
585/* The RXBD length is 16-bit so we can only support page sizes < 64K */
586#if (PAGE_SHIFT > 15)
587#define BNXT_RX_PAGE_SHIFT 15
588#else
589#define BNXT_RX_PAGE_SHIFT PAGE_SHIFT
590#endif
591
592#define BNXT_RX_PAGE_SIZE (1 << BNXT_RX_PAGE_SHIFT)
593
594#define BNXT_MAX_MTU 9500
595
596/* First RX buffer page in XDP multi-buf mode
597 *
598 * +-------------------------------------------------------------------------+
599 * | XDP_PACKET_HEADROOM | bp->rx_buf_use_size | skb_shared_info|
600 * | (bp->rx_dma_offset) | | |
601 * +-------------------------------------------------------------------------+
602 */
603#define BNXT_MAX_PAGE_MODE_MTU_SBUF \
604 ((unsigned int)PAGE_SIZE - VLAN_ETH_HLEN - NET_IP_ALIGN - \
605 XDP_PACKET_HEADROOM)
606#define BNXT_MAX_PAGE_MODE_MTU \
607 (BNXT_MAX_PAGE_MODE_MTU_SBUF - \
608 SKB_DATA_ALIGN((unsigned int)sizeof(struct skb_shared_info)))
609
610#define BNXT_MIN_PKT_SIZE 52
611
612#define BNXT_DEFAULT_RX_RING_SIZE 511
613#define BNXT_DEFAULT_TX_RING_SIZE 511
614
615#define MAX_TPA 64
616#define MAX_TPA_P5 256
617#define MAX_TPA_P5_MASK (MAX_TPA_P5 - 1)
618#define MAX_TPA_SEGS_P5 0x3f
619
620#if (BNXT_PAGE_SHIFT == 16)
621#define MAX_RX_PAGES_AGG_ENA 1
622#define MAX_RX_PAGES 4
623#define MAX_RX_AGG_PAGES 4
624#define MAX_TX_PAGES 1
625#define MAX_CP_PAGES 16
626#else
627#define MAX_RX_PAGES_AGG_ENA 8
628#define MAX_RX_PAGES 32
629#define MAX_RX_AGG_PAGES 32
630#define MAX_TX_PAGES 8
631#define MAX_CP_PAGES 128
632#endif
633
634#define RX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct rx_bd))
635#define TX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_bd))
636#define CP_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_cmp))
637
638#define SW_RXBD_RING_SIZE (sizeof(struct bnxt_sw_rx_bd) * RX_DESC_CNT)
639#define HW_RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT)
640
641#define SW_RXBD_AGG_RING_SIZE (sizeof(struct bnxt_sw_rx_agg_bd) * RX_DESC_CNT)
642
643#define SW_TXBD_RING_SIZE (sizeof(struct bnxt_sw_tx_bd) * TX_DESC_CNT)
644#define HW_TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT)
645
646#define HW_CMPD_RING_SIZE (sizeof(struct tx_cmp) * CP_DESC_CNT)
647
648#define BNXT_MAX_RX_DESC_CNT (RX_DESC_CNT * MAX_RX_PAGES - 1)
649#define BNXT_MAX_RX_DESC_CNT_JUM_ENA (RX_DESC_CNT * MAX_RX_PAGES_AGG_ENA - 1)
650#define BNXT_MAX_RX_JUM_DESC_CNT (RX_DESC_CNT * MAX_RX_AGG_PAGES - 1)
651#define BNXT_MAX_TX_DESC_CNT (TX_DESC_CNT * MAX_TX_PAGES - 1)
652
653/* Minimum TX BDs for a TX packet with MAX_SKB_FRAGS + 1. We need one extra
654 * BD because the first TX BD is always a long BD.
655 */
656#define BNXT_MIN_TX_DESC_CNT (MAX_SKB_FRAGS + 2)
657
658#define RX_RING(x) (((x) & ~(RX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
659#define RX_IDX(x) ((x) & (RX_DESC_CNT - 1))
660
661#define TX_RING(x) (((x) & ~(TX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
662#define TX_IDX(x) ((x) & (TX_DESC_CNT - 1))
663
664#define CP_RING(x) (((x) & ~(CP_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
665#define CP_IDX(x) ((x) & (CP_DESC_CNT - 1))
666
667#define TX_CMP_VALID(txcmp, raw_cons) \
668 (!!((txcmp)->tx_cmp_errors_v & cpu_to_le32(TX_CMP_V)) == \
669 !((raw_cons) & bp->cp_bit))
670
671#define RX_CMP_VALID(rxcmp1, raw_cons) \
672 (!!((rxcmp1)->rx_cmp_cfa_code_errors_v2 & cpu_to_le32(RX_CMP_V)) ==\
673 !((raw_cons) & bp->cp_bit))
674
675#define RX_AGG_CMP_VALID(agg, raw_cons) \
676 (!!((agg)->rx_agg_cmp_v & cpu_to_le32(RX_AGG_CMP_V)) == \
677 !((raw_cons) & bp->cp_bit))
678
679#define NQ_CMP_VALID(nqcmp, raw_cons) \
680 (!!((nqcmp)->v & cpu_to_le32(NQ_CN_V)) == !((raw_cons) & bp->cp_bit))
681
682#define TX_CMP_TYPE(txcmp) \
683 (le32_to_cpu((txcmp)->tx_cmp_flags_type) & CMP_TYPE)
684
685#define RX_CMP_TYPE(rxcmp) \
686 (le32_to_cpu((rxcmp)->rx_cmp_len_flags_type) & RX_CMP_CMP_TYPE)
687
688#define NEXT_RX(idx) (((idx) + 1) & bp->rx_ring_mask)
689
690#define NEXT_RX_AGG(idx) (((idx) + 1) & bp->rx_agg_ring_mask)
691
692#define NEXT_TX(idx) (((idx) + 1) & bp->tx_ring_mask)
693
694#define ADV_RAW_CMP(idx, n) ((idx) + (n))
695#define NEXT_RAW_CMP(idx) ADV_RAW_CMP(idx, 1)
696#define RING_CMP(idx) ((idx) & bp->cp_ring_mask)
697#define NEXT_CMP(idx) RING_CMP(ADV_RAW_CMP(idx, 1))
698
699#define DFLT_HWRM_CMD_TIMEOUT 500
700
701#define BNXT_RX_EVENT 1
702#define BNXT_AGG_EVENT 2
703#define BNXT_TX_EVENT 4
704#define BNXT_REDIRECT_EVENT 8
705
706struct bnxt_sw_tx_bd {
707 union {
708 struct sk_buff *skb;
709 struct xdp_frame *xdpf;
710 };
711 DEFINE_DMA_UNMAP_ADDR(mapping);
712 DEFINE_DMA_UNMAP_LEN(len);
713 struct page *page;
714 u8 is_gso;
715 u8 is_push;
716 u8 action;
717 unsigned short nr_frags;
718 u16 rx_prod;
719};
720
721struct bnxt_sw_rx_bd {
722 void *data;
723 u8 *data_ptr;
724 dma_addr_t mapping;
725};
726
727struct bnxt_sw_rx_agg_bd {
728 struct page *page;
729 unsigned int offset;
730 dma_addr_t mapping;
731};
732
733struct bnxt_mem_init {
734 u8 init_val;
735 u16 offset;
736#define BNXT_MEM_INVALID_OFFSET 0xffff
737 u16 size;
738};
739
740struct bnxt_ring_mem_info {
741 int nr_pages;
742 int page_size;
743 u16 flags;
744#define BNXT_RMEM_VALID_PTE_FLAG 1
745#define BNXT_RMEM_RING_PTE_FLAG 2
746#define BNXT_RMEM_USE_FULL_PAGE_FLAG 4
747
748 u16 depth;
749 struct bnxt_mem_init *mem_init;
750
751 void **pg_arr;
752 dma_addr_t *dma_arr;
753
754 __le64 *pg_tbl;
755 dma_addr_t pg_tbl_map;
756
757 int vmem_size;
758 void **vmem;
759};
760
761struct bnxt_ring_struct {
762 struct bnxt_ring_mem_info ring_mem;
763
764 u16 fw_ring_id; /* Ring id filled by Chimp FW */
765 union {
766 u16 grp_idx;
767 u16 map_idx; /* Used by cmpl rings */
768 };
769 u32 handle;
770 u8 queue_id;
771};
772
773struct tx_push_bd {
774 __le32 doorbell;
775 __le32 tx_bd_len_flags_type;
776 u32 tx_bd_opaque;
777 struct tx_bd_ext txbd2;
778};
779
780struct tx_push_buffer {
781 struct tx_push_bd push_bd;
782 u32 data[25];
783};
784
785struct bnxt_db_info {
786 void __iomem *doorbell;
787 union {
788 u64 db_key64;
789 u32 db_key32;
790 };
791};
792
793struct bnxt_tx_ring_info {
794 struct bnxt_napi *bnapi;
795 u16 tx_prod;
796 u16 tx_cons;
797 u16 txq_index;
798 u8 kick_pending;
799 struct bnxt_db_info tx_db;
800
801 struct tx_bd *tx_desc_ring[MAX_TX_PAGES];
802 struct bnxt_sw_tx_bd *tx_buf_ring;
803
804 dma_addr_t tx_desc_mapping[MAX_TX_PAGES];
805
806 struct tx_push_buffer *tx_push;
807 dma_addr_t tx_push_mapping;
808 __le64 data_mapping;
809
810#define BNXT_DEV_STATE_CLOSING 0x1
811 u32 dev_state;
812
813 struct bnxt_ring_struct tx_ring_struct;
814 /* Synchronize simultaneous xdp_xmit on same ring */
815 spinlock_t xdp_tx_lock;
816};
817
818#define BNXT_LEGACY_COAL_CMPL_PARAMS \
819 (RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN | \
820 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX | \
821 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET | \
822 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE | \
823 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR | \
824 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT | \
825 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR | \
826 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT | \
827 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT)
828
829#define BNXT_COAL_CMPL_ENABLES \
830 (RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR | \
831 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR | \
832 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX | \
833 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT)
834
835#define BNXT_COAL_CMPL_MIN_TMR_ENABLE \
836 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN
837
838#define BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE \
839 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT
840
841struct bnxt_coal_cap {
842 u32 cmpl_params;
843 u32 nq_params;
844 u16 num_cmpl_dma_aggr_max;
845 u16 num_cmpl_dma_aggr_during_int_max;
846 u16 cmpl_aggr_dma_tmr_max;
847 u16 cmpl_aggr_dma_tmr_during_int_max;
848 u16 int_lat_tmr_min_max;
849 u16 int_lat_tmr_max_max;
850 u16 num_cmpl_aggr_int_max;
851 u16 timer_units;
852};
853
854struct bnxt_coal {
855 u16 coal_ticks;
856 u16 coal_ticks_irq;
857 u16 coal_bufs;
858 u16 coal_bufs_irq;
859 /* RING_IDLE enabled when coal ticks < idle_thresh */
860 u16 idle_thresh;
861 u8 bufs_per_record;
862 u8 budget;
863 u16 flags;
864};
865
866struct bnxt_tpa_info {
867 void *data;
868 u8 *data_ptr;
869 dma_addr_t mapping;
870 u16 len;
871 unsigned short gso_type;
872 u32 flags2;
873 u32 metadata;
874 enum pkt_hash_types hash_type;
875 u32 rss_hash;
876 u32 hdr_info;
877
878#define BNXT_TPA_L4_SIZE(hdr_info) \
879 (((hdr_info) & 0xf8000000) ? ((hdr_info) >> 27) : 32)
880
881#define BNXT_TPA_INNER_L3_OFF(hdr_info) \
882 (((hdr_info) >> 18) & 0x1ff)
883
884#define BNXT_TPA_INNER_L2_OFF(hdr_info) \
885 (((hdr_info) >> 9) & 0x1ff)
886
887#define BNXT_TPA_OUTER_L3_OFF(hdr_info) \
888 ((hdr_info) & 0x1ff)
889
890 u16 cfa_code; /* cfa_code in TPA start compl */
891 u8 agg_count;
892 struct rx_agg_cmp *agg_arr;
893};
894
895#define BNXT_AGG_IDX_BMAP_SIZE (MAX_TPA_P5 / BITS_PER_LONG)
896
897struct bnxt_tpa_idx_map {
898 u16 agg_id_tbl[1024];
899 unsigned long agg_idx_bmap[BNXT_AGG_IDX_BMAP_SIZE];
900};
901
902struct bnxt_rx_ring_info {
903 struct bnxt_napi *bnapi;
904 u16 rx_prod;
905 u16 rx_agg_prod;
906 u16 rx_sw_agg_prod;
907 u16 rx_next_cons;
908 struct bnxt_db_info rx_db;
909 struct bnxt_db_info rx_agg_db;
910
911 struct bpf_prog *xdp_prog;
912
913 struct rx_bd *rx_desc_ring[MAX_RX_PAGES];
914 struct bnxt_sw_rx_bd *rx_buf_ring;
915
916 struct rx_bd *rx_agg_desc_ring[MAX_RX_AGG_PAGES];
917 struct bnxt_sw_rx_agg_bd *rx_agg_ring;
918
919 unsigned long *rx_agg_bmap;
920 u16 rx_agg_bmap_size;
921
922 dma_addr_t rx_desc_mapping[MAX_RX_PAGES];
923 dma_addr_t rx_agg_desc_mapping[MAX_RX_AGG_PAGES];
924
925 struct bnxt_tpa_info *rx_tpa;
926 struct bnxt_tpa_idx_map *rx_tpa_idx_map;
927
928 struct bnxt_ring_struct rx_ring_struct;
929 struct bnxt_ring_struct rx_agg_ring_struct;
930 struct xdp_rxq_info xdp_rxq;
931 struct page_pool *page_pool;
932};
933
934struct bnxt_rx_sw_stats {
935 u64 rx_l4_csum_errors;
936 u64 rx_resets;
937 u64 rx_buf_errors;
938 u64 rx_oom_discards;
939 u64 rx_netpoll_discards;
940};
941
942struct bnxt_tx_sw_stats {
943 u64 tx_resets;
944};
945
946struct bnxt_cmn_sw_stats {
947 u64 missed_irqs;
948};
949
950struct bnxt_sw_stats {
951 struct bnxt_rx_sw_stats rx;
952 struct bnxt_tx_sw_stats tx;
953 struct bnxt_cmn_sw_stats cmn;
954};
955
956struct bnxt_total_ring_err_stats {
957 u64 rx_total_l4_csum_errors;
958 u64 rx_total_resets;
959 u64 rx_total_buf_errors;
960 u64 rx_total_oom_discards;
961 u64 rx_total_netpoll_discards;
962 u64 rx_total_ring_discards;
963 u64 tx_total_resets;
964 u64 tx_total_ring_discards;
965 u64 total_missed_irqs;
966};
967
968struct bnxt_stats_mem {
969 u64 *sw_stats;
970 u64 *hw_masks;
971 void *hw_stats;
972 dma_addr_t hw_stats_map;
973 int len;
974};
975
976struct bnxt_cp_ring_info {
977 struct bnxt_napi *bnapi;
978 u32 cp_raw_cons;
979 struct bnxt_db_info cp_db;
980
981 u8 had_work_done:1;
982 u8 has_more_work:1;
983
984 u32 last_cp_raw_cons;
985
986 struct bnxt_coal rx_ring_coal;
987 u64 rx_packets;
988 u64 rx_bytes;
989 u64 event_ctr;
990
991 struct dim dim;
992
993 union {
994 struct tx_cmp **cp_desc_ring;
995 struct nqe_cn **nq_desc_ring;
996 };
997
998 dma_addr_t *cp_desc_mapping;
999
1000 struct bnxt_stats_mem stats;
1001 u32 hw_stats_ctx_id;
1002
1003 struct bnxt_sw_stats sw_stats;
1004
1005 struct bnxt_ring_struct cp_ring_struct;
1006
1007 struct bnxt_cp_ring_info *cp_ring_arr[2];
1008#define BNXT_RX_HDL 0
1009#define BNXT_TX_HDL 1
1010};
1011
1012struct bnxt_napi {
1013 struct napi_struct napi;
1014 struct bnxt *bp;
1015
1016 int index;
1017 struct bnxt_cp_ring_info cp_ring;
1018 struct bnxt_rx_ring_info *rx_ring;
1019 struct bnxt_tx_ring_info *tx_ring;
1020
1021 void (*tx_int)(struct bnxt *, struct bnxt_napi *,
1022 int budget);
1023 int tx_pkts;
1024 u8 events;
1025 u8 tx_fault:1;
1026
1027 u32 flags;
1028#define BNXT_NAPI_FLAG_XDP 0x1
1029
1030 bool in_reset;
1031};
1032
1033struct bnxt_irq {
1034 irq_handler_t handler;
1035 unsigned int vector;
1036 u8 requested:1;
1037 u8 have_cpumask:1;
1038 char name[IFNAMSIZ + 2];
1039 cpumask_var_t cpu_mask;
1040};
1041
1042#define HWRM_RING_ALLOC_TX 0x1
1043#define HWRM_RING_ALLOC_RX 0x2
1044#define HWRM_RING_ALLOC_AGG 0x4
1045#define HWRM_RING_ALLOC_CMPL 0x8
1046#define HWRM_RING_ALLOC_NQ 0x10
1047
1048#define INVALID_STATS_CTX_ID -1
1049
1050struct bnxt_ring_grp_info {
1051 u16 fw_stats_ctx;
1052 u16 fw_grp_id;
1053 u16 rx_fw_ring_id;
1054 u16 agg_fw_ring_id;
1055 u16 cp_fw_ring_id;
1056};
1057
1058struct bnxt_vnic_info {
1059 u16 fw_vnic_id; /* returned by Chimp during alloc */
1060#define BNXT_MAX_CTX_PER_VNIC 8
1061 u16 fw_rss_cos_lb_ctx[BNXT_MAX_CTX_PER_VNIC];
1062 u16 fw_l2_ctx_id;
1063#define BNXT_MAX_UC_ADDRS 4
1064 __le64 fw_l2_filter_id[BNXT_MAX_UC_ADDRS];
1065 /* index 0 always dev_addr */
1066 u16 uc_filter_count;
1067 u8 *uc_list;
1068
1069 u16 *fw_grp_ids;
1070 dma_addr_t rss_table_dma_addr;
1071 __le16 *rss_table;
1072 dma_addr_t rss_hash_key_dma_addr;
1073 u64 *rss_hash_key;
1074 int rss_table_size;
1075#define BNXT_RSS_TABLE_ENTRIES_P5 64
1076#define BNXT_RSS_TABLE_SIZE_P5 (BNXT_RSS_TABLE_ENTRIES_P5 * 4)
1077#define BNXT_RSS_TABLE_MAX_TBL_P5 8
1078#define BNXT_MAX_RSS_TABLE_SIZE_P5 \
1079 (BNXT_RSS_TABLE_SIZE_P5 * BNXT_RSS_TABLE_MAX_TBL_P5)
1080#define BNXT_MAX_RSS_TABLE_ENTRIES_P5 \
1081 (BNXT_RSS_TABLE_ENTRIES_P5 * BNXT_RSS_TABLE_MAX_TBL_P5)
1082
1083 u32 rx_mask;
1084
1085 u8 *mc_list;
1086 int mc_list_size;
1087 int mc_list_count;
1088 dma_addr_t mc_list_mapping;
1089#define BNXT_MAX_MC_ADDRS 16
1090
1091 u32 flags;
1092#define BNXT_VNIC_RSS_FLAG 1
1093#define BNXT_VNIC_RFS_FLAG 2
1094#define BNXT_VNIC_MCAST_FLAG 4
1095#define BNXT_VNIC_UCAST_FLAG 8
1096#define BNXT_VNIC_RFS_NEW_RSS_FLAG 0x10
1097};
1098
1099struct bnxt_hw_resc {
1100 u16 min_rsscos_ctxs;
1101 u16 max_rsscos_ctxs;
1102 u16 min_cp_rings;
1103 u16 max_cp_rings;
1104 u16 resv_cp_rings;
1105 u16 min_tx_rings;
1106 u16 max_tx_rings;
1107 u16 resv_tx_rings;
1108 u16 max_tx_sch_inputs;
1109 u16 min_rx_rings;
1110 u16 max_rx_rings;
1111 u16 resv_rx_rings;
1112 u16 min_hw_ring_grps;
1113 u16 max_hw_ring_grps;
1114 u16 resv_hw_ring_grps;
1115 u16 min_l2_ctxs;
1116 u16 max_l2_ctxs;
1117 u16 min_vnics;
1118 u16 max_vnics;
1119 u16 resv_vnics;
1120 u16 min_stat_ctxs;
1121 u16 max_stat_ctxs;
1122 u16 resv_stat_ctxs;
1123 u16 max_nqs;
1124 u16 max_irqs;
1125 u16 resv_irqs;
1126};
1127
1128#if defined(CONFIG_BNXT_SRIOV)
1129struct bnxt_vf_info {
1130 u16 fw_fid;
1131 u8 mac_addr[ETH_ALEN]; /* PF assigned MAC Address */
1132 u8 vf_mac_addr[ETH_ALEN]; /* VF assigned MAC address, only
1133 * stored by PF.
1134 */
1135 u16 vlan;
1136 u16 func_qcfg_flags;
1137 u32 flags;
1138#define BNXT_VF_QOS 0x1
1139#define BNXT_VF_SPOOFCHK 0x2
1140#define BNXT_VF_LINK_FORCED 0x4
1141#define BNXT_VF_LINK_UP 0x8
1142#define BNXT_VF_TRUST 0x10
1143 u32 min_tx_rate;
1144 u32 max_tx_rate;
1145 void *hwrm_cmd_req_addr;
1146 dma_addr_t hwrm_cmd_req_dma_addr;
1147};
1148#endif
1149
1150struct bnxt_pf_info {
1151#define BNXT_FIRST_PF_FID 1
1152#define BNXT_FIRST_VF_FID 128
1153 u16 fw_fid;
1154 u16 port_id;
1155 u8 mac_addr[ETH_ALEN];
1156 u32 first_vf_id;
1157 u16 active_vfs;
1158 u16 registered_vfs;
1159 u16 max_vfs;
1160 u32 max_encap_records;
1161 u32 max_decap_records;
1162 u32 max_tx_em_flows;
1163 u32 max_tx_wm_flows;
1164 u32 max_rx_em_flows;
1165 u32 max_rx_wm_flows;
1166 unsigned long *vf_event_bmap;
1167 u16 hwrm_cmd_req_pages;
1168 u8 vf_resv_strategy;
1169#define BNXT_VF_RESV_STRATEGY_MAXIMAL 0
1170#define BNXT_VF_RESV_STRATEGY_MINIMAL 1
1171#define BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC 2
1172 void *hwrm_cmd_req_addr[4];
1173 dma_addr_t hwrm_cmd_req_dma_addr[4];
1174 struct bnxt_vf_info *vf;
1175};
1176
1177struct bnxt_ntuple_filter {
1178 struct hlist_node hash;
1179 u8 dst_mac_addr[ETH_ALEN];
1180 u8 src_mac_addr[ETH_ALEN];
1181 struct flow_keys fkeys;
1182 __le64 filter_id;
1183 u16 sw_id;
1184 u8 l2_fltr_idx;
1185 u16 rxq;
1186 u32 flow_id;
1187 unsigned long state;
1188#define BNXT_FLTR_VALID 0
1189#define BNXT_FLTR_UPDATE 1
1190};
1191
1192struct bnxt_link_info {
1193 u8 phy_type;
1194 u8 media_type;
1195 u8 transceiver;
1196 u8 phy_addr;
1197 u8 phy_link_status;
1198#define BNXT_LINK_NO_LINK PORT_PHY_QCFG_RESP_LINK_NO_LINK
1199#define BNXT_LINK_SIGNAL PORT_PHY_QCFG_RESP_LINK_SIGNAL
1200#define BNXT_LINK_LINK PORT_PHY_QCFG_RESP_LINK_LINK
1201 u8 wire_speed;
1202 u8 phy_state;
1203#define BNXT_PHY_STATE_ENABLED 0
1204#define BNXT_PHY_STATE_DISABLED 1
1205
1206 u8 link_state;
1207#define BNXT_LINK_STATE_UNKNOWN 0
1208#define BNXT_LINK_STATE_DOWN 1
1209#define BNXT_LINK_STATE_UP 2
1210#define BNXT_LINK_IS_UP(bp) ((bp)->link_info.link_state == BNXT_LINK_STATE_UP)
1211 u8 duplex;
1212#define BNXT_LINK_DUPLEX_HALF PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF
1213#define BNXT_LINK_DUPLEX_FULL PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL
1214 u8 pause;
1215#define BNXT_LINK_PAUSE_TX PORT_PHY_QCFG_RESP_PAUSE_TX
1216#define BNXT_LINK_PAUSE_RX PORT_PHY_QCFG_RESP_PAUSE_RX
1217#define BNXT_LINK_PAUSE_BOTH (PORT_PHY_QCFG_RESP_PAUSE_RX | \
1218 PORT_PHY_QCFG_RESP_PAUSE_TX)
1219 u8 lp_pause;
1220 u8 auto_pause_setting;
1221 u8 force_pause_setting;
1222 u8 duplex_setting;
1223 u8 auto_mode;
1224#define BNXT_AUTO_MODE(mode) ((mode) > BNXT_LINK_AUTO_NONE && \
1225 (mode) <= BNXT_LINK_AUTO_MSK)
1226#define BNXT_LINK_AUTO_NONE PORT_PHY_QCFG_RESP_AUTO_MODE_NONE
1227#define BNXT_LINK_AUTO_ALLSPDS PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS
1228#define BNXT_LINK_AUTO_ONESPD PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED
1229#define BNXT_LINK_AUTO_ONEORBELOW PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW
1230#define BNXT_LINK_AUTO_MSK PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK
1231#define PHY_VER_LEN 3
1232 u8 phy_ver[PHY_VER_LEN];
1233 u16 link_speed;
1234#define BNXT_LINK_SPEED_100MB PORT_PHY_QCFG_RESP_LINK_SPEED_100MB
1235#define BNXT_LINK_SPEED_1GB PORT_PHY_QCFG_RESP_LINK_SPEED_1GB
1236#define BNXT_LINK_SPEED_2GB PORT_PHY_QCFG_RESP_LINK_SPEED_2GB
1237#define BNXT_LINK_SPEED_2_5GB PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB
1238#define BNXT_LINK_SPEED_10GB PORT_PHY_QCFG_RESP_LINK_SPEED_10GB
1239#define BNXT_LINK_SPEED_20GB PORT_PHY_QCFG_RESP_LINK_SPEED_20GB
1240#define BNXT_LINK_SPEED_25GB PORT_PHY_QCFG_RESP_LINK_SPEED_25GB
1241#define BNXT_LINK_SPEED_40GB PORT_PHY_QCFG_RESP_LINK_SPEED_40GB
1242#define BNXT_LINK_SPEED_50GB PORT_PHY_QCFG_RESP_LINK_SPEED_50GB
1243#define BNXT_LINK_SPEED_100GB PORT_PHY_QCFG_RESP_LINK_SPEED_100GB
1244#define BNXT_LINK_SPEED_200GB PORT_PHY_QCFG_RESP_LINK_SPEED_200GB
1245 u16 support_speeds;
1246 u16 support_pam4_speeds;
1247 u16 auto_link_speeds; /* fw adv setting */
1248#define BNXT_LINK_SPEED_MSK_100MB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB
1249#define BNXT_LINK_SPEED_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB
1250#define BNXT_LINK_SPEED_MSK_2GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB
1251#define BNXT_LINK_SPEED_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB
1252#define BNXT_LINK_SPEED_MSK_2_5GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB
1253#define BNXT_LINK_SPEED_MSK_20GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB
1254#define BNXT_LINK_SPEED_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB
1255#define BNXT_LINK_SPEED_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB
1256#define BNXT_LINK_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB
1257#define BNXT_LINK_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB
1258 u16 auto_pam4_link_speeds;
1259#define BNXT_LINK_PAM4_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G
1260#define BNXT_LINK_PAM4_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G
1261#define BNXT_LINK_PAM4_SPEED_MSK_200GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G
1262 u16 support_auto_speeds;
1263 u16 support_pam4_auto_speeds;
1264 u16 lp_auto_link_speeds;
1265 u16 lp_auto_pam4_link_speeds;
1266 u16 force_link_speed;
1267 u16 force_pam4_link_speed;
1268 u32 preemphasis;
1269 u8 module_status;
1270 u8 active_fec_sig_mode;
1271 u16 fec_cfg;
1272#define BNXT_FEC_NONE PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED
1273#define BNXT_FEC_AUTONEG_CAP PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED
1274#define BNXT_FEC_AUTONEG PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED
1275#define BNXT_FEC_ENC_BASE_R_CAP \
1276 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED
1277#define BNXT_FEC_ENC_BASE_R PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED
1278#define BNXT_FEC_ENC_RS_CAP \
1279 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED
1280#define BNXT_FEC_ENC_LLRS_CAP \
1281 (PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_SUPPORTED | \
1282 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_SUPPORTED)
1283#define BNXT_FEC_ENC_RS \
1284 (PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED | \
1285 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_ENABLED | \
1286 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_ENABLED)
1287#define BNXT_FEC_ENC_LLRS \
1288 (PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_ENABLED | \
1289 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_ENABLED)
1290
1291 /* copy of requested setting from ethtool cmd */
1292 u8 autoneg;
1293#define BNXT_AUTONEG_SPEED 1
1294#define BNXT_AUTONEG_FLOW_CTRL 2
1295 u8 req_signal_mode;
1296#define BNXT_SIG_MODE_NRZ PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ
1297#define BNXT_SIG_MODE_PAM4 PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4
1298#define BNXT_SIG_MODE_MAX (PORT_PHY_QCFG_RESP_SIGNAL_MODE_LAST + 1)
1299 u8 req_duplex;
1300 u8 req_flow_ctrl;
1301 u16 req_link_speed;
1302 u16 advertising; /* user adv setting */
1303 u16 advertising_pam4;
1304 bool force_link_chng;
1305
1306 bool phy_retry;
1307 unsigned long phy_retry_expires;
1308
1309 /* a copy of phy_qcfg output used to report link
1310 * info to VF
1311 */
1312 struct hwrm_port_phy_qcfg_output phy_qcfg_resp;
1313};
1314
1315#define BNXT_FEC_RS544_ON \
1316 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_ENABLE | \
1317 PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_ENABLE)
1318
1319#define BNXT_FEC_RS544_OFF \
1320 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_DISABLE | \
1321 PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_DISABLE)
1322
1323#define BNXT_FEC_RS272_ON \
1324 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_ENABLE | \
1325 PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_ENABLE)
1326
1327#define BNXT_FEC_RS272_OFF \
1328 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_DISABLE | \
1329 PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_DISABLE)
1330
1331#define BNXT_PAM4_SUPPORTED(link_info) \
1332 ((link_info)->support_pam4_speeds)
1333
1334#define BNXT_FEC_RS_ON(link_info) \
1335 (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE | \
1336 PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE | \
1337 (BNXT_PAM4_SUPPORTED(link_info) ? \
1338 (BNXT_FEC_RS544_ON | BNXT_FEC_RS272_OFF) : 0))
1339
1340#define BNXT_FEC_LLRS_ON \
1341 (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE | \
1342 PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE | \
1343 BNXT_FEC_RS272_ON | BNXT_FEC_RS544_OFF)
1344
1345#define BNXT_FEC_RS_OFF(link_info) \
1346 (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE | \
1347 (BNXT_PAM4_SUPPORTED(link_info) ? \
1348 (BNXT_FEC_RS544_OFF | BNXT_FEC_RS272_OFF) : 0))
1349
1350#define BNXT_FEC_BASE_R_ON(link_info) \
1351 (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE | \
1352 BNXT_FEC_RS_OFF(link_info))
1353
1354#define BNXT_FEC_ALL_OFF(link_info) \
1355 (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE | \
1356 BNXT_FEC_RS_OFF(link_info))
1357
1358#define BNXT_MAX_QUEUE 8
1359
1360struct bnxt_queue_info {
1361 u8 queue_id;
1362 u8 queue_profile;
1363};
1364
1365#define BNXT_MAX_LED 4
1366
1367struct bnxt_led_info {
1368 u8 led_id;
1369 u8 led_type;
1370 u8 led_group_id;
1371 u8 unused;
1372 __le16 led_state_caps;
1373#define BNXT_LED_ALT_BLINK_CAP(x) ((x) & \
1374 cpu_to_le16(PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED))
1375
1376 __le16 led_color_caps;
1377};
1378
1379#define BNXT_MAX_TEST 8
1380
1381struct bnxt_test_info {
1382 u8 offline_mask;
1383 u16 timeout;
1384 char string[BNXT_MAX_TEST][ETH_GSTRING_LEN];
1385};
1386
1387#define CHIMP_REG_VIEW_ADDR \
1388 ((bp->flags & BNXT_FLAG_CHIP_P5) ? 0x80000000 : 0xb1000000)
1389
1390#define BNXT_GRCPF_REG_CHIMP_COMM 0x0
1391#define BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER 0x100
1392#define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400
1393#define BNXT_CAG_REG_LEGACY_INT_STATUS 0x4014
1394#define BNXT_CAG_REG_BASE 0x300000
1395
1396#define BNXT_GRC_REG_STATUS_P5 0x520
1397
1398#define BNXT_GRCPF_REG_KONG_COMM 0xA00
1399#define BNXT_GRCPF_REG_KONG_COMM_TRIGGER 0xB00
1400
1401#define BNXT_GRC_REG_CHIP_NUM 0x48
1402#define BNXT_GRC_REG_BASE 0x260000
1403
1404#define BNXT_TS_REG_TIMESYNC_TS0_LOWER 0x640180c
1405#define BNXT_TS_REG_TIMESYNC_TS0_UPPER 0x6401810
1406
1407#define BNXT_GRC_BASE_MASK 0xfffff000
1408#define BNXT_GRC_OFFSET_MASK 0x00000ffc
1409
1410struct bnxt_tc_flow_stats {
1411 u64 packets;
1412 u64 bytes;
1413};
1414
1415#ifdef CONFIG_BNXT_FLOWER_OFFLOAD
1416struct bnxt_flower_indr_block_cb_priv {
1417 struct net_device *tunnel_netdev;
1418 struct bnxt *bp;
1419 struct list_head list;
1420};
1421#endif
1422
1423struct bnxt_tc_info {
1424 bool enabled;
1425
1426 /* hash table to store TC offloaded flows */
1427 struct rhashtable flow_table;
1428 struct rhashtable_params flow_ht_params;
1429
1430 /* hash table to store L2 keys of TC flows */
1431 struct rhashtable l2_table;
1432 struct rhashtable_params l2_ht_params;
1433 /* hash table to store L2 keys for TC tunnel decap */
1434 struct rhashtable decap_l2_table;
1435 struct rhashtable_params decap_l2_ht_params;
1436 /* hash table to store tunnel decap entries */
1437 struct rhashtable decap_table;
1438 struct rhashtable_params decap_ht_params;
1439 /* hash table to store tunnel encap entries */
1440 struct rhashtable encap_table;
1441 struct rhashtable_params encap_ht_params;
1442
1443 /* lock to atomically add/del an l2 node when a flow is
1444 * added or deleted.
1445 */
1446 struct mutex lock;
1447
1448 /* Fields used for batching stats query */
1449 struct rhashtable_iter iter;
1450#define BNXT_FLOW_STATS_BATCH_MAX 10
1451 struct bnxt_tc_stats_batch {
1452 void *flow_node;
1453 struct bnxt_tc_flow_stats hw_stats;
1454 } stats_batch[BNXT_FLOW_STATS_BATCH_MAX];
1455
1456 /* Stat counter mask (width) */
1457 u64 bytes_mask;
1458 u64 packets_mask;
1459};
1460
1461struct bnxt_vf_rep_stats {
1462 u64 packets;
1463 u64 bytes;
1464 u64 dropped;
1465};
1466
1467struct bnxt_vf_rep {
1468 struct bnxt *bp;
1469 struct net_device *dev;
1470 struct metadata_dst *dst;
1471 u16 vf_idx;
1472 u16 tx_cfa_action;
1473 u16 rx_cfa_code;
1474
1475 struct bnxt_vf_rep_stats rx_stats;
1476 struct bnxt_vf_rep_stats tx_stats;
1477};
1478
1479#define PTU_PTE_VALID 0x1UL
1480#define PTU_PTE_LAST 0x2UL
1481#define PTU_PTE_NEXT_TO_LAST 0x4UL
1482
1483#define MAX_CTX_PAGES (BNXT_PAGE_SIZE / 8)
1484#define MAX_CTX_TOTAL_PAGES (MAX_CTX_PAGES * MAX_CTX_PAGES)
1485
1486struct bnxt_ctx_pg_info {
1487 u32 entries;
1488 u32 nr_pages;
1489 void *ctx_pg_arr[MAX_CTX_PAGES];
1490 dma_addr_t ctx_dma_arr[MAX_CTX_PAGES];
1491 struct bnxt_ring_mem_info ring_mem;
1492 struct bnxt_ctx_pg_info **ctx_pg_tbl;
1493};
1494
1495#define BNXT_MAX_TQM_SP_RINGS 1
1496#define BNXT_MAX_TQM_FP_RINGS 8
1497#define BNXT_MAX_TQM_RINGS \
1498 (BNXT_MAX_TQM_SP_RINGS + BNXT_MAX_TQM_FP_RINGS)
1499
1500#define BNXT_BACKING_STORE_CFG_LEGACY_LEN 256
1501
1502#define BNXT_SET_CTX_PAGE_ATTR(attr) \
1503do { \
1504 if (BNXT_PAGE_SIZE == 0x2000) \
1505 attr = FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K; \
1506 else if (BNXT_PAGE_SIZE == 0x10000) \
1507 attr = FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K; \
1508 else \
1509 attr = FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K; \
1510} while (0)
1511
1512struct bnxt_ctx_mem_info {
1513 u32 qp_max_entries;
1514 u16 qp_min_qp1_entries;
1515 u16 qp_max_l2_entries;
1516 u16 qp_entry_size;
1517 u16 srq_max_l2_entries;
1518 u32 srq_max_entries;
1519 u16 srq_entry_size;
1520 u16 cq_max_l2_entries;
1521 u32 cq_max_entries;
1522 u16 cq_entry_size;
1523 u16 vnic_max_vnic_entries;
1524 u16 vnic_max_ring_table_entries;
1525 u16 vnic_entry_size;
1526 u32 stat_max_entries;
1527 u16 stat_entry_size;
1528 u16 tqm_entry_size;
1529 u32 tqm_min_entries_per_ring;
1530 u32 tqm_max_entries_per_ring;
1531 u32 mrav_max_entries;
1532 u16 mrav_entry_size;
1533 u16 tim_entry_size;
1534 u32 tim_max_entries;
1535 u16 mrav_num_entries_units;
1536 u8 tqm_entries_multiple;
1537 u8 tqm_fp_rings_count;
1538
1539 u32 flags;
1540 #define BNXT_CTX_FLAG_INITED 0x01
1541
1542 struct bnxt_ctx_pg_info qp_mem;
1543 struct bnxt_ctx_pg_info srq_mem;
1544 struct bnxt_ctx_pg_info cq_mem;
1545 struct bnxt_ctx_pg_info vnic_mem;
1546 struct bnxt_ctx_pg_info stat_mem;
1547 struct bnxt_ctx_pg_info mrav_mem;
1548 struct bnxt_ctx_pg_info tim_mem;
1549 struct bnxt_ctx_pg_info *tqm_mem[BNXT_MAX_TQM_RINGS];
1550
1551#define BNXT_CTX_MEM_INIT_QP 0
1552#define BNXT_CTX_MEM_INIT_SRQ 1
1553#define BNXT_CTX_MEM_INIT_CQ 2
1554#define BNXT_CTX_MEM_INIT_VNIC 3
1555#define BNXT_CTX_MEM_INIT_STAT 4
1556#define BNXT_CTX_MEM_INIT_MRAV 5
1557#define BNXT_CTX_MEM_INIT_MAX 6
1558 struct bnxt_mem_init mem_init[BNXT_CTX_MEM_INIT_MAX];
1559};
1560
1561enum bnxt_health_severity {
1562 SEVERITY_NORMAL = 0,
1563 SEVERITY_WARNING,
1564 SEVERITY_RECOVERABLE,
1565 SEVERITY_FATAL,
1566};
1567
1568enum bnxt_health_remedy {
1569 REMEDY_DEVLINK_RECOVER,
1570 REMEDY_POWER_CYCLE_DEVICE,
1571 REMEDY_POWER_CYCLE_HOST,
1572 REMEDY_FW_UPDATE,
1573 REMEDY_HW_REPLACE,
1574};
1575
1576struct bnxt_fw_health {
1577 u32 flags;
1578 u32 polling_dsecs;
1579 u32 master_func_wait_dsecs;
1580 u32 normal_func_wait_dsecs;
1581 u32 post_reset_wait_dsecs;
1582 u32 post_reset_max_wait_dsecs;
1583 u32 regs[4];
1584 u32 mapped_regs[4];
1585#define BNXT_FW_HEALTH_REG 0
1586#define BNXT_FW_HEARTBEAT_REG 1
1587#define BNXT_FW_RESET_CNT_REG 2
1588#define BNXT_FW_RESET_INPROG_REG 3
1589 u32 fw_reset_inprog_reg_mask;
1590 u32 last_fw_heartbeat;
1591 u32 last_fw_reset_cnt;
1592 u8 enabled:1;
1593 u8 primary:1;
1594 u8 status_reliable:1;
1595 u8 resets_reliable:1;
1596 u8 tmr_multiplier;
1597 u8 tmr_counter;
1598 u8 fw_reset_seq_cnt;
1599 u32 fw_reset_seq_regs[16];
1600 u32 fw_reset_seq_vals[16];
1601 u32 fw_reset_seq_delay_msec[16];
1602 u32 echo_req_data1;
1603 u32 echo_req_data2;
1604 struct devlink_health_reporter *fw_reporter;
1605 /* Protects severity and remedy */
1606 struct mutex lock;
1607 enum bnxt_health_severity severity;
1608 enum bnxt_health_remedy remedy;
1609 u32 arrests;
1610 u32 discoveries;
1611 u32 survivals;
1612 u32 fatalities;
1613 u32 diagnoses;
1614};
1615
1616#define BNXT_FW_HEALTH_REG_TYPE_MASK 3
1617#define BNXT_FW_HEALTH_REG_TYPE_CFG 0
1618#define BNXT_FW_HEALTH_REG_TYPE_GRC 1
1619#define BNXT_FW_HEALTH_REG_TYPE_BAR0 2
1620#define BNXT_FW_HEALTH_REG_TYPE_BAR1 3
1621
1622#define BNXT_FW_HEALTH_REG_TYPE(reg) ((reg) & BNXT_FW_HEALTH_REG_TYPE_MASK)
1623#define BNXT_FW_HEALTH_REG_OFF(reg) ((reg) & ~BNXT_FW_HEALTH_REG_TYPE_MASK)
1624
1625#define BNXT_FW_HEALTH_WIN_BASE 0x3000
1626#define BNXT_FW_HEALTH_WIN_MAP_OFF 8
1627
1628#define BNXT_FW_HEALTH_WIN_OFF(reg) (BNXT_FW_HEALTH_WIN_BASE + \
1629 ((reg) & BNXT_GRC_OFFSET_MASK))
1630
1631#define BNXT_FW_STATUS_HEALTH_MSK 0xffff
1632#define BNXT_FW_STATUS_HEALTHY 0x8000
1633#define BNXT_FW_STATUS_SHUTDOWN 0x100000
1634#define BNXT_FW_STATUS_RECOVERING 0x400000
1635
1636#define BNXT_FW_IS_HEALTHY(sts) (((sts) & BNXT_FW_STATUS_HEALTH_MSK) ==\
1637 BNXT_FW_STATUS_HEALTHY)
1638
1639#define BNXT_FW_IS_BOOTING(sts) (((sts) & BNXT_FW_STATUS_HEALTH_MSK) < \
1640 BNXT_FW_STATUS_HEALTHY)
1641
1642#define BNXT_FW_IS_ERR(sts) (((sts) & BNXT_FW_STATUS_HEALTH_MSK) > \
1643 BNXT_FW_STATUS_HEALTHY)
1644
1645#define BNXT_FW_IS_RECOVERING(sts) (BNXT_FW_IS_ERR(sts) && \
1646 ((sts) & BNXT_FW_STATUS_RECOVERING))
1647
1648#define BNXT_FW_RETRY 5
1649#define BNXT_FW_IF_RETRY 10
1650#define BNXT_FW_SLOT_RESET_RETRY 4
1651
1652struct bnxt_aux_priv {
1653 struct auxiliary_device aux_dev;
1654 struct bnxt_en_dev *edev;
1655 int id;
1656};
1657
1658enum board_idx {
1659 BCM57301,
1660 BCM57302,
1661 BCM57304,
1662 BCM57417_NPAR,
1663 BCM58700,
1664 BCM57311,
1665 BCM57312,
1666 BCM57402,
1667 BCM57404,
1668 BCM57406,
1669 BCM57402_NPAR,
1670 BCM57407,
1671 BCM57412,
1672 BCM57414,
1673 BCM57416,
1674 BCM57417,
1675 BCM57412_NPAR,
1676 BCM57314,
1677 BCM57417_SFP,
1678 BCM57416_SFP,
1679 BCM57404_NPAR,
1680 BCM57406_NPAR,
1681 BCM57407_SFP,
1682 BCM57407_NPAR,
1683 BCM57414_NPAR,
1684 BCM57416_NPAR,
1685 BCM57452,
1686 BCM57454,
1687 BCM5745x_NPAR,
1688 BCM57508,
1689 BCM57504,
1690 BCM57502,
1691 BCM57508_NPAR,
1692 BCM57504_NPAR,
1693 BCM57502_NPAR,
1694 BCM58802,
1695 BCM58804,
1696 BCM58808,
1697 NETXTREME_E_VF,
1698 NETXTREME_C_VF,
1699 NETXTREME_S_VF,
1700 NETXTREME_C_VF_HV,
1701 NETXTREME_E_VF_HV,
1702 NETXTREME_E_P5_VF,
1703 NETXTREME_E_P5_VF_HV,
1704};
1705
1706struct bnxt {
1707 void __iomem *bar0;
1708 void __iomem *bar1;
1709 void __iomem *bar2;
1710
1711 u32 reg_base;
1712 u16 chip_num;
1713#define CHIP_NUM_57301 0x16c8
1714#define CHIP_NUM_57302 0x16c9
1715#define CHIP_NUM_57304 0x16ca
1716#define CHIP_NUM_58700 0x16cd
1717#define CHIP_NUM_57402 0x16d0
1718#define CHIP_NUM_57404 0x16d1
1719#define CHIP_NUM_57406 0x16d2
1720#define CHIP_NUM_57407 0x16d5
1721
1722#define CHIP_NUM_57311 0x16ce
1723#define CHIP_NUM_57312 0x16cf
1724#define CHIP_NUM_57314 0x16df
1725#define CHIP_NUM_57317 0x16e0
1726#define CHIP_NUM_57412 0x16d6
1727#define CHIP_NUM_57414 0x16d7
1728#define CHIP_NUM_57416 0x16d8
1729#define CHIP_NUM_57417 0x16d9
1730#define CHIP_NUM_57412L 0x16da
1731#define CHIP_NUM_57414L 0x16db
1732
1733#define CHIP_NUM_5745X 0xd730
1734#define CHIP_NUM_57452 0xc452
1735#define CHIP_NUM_57454 0xc454
1736
1737#define CHIP_NUM_57508 0x1750
1738#define CHIP_NUM_57504 0x1751
1739#define CHIP_NUM_57502 0x1752
1740
1741#define CHIP_NUM_58802 0xd802
1742#define CHIP_NUM_58804 0xd804
1743#define CHIP_NUM_58808 0xd808
1744
1745 u8 chip_rev;
1746
1747#define CHIP_NUM_58818 0xd818
1748
1749#define BNXT_CHIP_NUM_5730X(chip_num) \
1750 ((chip_num) >= CHIP_NUM_57301 && \
1751 (chip_num) <= CHIP_NUM_57304)
1752
1753#define BNXT_CHIP_NUM_5740X(chip_num) \
1754 (((chip_num) >= CHIP_NUM_57402 && \
1755 (chip_num) <= CHIP_NUM_57406) || \
1756 (chip_num) == CHIP_NUM_57407)
1757
1758#define BNXT_CHIP_NUM_5731X(chip_num) \
1759 ((chip_num) == CHIP_NUM_57311 || \
1760 (chip_num) == CHIP_NUM_57312 || \
1761 (chip_num) == CHIP_NUM_57314 || \
1762 (chip_num) == CHIP_NUM_57317)
1763
1764#define BNXT_CHIP_NUM_5741X(chip_num) \
1765 ((chip_num) >= CHIP_NUM_57412 && \
1766 (chip_num) <= CHIP_NUM_57414L)
1767
1768#define BNXT_CHIP_NUM_58700(chip_num) \
1769 ((chip_num) == CHIP_NUM_58700)
1770
1771#define BNXT_CHIP_NUM_5745X(chip_num) \
1772 ((chip_num) == CHIP_NUM_5745X || \
1773 (chip_num) == CHIP_NUM_57452 || \
1774 (chip_num) == CHIP_NUM_57454)
1775
1776
1777#define BNXT_CHIP_NUM_57X0X(chip_num) \
1778 (BNXT_CHIP_NUM_5730X(chip_num) || BNXT_CHIP_NUM_5740X(chip_num))
1779
1780#define BNXT_CHIP_NUM_57X1X(chip_num) \
1781 (BNXT_CHIP_NUM_5731X(chip_num) || BNXT_CHIP_NUM_5741X(chip_num))
1782
1783#define BNXT_CHIP_NUM_588XX(chip_num) \
1784 ((chip_num) == CHIP_NUM_58802 || \
1785 (chip_num) == CHIP_NUM_58804 || \
1786 (chip_num) == CHIP_NUM_58808)
1787
1788#define BNXT_VPD_FLD_LEN 32
1789 char board_partno[BNXT_VPD_FLD_LEN];
1790 char board_serialno[BNXT_VPD_FLD_LEN];
1791
1792 struct net_device *dev;
1793 struct pci_dev *pdev;
1794
1795 atomic_t intr_sem;
1796
1797 u32 flags;
1798 #define BNXT_FLAG_CHIP_P5 0x1
1799 #define BNXT_FLAG_VF 0x2
1800 #define BNXT_FLAG_LRO 0x4
1801#ifdef CONFIG_INET
1802 #define BNXT_FLAG_GRO 0x8
1803#else
1804 /* Cannot support hardware GRO if CONFIG_INET is not set */
1805 #define BNXT_FLAG_GRO 0x0
1806#endif
1807 #define BNXT_FLAG_TPA (BNXT_FLAG_LRO | BNXT_FLAG_GRO)
1808 #define BNXT_FLAG_JUMBO 0x10
1809 #define BNXT_FLAG_STRIP_VLAN 0x20
1810 #define BNXT_FLAG_AGG_RINGS (BNXT_FLAG_JUMBO | BNXT_FLAG_GRO | \
1811 BNXT_FLAG_LRO)
1812 #define BNXT_FLAG_USING_MSIX 0x40
1813 #define BNXT_FLAG_MSIX_CAP 0x80
1814 #define BNXT_FLAG_RFS 0x100
1815 #define BNXT_FLAG_SHARED_RINGS 0x200
1816 #define BNXT_FLAG_PORT_STATS 0x400
1817 #define BNXT_FLAG_UDP_RSS_CAP 0x800
1818 #define BNXT_FLAG_NEW_RSS_CAP 0x2000
1819 #define BNXT_FLAG_WOL_CAP 0x4000
1820 #define BNXT_FLAG_ROCEV1_CAP 0x8000
1821 #define BNXT_FLAG_ROCEV2_CAP 0x10000
1822 #define BNXT_FLAG_ROCE_CAP (BNXT_FLAG_ROCEV1_CAP | \
1823 BNXT_FLAG_ROCEV2_CAP)
1824 #define BNXT_FLAG_NO_AGG_RINGS 0x20000
1825 #define BNXT_FLAG_RX_PAGE_MODE 0x40000
1826 #define BNXT_FLAG_CHIP_SR2 0x80000
1827 #define BNXT_FLAG_MULTI_HOST 0x100000
1828 #define BNXT_FLAG_DSN_VALID 0x200000
1829 #define BNXT_FLAG_DOUBLE_DB 0x400000
1830 #define BNXT_FLAG_CHIP_NITRO_A0 0x1000000
1831 #define BNXT_FLAG_DIM 0x2000000
1832 #define BNXT_FLAG_ROCE_MIRROR_CAP 0x4000000
1833 #define BNXT_FLAG_PORT_STATS_EXT 0x10000000
1834
1835 #define BNXT_FLAG_ALL_CONFIG_FEATS (BNXT_FLAG_TPA | \
1836 BNXT_FLAG_RFS | \
1837 BNXT_FLAG_STRIP_VLAN)
1838
1839#define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF))
1840#define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF)
1841#define BNXT_NPAR(bp) ((bp)->port_partition_type)
1842#define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST)
1843#define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
1844#define BNXT_SH_PORT_CFG_OK(bp) (BNXT_PF(bp) && \
1845 ((bp)->phy_flags & BNXT_PHY_FL_SHARED_PORT_CFG))
1846#define BNXT_PHY_CFG_ABLE(bp) ((BNXT_SINGLE_PF(bp) || \
1847 BNXT_SH_PORT_CFG_OK(bp)) && \
1848 (bp)->link_info.phy_state == BNXT_PHY_STATE_ENABLED)
1849#define BNXT_CHIP_TYPE_NITRO_A0(bp) ((bp)->flags & BNXT_FLAG_CHIP_NITRO_A0)
1850#define BNXT_RX_PAGE_MODE(bp) ((bp)->flags & BNXT_FLAG_RX_PAGE_MODE)
1851#define BNXT_SUPPORTS_TPA(bp) (!BNXT_CHIP_TYPE_NITRO_A0(bp) && \
1852 (!((bp)->flags & BNXT_FLAG_CHIP_P5) || \
1853 (bp)->max_tpa_v2) && !is_kdump_kernel())
1854#define BNXT_RX_JUMBO_MODE(bp) ((bp)->flags & BNXT_FLAG_JUMBO)
1855
1856#define BNXT_CHIP_SR2(bp) \
1857 ((bp)->chip_num == CHIP_NUM_58818)
1858
1859#define BNXT_CHIP_P5_THOR(bp) \
1860 ((bp)->chip_num == CHIP_NUM_57508 || \
1861 (bp)->chip_num == CHIP_NUM_57504 || \
1862 (bp)->chip_num == CHIP_NUM_57502)
1863
1864/* Chip class phase 5 */
1865#define BNXT_CHIP_P5(bp) \
1866 (BNXT_CHIP_P5_THOR(bp) || BNXT_CHIP_SR2(bp))
1867
1868/* Chip class phase 4.x */
1869#define BNXT_CHIP_P4(bp) \
1870 (BNXT_CHIP_NUM_57X1X((bp)->chip_num) || \
1871 BNXT_CHIP_NUM_5745X((bp)->chip_num) || \
1872 BNXT_CHIP_NUM_588XX((bp)->chip_num) || \
1873 (BNXT_CHIP_NUM_58700((bp)->chip_num) && \
1874 !BNXT_CHIP_TYPE_NITRO_A0(bp)))
1875
1876#define BNXT_CHIP_P4_PLUS(bp) \
1877 (BNXT_CHIP_P4(bp) || BNXT_CHIP_P5(bp))
1878
1879 struct bnxt_aux_priv *aux_priv;
1880 struct bnxt_en_dev *edev;
1881
1882 struct bnxt_napi **bnapi;
1883
1884 struct bnxt_rx_ring_info *rx_ring;
1885 struct bnxt_tx_ring_info *tx_ring;
1886 u16 *tx_ring_map;
1887
1888 struct sk_buff * (*gro_func)(struct bnxt_tpa_info *, int, int,
1889 struct sk_buff *);
1890
1891 struct sk_buff * (*rx_skb_func)(struct bnxt *,
1892 struct bnxt_rx_ring_info *,
1893 u16, void *, u8 *, dma_addr_t,
1894 unsigned int);
1895
1896 u16 max_tpa_v2;
1897 u16 max_tpa;
1898 u32 rx_buf_size;
1899 u32 rx_buf_use_size; /* useable size */
1900 u16 rx_offset;
1901 u16 rx_dma_offset;
1902 enum dma_data_direction rx_dir;
1903 u32 rx_ring_size;
1904 u32 rx_agg_ring_size;
1905 u32 rx_copy_thresh;
1906 u32 rx_ring_mask;
1907 u32 rx_agg_ring_mask;
1908 int rx_nr_pages;
1909 int rx_agg_nr_pages;
1910 int rx_nr_rings;
1911 int rsscos_nr_ctxs;
1912
1913 u32 tx_ring_size;
1914 u32 tx_ring_mask;
1915 int tx_nr_pages;
1916 int tx_nr_rings;
1917 int tx_nr_rings_per_tc;
1918 int tx_nr_rings_xdp;
1919
1920 int tx_wake_thresh;
1921 int tx_push_thresh;
1922 int tx_push_size;
1923
1924 u32 cp_ring_size;
1925 u32 cp_ring_mask;
1926 u32 cp_bit;
1927 int cp_nr_pages;
1928 int cp_nr_rings;
1929
1930 /* grp_info indexed by completion ring index */
1931 struct bnxt_ring_grp_info *grp_info;
1932 struct bnxt_vnic_info *vnic_info;
1933 int nr_vnics;
1934 u16 *rss_indir_tbl;
1935 u16 rss_indir_tbl_entries;
1936 u32 rss_hash_cfg;
1937 u32 rss_hash_delta;
1938
1939 u16 max_mtu;
1940 u8 max_tc;
1941 u8 max_lltc; /* lossless TCs */
1942 struct bnxt_queue_info q_info[BNXT_MAX_QUEUE];
1943 u8 tc_to_qidx[BNXT_MAX_QUEUE];
1944 u8 q_ids[BNXT_MAX_QUEUE];
1945 u8 max_q;
1946
1947 unsigned int current_interval;
1948#define BNXT_TIMER_INTERVAL HZ
1949
1950 struct timer_list timer;
1951
1952 unsigned long state;
1953#define BNXT_STATE_OPEN 0
1954#define BNXT_STATE_IN_SP_TASK 1
1955#define BNXT_STATE_READ_STATS 2
1956#define BNXT_STATE_FW_RESET_DET 3
1957#define BNXT_STATE_IN_FW_RESET 4
1958#define BNXT_STATE_ABORT_ERR 5
1959#define BNXT_STATE_FW_FATAL_COND 6
1960#define BNXT_STATE_DRV_REGISTERED 7
1961#define BNXT_STATE_PCI_CHANNEL_IO_FROZEN 8
1962#define BNXT_STATE_NAPI_DISABLED 9
1963#define BNXT_STATE_L2_FILTER_RETRY 10
1964#define BNXT_STATE_FW_ACTIVATE 11
1965#define BNXT_STATE_RECOVER 12
1966#define BNXT_STATE_FW_NON_FATAL_COND 13
1967#define BNXT_STATE_FW_ACTIVATE_RESET 14
1968#define BNXT_STATE_HALF_OPEN 15 /* For offline ethtool tests */
1969
1970#define BNXT_NO_FW_ACCESS(bp) \
1971 (test_bit(BNXT_STATE_FW_FATAL_COND, &(bp)->state) || \
1972 pci_channel_offline((bp)->pdev))
1973
1974 struct bnxt_irq *irq_tbl;
1975 int total_irqs;
1976 u8 mac_addr[ETH_ALEN];
1977
1978#ifdef CONFIG_BNXT_DCB
1979 struct ieee_pfc *ieee_pfc;
1980 struct ieee_ets *ieee_ets;
1981 u8 dcbx_cap;
1982 u8 default_pri;
1983 u8 max_dscp_value;
1984#endif /* CONFIG_BNXT_DCB */
1985
1986 u32 msg_enable;
1987
1988 u64 fw_cap;
1989 #define BNXT_FW_CAP_SHORT_CMD BIT_ULL(0)
1990 #define BNXT_FW_CAP_LLDP_AGENT BIT_ULL(1)
1991 #define BNXT_FW_CAP_DCBX_AGENT BIT_ULL(2)
1992 #define BNXT_FW_CAP_NEW_RM BIT_ULL(3)
1993 #define BNXT_FW_CAP_IF_CHANGE BIT_ULL(4)
1994 #define BNXT_FW_CAP_KONG_MB_CHNL BIT_ULL(7)
1995 #define BNXT_FW_CAP_OVS_64BIT_HANDLE BIT_ULL(10)
1996 #define BNXT_FW_CAP_TRUSTED_VF BIT_ULL(11)
1997 #define BNXT_FW_CAP_ERROR_RECOVERY BIT_ULL(13)
1998 #define BNXT_FW_CAP_PKG_VER BIT_ULL(14)
1999 #define BNXT_FW_CAP_CFA_ADV_FLOW BIT_ULL(15)
2000 #define BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2 BIT_ULL(16)
2001 #define BNXT_FW_CAP_PCIE_STATS_SUPPORTED BIT_ULL(17)
2002 #define BNXT_FW_CAP_EXT_STATS_SUPPORTED BIT_ULL(18)
2003 #define BNXT_FW_CAP_RSS_HASH_TYPE_DELTA BIT_ULL(19)
2004 #define BNXT_FW_CAP_ERR_RECOVER_RELOAD BIT_ULL(20)
2005 #define BNXT_FW_CAP_HOT_RESET BIT_ULL(21)
2006 #define BNXT_FW_CAP_PTP_RTC BIT_ULL(22)
2007 #define BNXT_FW_CAP_RX_ALL_PKT_TS BIT_ULL(23)
2008 #define BNXT_FW_CAP_VLAN_RX_STRIP BIT_ULL(24)
2009 #define BNXT_FW_CAP_VLAN_TX_INSERT BIT_ULL(25)
2010 #define BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED BIT_ULL(26)
2011 #define BNXT_FW_CAP_LIVEPATCH BIT_ULL(27)
2012 #define BNXT_FW_CAP_PTP_PPS BIT_ULL(28)
2013 #define BNXT_FW_CAP_HOT_RESET_IF BIT_ULL(29)
2014 #define BNXT_FW_CAP_RING_MONITOR BIT_ULL(30)
2015 #define BNXT_FW_CAP_DBG_QCAPS BIT_ULL(31)
2016 #define BNXT_FW_CAP_PTP BIT_ULL(32)
2017 #define BNXT_FW_CAP_THRESHOLD_TEMP_SUPPORTED BIT_ULL(33)
2018 #define BNXT_FW_CAP_DFLT_VLAN_TPID_PCP BIT_ULL(34)
2019 #define BNXT_FW_CAP_PRE_RESV_VNICS BIT_ULL(35)
2020
2021 u32 fw_dbg_cap;
2022
2023#define BNXT_NEW_RM(bp) ((bp)->fw_cap & BNXT_FW_CAP_NEW_RM)
2024#define BNXT_PTP_USE_RTC(bp) (!BNXT_MH(bp) && \
2025 ((bp)->fw_cap & BNXT_FW_CAP_PTP_RTC))
2026 u32 hwrm_spec_code;
2027 u16 hwrm_cmd_seq;
2028 u16 hwrm_cmd_kong_seq;
2029 struct dma_pool *hwrm_dma_pool;
2030 struct hlist_head hwrm_pending_list;
2031
2032 struct rtnl_link_stats64 net_stats_prev;
2033 struct bnxt_stats_mem port_stats;
2034 struct bnxt_stats_mem rx_port_stats_ext;
2035 struct bnxt_stats_mem tx_port_stats_ext;
2036 u16 fw_rx_stats_ext_size;
2037 u16 fw_tx_stats_ext_size;
2038 u16 hw_ring_stats_size;
2039 u8 pri2cos_idx[8];
2040 u8 pri2cos_valid;
2041
2042 struct bnxt_total_ring_err_stats ring_err_stats_prev;
2043
2044 u16 hwrm_max_req_len;
2045 u16 hwrm_max_ext_req_len;
2046 unsigned int hwrm_cmd_timeout;
2047 unsigned int hwrm_cmd_max_timeout;
2048 struct mutex hwrm_cmd_lock; /* serialize hwrm messages */
2049 struct hwrm_ver_get_output ver_resp;
2050#define FW_VER_STR_LEN 32
2051#define BC_HWRM_STR_LEN 21
2052#define PHY_VER_STR_LEN (FW_VER_STR_LEN - BC_HWRM_STR_LEN)
2053 char fw_ver_str[FW_VER_STR_LEN];
2054 char hwrm_ver_supp[FW_VER_STR_LEN];
2055 char nvm_cfg_ver[FW_VER_STR_LEN];
2056 u64 fw_ver_code;
2057#define BNXT_FW_VER_CODE(maj, min, bld, rsv) \
2058 ((u64)(maj) << 48 | (u64)(min) << 32 | (u64)(bld) << 16 | (rsv))
2059#define BNXT_FW_MAJ(bp) ((bp)->fw_ver_code >> 48)
2060#define BNXT_FW_BLD(bp) (((bp)->fw_ver_code >> 16) & 0xffff)
2061
2062 u16 vxlan_fw_dst_port_id;
2063 u16 nge_fw_dst_port_id;
2064 __be16 vxlan_port;
2065 __be16 nge_port;
2066 u8 port_partition_type;
2067 u8 port_count;
2068 u16 br_mode;
2069
2070 struct bnxt_coal_cap coal_cap;
2071 struct bnxt_coal rx_coal;
2072 struct bnxt_coal tx_coal;
2073
2074 u32 stats_coal_ticks;
2075#define BNXT_DEF_STATS_COAL_TICKS 1000000
2076#define BNXT_MIN_STATS_COAL_TICKS 250000
2077#define BNXT_MAX_STATS_COAL_TICKS 1000000
2078
2079 struct work_struct sp_task;
2080 unsigned long sp_event;
2081#define BNXT_RX_MASK_SP_EVENT 0
2082#define BNXT_RX_NTP_FLTR_SP_EVENT 1
2083#define BNXT_LINK_CHNG_SP_EVENT 2
2084#define BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT 3
2085#define BNXT_RESET_TASK_SP_EVENT 6
2086#define BNXT_RST_RING_SP_EVENT 7
2087#define BNXT_HWRM_PF_UNLOAD_SP_EVENT 8
2088#define BNXT_PERIODIC_STATS_SP_EVENT 9
2089#define BNXT_HWRM_PORT_MODULE_SP_EVENT 10
2090#define BNXT_RESET_TASK_SILENT_SP_EVENT 11
2091#define BNXT_LINK_SPEED_CHNG_SP_EVENT 14
2092#define BNXT_FLOW_STATS_SP_EVENT 15
2093#define BNXT_UPDATE_PHY_SP_EVENT 16
2094#define BNXT_RING_COAL_NOW_SP_EVENT 17
2095#define BNXT_FW_RESET_NOTIFY_SP_EVENT 18
2096#define BNXT_FW_EXCEPTION_SP_EVENT 19
2097#define BNXT_LINK_CFG_CHANGE_SP_EVENT 21
2098#define BNXT_THERMAL_THRESHOLD_SP_EVENT 22
2099#define BNXT_FW_ECHO_REQUEST_SP_EVENT 23
2100
2101 struct delayed_work fw_reset_task;
2102 int fw_reset_state;
2103#define BNXT_FW_RESET_STATE_POLL_VF 1
2104#define BNXT_FW_RESET_STATE_RESET_FW 2
2105#define BNXT_FW_RESET_STATE_ENABLE_DEV 3
2106#define BNXT_FW_RESET_STATE_POLL_FW 4
2107#define BNXT_FW_RESET_STATE_OPENING 5
2108#define BNXT_FW_RESET_STATE_POLL_FW_DOWN 6
2109
2110 u16 fw_reset_min_dsecs;
2111#define BNXT_DFLT_FW_RST_MIN_DSECS 20
2112 u16 fw_reset_max_dsecs;
2113#define BNXT_DFLT_FW_RST_MAX_DSECS 60
2114 unsigned long fw_reset_timestamp;
2115
2116 struct bnxt_fw_health *fw_health;
2117
2118 struct bnxt_hw_resc hw_resc;
2119 struct bnxt_pf_info pf;
2120 struct bnxt_ctx_mem_info *ctx;
2121#ifdef CONFIG_BNXT_SRIOV
2122 int nr_vfs;
2123 struct bnxt_vf_info vf;
2124 wait_queue_head_t sriov_cfg_wait;
2125 bool sriov_cfg;
2126#define BNXT_SRIOV_CFG_WAIT_TMO msecs_to_jiffies(10000)
2127#endif
2128
2129#if BITS_PER_LONG == 32
2130 /* ensure atomic 64-bit doorbell writes on 32-bit systems. */
2131 spinlock_t db_lock;
2132#endif
2133 int db_size;
2134
2135#define BNXT_NTP_FLTR_MAX_FLTR 4096
2136#define BNXT_NTP_FLTR_HASH_SIZE 512
2137#define BNXT_NTP_FLTR_HASH_MASK (BNXT_NTP_FLTR_HASH_SIZE - 1)
2138 struct hlist_head ntp_fltr_hash_tbl[BNXT_NTP_FLTR_HASH_SIZE];
2139 spinlock_t ntp_fltr_lock; /* for hash table add, del */
2140
2141 unsigned long *ntp_fltr_bmap;
2142 int ntp_fltr_count;
2143
2144 /* To protect link related settings during link changes and
2145 * ethtool settings changes.
2146 */
2147 struct mutex link_lock;
2148 struct bnxt_link_info link_info;
2149 struct ethtool_eee eee;
2150 u32 lpi_tmr_lo;
2151 u32 lpi_tmr_hi;
2152
2153 /* copied from flags and flags2 in hwrm_port_phy_qcaps_output */
2154 u32 phy_flags;
2155#define BNXT_PHY_FL_EEE_CAP PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED
2156#define BNXT_PHY_FL_EXT_LPBK PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED
2157#define BNXT_PHY_FL_AN_PHY_LPBK PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED
2158#define BNXT_PHY_FL_SHARED_PORT_CFG PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED
2159#define BNXT_PHY_FL_PORT_STATS_NO_RESET PORT_PHY_QCAPS_RESP_FLAGS_CUMULATIVE_COUNTERS_ON_RESET
2160#define BNXT_PHY_FL_NO_PHY_LPBK PORT_PHY_QCAPS_RESP_FLAGS_LOCAL_LPBK_NOT_SUPPORTED
2161#define BNXT_PHY_FL_FW_MANAGED_LKDN PORT_PHY_QCAPS_RESP_FLAGS_FW_MANAGED_LINK_DOWN
2162#define BNXT_PHY_FL_NO_FCS PORT_PHY_QCAPS_RESP_FLAGS_NO_FCS
2163#define BNXT_PHY_FL_NO_PAUSE (PORT_PHY_QCAPS_RESP_FLAGS2_PAUSE_UNSUPPORTED << 8)
2164#define BNXT_PHY_FL_NO_PFC (PORT_PHY_QCAPS_RESP_FLAGS2_PFC_UNSUPPORTED << 8)
2165#define BNXT_PHY_FL_BANK_SEL (PORT_PHY_QCAPS_RESP_FLAGS2_BANK_ADDR_SUPPORTED << 8)
2166
2167 u8 num_tests;
2168 struct bnxt_test_info *test_info;
2169
2170 u8 wol_filter_id;
2171 u8 wol;
2172
2173 u8 num_leds;
2174 struct bnxt_led_info leds[BNXT_MAX_LED];
2175 u16 dump_flag;
2176#define BNXT_DUMP_LIVE 0
2177#define BNXT_DUMP_CRASH 1
2178
2179 struct bpf_prog *xdp_prog;
2180
2181 struct bnxt_ptp_cfg *ptp_cfg;
2182 u8 ptp_all_rx_tstamp;
2183
2184 /* devlink interface and vf-rep structs */
2185 struct devlink *dl;
2186 struct devlink_port dl_port;
2187 enum devlink_eswitch_mode eswitch_mode;
2188 struct bnxt_vf_rep **vf_reps; /* array of vf-rep ptrs */
2189 u16 *cfa_code_map; /* cfa_code -> vf_idx map */
2190 u8 dsn[8];
2191 struct bnxt_tc_info *tc_info;
2192 struct list_head tc_indr_block_list;
2193 struct dentry *debugfs_pdev;
2194#ifdef CONFIG_BNXT_HWMON
2195 struct device *hwmon_dev;
2196 u8 warn_thresh_temp;
2197 u8 crit_thresh_temp;
2198 u8 fatal_thresh_temp;
2199 u8 shutdown_thresh_temp;
2200#endif
2201 u32 thermal_threshold_type;
2202 enum board_idx board_idx;
2203};
2204
2205#define BNXT_NUM_RX_RING_STATS 8
2206#define BNXT_NUM_TX_RING_STATS 8
2207#define BNXT_NUM_TPA_RING_STATS 4
2208#define BNXT_NUM_TPA_RING_STATS_P5 5
2209#define BNXT_NUM_TPA_RING_STATS_P5_SR2 6
2210
2211#define BNXT_RING_STATS_SIZE_P5 \
2212 ((BNXT_NUM_RX_RING_STATS + BNXT_NUM_TX_RING_STATS + \
2213 BNXT_NUM_TPA_RING_STATS_P5) * 8)
2214
2215#define BNXT_RING_STATS_SIZE_P5_SR2 \
2216 ((BNXT_NUM_RX_RING_STATS + BNXT_NUM_TX_RING_STATS + \
2217 BNXT_NUM_TPA_RING_STATS_P5_SR2) * 8)
2218
2219#define BNXT_GET_RING_STATS64(sw, counter) \
2220 (*((sw) + offsetof(struct ctx_hw_stats, counter) / 8))
2221
2222#define BNXT_GET_RX_PORT_STATS64(sw, counter) \
2223 (*((sw) + offsetof(struct rx_port_stats, counter) / 8))
2224
2225#define BNXT_GET_TX_PORT_STATS64(sw, counter) \
2226 (*((sw) + offsetof(struct tx_port_stats, counter) / 8))
2227
2228#define BNXT_PORT_STATS_SIZE \
2229 (sizeof(struct rx_port_stats) + sizeof(struct tx_port_stats) + 1024)
2230
2231#define BNXT_TX_PORT_STATS_BYTE_OFFSET \
2232 (sizeof(struct rx_port_stats) + 512)
2233
2234#define BNXT_RX_STATS_OFFSET(counter) \
2235 (offsetof(struct rx_port_stats, counter) / 8)
2236
2237#define BNXT_TX_STATS_OFFSET(counter) \
2238 ((offsetof(struct tx_port_stats, counter) + \
2239 BNXT_TX_PORT_STATS_BYTE_OFFSET) / 8)
2240
2241#define BNXT_RX_STATS_EXT_OFFSET(counter) \
2242 (offsetof(struct rx_port_stats_ext, counter) / 8)
2243
2244#define BNXT_RX_STATS_EXT_NUM_LEGACY \
2245 BNXT_RX_STATS_EXT_OFFSET(rx_fec_corrected_blocks)
2246
2247#define BNXT_TX_STATS_EXT_OFFSET(counter) \
2248 (offsetof(struct tx_port_stats_ext, counter) / 8)
2249
2250#define BNXT_HW_FEATURE_VLAN_ALL_RX \
2251 (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)
2252#define BNXT_HW_FEATURE_VLAN_ALL_TX \
2253 (NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_STAG_TX)
2254
2255#define I2C_DEV_ADDR_A0 0xa0
2256#define I2C_DEV_ADDR_A2 0xa2
2257#define SFF_DIAG_SUPPORT_OFFSET 0x5c
2258#define SFF_MODULE_ID_SFP 0x3
2259#define SFF_MODULE_ID_QSFP 0xc
2260#define SFF_MODULE_ID_QSFP_PLUS 0xd
2261#define SFF_MODULE_ID_QSFP28 0x11
2262#define BNXT_MAX_PHY_I2C_RESP_SIZE 64
2263
2264static inline u32 bnxt_tx_avail(struct bnxt *bp,
2265 const struct bnxt_tx_ring_info *txr)
2266{
2267 u32 used = READ_ONCE(txr->tx_prod) - READ_ONCE(txr->tx_cons);
2268
2269 return bp->tx_ring_size - (used & bp->tx_ring_mask);
2270}
2271
2272static inline void bnxt_writeq(struct bnxt *bp, u64 val,
2273 volatile void __iomem *addr)
2274{
2275#if BITS_PER_LONG == 32
2276 spin_lock(&bp->db_lock);
2277 lo_hi_writeq(val, addr);
2278 spin_unlock(&bp->db_lock);
2279#else
2280 writeq(val, addr);
2281#endif
2282}
2283
2284static inline void bnxt_writeq_relaxed(struct bnxt *bp, u64 val,
2285 volatile void __iomem *addr)
2286{
2287#if BITS_PER_LONG == 32
2288 spin_lock(&bp->db_lock);
2289 lo_hi_writeq_relaxed(val, addr);
2290 spin_unlock(&bp->db_lock);
2291#else
2292 writeq_relaxed(val, addr);
2293#endif
2294}
2295
2296/* For TX and RX ring doorbells with no ordering guarantee*/
2297static inline void bnxt_db_write_relaxed(struct bnxt *bp,
2298 struct bnxt_db_info *db, u32 idx)
2299{
2300 if (bp->flags & BNXT_FLAG_CHIP_P5) {
2301 bnxt_writeq_relaxed(bp, val: db->db_key64 | idx, addr: db->doorbell);
2302 } else {
2303 u32 db_val = db->db_key32 | idx;
2304
2305 writel_relaxed(db_val, db->doorbell);
2306 if (bp->flags & BNXT_FLAG_DOUBLE_DB)
2307 writel_relaxed(db_val, db->doorbell);
2308 }
2309}
2310
2311/* For TX and RX ring doorbells */
2312static inline void bnxt_db_write(struct bnxt *bp, struct bnxt_db_info *db,
2313 u32 idx)
2314{
2315 if (bp->flags & BNXT_FLAG_CHIP_P5) {
2316 bnxt_writeq(bp, val: db->db_key64 | idx, addr: db->doorbell);
2317 } else {
2318 u32 db_val = db->db_key32 | idx;
2319
2320 writel(val: db_val, addr: db->doorbell);
2321 if (bp->flags & BNXT_FLAG_DOUBLE_DB)
2322 writel(val: db_val, addr: db->doorbell);
2323 }
2324}
2325
2326/* Must hold rtnl_lock */
2327static inline bool bnxt_sriov_cfg(struct bnxt *bp)
2328{
2329#if defined(CONFIG_BNXT_SRIOV)
2330 return BNXT_PF(bp) && (bp->pf.active_vfs || bp->sriov_cfg);
2331#else
2332 return false;
2333#endif
2334}
2335
2336extern const u16 bnxt_lhint_arr[];
2337
2338int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
2339 u16 prod, gfp_t gfp);
2340void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data);
2341u32 bnxt_fw_health_readl(struct bnxt *bp, int reg_idx);
2342void bnxt_set_tpa_flags(struct bnxt *bp);
2343void bnxt_set_ring_params(struct bnxt *);
2344int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode);
2345int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp, unsigned long *bmap,
2346 int bmap_size, bool async_only);
2347int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp);
2348int bnxt_get_nr_rss_ctxs(struct bnxt *bp, int rx_rings);
2349int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id);
2350int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings);
2351int bnxt_nq_rings_in_use(struct bnxt *bp);
2352int bnxt_hwrm_set_coal(struct bnxt *);
2353void bnxt_free_ctx_mem(struct bnxt *bp);
2354unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp);
2355unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp);
2356unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp);
2357unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp);
2358int bnxt_get_avail_msix(struct bnxt *bp, int num);
2359int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init);
2360void bnxt_tx_disable(struct bnxt *bp);
2361void bnxt_tx_enable(struct bnxt *bp);
2362void bnxt_sched_reset_txr(struct bnxt *bp, struct bnxt_tx_ring_info *txr,
2363 int idx);
2364void bnxt_report_link(struct bnxt *bp);
2365int bnxt_update_link(struct bnxt *bp, bool chng_link_state);
2366int bnxt_hwrm_set_pause(struct bnxt *);
2367int bnxt_hwrm_set_link_setting(struct bnxt *, bool, bool);
2368int bnxt_cancel_reservations(struct bnxt *bp, bool fw_reset);
2369int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp);
2370int bnxt_hwrm_free_wol_fltr(struct bnxt *bp);
2371int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all);
2372int bnxt_hwrm_func_qcaps(struct bnxt *bp);
2373int bnxt_hwrm_fw_set_time(struct bnxt *);
2374int bnxt_open_nic(struct bnxt *, bool, bool);
2375int bnxt_half_open_nic(struct bnxt *bp);
2376void bnxt_half_close_nic(struct bnxt *bp);
2377void bnxt_reenable_sriov(struct bnxt *bp);
2378int bnxt_close_nic(struct bnxt *, bool, bool);
2379void bnxt_get_ring_err_stats(struct bnxt *bp,
2380 struct bnxt_total_ring_err_stats *stats);
2381int bnxt_dbg_hwrm_rd_reg(struct bnxt *bp, u32 reg_off, u16 num_words,
2382 u32 *reg_buf);
2383void bnxt_fw_exception(struct bnxt *bp);
2384void bnxt_fw_reset(struct bnxt *bp);
2385int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
2386 int tx_xdp);
2387int bnxt_fw_init_one(struct bnxt *bp);
2388bool bnxt_hwrm_reset_permitted(struct bnxt *bp);
2389int bnxt_setup_mq_tc(struct net_device *dev, u8 tc);
2390int bnxt_get_max_rings(struct bnxt *, int *, int *, bool);
2391int bnxt_restore_pf_fw_resources(struct bnxt *bp);
2392int bnxt_get_port_parent_id(struct net_device *dev,
2393 struct netdev_phys_item_id *ppid);
2394void bnxt_dim_work(struct work_struct *work);
2395int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi);
2396void bnxt_print_device_info(struct bnxt *bp);
2397#endif
2398

source code of linux/drivers/net/ethernet/broadcom/bnxt/bnxt.h