1	/* Broadcom NetXtreme-C/E network driver.
2	*
3	* Copyright (c) 2014-2016 Broadcom Corporation
4	* Copyright (c) 2014-2018 Broadcom Limited
5	* Copyright (c) 2018-2023 Broadcom Inc.
6	*
7	* This program is free software; you can redistribute it and/or modify
8	* it under the terms of the GNU General Public License as published by
9	* the Free Software Foundation.
10	*
11	* DO NOT MODIFY!!! This file is automatically generated.
12	*/
13
14	#ifndef _BNXT_HSI_H_
15	#define _BNXT_HSI_H_
16
17	/* hwrm_cmd_hdr (size:128b/16B) */
18	struct hwrm_cmd_hdr {
19	__le16 req_type;
20	__le16 cmpl_ring;
21	__le16 seq_id;
22	__le16 target_id;
23	__le64 resp_addr;
24	};
25
26	/* hwrm_resp_hdr (size:64b/8B) */
27	struct hwrm_resp_hdr {
28	__le16 error_code;
29	__le16 req_type;
30	__le16 seq_id;
31	__le16 resp_len;
32	};
33
34	#define CMD_DISCR_TLV_ENCAP 0x8000UL
35	#define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP
36
37
38	#define TLV_TYPE_HWRM_REQUEST 0x1UL
39	#define TLV_TYPE_HWRM_RESPONSE 0x2UL
40	#define TLV_TYPE_ROCE_SP_COMMAND 0x3UL
41	#define TLV_TYPE_QUERY_ROCE_CC_GEN1 0x4UL
42	#define TLV_TYPE_MODIFY_ROCE_CC_GEN1 0x5UL
43	#define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY 0x8001UL
44	#define TLV_TYPE_ENGINE_CKV_IV 0x8003UL
45	#define TLV_TYPE_ENGINE_CKV_AUTH_TAG 0x8004UL
46	#define TLV_TYPE_ENGINE_CKV_CIPHERTEXT 0x8005UL
47	#define TLV_TYPE_ENGINE_CKV_HOST_ALGORITHMS 0x8006UL
48	#define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY 0x8007UL
49	#define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE 0x8008UL
50	#define TLV_TYPE_ENGINE_CKV_FW_ECC_PUBLIC_KEY 0x8009UL
51	#define TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS 0x800aUL
52	#define TLV_TYPE_LAST TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS
53
54
55	/* tlv (size:64b/8B) */
56	struct tlv {
57	__le16 cmd_discr;
58	u8 reserved_8b;
59	u8 flags;
60	#define TLV_FLAGS_MORE 0x1UL
61	#define TLV_FLAGS_MORE_LAST 0x0UL
62	#define TLV_FLAGS_MORE_NOT_LAST 0x1UL
63	#define TLV_FLAGS_REQUIRED 0x2UL
64	#define TLV_FLAGS_REQUIRED_NO (0x0UL << 1)
65	#define TLV_FLAGS_REQUIRED_YES (0x1UL << 1)
66	#define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES
67	__le16 tlv_type;
68	__le16 length;
69	};
70
71	/* input (size:128b/16B) */
72	struct input {
73	__le16 req_type;
74	__le16 cmpl_ring;
75	__le16 seq_id;
76	__le16 target_id;
77	__le64 resp_addr;
78	};
79
80	/* output (size:64b/8B) */
81	struct output {
82	__le16 error_code;
83	__le16 req_type;
84	__le16 seq_id;
85	__le16 resp_len;
86	};
87
88	/* hwrm_short_input (size:128b/16B) */
89	struct hwrm_short_input {
90	__le16 req_type;
91	__le16 signature;
92	#define SHORT_REQ_SIGNATURE_SHORT_CMD 0x4321UL
93	#define SHORT_REQ_SIGNATURE_LAST SHORT_REQ_SIGNATURE_SHORT_CMD
94	__le16 target_id;
95	#define SHORT_REQ_TARGET_ID_DEFAULT 0x0UL
96	#define SHORT_REQ_TARGET_ID_TOOLS 0xfffdUL
97	#define SHORT_REQ_TARGET_ID_LAST SHORT_REQ_TARGET_ID_TOOLS
98	__le16 size;
99	__le64 req_addr;
100	};
101
102	/* cmd_nums (size:64b/8B) */
103	struct cmd_nums {
104	__le16 req_type;
105	#define HWRM_VER_GET 0x0UL
106	#define HWRM_FUNC_ECHO_RESPONSE 0xbUL
107	#define HWRM_ERROR_RECOVERY_QCFG 0xcUL
108	#define HWRM_FUNC_DRV_IF_CHANGE 0xdUL
109	#define HWRM_FUNC_BUF_UNRGTR 0xeUL
110	#define HWRM_FUNC_VF_CFG 0xfUL
111	#define HWRM_RESERVED1 0x10UL
112	#define HWRM_FUNC_RESET 0x11UL
113	#define HWRM_FUNC_GETFID 0x12UL
114	#define HWRM_FUNC_VF_ALLOC 0x13UL
115	#define HWRM_FUNC_VF_FREE 0x14UL
116	#define HWRM_FUNC_QCAPS 0x15UL
117	#define HWRM_FUNC_QCFG 0x16UL
118	#define HWRM_FUNC_CFG 0x17UL
119	#define HWRM_FUNC_QSTATS 0x18UL
120	#define HWRM_FUNC_CLR_STATS 0x19UL
121	#define HWRM_FUNC_DRV_UNRGTR 0x1aUL
122	#define HWRM_FUNC_VF_RESC_FREE 0x1bUL
123	#define HWRM_FUNC_VF_VNIC_IDS_QUERY 0x1cUL
124	#define HWRM_FUNC_DRV_RGTR 0x1dUL
125	#define HWRM_FUNC_DRV_QVER 0x1eUL
126	#define HWRM_FUNC_BUF_RGTR 0x1fUL
127	#define HWRM_PORT_PHY_CFG 0x20UL
128	#define HWRM_PORT_MAC_CFG 0x21UL
129	#define HWRM_PORT_TS_QUERY 0x22UL
130	#define HWRM_PORT_QSTATS 0x23UL
131	#define HWRM_PORT_LPBK_QSTATS 0x24UL
132	#define HWRM_PORT_CLR_STATS 0x25UL
133	#define HWRM_PORT_LPBK_CLR_STATS 0x26UL
134	#define HWRM_PORT_PHY_QCFG 0x27UL
135	#define HWRM_PORT_MAC_QCFG 0x28UL
136	#define HWRM_PORT_MAC_PTP_QCFG 0x29UL
137	#define HWRM_PORT_PHY_QCAPS 0x2aUL
138	#define HWRM_PORT_PHY_I2C_WRITE 0x2bUL
139	#define HWRM_PORT_PHY_I2C_READ 0x2cUL
140	#define HWRM_PORT_LED_CFG 0x2dUL
141	#define HWRM_PORT_LED_QCFG 0x2eUL
142	#define HWRM_PORT_LED_QCAPS 0x2fUL
143	#define HWRM_QUEUE_QPORTCFG 0x30UL
144	#define HWRM_QUEUE_QCFG 0x31UL
145	#define HWRM_QUEUE_CFG 0x32UL
146	#define HWRM_FUNC_VLAN_CFG 0x33UL
147	#define HWRM_FUNC_VLAN_QCFG 0x34UL
148	#define HWRM_QUEUE_PFCENABLE_QCFG 0x35UL
149	#define HWRM_QUEUE_PFCENABLE_CFG 0x36UL
150	#define HWRM_QUEUE_PRI2COS_QCFG 0x37UL
151	#define HWRM_QUEUE_PRI2COS_CFG 0x38UL
152	#define HWRM_QUEUE_COS2BW_QCFG 0x39UL
153	#define HWRM_QUEUE_COS2BW_CFG 0x3aUL
154	#define HWRM_QUEUE_DSCP_QCAPS 0x3bUL
155	#define HWRM_QUEUE_DSCP2PRI_QCFG 0x3cUL
156	#define HWRM_QUEUE_DSCP2PRI_CFG 0x3dUL
157	#define HWRM_VNIC_ALLOC 0x40UL
158	#define HWRM_VNIC_FREE 0x41UL
159	#define HWRM_VNIC_CFG 0x42UL
160	#define HWRM_VNIC_QCFG 0x43UL
161	#define HWRM_VNIC_TPA_CFG 0x44UL
162	#define HWRM_VNIC_TPA_QCFG 0x45UL
163	#define HWRM_VNIC_RSS_CFG 0x46UL
164	#define HWRM_VNIC_RSS_QCFG 0x47UL
165	#define HWRM_VNIC_PLCMODES_CFG 0x48UL
166	#define HWRM_VNIC_PLCMODES_QCFG 0x49UL
167	#define HWRM_VNIC_QCAPS 0x4aUL
168	#define HWRM_VNIC_UPDATE 0x4bUL
169	#define HWRM_RING_ALLOC 0x50UL
170	#define HWRM_RING_FREE 0x51UL
171	#define HWRM_RING_CMPL_RING_QAGGINT_PARAMS 0x52UL
172	#define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS 0x53UL
173	#define HWRM_RING_AGGINT_QCAPS 0x54UL
174	#define HWRM_RING_SCHQ_ALLOC 0x55UL
175	#define HWRM_RING_SCHQ_CFG 0x56UL
176	#define HWRM_RING_SCHQ_FREE 0x57UL
177	#define HWRM_RING_RESET 0x5eUL
178	#define HWRM_RING_GRP_ALLOC 0x60UL
179	#define HWRM_RING_GRP_FREE 0x61UL
180	#define HWRM_RING_CFG 0x62UL
181	#define HWRM_RING_QCFG 0x63UL
182	#define HWRM_RESERVED5 0x64UL
183	#define HWRM_RESERVED6 0x65UL
184	#define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC 0x70UL
185	#define HWRM_VNIC_RSS_COS_LB_CTX_FREE 0x71UL
186	#define HWRM_QUEUE_MPLS_QCAPS 0x80UL
187	#define HWRM_QUEUE_MPLSTC2PRI_QCFG 0x81UL
188	#define HWRM_QUEUE_MPLSTC2PRI_CFG 0x82UL
189	#define HWRM_QUEUE_VLANPRI_QCAPS 0x83UL
190	#define HWRM_QUEUE_VLANPRI2PRI_QCFG 0x84UL
191	#define HWRM_QUEUE_VLANPRI2PRI_CFG 0x85UL
192	#define HWRM_QUEUE_GLOBAL_CFG 0x86UL
193	#define HWRM_QUEUE_GLOBAL_QCFG 0x87UL
194	#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG 0x88UL
195	#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG 0x89UL
196	#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG 0x8aUL
197	#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG 0x8bUL
198	#define HWRM_QUEUE_QCAPS 0x8cUL
199	#define HWRM_CFA_L2_FILTER_ALLOC 0x90UL
200	#define HWRM_CFA_L2_FILTER_FREE 0x91UL
201	#define HWRM_CFA_L2_FILTER_CFG 0x92UL
202	#define HWRM_CFA_L2_SET_RX_MASK 0x93UL
203	#define HWRM_CFA_VLAN_ANTISPOOF_CFG 0x94UL
204	#define HWRM_CFA_TUNNEL_FILTER_ALLOC 0x95UL
205	#define HWRM_CFA_TUNNEL_FILTER_FREE 0x96UL
206	#define HWRM_CFA_ENCAP_RECORD_ALLOC 0x97UL
207	#define HWRM_CFA_ENCAP_RECORD_FREE 0x98UL
208	#define HWRM_CFA_NTUPLE_FILTER_ALLOC 0x99UL
209	#define HWRM_CFA_NTUPLE_FILTER_FREE 0x9aUL
210	#define HWRM_CFA_NTUPLE_FILTER_CFG 0x9bUL
211	#define HWRM_CFA_EM_FLOW_ALLOC 0x9cUL
212	#define HWRM_CFA_EM_FLOW_FREE 0x9dUL
213	#define HWRM_CFA_EM_FLOW_CFG 0x9eUL
214	#define HWRM_TUNNEL_DST_PORT_QUERY 0xa0UL
215	#define HWRM_TUNNEL_DST_PORT_ALLOC 0xa1UL
216	#define HWRM_TUNNEL_DST_PORT_FREE 0xa2UL
217	#define HWRM_STAT_CTX_ENG_QUERY 0xafUL
218	#define HWRM_STAT_CTX_ALLOC 0xb0UL
219	#define HWRM_STAT_CTX_FREE 0xb1UL
220	#define HWRM_STAT_CTX_QUERY 0xb2UL
221	#define HWRM_STAT_CTX_CLR_STATS 0xb3UL
222	#define HWRM_PORT_QSTATS_EXT 0xb4UL
223	#define HWRM_PORT_PHY_MDIO_WRITE 0xb5UL
224	#define HWRM_PORT_PHY_MDIO_READ 0xb6UL
225	#define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE 0xb7UL
226	#define HWRM_PORT_PHY_MDIO_BUS_RELEASE 0xb8UL
227	#define HWRM_PORT_QSTATS_EXT_PFC_WD 0xb9UL
228	#define HWRM_RESERVED7 0xbaUL
229	#define HWRM_PORT_TX_FIR_CFG 0xbbUL
230	#define HWRM_PORT_TX_FIR_QCFG 0xbcUL
231	#define HWRM_PORT_ECN_QSTATS 0xbdUL
232	#define HWRM_FW_LIVEPATCH_QUERY 0xbeUL
233	#define HWRM_FW_LIVEPATCH 0xbfUL
234	#define HWRM_FW_RESET 0xc0UL
235	#define HWRM_FW_QSTATUS 0xc1UL
236	#define HWRM_FW_HEALTH_CHECK 0xc2UL
237	#define HWRM_FW_SYNC 0xc3UL
238	#define HWRM_FW_STATE_QCAPS 0xc4UL
239	#define HWRM_FW_STATE_QUIESCE 0xc5UL
240	#define HWRM_FW_STATE_BACKUP 0xc6UL
241	#define HWRM_FW_STATE_RESTORE 0xc7UL
242	#define HWRM_FW_SET_TIME 0xc8UL
243	#define HWRM_FW_GET_TIME 0xc9UL
244	#define HWRM_FW_SET_STRUCTURED_DATA 0xcaUL
245	#define HWRM_FW_GET_STRUCTURED_DATA 0xcbUL
246	#define HWRM_FW_IPC_MAILBOX 0xccUL
247	#define HWRM_FW_ECN_CFG 0xcdUL
248	#define HWRM_FW_ECN_QCFG 0xceUL
249	#define HWRM_FW_SECURE_CFG 0xcfUL
250	#define HWRM_EXEC_FWD_RESP 0xd0UL
251	#define HWRM_REJECT_FWD_RESP 0xd1UL
252	#define HWRM_FWD_RESP 0xd2UL
253	#define HWRM_FWD_ASYNC_EVENT_CMPL 0xd3UL
254	#define HWRM_OEM_CMD 0xd4UL
255	#define HWRM_PORT_PRBS_TEST 0xd5UL
256	#define HWRM_PORT_SFP_SIDEBAND_CFG 0xd6UL
257	#define HWRM_PORT_SFP_SIDEBAND_QCFG 0xd7UL
258	#define HWRM_FW_STATE_UNQUIESCE 0xd8UL
259	#define HWRM_PORT_DSC_DUMP 0xd9UL
260	#define HWRM_PORT_EP_TX_QCFG 0xdaUL
261	#define HWRM_PORT_EP_TX_CFG 0xdbUL
262	#define HWRM_PORT_CFG 0xdcUL
263	#define HWRM_PORT_QCFG 0xddUL
264	#define HWRM_TEMP_MONITOR_QUERY 0xe0UL
265	#define HWRM_REG_POWER_QUERY 0xe1UL
266	#define HWRM_CORE_FREQUENCY_QUERY 0xe2UL
267	#define HWRM_REG_POWER_HISTOGRAM 0xe3UL
268	#define HWRM_WOL_FILTER_ALLOC 0xf0UL
269	#define HWRM_WOL_FILTER_FREE 0xf1UL
270	#define HWRM_WOL_FILTER_QCFG 0xf2UL
271	#define HWRM_WOL_REASON_QCFG 0xf3UL
272	#define HWRM_CFA_METER_QCAPS 0xf4UL
273	#define HWRM_CFA_METER_PROFILE_ALLOC 0xf5UL
274	#define HWRM_CFA_METER_PROFILE_FREE 0xf6UL
275	#define HWRM_CFA_METER_PROFILE_CFG 0xf7UL
276	#define HWRM_CFA_METER_INSTANCE_ALLOC 0xf8UL
277	#define HWRM_CFA_METER_INSTANCE_FREE 0xf9UL
278	#define HWRM_CFA_METER_INSTANCE_CFG 0xfaUL
279	#define HWRM_CFA_VFR_ALLOC 0xfdUL
280	#define HWRM_CFA_VFR_FREE 0xfeUL
281	#define HWRM_CFA_VF_PAIR_ALLOC 0x100UL
282	#define HWRM_CFA_VF_PAIR_FREE 0x101UL
283	#define HWRM_CFA_VF_PAIR_INFO 0x102UL
284	#define HWRM_CFA_FLOW_ALLOC 0x103UL
285	#define HWRM_CFA_FLOW_FREE 0x104UL
286	#define HWRM_CFA_FLOW_FLUSH 0x105UL
287	#define HWRM_CFA_FLOW_STATS 0x106UL
288	#define HWRM_CFA_FLOW_INFO 0x107UL
289	#define HWRM_CFA_DECAP_FILTER_ALLOC 0x108UL
290	#define HWRM_CFA_DECAP_FILTER_FREE 0x109UL
291	#define HWRM_CFA_VLAN_ANTISPOOF_QCFG 0x10aUL
292	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC 0x10bUL
293	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE 0x10cUL
294	#define HWRM_CFA_PAIR_ALLOC 0x10dUL
295	#define HWRM_CFA_PAIR_FREE 0x10eUL
296	#define HWRM_CFA_PAIR_INFO 0x10fUL
297	#define HWRM_FW_IPC_MSG 0x110UL
298	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO 0x111UL
299	#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE 0x112UL
300	#define HWRM_CFA_FLOW_AGING_TIMER_RESET 0x113UL
301	#define HWRM_CFA_FLOW_AGING_CFG 0x114UL
302	#define HWRM_CFA_FLOW_AGING_QCFG 0x115UL
303	#define HWRM_CFA_FLOW_AGING_QCAPS 0x116UL
304	#define HWRM_CFA_CTX_MEM_RGTR 0x117UL
305	#define HWRM_CFA_CTX_MEM_UNRGTR 0x118UL
306	#define HWRM_CFA_CTX_MEM_QCTX 0x119UL
307	#define HWRM_CFA_CTX_MEM_QCAPS 0x11aUL
308	#define HWRM_CFA_COUNTER_QCAPS 0x11bUL
309	#define HWRM_CFA_COUNTER_CFG 0x11cUL
310	#define HWRM_CFA_COUNTER_QCFG 0x11dUL
311	#define HWRM_CFA_COUNTER_QSTATS 0x11eUL
312	#define HWRM_CFA_TCP_FLAG_PROCESS_QCFG 0x11fUL
313	#define HWRM_CFA_EEM_QCAPS 0x120UL
314	#define HWRM_CFA_EEM_CFG 0x121UL
315	#define HWRM_CFA_EEM_QCFG 0x122UL
316	#define HWRM_CFA_EEM_OP 0x123UL
317	#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS 0x124UL
318	#define HWRM_CFA_TFLIB 0x125UL
319	#define HWRM_CFA_LAG_GROUP_MEMBER_RGTR 0x126UL
320	#define HWRM_CFA_LAG_GROUP_MEMBER_UNRGTR 0x127UL
321	#define HWRM_CFA_TLS_FILTER_ALLOC 0x128UL
322	#define HWRM_CFA_TLS_FILTER_FREE 0x129UL
323	#define HWRM_CFA_RELEASE_AFM_FUNC 0x12aUL
324	#define HWRM_ENGINE_CKV_STATUS 0x12eUL
325	#define HWRM_ENGINE_CKV_CKEK_ADD 0x12fUL
326	#define HWRM_ENGINE_CKV_CKEK_DELETE 0x130UL
327	#define HWRM_ENGINE_CKV_KEY_ADD 0x131UL
328	#define HWRM_ENGINE_CKV_KEY_DELETE 0x132UL
329	#define HWRM_ENGINE_CKV_FLUSH 0x133UL
330	#define HWRM_ENGINE_CKV_RNG_GET 0x134UL
331	#define HWRM_ENGINE_CKV_KEY_GEN 0x135UL
332	#define HWRM_ENGINE_CKV_KEY_LABEL_CFG 0x136UL
333	#define HWRM_ENGINE_CKV_KEY_LABEL_QCFG 0x137UL
334	#define HWRM_ENGINE_QG_CONFIG_QUERY 0x13cUL
335	#define HWRM_ENGINE_QG_QUERY 0x13dUL
336	#define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY 0x13eUL
337	#define HWRM_ENGINE_QG_METER_PROFILE_QUERY 0x13fUL
338	#define HWRM_ENGINE_QG_METER_PROFILE_ALLOC 0x140UL
339	#define HWRM_ENGINE_QG_METER_PROFILE_FREE 0x141UL
340	#define HWRM_ENGINE_QG_METER_QUERY 0x142UL
341	#define HWRM_ENGINE_QG_METER_BIND 0x143UL
342	#define HWRM_ENGINE_QG_METER_UNBIND 0x144UL
343	#define HWRM_ENGINE_QG_FUNC_BIND 0x145UL
344	#define HWRM_ENGINE_SG_CONFIG_QUERY 0x146UL
345	#define HWRM_ENGINE_SG_QUERY 0x147UL
346	#define HWRM_ENGINE_SG_METER_QUERY 0x148UL
347	#define HWRM_ENGINE_SG_METER_CONFIG 0x149UL
348	#define HWRM_ENGINE_SG_QG_BIND 0x14aUL
349	#define HWRM_ENGINE_QG_SG_UNBIND 0x14bUL
350	#define HWRM_ENGINE_CONFIG_QUERY 0x154UL
351	#define HWRM_ENGINE_STATS_CONFIG 0x155UL
352	#define HWRM_ENGINE_STATS_CLEAR 0x156UL
353	#define HWRM_ENGINE_STATS_QUERY 0x157UL
354	#define HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR 0x158UL
355	#define HWRM_ENGINE_RQ_ALLOC 0x15eUL
356	#define HWRM_ENGINE_RQ_FREE 0x15fUL
357	#define HWRM_ENGINE_CQ_ALLOC 0x160UL
358	#define HWRM_ENGINE_CQ_FREE 0x161UL
359	#define HWRM_ENGINE_NQ_ALLOC 0x162UL
360	#define HWRM_ENGINE_NQ_FREE 0x163UL
361	#define HWRM_ENGINE_ON_DIE_RQE_CREDITS 0x164UL
362	#define HWRM_ENGINE_FUNC_QCFG 0x165UL
363	#define HWRM_FUNC_RESOURCE_QCAPS 0x190UL
364	#define HWRM_FUNC_VF_RESOURCE_CFG 0x191UL
365	#define HWRM_FUNC_BACKING_STORE_QCAPS 0x192UL
366	#define HWRM_FUNC_BACKING_STORE_CFG 0x193UL
367	#define HWRM_FUNC_BACKING_STORE_QCFG 0x194UL
368	#define HWRM_FUNC_VF_BW_CFG 0x195UL
369	#define HWRM_FUNC_VF_BW_QCFG 0x196UL
370	#define HWRM_FUNC_HOST_PF_IDS_QUERY 0x197UL
371	#define HWRM_FUNC_QSTATS_EXT 0x198UL
372	#define HWRM_STAT_EXT_CTX_QUERY 0x199UL
373	#define HWRM_FUNC_SPD_CFG 0x19aUL
374	#define HWRM_FUNC_SPD_QCFG 0x19bUL
375	#define HWRM_FUNC_PTP_PIN_QCFG 0x19cUL
376	#define HWRM_FUNC_PTP_PIN_CFG 0x19dUL
377	#define HWRM_FUNC_PTP_CFG 0x19eUL
378	#define HWRM_FUNC_PTP_TS_QUERY 0x19fUL
379	#define HWRM_FUNC_PTP_EXT_CFG 0x1a0UL
380	#define HWRM_FUNC_PTP_EXT_QCFG 0x1a1UL
381	#define HWRM_FUNC_KEY_CTX_ALLOC 0x1a2UL
382	#define HWRM_FUNC_BACKING_STORE_CFG_V2 0x1a3UL
383	#define HWRM_FUNC_BACKING_STORE_QCFG_V2 0x1a4UL
384	#define HWRM_FUNC_DBR_PACING_CFG 0x1a5UL
385	#define HWRM_FUNC_DBR_PACING_QCFG 0x1a6UL
386	#define HWRM_FUNC_DBR_PACING_BROADCAST_EVENT 0x1a7UL
387	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2 0x1a8UL
388	#define HWRM_FUNC_DBR_PACING_NQLIST_QUERY 0x1a9UL
389	#define HWRM_FUNC_DBR_RECOVERY_COMPLETED 0x1aaUL
390	#define HWRM_FUNC_SYNCE_CFG 0x1abUL
391	#define HWRM_FUNC_SYNCE_QCFG 0x1acUL
392	#define HWRM_FUNC_KEY_CTX_FREE 0x1adUL
393	#define HWRM_FUNC_LAG_MODE_CFG 0x1aeUL
394	#define HWRM_FUNC_LAG_MODE_QCFG 0x1afUL
395	#define HWRM_SELFTEST_QLIST 0x200UL
396	#define HWRM_SELFTEST_EXEC 0x201UL
397	#define HWRM_SELFTEST_IRQ 0x202UL
398	#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA 0x203UL
399	#define HWRM_PCIE_QSTATS 0x204UL
400	#define HWRM_MFG_FRU_WRITE_CONTROL 0x205UL
401	#define HWRM_MFG_TIMERS_QUERY 0x206UL
402	#define HWRM_MFG_OTP_CFG 0x207UL
403	#define HWRM_MFG_OTP_QCFG 0x208UL
404	#define HWRM_MFG_HDMA_TEST 0x209UL
405	#define HWRM_MFG_FRU_EEPROM_WRITE 0x20aUL
406	#define HWRM_MFG_FRU_EEPROM_READ 0x20bUL
407	#define HWRM_MFG_SOC_IMAGE 0x20cUL
408	#define HWRM_MFG_SOC_QSTATUS 0x20dUL
409	#define HWRM_MFG_PARAM_SEEPROM_SYNC 0x20eUL
410	#define HWRM_MFG_PARAM_SEEPROM_READ 0x20fUL
411	#define HWRM_MFG_PARAM_SEEPROM_HEALTH 0x210UL
412	#define HWRM_MFG_PRVSN_EXPORT_CSR 0x211UL
413	#define HWRM_MFG_PRVSN_IMPORT_CERT 0x212UL
414	#define HWRM_MFG_PRVSN_GET_STATE 0x213UL
415	#define HWRM_MFG_GET_NVM_MEASUREMENT 0x214UL
416	#define HWRM_MFG_PSOC_QSTATUS 0x215UL
417	#define HWRM_MFG_SELFTEST_QLIST 0x216UL
418	#define HWRM_MFG_SELFTEST_EXEC 0x217UL
419	#define HWRM_STAT_GENERIC_QSTATS 0x218UL
420	#define HWRM_MFG_PRVSN_EXPORT_CERT 0x219UL
421	#define HWRM_TF 0x2bcUL
422	#define HWRM_TF_VERSION_GET 0x2bdUL
423	#define HWRM_TF_SESSION_OPEN 0x2c6UL
424	#define HWRM_TF_SESSION_REGISTER 0x2c8UL
425	#define HWRM_TF_SESSION_UNREGISTER 0x2c9UL
426	#define HWRM_TF_SESSION_CLOSE 0x2caUL
427	#define HWRM_TF_SESSION_QCFG 0x2cbUL
428	#define HWRM_TF_SESSION_RESC_QCAPS 0x2ccUL
429	#define HWRM_TF_SESSION_RESC_ALLOC 0x2cdUL
430	#define HWRM_TF_SESSION_RESC_FREE 0x2ceUL
431	#define HWRM_TF_SESSION_RESC_FLUSH 0x2cfUL
432	#define HWRM_TF_SESSION_RESC_INFO 0x2d0UL
433	#define HWRM_TF_SESSION_HOTUP_STATE_SET 0x2d1UL
434	#define HWRM_TF_SESSION_HOTUP_STATE_GET 0x2d2UL
435	#define HWRM_TF_TBL_TYPE_GET 0x2daUL
436	#define HWRM_TF_TBL_TYPE_SET 0x2dbUL
437	#define HWRM_TF_TBL_TYPE_BULK_GET 0x2dcUL
438	#define HWRM_TF_EM_INSERT 0x2eaUL
439	#define HWRM_TF_EM_DELETE 0x2ebUL
440	#define HWRM_TF_EM_HASH_INSERT 0x2ecUL
441	#define HWRM_TF_EM_MOVE 0x2edUL
442	#define HWRM_TF_TCAM_SET 0x2f8UL
443	#define HWRM_TF_TCAM_GET 0x2f9UL
444	#define HWRM_TF_TCAM_MOVE 0x2faUL
445	#define HWRM_TF_TCAM_FREE 0x2fbUL
446	#define HWRM_TF_GLOBAL_CFG_SET 0x2fcUL
447	#define HWRM_TF_GLOBAL_CFG_GET 0x2fdUL
448	#define HWRM_TF_IF_TBL_SET 0x2feUL
449	#define HWRM_TF_IF_TBL_GET 0x2ffUL
450	#define HWRM_TFC_TBL_SCOPE_QCAPS 0x380UL
451	#define HWRM_TFC_TBL_SCOPE_ID_ALLOC 0x381UL
452	#define HWRM_TFC_TBL_SCOPE_CONFIG 0x382UL
453	#define HWRM_TFC_TBL_SCOPE_DECONFIG 0x383UL
454	#define HWRM_TFC_TBL_SCOPE_FID_ADD 0x384UL
455	#define HWRM_TFC_TBL_SCOPE_FID_REM 0x385UL
456	#define HWRM_TFC_TBL_SCOPE_POOL_ALLOC 0x386UL
457	#define HWRM_TFC_TBL_SCOPE_POOL_FREE 0x387UL
458	#define HWRM_TFC_SESSION_ID_ALLOC 0x388UL
459	#define HWRM_TFC_SESSION_FID_ADD 0x389UL
460	#define HWRM_TFC_SESSION_FID_REM 0x38aUL
461	#define HWRM_TFC_IDENT_ALLOC 0x38bUL
462	#define HWRM_TFC_IDENT_FREE 0x38cUL
463	#define HWRM_TFC_IDX_TBL_ALLOC 0x38dUL
464	#define HWRM_TFC_IDX_TBL_ALLOC_SET 0x38eUL
465	#define HWRM_TFC_IDX_TBL_SET 0x38fUL
466	#define HWRM_TFC_IDX_TBL_GET 0x390UL
467	#define HWRM_TFC_IDX_TBL_FREE 0x391UL
468	#define HWRM_TFC_GLOBAL_ID_ALLOC 0x392UL
469	#define HWRM_TFC_TCAM_SET 0x393UL
470	#define HWRM_TFC_TCAM_GET 0x394UL
471	#define HWRM_TFC_TCAM_ALLOC 0x395UL
472	#define HWRM_TFC_TCAM_ALLOC_SET 0x396UL
473	#define HWRM_TFC_TCAM_FREE 0x397UL
474	#define HWRM_TFC_IF_TBL_SET 0x398UL
475	#define HWRM_TFC_IF_TBL_GET 0x399UL
476	#define HWRM_TFC_TBL_SCOPE_CONFIG_GET 0x39aUL
477	#define HWRM_SV 0x400UL
478	#define HWRM_DBG_READ_DIRECT 0xff10UL
479	#define HWRM_DBG_READ_INDIRECT 0xff11UL
480	#define HWRM_DBG_WRITE_DIRECT 0xff12UL
481	#define HWRM_DBG_WRITE_INDIRECT 0xff13UL
482	#define HWRM_DBG_DUMP 0xff14UL
483	#define HWRM_DBG_ERASE_NVM 0xff15UL
484	#define HWRM_DBG_CFG 0xff16UL
485	#define HWRM_DBG_COREDUMP_LIST 0xff17UL
486	#define HWRM_DBG_COREDUMP_INITIATE 0xff18UL
487	#define HWRM_DBG_COREDUMP_RETRIEVE 0xff19UL
488	#define HWRM_DBG_FW_CLI 0xff1aUL
489	#define HWRM_DBG_I2C_CMD 0xff1bUL
490	#define HWRM_DBG_RING_INFO_GET 0xff1cUL
491	#define HWRM_DBG_CRASHDUMP_HEADER 0xff1dUL
492	#define HWRM_DBG_CRASHDUMP_ERASE 0xff1eUL
493	#define HWRM_DBG_DRV_TRACE 0xff1fUL
494	#define HWRM_DBG_QCAPS 0xff20UL
495	#define HWRM_DBG_QCFG 0xff21UL
496	#define HWRM_DBG_CRASHDUMP_MEDIUM_CFG 0xff22UL
497	#define HWRM_DBG_USEQ_ALLOC 0xff23UL
498	#define HWRM_DBG_USEQ_FREE 0xff24UL
499	#define HWRM_DBG_USEQ_FLUSH 0xff25UL
500	#define HWRM_DBG_USEQ_QCAPS 0xff26UL
501	#define HWRM_DBG_USEQ_CW_CFG 0xff27UL
502	#define HWRM_DBG_USEQ_SCHED_CFG 0xff28UL
503	#define HWRM_DBG_USEQ_RUN 0xff29UL
504	#define HWRM_DBG_USEQ_DELIVERY_REQ 0xff2aUL
505	#define HWRM_DBG_USEQ_RESP_HDR 0xff2bUL
506	#define HWRM_NVM_GET_VPD_FIELD_INFO 0xffeaUL
507	#define HWRM_NVM_SET_VPD_FIELD_INFO 0xffebUL
508	#define HWRM_NVM_DEFRAG 0xffecUL
509	#define HWRM_NVM_REQ_ARBITRATION 0xffedUL
510	#define HWRM_NVM_FACTORY_DEFAULTS 0xffeeUL
511	#define HWRM_NVM_VALIDATE_OPTION 0xffefUL
512	#define HWRM_NVM_FLUSH 0xfff0UL
513	#define HWRM_NVM_GET_VARIABLE 0xfff1UL
514	#define HWRM_NVM_SET_VARIABLE 0xfff2UL
515	#define HWRM_NVM_INSTALL_UPDATE 0xfff3UL
516	#define HWRM_NVM_MODIFY 0xfff4UL
517	#define HWRM_NVM_VERIFY_UPDATE 0xfff5UL
518	#define HWRM_NVM_GET_DEV_INFO 0xfff6UL
519	#define HWRM_NVM_ERASE_DIR_ENTRY 0xfff7UL
520	#define HWRM_NVM_MOD_DIR_ENTRY 0xfff8UL
521	#define HWRM_NVM_FIND_DIR_ENTRY 0xfff9UL
522	#define HWRM_NVM_GET_DIR_ENTRIES 0xfffaUL
523	#define HWRM_NVM_GET_DIR_INFO 0xfffbUL
524	#define HWRM_NVM_RAW_DUMP 0xfffcUL
525	#define HWRM_NVM_READ 0xfffdUL
526	#define HWRM_NVM_WRITE 0xfffeUL
527	#define HWRM_NVM_RAW_WRITE_BLK 0xffffUL
528	#define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK
529	__le16 unused_0[3];
530	};
531
532	/* ret_codes (size:64b/8B) */
533	struct ret_codes {
534	__le16 error_code;
535	#define HWRM_ERR_CODE_SUCCESS 0x0UL
536	#define HWRM_ERR_CODE_FAIL 0x1UL
537	#define HWRM_ERR_CODE_INVALID_PARAMS 0x2UL
538	#define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED 0x3UL
539	#define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR 0x4UL
540	#define HWRM_ERR_CODE_INVALID_FLAGS 0x5UL
541	#define HWRM_ERR_CODE_INVALID_ENABLES 0x6UL
542	#define HWRM_ERR_CODE_UNSUPPORTED_TLV 0x7UL
543	#define HWRM_ERR_CODE_NO_BUFFER 0x8UL
544	#define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR 0x9UL
545	#define HWRM_ERR_CODE_HOT_RESET_PROGRESS 0xaUL
546	#define HWRM_ERR_CODE_HOT_RESET_FAIL 0xbUL
547	#define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC 0xcUL
548	#define HWRM_ERR_CODE_KEY_HASH_COLLISION 0xdUL
549	#define HWRM_ERR_CODE_KEY_ALREADY_EXISTS 0xeUL
550	#define HWRM_ERR_CODE_HWRM_ERROR 0xfUL
551	#define HWRM_ERR_CODE_BUSY 0x10UL
552	#define HWRM_ERR_CODE_RESOURCE_LOCKED 0x11UL
553	#define HWRM_ERR_CODE_PF_UNAVAILABLE 0x12UL
554	#define HWRM_ERR_CODE_ENTITY_NOT_PRESENT 0x13UL
555	#define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE 0x8000UL
556	#define HWRM_ERR_CODE_UNKNOWN_ERR 0xfffeUL
557	#define HWRM_ERR_CODE_CMD_NOT_SUPPORTED 0xffffUL
558	#define HWRM_ERR_CODE_LAST HWRM_ERR_CODE_CMD_NOT_SUPPORTED
559	__le16 unused_0[3];
560	};
561
562	/* hwrm_err_output (size:128b/16B) */
563	struct hwrm_err_output {
564	__le16 error_code;
565	__le16 req_type;
566	__le16 seq_id;
567	__le16 resp_len;
568	__le32 opaque_0;
569	__le16 opaque_1;
570	u8 cmd_err;
571	u8 valid;
572	};
573	#define HWRM_NA_SIGNATURE ((__le32)(-1))
574	#define HWRM_MAX_REQ_LEN 128
575	#define HWRM_MAX_RESP_LEN 704
576	#define HW_HASH_INDEX_SIZE 0x80
577	#define HW_HASH_KEY_SIZE 40
578	#define HWRM_RESP_VALID_KEY 1
579	#define HWRM_TARGET_ID_BONO 0xFFF8
580	#define HWRM_TARGET_ID_KONG 0xFFF9
581	#define HWRM_TARGET_ID_APE 0xFFFA
582	#define HWRM_TARGET_ID_TOOLS 0xFFFD
583	#define HWRM_VERSION_MAJOR 1
584	#define HWRM_VERSION_MINOR 10
585	#define HWRM_VERSION_UPDATE 2
586	#define HWRM_VERSION_RSVD 171
587	#define HWRM_VERSION_STR "1.10.2.171"
588
589	/* hwrm_ver_get_input (size:192b/24B) */
590	struct hwrm_ver_get_input {
591	__le16 req_type;
592	__le16 cmpl_ring;
593	__le16 seq_id;
594	__le16 target_id;
595	__le64 resp_addr;
596	u8 hwrm_intf_maj;
597	u8 hwrm_intf_min;
598	u8 hwrm_intf_upd;
599	u8 unused_0[5];
600	};
601
602	/* hwrm_ver_get_output (size:1408b/176B) */
603	struct hwrm_ver_get_output {
604	__le16 error_code;
605	__le16 req_type;
606	__le16 seq_id;
607	__le16 resp_len;
608	u8 hwrm_intf_maj_8b;
609	u8 hwrm_intf_min_8b;
610	u8 hwrm_intf_upd_8b;
611	u8 hwrm_intf_rsvd_8b;
612	u8 hwrm_fw_maj_8b;
613	u8 hwrm_fw_min_8b;
614	u8 hwrm_fw_bld_8b;
615	u8 hwrm_fw_rsvd_8b;
616	u8 mgmt_fw_maj_8b;
617	u8 mgmt_fw_min_8b;
618	u8 mgmt_fw_bld_8b;
619	u8 mgmt_fw_rsvd_8b;
620	u8 netctrl_fw_maj_8b;
621	u8 netctrl_fw_min_8b;
622	u8 netctrl_fw_bld_8b;
623	u8 netctrl_fw_rsvd_8b;
624	__le32 dev_caps_cfg;
625	#define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED 0x1UL
626	#define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED 0x2UL
627	#define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED 0x4UL
628	#define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED 0x8UL
629	#define VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED 0x10UL
630	#define VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED 0x20UL
631	#define VER_GET_RESP_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED 0x40UL
632	#define VER_GET_RESP_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED 0x80UL
633	#define VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED 0x100UL
634	#define VER_GET_RESP_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED 0x200UL
635	#define VER_GET_RESP_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED 0x400UL
636	#define VER_GET_RESP_DEV_CAPS_CFG_CFA_EEM_SUPPORTED 0x800UL
637	#define VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED 0x1000UL
638	#define VER_GET_RESP_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED 0x2000UL
639	#define VER_GET_RESP_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED 0x4000UL
640	#define VER_GET_RESP_DEV_CAPS_CFG_SECURE_BOOT_CAPABLE 0x8000UL
641	u8 roce_fw_maj_8b;
642	u8 roce_fw_min_8b;
643	u8 roce_fw_bld_8b;
644	u8 roce_fw_rsvd_8b;
645	char hwrm_fw_name[16];
646	char mgmt_fw_name[16];
647	char netctrl_fw_name[16];
648	char active_pkg_name[16];
649	char roce_fw_name[16];
650	__le16 chip_num;
651	u8 chip_rev;
652	u8 chip_metal;
653	u8 chip_bond_id;
654	u8 chip_platform_type;
655	#define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC 0x0UL
656	#define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA 0x1UL
657	#define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 0x2UL
658	#define VER_GET_RESP_CHIP_PLATFORM_TYPE_LAST VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM
659	__le16 max_req_win_len;
660	__le16 max_resp_len;
661	__le16 def_req_timeout;
662	u8 flags;
663	#define VER_GET_RESP_FLAGS_DEV_NOT_RDY 0x1UL
664	#define VER_GET_RESP_FLAGS_EXT_VER_AVAIL 0x2UL
665	#define VER_GET_RESP_FLAGS_DEV_NOT_RDY_BACKING_STORE 0x4UL
666	u8 unused_0[2];
667	u8 always_1;
668	__le16 hwrm_intf_major;
669	__le16 hwrm_intf_minor;
670	__le16 hwrm_intf_build;
671	__le16 hwrm_intf_patch;
672	__le16 hwrm_fw_major;
673	__le16 hwrm_fw_minor;
674	__le16 hwrm_fw_build;
675	__le16 hwrm_fw_patch;
676	__le16 mgmt_fw_major;
677	__le16 mgmt_fw_minor;
678	__le16 mgmt_fw_build;
679	__le16 mgmt_fw_patch;
680	__le16 netctrl_fw_major;
681	__le16 netctrl_fw_minor;
682	__le16 netctrl_fw_build;
683	__le16 netctrl_fw_patch;
684	__le16 roce_fw_major;
685	__le16 roce_fw_minor;
686	__le16 roce_fw_build;
687	__le16 roce_fw_patch;
688	__le16 max_ext_req_len;
689	__le16 max_req_timeout;
690	u8 unused_1[3];
691	u8 valid;
692	};
693
694	/* eject_cmpl (size:128b/16B) */
695	struct eject_cmpl {
696	__le16 type;
697	#define EJECT_CMPL_TYPE_MASK 0x3fUL
698	#define EJECT_CMPL_TYPE_SFT 0
699	#define EJECT_CMPL_TYPE_STAT_EJECT 0x1aUL
700	#define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT
701	#define EJECT_CMPL_FLAGS_MASK 0xffc0UL
702	#define EJECT_CMPL_FLAGS_SFT 6
703	#define EJECT_CMPL_FLAGS_ERROR 0x40UL
704	__le16 len;
705	__le32 opaque;
706	__le16 v;
707	#define EJECT_CMPL_V 0x1UL
708	#define EJECT_CMPL_ERRORS_MASK 0xfffeUL
709	#define EJECT_CMPL_ERRORS_SFT 1
710	#define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK 0xeUL
711	#define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
712	#define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0UL << 1)
713	#define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1UL << 1)
714	#define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3UL << 1)
715	#define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH (0x5UL << 1)
716	#define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
717	__le16 reserved16;
718	__le32 unused_2;
719	};
720
721	/* hwrm_cmpl (size:128b/16B) */
722	struct hwrm_cmpl {
723	__le16 type;
724	#define CMPL_TYPE_MASK 0x3fUL
725	#define CMPL_TYPE_SFT 0
726	#define CMPL_TYPE_HWRM_DONE 0x20UL
727	#define CMPL_TYPE_LAST CMPL_TYPE_HWRM_DONE
728	__le16 sequence_id;
729	__le32 unused_1;
730	__le32 v;
731	#define CMPL_V 0x1UL
732	__le32 unused_3;
733	};
734
735	/* hwrm_fwd_req_cmpl (size:128b/16B) */
736	struct hwrm_fwd_req_cmpl {
737	__le16 req_len_type;
738	#define FWD_REQ_CMPL_TYPE_MASK 0x3fUL
739	#define FWD_REQ_CMPL_TYPE_SFT 0
740	#define FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 0x22UL
741	#define FWD_REQ_CMPL_TYPE_LAST FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ
742	#define FWD_REQ_CMPL_REQ_LEN_MASK 0xffc0UL
743	#define FWD_REQ_CMPL_REQ_LEN_SFT 6
744	__le16 source_id;
745	__le32 unused0;
746	__le32 req_buf_addr_v[2];
747	#define FWD_REQ_CMPL_V 0x1UL
748	#define FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL
749	#define FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1
750	};
751
752	/* hwrm_fwd_resp_cmpl (size:128b/16B) */
753	struct hwrm_fwd_resp_cmpl {
754	__le16 type;
755	#define FWD_RESP_CMPL_TYPE_MASK 0x3fUL
756	#define FWD_RESP_CMPL_TYPE_SFT 0
757	#define FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 0x24UL
758	#define FWD_RESP_CMPL_TYPE_LAST FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP
759	__le16 source_id;
760	__le16 resp_len;
761	__le16 unused_1;
762	__le32 resp_buf_addr_v[2];
763	#define FWD_RESP_CMPL_V 0x1UL
764	#define FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL
765	#define FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1
766	};
767
768	/* hwrm_async_event_cmpl (size:128b/16B) */
769	struct hwrm_async_event_cmpl {
770	__le16 type;
771	#define ASYNC_EVENT_CMPL_TYPE_MASK 0x3fUL
772	#define ASYNC_EVENT_CMPL_TYPE_SFT 0
773	#define ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 0x2eUL
774	#define ASYNC_EVENT_CMPL_TYPE_LAST ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT
775	__le16 event_id;
776	#define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE 0x0UL
777	#define ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE 0x1UL
778	#define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE 0x2UL
779	#define ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL
780	#define ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL
781	#define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL
782	#define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL
783	#define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE 0x7UL
784	#define ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY 0x8UL
785	#define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY 0x9UL
786	#define ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG 0xaUL
787	#define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL
788	#define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD 0x11UL
789	#define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL
790	#define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD 0x20UL
791	#define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD 0x21UL
792	#define ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR 0x30UL
793	#define ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL
794	#define ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL
795	#define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE 0x33UL
796	#define ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE 0x34UL
797	#define ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE 0x35UL
798	#define ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED 0x36UL
799	#define ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION 0x37UL
800	#define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL
801	#define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL
802	#define ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE 0x3aUL
803	#define ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE 0x3bUL
804	#define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE 0x3cUL
805	#define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE 0x3dUL
806	#define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE 0x3eUL
807	#define ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE 0x3fUL
808	#define ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE 0x40UL
809	#define ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE 0x41UL
810	#define ASYNC_EVENT_CMPL_EVENT_ID_ECHO_REQUEST 0x42UL
811	#define ASYNC_EVENT_CMPL_EVENT_ID_PHC_UPDATE 0x43UL
812	#define ASYNC_EVENT_CMPL_EVENT_ID_PPS_TIMESTAMP 0x44UL
813	#define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_REPORT 0x45UL
814	#define ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_THRESHOLD 0x46UL
815	#define ASYNC_EVENT_CMPL_EVENT_ID_RSS_CHANGE 0x47UL
816	#define ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_NQ_UPDATE 0x48UL
817	#define ASYNC_EVENT_CMPL_EVENT_ID_HW_DOORBELL_RECOVERY_READ_ERROR 0x49UL
818	#define ASYNC_EVENT_CMPL_EVENT_ID_CTX_ERROR 0x4aUL
819	#define ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID 0x4bUL
820	#define ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG 0xfeUL
821	#define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL
822	#define ASYNC_EVENT_CMPL_EVENT_ID_LAST ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR
823	__le32 event_data2;
824	u8 opaque_v;
825	#define ASYNC_EVENT_CMPL_V 0x1UL
826	#define ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL
827	#define ASYNC_EVENT_CMPL_OPAQUE_SFT 1
828	u8 timestamp_lo;
829	__le16 timestamp_hi;
830	__le32 event_data1;
831	};
832
833	/* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */
834	struct hwrm_async_event_cmpl_link_status_change {
835	__le16 type;
836	#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK 0x3fUL
837	#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0
838	#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
839	#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
840	__le16 event_id;
841	#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 0x0UL
842	#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE
843	__le32 event_data2;
844	u8 opaque_v;
845	#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V 0x1UL
846	#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL
847	#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1
848	u8 timestamp_lo;
849	__le16 timestamp_hi;
850	__le32 event_data1;
851	#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE 0x1UL
852	#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN 0x0UL
853	#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 0x1UL
854	#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP
855	#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK 0xeUL
856	#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1
857	#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL
858	#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4
859	#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK 0xff00000UL
860	#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT 20
861	};
862
863	/* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */
864	struct hwrm_async_event_cmpl_port_conn_not_allowed {
865	__le16 type;
866	#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK 0x3fUL
867	#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0
868	#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL
869	#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
870	__le16 event_id;
871	#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL
872	#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED
873	__le32 event_data2;
874	u8 opaque_v;
875	#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V 0x1UL
876	#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL
877	#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1
878	u8 timestamp_lo;
879	__le16 timestamp_hi;
880	__le32 event_data1;
881	#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL
882	#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0
883	#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK 0xff0000UL
884	#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT 16
885	#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (0x0UL << 16)
886	#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (0x1UL << 16)
887	#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (0x2UL << 16)
888	#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (0x3UL << 16)
889	#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN
890	};
891
892	/* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */
893	struct hwrm_async_event_cmpl_link_speed_cfg_change {
894	__le16 type;
895	#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK 0x3fUL
896	#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT 0
897	#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
898	#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
899	__le16 event_id;
900	#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL
901	#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE
902	__le32 event_data2;
903	u8 opaque_v;
904	#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V 0x1UL
905	#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL
906	#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1
907	u8 timestamp_lo;
908	__le16 timestamp_hi;
909	__le32 event_data1;
910	#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL
911	#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0
912	#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE 0x10000UL
913	#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG 0x20000UL
914	};
915
916	/* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */
917	struct hwrm_async_event_cmpl_reset_notify {
918	__le16 type;
919	#define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK 0x3fUL
920	#define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0
921	#define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 0x2eUL
922	#define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT
923	__le16 event_id;
924	#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 0x8UL
925	#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY
926	__le32 event_data2;
927	#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK 0xffffUL
928	#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_SFT 0
929	u8 opaque_v;
930	#define ASYNC_EVENT_CMPL_RESET_NOTIFY_V 0x1UL
931	#define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK 0xfeUL
932	#define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1
933	u8 timestamp_lo;
934	__le16 timestamp_hi;
935	__le32 event_data1;
936	#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK 0xffUL
937	#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT 0
938	#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE 0x1UL
939	#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 0x2UL
940	#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN
941	#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK 0xff00UL
942	#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT 8
943	#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST (0x1UL << 8)
944	#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL (0x2UL << 8)
945	#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL (0x3UL << 8)
946	#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET (0x4UL << 8)
947	#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION (0x5UL << 8)
948	#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION
949	#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK 0xffff0000UL
950	#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT 16
951	};
952
953	/* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */
954	struct hwrm_async_event_cmpl_error_recovery {
955	__le16 type;
956	#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK 0x3fUL
957	#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0
958	#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT 0x2eUL
959	#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT
960	__le16 event_id;
961	#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 0x9UL
962	#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY
963	__le32 event_data2;
964	u8 opaque_v;
965	#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_V 0x1UL
966	#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK 0xfeUL
967	#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1
968	u8 timestamp_lo;
969	__le16 timestamp_hi;
970	__le32 event_data1;
971	#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK 0xffUL
972	#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT 0
973	#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC 0x1UL
974	#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED 0x2UL
975	};
976
977	/* hwrm_async_event_cmpl_ring_monitor_msg (size:128b/16B) */
978	struct hwrm_async_event_cmpl_ring_monitor_msg {
979	__le16 type;
980	#define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_MASK 0x3fUL
981	#define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_SFT 0
982	#define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT 0x2eUL
983	#define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT
984	__le16 event_id;
985	#define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG 0xaUL
986	#define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG
987	__le32 event_data2;
988	#define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_MASK 0xffUL
989	#define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_SFT 0
990	#define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_TX 0x0UL
991	#define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_RX 0x1UL
992	#define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL 0x2UL
993	#define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL
994	u8 opaque_v;
995	#define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_V 0x1UL
996	#define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_MASK 0xfeUL
997	#define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_SFT 1
998	u8 timestamp_lo;
999	__le16 timestamp_hi;
1000	__le32 event_data1;
1001	};
1002
1003	/* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */
1004	struct hwrm_async_event_cmpl_vf_cfg_change {
1005	__le16 type;
1006	#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK 0x3fUL
1007	#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0
1008	#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1009	#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
1010	__le16 event_id;
1011	#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 0x33UL
1012	#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE
1013	__le32 event_data2;
1014	#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_MASK 0xffffUL
1015	#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_SFT 0
1016	u8 opaque_v;
1017	#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V 0x1UL
1018	#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL
1019	#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1
1020	u8 timestamp_lo;
1021	__le16 timestamp_hi;
1022	__le32 event_data1;
1023	#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL
1024	#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL
1025	#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL
1026	#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL
1027	#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE 0x10UL
1028	#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TF_OWNERSHIP_RELEASE 0x20UL
1029	};
1030
1031	/* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */
1032	struct hwrm_async_event_cmpl_default_vnic_change {
1033	__le16 type;
1034	#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK 0x3fUL
1035	#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT 0
1036	#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1037	#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT
1038	#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK 0xffc0UL
1039	#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT 6
1040	__le16 event_id;
1041	#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 0x35UL
1042	#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION
1043	__le32 event_data2;
1044	u8 opaque_v;
1045	#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V 0x1UL
1046	#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK 0xfeUL
1047	#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1
1048	u8 timestamp_lo;
1049	__le16 timestamp_hi;
1050	__le32 event_data1;
1051	#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK 0x3UL
1052	#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT 0
1053	#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC 0x1UL
1054	#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 0x2UL
1055	#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE
1056	#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK 0x3fcUL
1057	#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT 2
1058	#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK 0x3fffc00UL
1059	#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT 10
1060	};
1061
1062	/* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */
1063	struct hwrm_async_event_cmpl_hw_flow_aged {
1064	__le16 type;
1065	#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK 0x3fUL
1066	#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0
1067	#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1068	#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT
1069	__le16 event_id;
1070	#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 0x36UL
1071	#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED
1072	__le32 event_data2;
1073	u8 opaque_v;
1074	#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_V 0x1UL
1075	#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK 0xfeUL
1076	#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1
1077	u8 timestamp_lo;
1078	__le16 timestamp_hi;
1079	__le32 event_data1;
1080	#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK 0x7fffffffUL
1081	#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT 0
1082	#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION 0x80000000UL
1083	#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX (0x0UL << 31)
1084	#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX (0x1UL << 31)
1085	#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX
1086	};
1087
1088	/* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */
1089	struct hwrm_async_event_cmpl_eem_cache_flush_req {
1090	__le16 type;
1091	#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK 0x3fUL
1092	#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT 0
1093	#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1094	#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT
1095	__le16 event_id;
1096	#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL
1097	#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ
1098	__le32 event_data2;
1099	u8 opaque_v;
1100	#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V 0x1UL
1101	#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK 0xfeUL
1102	#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1
1103	u8 timestamp_lo;
1104	__le16 timestamp_hi;
1105	__le32 event_data1;
1106	};
1107
1108	/* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */
1109	struct hwrm_async_event_cmpl_eem_cache_flush_done {
1110	__le16 type;
1111	#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK 0x3fUL
1112	#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT 0
1113	#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1114	#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT
1115	__le16 event_id;
1116	#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL
1117	#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE
1118	__le32 event_data2;
1119	u8 opaque_v;
1120	#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V 0x1UL
1121	#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK 0xfeUL
1122	#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1
1123	u8 timestamp_lo;
1124	__le16 timestamp_hi;
1125	__le32 event_data1;
1126	#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK 0xffffUL
1127	#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT 0
1128	};
1129
1130	/* hwrm_async_event_cmpl_deferred_response (size:128b/16B) */
1131	struct hwrm_async_event_cmpl_deferred_response {
1132	__le16 type;
1133	#define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_MASK 0x3fUL
1134	#define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_SFT 0
1135	#define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1136	#define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_LAST ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT
1137	__le16 event_id;
1138	#define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE 0x40UL
1139	#define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_LAST ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE
1140	__le32 event_data2;
1141	#define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_MASK 0xffffUL
1142	#define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_SFT 0
1143	u8 opaque_v;
1144	#define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_V 0x1UL
1145	#define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_MASK 0xfeUL
1146	#define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_SFT 1
1147	u8 timestamp_lo;
1148	__le16 timestamp_hi;
1149	__le32 event_data1;
1150	};
1151
1152	/* hwrm_async_event_cmpl_echo_request (size:128b/16B) */
1153	struct hwrm_async_event_cmpl_echo_request {
1154	__le16 type;
1155	#define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_MASK 0x3fUL
1156	#define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_SFT 0
1157	#define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1158	#define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_LAST ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT
1159	__le16 event_id;
1160	#define ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST 0x42UL
1161	#define ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_LAST ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST
1162	__le32 event_data2;
1163	u8 opaque_v;
1164	#define ASYNC_EVENT_CMPL_ECHO_REQUEST_V 0x1UL
1165	#define ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_MASK 0xfeUL
1166	#define ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_SFT 1
1167	u8 timestamp_lo;
1168	__le16 timestamp_hi;
1169	__le32 event_data1;
1170	};
1171
1172	/* hwrm_async_event_cmpl_phc_update (size:128b/16B) */
1173	struct hwrm_async_event_cmpl_phc_update {
1174	__le16 type;
1175	#define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_MASK 0x3fUL
1176	#define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_SFT 0
1177	#define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1178	#define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_LAST ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_HWRM_ASYNC_EVENT
1179	__le16 event_id;
1180	#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_PHC_UPDATE 0x43UL
1181	#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_LAST ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_PHC_UPDATE
1182	__le32 event_data2;
1183	#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_MASTER_FID_MASK 0xffffUL
1184	#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_MASTER_FID_SFT 0
1185	#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_SEC_FID_MASK 0xffff0000UL
1186	#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_SEC_FID_SFT 16
1187	u8 opaque_v;
1188	#define ASYNC_EVENT_CMPL_PHC_UPDATE_V 0x1UL
1189	#define ASYNC_EVENT_CMPL_PHC_UPDATE_OPAQUE_MASK 0xfeUL
1190	#define ASYNC_EVENT_CMPL_PHC_UPDATE_OPAQUE_SFT 1
1191	u8 timestamp_lo;
1192	__le16 timestamp_hi;
1193	__le32 event_data1;
1194	#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_MASK 0xfUL
1195	#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_SFT 0
1196	#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_MASTER 0x1UL
1197	#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_SECONDARY 0x2UL
1198	#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_FAILOVER 0x3UL
1199	#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_RTC_UPDATE 0x4UL
1200	#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_LAST ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_RTC_UPDATE
1201	#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_PHC_TIME_MSB_MASK 0xffff0UL
1202	#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_PHC_TIME_MSB_SFT 4
1203	};
1204
1205	/* hwrm_async_event_cmpl_pps_timestamp (size:128b/16B) */
1206	struct hwrm_async_event_cmpl_pps_timestamp {
1207	__le16 type;
1208	#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_MASK 0x3fUL
1209	#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_SFT 0
1210	#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1211	#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_LAST ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT
1212	__le16 event_id;
1213	#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP 0x44UL
1214	#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_LAST ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP
1215	__le32 event_data2;
1216	#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE 0x1UL
1217	#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_INTERNAL 0x0UL
1218	#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL 0x1UL
1219	#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_LAST ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL
1220	#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_MASK 0xeUL
1221	#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_SFT 1
1222	#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_MASK 0xffff0UL
1223	#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_SFT 4
1224	u8 opaque_v;
1225	#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_V 0x1UL
1226	#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_MASK 0xfeUL
1227	#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_SFT 1
1228	u8 timestamp_lo;
1229	__le16 timestamp_hi;
1230	__le32 event_data1;
1231	#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_MASK 0xffffffffUL
1232	#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_SFT 0
1233	};
1234
1235	/* hwrm_async_event_cmpl_error_report (size:128b/16B) */
1236	struct hwrm_async_event_cmpl_error_report {
1237	__le16 type;
1238	#define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_MASK 0x3fUL
1239	#define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_SFT 0
1240	#define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1241	#define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT
1242	__le16 event_id;
1243	#define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT 0x45UL
1244	#define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT
1245	__le32 event_data2;
1246	u8 opaque_v;
1247	#define ASYNC_EVENT_CMPL_ERROR_REPORT_V 0x1UL
1248	#define ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_MASK 0xfeUL
1249	#define ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_SFT 1
1250	u8 timestamp_lo;
1251	__le16 timestamp_hi;
1252	__le32 event_data1;
1253	#define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL
1254	#define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_SFT 0
1255	};
1256
1257	/* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */
1258	struct hwrm_async_event_cmpl_hwrm_error {
1259	__le16 type;
1260	#define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK 0x3fUL
1261	#define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0
1262	#define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1263	#define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT
1264	__le16 event_id;
1265	#define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR 0xffUL
1266	#define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR
1267	__le32 event_data2;
1268	#define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK 0xffUL
1269	#define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0
1270	#define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING 0x0UL
1271	#define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL 0x1UL
1272	#define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL 0x2UL
1273	#define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL
1274	u8 opaque_v;
1275	#define ASYNC_EVENT_CMPL_HWRM_ERROR_V 0x1UL
1276	#define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK 0xfeUL
1277	#define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1
1278	u8 timestamp_lo;
1279	__le16 timestamp_hi;
1280	__le32 event_data1;
1281	#define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP 0x1UL
1282	};
1283
1284	/* hwrm_async_event_cmpl_error_report_base (size:128b/16B) */
1285	struct hwrm_async_event_cmpl_error_report_base {
1286	__le16 type;
1287	#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_MASK 0x3fUL
1288	#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_SFT 0
1289	#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1290	#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT
1291	__le16 event_id;
1292	#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT 0x45UL
1293	#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT
1294	__le32 event_data2;
1295	u8 opaque_v;
1296	#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_V 0x1UL
1297	#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_MASK 0xfeUL
1298	#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_SFT 1
1299	u8 timestamp_lo;
1300	__le16 timestamp_hi;
1301	__le32 event_data1;
1302	#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL
1303	#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT 0
1304	#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_RESERVED 0x0UL
1305	#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM 0x1UL
1306	#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL 0x2UL
1307	#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_NVM 0x3UL
1308	#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD 0x4UL
1309	#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_THERMAL_THRESHOLD 0x5UL
1310	#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_THERMAL_THRESHOLD
1311	};
1312
1313	/* hwrm_async_event_cmpl_error_report_pause_storm (size:128b/16B) */
1314	struct hwrm_async_event_cmpl_error_report_pause_storm {
1315	__le16 type;
1316	#define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_MASK 0x3fUL
1317	#define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_SFT 0
1318	#define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1319	#define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT
1320	__le16 event_id;
1321	#define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT 0x45UL
1322	#define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT
1323	__le32 event_data2;
1324	u8 opaque_v;
1325	#define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_V 0x1UL
1326	#define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_MASK 0xfeUL
1327	#define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_SFT 1
1328	u8 timestamp_lo;
1329	__le16 timestamp_hi;
1330	__le32 event_data1;
1331	#define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL
1332	#define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_SFT 0
1333	#define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM 0x1UL
1334	#define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM
1335	};
1336
1337	/* hwrm_async_event_cmpl_error_report_invalid_signal (size:128b/16B) */
1338	struct hwrm_async_event_cmpl_error_report_invalid_signal {
1339	__le16 type;
1340	#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_MASK 0x3fUL
1341	#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_SFT 0
1342	#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1343	#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT
1344	__le16 event_id;
1345	#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT 0x45UL
1346	#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT
1347	__le32 event_data2;
1348	#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_MASK 0xffUL
1349	#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_SFT 0
1350	u8 opaque_v;
1351	#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_V 0x1UL
1352	#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_MASK 0xfeUL
1353	#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_SFT 1
1354	u8 timestamp_lo;
1355	__le16 timestamp_hi;
1356	__le32 event_data1;
1357	#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL
1358	#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_SFT 0
1359	#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL 0x2UL
1360	#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL
1361	};
1362
1363	/* hwrm_async_event_cmpl_error_report_nvm (size:128b/16B) */
1364	struct hwrm_async_event_cmpl_error_report_nvm {
1365	__le16 type;
1366	#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_MASK 0x3fUL
1367	#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_SFT 0
1368	#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1369	#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT
1370	__le16 event_id;
1371	#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT 0x45UL
1372	#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT
1373	__le32 event_data2;
1374	#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_MASK 0xffffffffUL
1375	#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_SFT 0
1376	u8 opaque_v;
1377	#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_V 0x1UL
1378	#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_MASK 0xfeUL
1379	#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_SFT 1
1380	u8 timestamp_lo;
1381	__le16 timestamp_hi;
1382	__le32 event_data1;
1383	#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL
1384	#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_SFT 0
1385	#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR 0x3UL
1386	#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR
1387	#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_MASK 0xff00UL
1388	#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_SFT 8
1389	#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_WRITE (0x1UL << 8)
1390	#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE (0x2UL << 8)
1391	#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE
1392	};
1393
1394	/* hwrm_async_event_cmpl_error_report_doorbell_drop_threshold (size:128b/16B) */
1395	struct hwrm_async_event_cmpl_error_report_doorbell_drop_threshold {
1396	__le16 type;
1397	#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_MASK 0x3fUL
1398	#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_SFT 0
1399	#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1400	#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT
1401	__le16 event_id;
1402	#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT 0x45UL
1403	#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT
1404	__le32 event_data2;
1405	u8 opaque_v;
1406	#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_V 0x1UL
1407	#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_MASK 0xfeUL
1408	#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_SFT 1
1409	u8 timestamp_lo;
1410	__le16 timestamp_hi;
1411	__le32 event_data1;
1412	#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL
1413	#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_SFT 0
1414	#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD 0x4UL
1415	#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD
1416	#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_MASK 0xffffff00UL
1417	#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_SFT 8
1418	};
1419
1420	/* hwrm_async_event_cmpl_error_report_thermal (size:128b/16B) */
1421	struct hwrm_async_event_cmpl_error_report_thermal {
1422	__le16 type;
1423	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_MASK 0x3fUL
1424	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_SFT 0
1425	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1426	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_HWRM_ASYNC_EVENT
1427	__le16 event_id;
1428	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_ID_ERROR_REPORT 0x45UL
1429	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_ID_ERROR_REPORT
1430	__le32 event_data2;
1431	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_CURRENT_TEMP_MASK 0xffUL
1432	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_CURRENT_TEMP_SFT 0
1433	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_THRESHOLD_TEMP_MASK 0xff00UL
1434	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_THRESHOLD_TEMP_SFT 8
1435	u8 opaque_v;
1436	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_V 0x1UL
1437	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_OPAQUE_MASK 0xfeUL
1438	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_OPAQUE_SFT 1
1439	u8 timestamp_lo;
1440	__le16 timestamp_hi;
1441	__le32 event_data1;
1442	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL
1443	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_SFT 0
1444	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_THERMAL_EVENT 0x5UL
1445	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_THERMAL_EVENT
1446	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_MASK 0x700UL
1447	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_SFT 8
1448	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_WARN (0x0UL << 8)
1449	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_CRITICAL (0x1UL << 8)
1450	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_FATAL (0x2UL << 8)
1451	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_SHUTDOWN (0x3UL << 8)
1452	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_SHUTDOWN
1453	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR 0x800UL
1454	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_DECREASING (0x0UL << 11)
1455	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_INCREASING (0x1UL << 11)
1456	#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_INCREASING
1457	};
1458
1459	/* hwrm_func_reset_input (size:192b/24B) */
1460	struct hwrm_func_reset_input {
1461	__le16 req_type;
1462	__le16 cmpl_ring;
1463	__le16 seq_id;
1464	__le16 target_id;
1465	__le64 resp_addr;
1466	__le32 enables;
1467	#define FUNC_RESET_REQ_ENABLES_VF_ID_VALID 0x1UL
1468	__le16 vf_id;
1469	u8 func_reset_level;
1470	#define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL 0x0UL
1471	#define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME 0x1UL
1472	#define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN 0x2UL
1473	#define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 0x3UL
1474	#define FUNC_RESET_REQ_FUNC_RESET_LEVEL_LAST FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF
1475	u8 unused_0;
1476	};
1477
1478	/* hwrm_func_reset_output (size:128b/16B) */
1479	struct hwrm_func_reset_output {
1480	__le16 error_code;
1481	__le16 req_type;
1482	__le16 seq_id;
1483	__le16 resp_len;
1484	u8 unused_0[7];
1485	u8 valid;
1486	};
1487
1488	/* hwrm_func_getfid_input (size:192b/24B) */
1489	struct hwrm_func_getfid_input {
1490	__le16 req_type;
1491	__le16 cmpl_ring;
1492	__le16 seq_id;
1493	__le16 target_id;
1494	__le64 resp_addr;
1495	__le32 enables;
1496	#define FUNC_GETFID_REQ_ENABLES_PCI_ID 0x1UL
1497	__le16 pci_id;
1498	u8 unused_0[2];
1499	};
1500
1501	/* hwrm_func_getfid_output (size:128b/16B) */
1502	struct hwrm_func_getfid_output {
1503	__le16 error_code;
1504	__le16 req_type;
1505	__le16 seq_id;
1506	__le16 resp_len;
1507	__le16 fid;
1508	u8 unused_0[5];
1509	u8 valid;
1510	};
1511
1512	/* hwrm_func_vf_alloc_input (size:192b/24B) */
1513	struct hwrm_func_vf_alloc_input {
1514	__le16 req_type;
1515	__le16 cmpl_ring;
1516	__le16 seq_id;
1517	__le16 target_id;
1518	__le64 resp_addr;
1519	__le32 enables;
1520	#define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID 0x1UL
1521	__le16 first_vf_id;
1522	__le16 num_vfs;
1523	};
1524
1525	/* hwrm_func_vf_alloc_output (size:128b/16B) */
1526	struct hwrm_func_vf_alloc_output {
1527	__le16 error_code;
1528	__le16 req_type;
1529	__le16 seq_id;
1530	__le16 resp_len;
1531	__le16 first_vf_id;
1532	u8 unused_0[5];
1533	u8 valid;
1534	};
1535
1536	/* hwrm_func_vf_free_input (size:192b/24B) */
1537	struct hwrm_func_vf_free_input {
1538	__le16 req_type;
1539	__le16 cmpl_ring;
1540	__le16 seq_id;
1541	__le16 target_id;
1542	__le64 resp_addr;
1543	__le32 enables;
1544	#define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID 0x1UL
1545	__le16 first_vf_id;
1546	__le16 num_vfs;
1547	};
1548
1549	/* hwrm_func_vf_free_output (size:128b/16B) */
1550	struct hwrm_func_vf_free_output {
1551	__le16 error_code;
1552	__le16 req_type;
1553	__le16 seq_id;
1554	__le16 resp_len;
1555	u8 unused_0[7];
1556	u8 valid;
1557	};
1558
1559	/* hwrm_func_vf_cfg_input (size:576b/72B) */
1560	struct hwrm_func_vf_cfg_input {
1561	__le16 req_type;
1562	__le16 cmpl_ring;
1563	__le16 seq_id;
1564	__le16 target_id;
1565	__le64 resp_addr;
1566	__le32 enables;
1567	#define FUNC_VF_CFG_REQ_ENABLES_MTU 0x1UL
1568	#define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN 0x2UL
1569	#define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4UL
1570	#define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x8UL
1571	#define FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x10UL
1572	#define FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x20UL
1573	#define FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS 0x40UL
1574	#define FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS 0x80UL
1575	#define FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS 0x100UL
1576	#define FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS 0x200UL
1577	#define FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x400UL
1578	#define FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x800UL
1579	#define FUNC_VF_CFG_REQ_ENABLES_NUM_KTLS_TX_KEY_CTXS 0x1000UL
1580	#define FUNC_VF_CFG_REQ_ENABLES_NUM_KTLS_RX_KEY_CTXS 0x2000UL
1581	#define FUNC_VF_CFG_REQ_ENABLES_NUM_QUIC_TX_KEY_CTXS 0x4000UL
1582	#define FUNC_VF_CFG_REQ_ENABLES_NUM_QUIC_RX_KEY_CTXS 0x8000UL
1583	__le16 mtu;
1584	__le16 guest_vlan;
1585	__le16 async_event_cr;
1586	u8 dflt_mac_addr[6];
1587	__le32 flags;
1588	#define FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x1UL
1589	#define FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x2UL
1590	#define FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x4UL
1591	#define FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x8UL
1592	#define FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x10UL
1593	#define FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x20UL
1594	#define FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x40UL
1595	#define FUNC_VF_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x80UL
1596	#define FUNC_VF_CFG_REQ_FLAGS_PPP_PUSH_MODE_ENABLE 0x100UL
1597	#define FUNC_VF_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE 0x200UL
1598	__le16 num_rsscos_ctxs;
1599	__le16 num_cmpl_rings;
1600	__le16 num_tx_rings;
1601	__le16 num_rx_rings;
1602	__le16 num_l2_ctxs;
1603	__le16 num_vnics;
1604	__le16 num_stat_ctxs;
1605	__le16 num_hw_ring_grps;
1606	__le32 num_ktls_tx_key_ctxs;
1607	__le32 num_ktls_rx_key_ctxs;
1608	__le16 num_msix;
1609	u8 unused[2];
1610	__le32 num_quic_tx_key_ctxs;
1611	__le32 num_quic_rx_key_ctxs;
1612	};
1613
1614	/* hwrm_func_vf_cfg_output (size:128b/16B) */
1615	struct hwrm_func_vf_cfg_output {
1616	__le16 error_code;
1617	__le16 req_type;
1618	__le16 seq_id;
1619	__le16 resp_len;
1620	u8 unused_0[7];
1621	u8 valid;
1622	};
1623
1624	/* hwrm_func_qcaps_input (size:192b/24B) */
1625	struct hwrm_func_qcaps_input {
1626	__le16 req_type;
1627	__le16 cmpl_ring;
1628	__le16 seq_id;
1629	__le16 target_id;
1630	__le64 resp_addr;
1631	__le16 fid;
1632	u8 unused_0[6];
1633	};
1634
1635	/* hwrm_func_qcaps_output (size:896b/112B) */
1636	struct hwrm_func_qcaps_output {
1637	__le16 error_code;
1638	__le16 req_type;
1639	__le16 seq_id;
1640	__le16 resp_len;
1641	__le16 fid;
1642	__le16 port_id;
1643	__le32 flags;
1644	#define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL
1645	#define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL
1646	#define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL
1647	#define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED 0x8UL
1648	#define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED 0x10UL
1649	#define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED 0x20UL
1650	#define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED 0x40UL
1651	#define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED 0x80UL
1652	#define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED 0x100UL
1653	#define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED 0x200UL
1654	#define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED 0x400UL
1655	#define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED 0x800UL
1656	#define FUNC_QCAPS_RESP_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED 0x1000UL
1657	#define FUNC_QCAPS_RESP_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED 0x2000UL
1658	#define FUNC_QCAPS_RESP_FLAGS_GRE_TUN_FLAGS_SUPPORTED 0x4000UL
1659	#define FUNC_QCAPS_RESP_FLAGS_MPLS_TUN_FLAGS_SUPPORTED 0x8000UL
1660	#define FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED 0x10000UL
1661	#define FUNC_QCAPS_RESP_FLAGS_ADOPTED_PF_SUPPORTED 0x20000UL
1662	#define FUNC_QCAPS_RESP_FLAGS_ADMIN_PF_SUPPORTED 0x40000UL
1663	#define FUNC_QCAPS_RESP_FLAGS_LINK_ADMIN_STATUS_SUPPORTED 0x80000UL
1664	#define FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE 0x100000UL
1665	#define FUNC_QCAPS_RESP_FLAGS_DYNAMIC_TX_RING_ALLOC 0x200000UL
1666	#define FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE 0x400000UL
1667	#define FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE 0x800000UL
1668	#define FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED 0x1000000UL
1669	#define FUNC_QCAPS_RESP_FLAGS_ERR_RECOVER_RELOAD 0x2000000UL
1670	#define FUNC_QCAPS_RESP_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED 0x4000000UL
1671	#define FUNC_QCAPS_RESP_FLAGS_VLAN_ACCELERATION_TX_DISABLED 0x8000000UL
1672	#define FUNC_QCAPS_RESP_FLAGS_COREDUMP_CMD_SUPPORTED 0x10000000UL
1673	#define FUNC_QCAPS_RESP_FLAGS_CRASHDUMP_CMD_SUPPORTED 0x20000000UL
1674	#define FUNC_QCAPS_RESP_FLAGS_PFC_WD_STATS_SUPPORTED 0x40000000UL
1675	#define FUNC_QCAPS_RESP_FLAGS_DBG_QCAPS_CMD_SUPPORTED 0x80000000UL
1676	u8 mac_address[6];
1677	__le16 max_rsscos_ctx;
1678	__le16 max_cmpl_rings;
1679	__le16 max_tx_rings;
1680	__le16 max_rx_rings;
1681	__le16 max_l2_ctxs;
1682	__le16 max_vnics;
1683	__le16 first_vf_id;
1684	__le16 max_vfs;
1685	__le16 max_stat_ctx;
1686	__le32 max_encap_records;
1687	__le32 max_decap_records;
1688	__le32 max_tx_em_flows;
1689	__le32 max_tx_wm_flows;
1690	__le32 max_rx_em_flows;
1691	__le32 max_rx_wm_flows;
1692	__le32 max_mcast_filters;
1693	__le32 max_flow_id;
1694	__le32 max_hw_ring_grps;
1695	__le16 max_sp_tx_rings;
1696	__le16 max_msix_vfs;
1697	__le32 flags_ext;
1698	#define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_MARK_SUPPORTED 0x1UL
1699	#define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_STATS_SUPPORTED 0x2UL
1700	#define FUNC_QCAPS_RESP_FLAGS_EXT_EXT_HW_STATS_SUPPORTED 0x4UL
1701	#define FUNC_QCAPS_RESP_FLAGS_EXT_HOT_RESET_IF_SUPPORT 0x8UL
1702	#define FUNC_QCAPS_RESP_FLAGS_EXT_PROXY_MODE_SUPPORT 0x10UL
1703	#define FUNC_QCAPS_RESP_FLAGS_EXT_TX_PROXY_SRC_INTF_OVERRIDE_SUPPORT 0x20UL
1704	#define FUNC_QCAPS_RESP_FLAGS_EXT_SCHQ_SUPPORTED 0x40UL
1705	#define FUNC_QCAPS_RESP_FLAGS_EXT_PPP_PUSH_MODE_SUPPORTED 0x80UL
1706	#define FUNC_QCAPS_RESP_FLAGS_EXT_EVB_MODE_CFG_NOT_SUPPORTED 0x100UL
1707	#define FUNC_QCAPS_RESP_FLAGS_EXT_SOC_SPD_SUPPORTED 0x200UL
1708	#define FUNC_QCAPS_RESP_FLAGS_EXT_FW_LIVEPATCH_SUPPORTED 0x400UL
1709	#define FUNC_QCAPS_RESP_FLAGS_EXT_FAST_RESET_CAPABLE 0x800UL
1710	#define FUNC_QCAPS_RESP_FLAGS_EXT_TX_METADATA_CFG_CAPABLE 0x1000UL
1711	#define FUNC_QCAPS_RESP_FLAGS_EXT_NVM_OPTION_ACTION_SUPPORTED 0x2000UL
1712	#define FUNC_QCAPS_RESP_FLAGS_EXT_BD_METADATA_SUPPORTED 0x4000UL
1713	#define FUNC_QCAPS_RESP_FLAGS_EXT_ECHO_REQUEST_SUPPORTED 0x8000UL
1714	#define FUNC_QCAPS_RESP_FLAGS_EXT_NPAR_1_2_SUPPORTED 0x10000UL
1715	#define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_PTM_SUPPORTED 0x20000UL
1716	#define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_PPS_SUPPORTED 0x40000UL
1717	#define FUNC_QCAPS_RESP_FLAGS_EXT_VF_CFG_ASYNC_FOR_PF_SUPPORTED 0x80000UL
1718	#define FUNC_QCAPS_RESP_FLAGS_EXT_PARTITION_BW_SUPPORTED 0x100000UL
1719	#define FUNC_QCAPS_RESP_FLAGS_EXT_DFLT_VLAN_TPID_PCP_SUPPORTED 0x200000UL
1720	#define FUNC_QCAPS_RESP_FLAGS_EXT_KTLS_SUPPORTED 0x400000UL
1721	#define FUNC_QCAPS_RESP_FLAGS_EXT_EP_RATE_CONTROL 0x800000UL
1722	#define FUNC_QCAPS_RESP_FLAGS_EXT_MIN_BW_SUPPORTED 0x1000000UL
1723	#define FUNC_QCAPS_RESP_FLAGS_EXT_TX_COAL_CMPL_CAP 0x2000000UL
1724	#define FUNC_QCAPS_RESP_FLAGS_EXT_BS_V2_SUPPORTED 0x4000000UL
1725	#define FUNC_QCAPS_RESP_FLAGS_EXT_BS_V2_REQUIRED 0x8000000UL
1726	#define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_64BIT_RTC_SUPPORTED 0x10000000UL
1727	#define FUNC_QCAPS_RESP_FLAGS_EXT_DBR_PACING_SUPPORTED 0x20000000UL
1728	#define FUNC_QCAPS_RESP_FLAGS_EXT_HW_DBR_DROP_RECOV_SUPPORTED 0x40000000UL
1729	#define FUNC_QCAPS_RESP_FLAGS_EXT_DISABLE_CQ_OVERFLOW_DETECTION_SUPPORTED 0x80000000UL
1730	u8 max_schqs;
1731	u8 mpc_chnls_cap;
1732	#define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TCE 0x1UL
1733	#define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_RCE 0x2UL
1734	#define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TE_CFA 0x4UL
1735	#define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_RE_CFA 0x8UL
1736	#define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_PRIMATE 0x10UL
1737	__le16 max_key_ctxs_alloc;
1738	__le32 flags_ext2;
1739	#define FUNC_QCAPS_RESP_FLAGS_EXT2_RX_ALL_PKTS_TIMESTAMPS_SUPPORTED 0x1UL
1740	#define FUNC_QCAPS_RESP_FLAGS_EXT2_QUIC_SUPPORTED 0x2UL
1741	#define FUNC_QCAPS_RESP_FLAGS_EXT2_KDNET_SUPPORTED 0x4UL
1742	#define FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_EXT_SUPPORTED 0x8UL
1743	#define FUNC_QCAPS_RESP_FLAGS_EXT2_SW_DBR_DROP_RECOVERY_SUPPORTED 0x10UL
1744	#define FUNC_QCAPS_RESP_FLAGS_EXT2_GENERIC_STATS_SUPPORTED 0x20UL
1745	#define FUNC_QCAPS_RESP_FLAGS_EXT2_UDP_GSO_SUPPORTED 0x40UL
1746	#define FUNC_QCAPS_RESP_FLAGS_EXT2_SYNCE_SUPPORTED 0x80UL
1747	#define FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_V0_SUPPORTED 0x100UL
1748	#define FUNC_QCAPS_RESP_FLAGS_EXT2_TX_PKT_TS_CMPL_SUPPORTED 0x200UL
1749	#define FUNC_QCAPS_RESP_FLAGS_EXT2_HW_LAG_SUPPORTED 0x400UL
1750	#define FUNC_QCAPS_RESP_FLAGS_EXT2_ON_CHIP_CTX_SUPPORTED 0x800UL
1751	#define FUNC_QCAPS_RESP_FLAGS_EXT2_STEERING_TAG_SUPPORTED 0x1000UL
1752	#define FUNC_QCAPS_RESP_FLAGS_EXT2_ENHANCED_VF_SCALE_SUPPORTED 0x2000UL
1753	#define FUNC_QCAPS_RESP_FLAGS_EXT2_KEY_XID_PARTITION_SUPPORTED 0x4000UL
1754	__le16 tunnel_disable_flag;
1755	#define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_VXLAN 0x1UL
1756	#define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_NGE 0x2UL
1757	#define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_NVGRE 0x4UL
1758	#define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_L2GRE 0x8UL
1759	#define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_GRE 0x10UL
1760	#define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_IPINIP 0x20UL
1761	#define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_MPLS 0x40UL
1762	#define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_PPPOE 0x80UL
1763	u8 key_xid_partition_cap;
1764	#define FUNC_QCAPS_RESP_KEY_XID_PARTITION_CAP_TKC 0x1UL
1765	#define FUNC_QCAPS_RESP_KEY_XID_PARTITION_CAP_RKC 0x2UL
1766	#define FUNC_QCAPS_RESP_KEY_XID_PARTITION_CAP_QUIC_TKC 0x4UL
1767	#define FUNC_QCAPS_RESP_KEY_XID_PARTITION_CAP_QUIC_RKC 0x8UL
1768	u8 unused_1;
1769	u8 device_serial_number[8];
1770	__le16 ctxs_per_partition;
1771	u8 unused_2[5];
1772	u8 valid;
1773	};
1774
1775	/* hwrm_func_qcfg_input (size:192b/24B) */
1776	struct hwrm_func_qcfg_input {
1777	__le16 req_type;
1778	__le16 cmpl_ring;
1779	__le16 seq_id;
1780	__le16 target_id;
1781	__le64 resp_addr;
1782	__le16 fid;
1783	u8 unused_0[6];
1784	};
1785
1786	/* hwrm_func_qcfg_output (size:1024b/128B) */
1787	struct hwrm_func_qcfg_output {
1788	__le16 error_code;
1789	__le16 req_type;
1790	__le16 seq_id;
1791	__le16 resp_len;
1792	__le16 fid;
1793	__le16 port_id;
1794	__le16 vlan;
1795	__le16 flags;
1796	#define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED 0x1UL
1797	#define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED 0x2UL
1798	#define FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED 0x4UL
1799	#define FUNC_QCFG_RESP_FLAGS_STD_TX_RING_MODE_ENABLED 0x8UL
1800	#define FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED 0x10UL
1801	#define FUNC_QCFG_RESP_FLAGS_MULTI_HOST 0x20UL
1802	#define FUNC_QCFG_RESP_FLAGS_TRUSTED_VF 0x40UL
1803	#define FUNC_QCFG_RESP_FLAGS_SECURE_MODE_ENABLED 0x80UL
1804	#define FUNC_QCFG_RESP_FLAGS_PREBOOT_LEGACY_L2_RINGS 0x100UL
1805	#define FUNC_QCFG_RESP_FLAGS_HOT_RESET_ALLOWED 0x200UL
1806	#define FUNC_QCFG_RESP_FLAGS_PPP_PUSH_MODE_ENABLED 0x400UL
1807	#define FUNC_QCFG_RESP_FLAGS_RING_MONITOR_ENABLED 0x800UL
1808	#define FUNC_QCFG_RESP_FLAGS_FAST_RESET_ALLOWED 0x1000UL
1809	#define FUNC_QCFG_RESP_FLAGS_MULTI_ROOT 0x2000UL
1810	#define FUNC_QCFG_RESP_FLAGS_ENABLE_RDMA_SRIOV 0x4000UL
1811	u8 mac_address[6];
1812	__le16 pci_id;
1813	__le16 alloc_rsscos_ctx;
1814	__le16 alloc_cmpl_rings;
1815	__le16 alloc_tx_rings;
1816	__le16 alloc_rx_rings;
1817	__le16 alloc_l2_ctx;
1818	__le16 alloc_vnics;
1819	__le16 admin_mtu;
1820	__le16 mru;
1821	__le16 stat_ctx_id;
1822	u8 port_partition_type;
1823	#define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF 0x0UL
1824	#define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS 0x1UL
1825	#define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL
1826	#define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 0x3UL
1827	#define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 0x4UL
1828	#define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_2 0x5UL
1829	#define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 0xffUL
1830	#define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_LAST FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN
1831	u8 port_pf_cnt;
1832	#define FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 0x0UL
1833	#define FUNC_QCFG_RESP_PORT_PF_CNT_LAST FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL
1834	__le16 dflt_vnic_id;
1835	__le16 max_mtu_configured;
1836	__le32 min_bw;
1837	#define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_MASK 0xfffffffUL
1838	#define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_SFT 0
1839	#define FUNC_QCFG_RESP_MIN_BW_SCALE 0x10000000UL
1840	#define FUNC_QCFG_RESP_MIN_BW_SCALE_BITS (0x0UL << 28)
1841	#define FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES (0x1UL << 28)
1842	#define FUNC_QCFG_RESP_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES
1843	#define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
1844	#define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_SFT 29
1845	#define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
1846	#define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
1847	#define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
1848	#define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
1849	#define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
1850	#define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
1851	#define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID
1852	__le32 max_bw;
1853	#define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_MASK 0xfffffffUL
1854	#define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_SFT 0
1855	#define FUNC_QCFG_RESP_MAX_BW_SCALE 0x10000000UL
1856	#define FUNC_QCFG_RESP_MAX_BW_SCALE_BITS (0x0UL << 28)
1857	#define FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES (0x1UL << 28)
1858	#define FUNC_QCFG_RESP_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES
1859	#define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
1860	#define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_SFT 29
1861	#define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
1862	#define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
1863	#define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
1864	#define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
1865	#define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
1866	#define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
1867	#define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID
1868	u8 evb_mode;
1869	#define FUNC_QCFG_RESP_EVB_MODE_NO_EVB 0x0UL
1870	#define FUNC_QCFG_RESP_EVB_MODE_VEB 0x1UL
1871	#define FUNC_QCFG_RESP_EVB_MODE_VEPA 0x2UL
1872	#define FUNC_QCFG_RESP_EVB_MODE_LAST FUNC_QCFG_RESP_EVB_MODE_VEPA
1873	u8 options;
1874	#define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_MASK 0x3UL
1875	#define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SFT 0
1876	#define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL
1877	#define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL
1878	#define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_LAST FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128
1879	#define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL
1880	#define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_SFT 2
1881	#define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2)
1882	#define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2)
1883	#define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2)
1884	#define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO
1885	#define FUNC_QCFG_RESP_OPTIONS_RSVD_MASK 0xf0UL
1886	#define FUNC_QCFG_RESP_OPTIONS_RSVD_SFT 4
1887	__le16 alloc_vfs;
1888	__le32 alloc_mcast_filters;
1889	__le32 alloc_hw_ring_grps;
1890	__le16 alloc_sp_tx_rings;
1891	__le16 alloc_stat_ctx;
1892	__le16 alloc_msix;
1893	__le16 registered_vfs;
1894	__le16 l2_doorbell_bar_size_kb;
1895	u8 unused_1;
1896	u8 always_1;
1897	__le32 reset_addr_poll;
1898	__le16 legacy_l2_db_size_kb;
1899	__le16 svif_info;
1900	#define FUNC_QCFG_RESP_SVIF_INFO_SVIF_MASK 0x7fffUL
1901	#define FUNC_QCFG_RESP_SVIF_INFO_SVIF_SFT 0
1902	#define FUNC_QCFG_RESP_SVIF_INFO_SVIF_VALID 0x8000UL
1903	u8 mpc_chnls;
1904	#define FUNC_QCFG_RESP_MPC_CHNLS_TCE_ENABLED 0x1UL
1905	#define FUNC_QCFG_RESP_MPC_CHNLS_RCE_ENABLED 0x2UL
1906	#define FUNC_QCFG_RESP_MPC_CHNLS_TE_CFA_ENABLED 0x4UL
1907	#define FUNC_QCFG_RESP_MPC_CHNLS_RE_CFA_ENABLED 0x8UL
1908	#define FUNC_QCFG_RESP_MPC_CHNLS_PRIMATE_ENABLED 0x10UL
1909	u8 db_page_size;
1910	#define FUNC_QCFG_RESP_DB_PAGE_SIZE_4KB 0x0UL
1911	#define FUNC_QCFG_RESP_DB_PAGE_SIZE_8KB 0x1UL
1912	#define FUNC_QCFG_RESP_DB_PAGE_SIZE_16KB 0x2UL
1913	#define FUNC_QCFG_RESP_DB_PAGE_SIZE_32KB 0x3UL
1914	#define FUNC_QCFG_RESP_DB_PAGE_SIZE_64KB 0x4UL
1915	#define FUNC_QCFG_RESP_DB_PAGE_SIZE_128KB 0x5UL
1916	#define FUNC_QCFG_RESP_DB_PAGE_SIZE_256KB 0x6UL
1917	#define FUNC_QCFG_RESP_DB_PAGE_SIZE_512KB 0x7UL
1918	#define FUNC_QCFG_RESP_DB_PAGE_SIZE_1MB 0x8UL
1919	#define FUNC_QCFG_RESP_DB_PAGE_SIZE_2MB 0x9UL
1920	#define FUNC_QCFG_RESP_DB_PAGE_SIZE_4MB 0xaUL
1921	#define FUNC_QCFG_RESP_DB_PAGE_SIZE_LAST FUNC_QCFG_RESP_DB_PAGE_SIZE_4MB
1922	u8 unused_2[2];
1923	__le32 partition_min_bw;
1924	#define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_MASK 0xfffffffUL
1925	#define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_SFT 0
1926	#define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE 0x10000000UL
1927	#define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BITS (0x0UL << 28)
1928	#define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BYTES (0x1UL << 28)
1929	#define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BYTES
1930	#define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
1931	#define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_SFT 29
1932	#define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
1933	#define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100
1934	__le32 partition_max_bw;
1935	#define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_MASK 0xfffffffUL
1936	#define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_SFT 0
1937	#define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE 0x10000000UL
1938	#define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BITS (0x0UL << 28)
1939	#define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BYTES (0x1UL << 28)
1940	#define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BYTES
1941	#define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
1942	#define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_SFT 29
1943	#define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
1944	#define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100
1945	__le16 host_mtu;
1946	u8 unused_3[2];
1947	u8 unused_4[2];
1948	u8 port_kdnet_mode;
1949	#define FUNC_QCFG_RESP_PORT_KDNET_MODE_DISABLED 0x0UL
1950	#define FUNC_QCFG_RESP_PORT_KDNET_MODE_ENABLED 0x1UL
1951	#define FUNC_QCFG_RESP_PORT_KDNET_MODE_LAST FUNC_QCFG_RESP_PORT_KDNET_MODE_ENABLED
1952	u8 kdnet_pcie_function;
1953	__le16 port_kdnet_fid;
1954	u8 unused_5[2];
1955	__le32 alloc_tx_key_ctxs;
1956	__le32 alloc_rx_key_ctxs;
1957	u8 lag_id;
1958	u8 parif;
1959	u8 unused_6[5];
1960	u8 valid;
1961	};
1962
1963	/* hwrm_func_cfg_input (size:1088b/136B) */
1964	struct hwrm_func_cfg_input {
1965	__le16 req_type;
1966	__le16 cmpl_ring;
1967	__le16 seq_id;
1968	__le16 target_id;
1969	__le64 resp_addr;
1970	__le16 fid;
1971	__le16 num_msix;
1972	__le32 flags;
1973	#define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE 0x1UL
1974	#define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE 0x2UL
1975	#define FUNC_CFG_REQ_FLAGS_RSVD_MASK 0x1fcUL
1976	#define FUNC_CFG_REQ_FLAGS_RSVD_SFT 2
1977	#define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_ENABLE 0x200UL
1978	#define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_DISABLE 0x400UL
1979	#define FUNC_CFG_REQ_FLAGS_VIRT_MAC_PERSIST 0x800UL
1980	#define FUNC_CFG_REQ_FLAGS_NO_AUTOCLEAR_STATISTIC 0x1000UL
1981	#define FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x2000UL
1982	#define FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x4000UL
1983	#define FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x8000UL
1984	#define FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x10000UL
1985	#define FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x20000UL
1986	#define FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x40000UL
1987	#define FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x80000UL
1988	#define FUNC_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x100000UL
1989	#define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_ENABLE 0x200000UL
1990	#define FUNC_CFG_REQ_FLAGS_DYNAMIC_TX_RING_ALLOC 0x400000UL
1991	#define FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST 0x800000UL
1992	#define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_DISABLE 0x1000000UL
1993	#define FUNC_CFG_REQ_FLAGS_PREBOOT_LEGACY_L2_RINGS 0x2000000UL
1994	#define FUNC_CFG_REQ_FLAGS_HOT_RESET_IF_EN_DIS 0x4000000UL
1995	#define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_ENABLE 0x8000000UL
1996	#define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE 0x10000000UL
1997	#define FUNC_CFG_REQ_FLAGS_BD_METADATA_ENABLE 0x20000000UL
1998	#define FUNC_CFG_REQ_FLAGS_BD_METADATA_DISABLE 0x40000000UL
1999	#define FUNC_CFG_REQ_FLAGS_KEY_CTX_ASSETS_TEST 0x80000000UL
2000	__le32 enables;
2001	#define FUNC_CFG_REQ_ENABLES_ADMIN_MTU 0x1UL
2002	#define FUNC_CFG_REQ_ENABLES_MRU 0x2UL
2003	#define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL
2004	#define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL
2005	#define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL
2006	#define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL
2007	#define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS 0x40UL
2008	#define FUNC_CFG_REQ_ENABLES_NUM_VNICS 0x80UL
2009	#define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL
2010	#define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x200UL
2011	#define FUNC_CFG_REQ_ENABLES_DFLT_VLAN 0x400UL
2012	#define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR 0x800UL
2013	#define FUNC_CFG_REQ_ENABLES_MIN_BW 0x1000UL
2014	#define FUNC_CFG_REQ_ENABLES_MAX_BW 0x2000UL
2015	#define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL
2016	#define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE 0x8000UL
2017	#define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS 0x10000UL
2018	#define FUNC_CFG_REQ_ENABLES_EVB_MODE 0x20000UL
2019	#define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL
2020	#define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL
2021	#define FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE 0x100000UL
2022	#define FUNC_CFG_REQ_ENABLES_NUM_MSIX 0x200000UL
2023	#define FUNC_CFG_REQ_ENABLES_ADMIN_LINK_STATE 0x400000UL
2024	#define FUNC_CFG_REQ_ENABLES_HOT_RESET_IF_SUPPORT 0x800000UL
2025	#define FUNC_CFG_REQ_ENABLES_SCHQ_ID 0x1000000UL
2026	#define FUNC_CFG_REQ_ENABLES_MPC_CHNLS 0x2000000UL
2027	#define FUNC_CFG_REQ_ENABLES_PARTITION_MIN_BW 0x4000000UL
2028	#define FUNC_CFG_REQ_ENABLES_PARTITION_MAX_BW 0x8000000UL
2029	#define FUNC_CFG_REQ_ENABLES_TPID 0x10000000UL
2030	#define FUNC_CFG_REQ_ENABLES_HOST_MTU 0x20000000UL
2031	#define FUNC_CFG_REQ_ENABLES_TX_KEY_CTXS 0x40000000UL
2032	#define FUNC_CFG_REQ_ENABLES_RX_KEY_CTXS 0x80000000UL
2033	__le16 admin_mtu;
2034	__le16 mru;
2035	__le16 num_rsscos_ctxs;
2036	__le16 num_cmpl_rings;
2037	__le16 num_tx_rings;
2038	__le16 num_rx_rings;
2039	__le16 num_l2_ctxs;
2040	__le16 num_vnics;
2041	__le16 num_stat_ctxs;
2042	__le16 num_hw_ring_grps;
2043	u8 dflt_mac_addr[6];
2044	__le16 dflt_vlan;
2045	__be32 dflt_ip_addr[4];
2046	__le32 min_bw;
2047	#define FUNC_CFG_REQ_MIN_BW_BW_VALUE_MASK 0xfffffffUL
2048	#define FUNC_CFG_REQ_MIN_BW_BW_VALUE_SFT 0
2049	#define FUNC_CFG_REQ_MIN_BW_SCALE 0x10000000UL
2050	#define FUNC_CFG_REQ_MIN_BW_SCALE_BITS (0x0UL << 28)
2051	#define FUNC_CFG_REQ_MIN_BW_SCALE_BYTES (0x1UL << 28)
2052	#define FUNC_CFG_REQ_MIN_BW_SCALE_LAST FUNC_CFG_REQ_MIN_BW_SCALE_BYTES
2053	#define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
2054	#define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_SFT 29
2055	#define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
2056	#define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
2057	#define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
2058	#define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
2059	#define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
2060	#define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
2061	#define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID
2062	__le32 max_bw;
2063	#define FUNC_CFG_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL
2064	#define FUNC_CFG_REQ_MAX_BW_BW_VALUE_SFT 0
2065	#define FUNC_CFG_REQ_MAX_BW_SCALE 0x10000000UL
2066	#define FUNC_CFG_REQ_MAX_BW_SCALE_BITS (0x0UL << 28)
2067	#define FUNC_CFG_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28)
2068	#define FUNC_CFG_REQ_MAX_BW_SCALE_LAST FUNC_CFG_REQ_MAX_BW_SCALE_BYTES
2069	#define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
2070	#define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29
2071	#define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
2072	#define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
2073	#define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
2074	#define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
2075	#define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
2076	#define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
2077	#define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID
2078	__le16 async_event_cr;
2079	u8 vlan_antispoof_mode;
2080	#define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK 0x0UL
2081	#define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN 0x1UL
2082	#define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE 0x2UL
2083	#define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 0x3UL
2084	#define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_LAST FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN
2085	u8 allowed_vlan_pris;
2086	u8 evb_mode;
2087	#define FUNC_CFG_REQ_EVB_MODE_NO_EVB 0x0UL
2088	#define FUNC_CFG_REQ_EVB_MODE_VEB 0x1UL
2089	#define FUNC_CFG_REQ_EVB_MODE_VEPA 0x2UL
2090	#define FUNC_CFG_REQ_EVB_MODE_LAST FUNC_CFG_REQ_EVB_MODE_VEPA
2091	u8 options;
2092	#define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_MASK 0x3UL
2093	#define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SFT 0
2094	#define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL
2095	#define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL
2096	#define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_LAST FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128
2097	#define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL
2098	#define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_SFT 2
2099	#define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2)
2100	#define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2)
2101	#define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2)
2102	#define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO
2103	#define FUNC_CFG_REQ_OPTIONS_RSVD_MASK 0xf0UL
2104	#define FUNC_CFG_REQ_OPTIONS_RSVD_SFT 4
2105	__le16 num_mcast_filters;
2106	__le16 schq_id;
2107	__le16 mpc_chnls;
2108	#define FUNC_CFG_REQ_MPC_CHNLS_TCE_ENABLE 0x1UL
2109	#define FUNC_CFG_REQ_MPC_CHNLS_TCE_DISABLE 0x2UL
2110	#define FUNC_CFG_REQ_MPC_CHNLS_RCE_ENABLE 0x4UL
2111	#define FUNC_CFG_REQ_MPC_CHNLS_RCE_DISABLE 0x8UL
2112	#define FUNC_CFG_REQ_MPC_CHNLS_TE_CFA_ENABLE 0x10UL
2113	#define FUNC_CFG_REQ_MPC_CHNLS_TE_CFA_DISABLE 0x20UL
2114	#define FUNC_CFG_REQ_MPC_CHNLS_RE_CFA_ENABLE 0x40UL
2115	#define FUNC_CFG_REQ_MPC_CHNLS_RE_CFA_DISABLE 0x80UL
2116	#define FUNC_CFG_REQ_MPC_CHNLS_PRIMATE_ENABLE 0x100UL
2117	#define FUNC_CFG_REQ_MPC_CHNLS_PRIMATE_DISABLE 0x200UL
2118	__le32 partition_min_bw;
2119	#define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_MASK 0xfffffffUL
2120	#define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_SFT 0
2121	#define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE 0x10000000UL
2122	#define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BITS (0x0UL << 28)
2123	#define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BYTES (0x1UL << 28)
2124	#define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_LAST FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BYTES
2125	#define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
2126	#define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_SFT 29
2127	#define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
2128	#define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100
2129	__le32 partition_max_bw;
2130	#define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_MASK 0xfffffffUL
2131	#define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_SFT 0
2132	#define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE 0x10000000UL
2133	#define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BITS (0x0UL << 28)
2134	#define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BYTES (0x1UL << 28)
2135	#define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_LAST FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BYTES
2136	#define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
2137	#define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_SFT 29
2138	#define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
2139	#define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100
2140	__be16 tpid;
2141	__le16 host_mtu;
2142	u8 unused_0[4];
2143	__le32 enables2;
2144	#define FUNC_CFG_REQ_ENABLES2_KDNET 0x1UL
2145	#define FUNC_CFG_REQ_ENABLES2_DB_PAGE_SIZE 0x2UL
2146	u8 port_kdnet_mode;
2147	#define FUNC_CFG_REQ_PORT_KDNET_MODE_DISABLED 0x0UL
2148	#define FUNC_CFG_REQ_PORT_KDNET_MODE_ENABLED 0x1UL
2149	#define FUNC_CFG_REQ_PORT_KDNET_MODE_LAST FUNC_CFG_REQ_PORT_KDNET_MODE_ENABLED
2150	u8 db_page_size;
2151	#define FUNC_CFG_REQ_DB_PAGE_SIZE_4KB 0x0UL
2152	#define FUNC_CFG_REQ_DB_PAGE_SIZE_8KB 0x1UL
2153	#define FUNC_CFG_REQ_DB_PAGE_SIZE_16KB 0x2UL
2154	#define FUNC_CFG_REQ_DB_PAGE_SIZE_32KB 0x3UL
2155	#define FUNC_CFG_REQ_DB_PAGE_SIZE_64KB 0x4UL
2156	#define FUNC_CFG_REQ_DB_PAGE_SIZE_128KB 0x5UL
2157	#define FUNC_CFG_REQ_DB_PAGE_SIZE_256KB 0x6UL
2158	#define FUNC_CFG_REQ_DB_PAGE_SIZE_512KB 0x7UL
2159	#define FUNC_CFG_REQ_DB_PAGE_SIZE_1MB 0x8UL
2160	#define FUNC_CFG_REQ_DB_PAGE_SIZE_2MB 0x9UL
2161	#define FUNC_CFG_REQ_DB_PAGE_SIZE_4MB 0xaUL
2162	#define FUNC_CFG_REQ_DB_PAGE_SIZE_LAST FUNC_CFG_REQ_DB_PAGE_SIZE_4MB
2163	u8 unused_1[2];
2164	__le32 num_ktls_tx_key_ctxs;
2165	__le32 num_ktls_rx_key_ctxs;
2166	__le32 num_quic_tx_key_ctxs;
2167	__le32 num_quic_rx_key_ctxs;
2168	__le32 unused_2;
2169	};
2170
2171	/* hwrm_func_cfg_output (size:128b/16B) */
2172	struct hwrm_func_cfg_output {
2173	__le16 error_code;
2174	__le16 req_type;
2175	__le16 seq_id;
2176	__le16 resp_len;
2177	u8 unused_0[7];
2178	u8 valid;
2179	};
2180
2181	/* hwrm_func_cfg_cmd_err (size:64b/8B) */
2182	struct hwrm_func_cfg_cmd_err {
2183	u8 code;
2184	#define FUNC_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL
2185	#define FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_BW_RANGE 0x1UL
2186	#define FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_MORE_THAN_MAX 0x2UL
2187	#define FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_BW_UNSUPPORTED 0x3UL
2188	#define FUNC_CFG_CMD_ERR_CODE_PARTITION_BW_PERCENT 0x4UL
2189	#define FUNC_CFG_CMD_ERR_CODE_LAST FUNC_CFG_CMD_ERR_CODE_PARTITION_BW_PERCENT
2190	u8 unused_0[7];
2191	};
2192
2193	/* hwrm_func_qstats_input (size:192b/24B) */
2194	struct hwrm_func_qstats_input {
2195	__le16 req_type;
2196	__le16 cmpl_ring;
2197	__le16 seq_id;
2198	__le16 target_id;
2199	__le64 resp_addr;
2200	__le16 fid;
2201	u8 flags;
2202	#define FUNC_QSTATS_REQ_FLAGS_ROCE_ONLY 0x1UL
2203	#define FUNC_QSTATS_REQ_FLAGS_COUNTER_MASK 0x2UL
2204	#define FUNC_QSTATS_REQ_FLAGS_L2_ONLY 0x4UL
2205	u8 unused_0[5];
2206	};
2207
2208	/* hwrm_func_qstats_output (size:1408b/176B) */
2209	struct hwrm_func_qstats_output {
2210	__le16 error_code;
2211	__le16 req_type;
2212	__le16 seq_id;
2213	__le16 resp_len;
2214	__le64 tx_ucast_pkts;
2215	__le64 tx_mcast_pkts;
2216	__le64 tx_bcast_pkts;
2217	__le64 tx_discard_pkts;
2218	__le64 tx_drop_pkts;
2219	__le64 tx_ucast_bytes;
2220	__le64 tx_mcast_bytes;
2221	__le64 tx_bcast_bytes;
2222	__le64 rx_ucast_pkts;
2223	__le64 rx_mcast_pkts;
2224	__le64 rx_bcast_pkts;
2225	__le64 rx_discard_pkts;
2226	__le64 rx_drop_pkts;
2227	__le64 rx_ucast_bytes;
2228	__le64 rx_mcast_bytes;
2229	__le64 rx_bcast_bytes;
2230	__le64 rx_agg_pkts;
2231	__le64 rx_agg_bytes;
2232	__le64 rx_agg_events;
2233	__le64 rx_agg_aborts;
2234	u8 clear_seq;
2235	u8 unused_0[6];
2236	u8 valid;
2237	};
2238
2239	/* hwrm_func_qstats_ext_input (size:256b/32B) */
2240	struct hwrm_func_qstats_ext_input {
2241	__le16 req_type;
2242	__le16 cmpl_ring;
2243	__le16 seq_id;
2244	__le16 target_id;
2245	__le64 resp_addr;
2246	__le16 fid;
2247	u8 flags;
2248	#define FUNC_QSTATS_EXT_REQ_FLAGS_ROCE_ONLY 0x1UL
2249	#define FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 0x2UL
2250	u8 unused_0[1];
2251	__le32 enables;
2252	#define FUNC_QSTATS_EXT_REQ_ENABLES_SCHQ_ID 0x1UL
2253	__le16 schq_id;
2254	__le16 traffic_class;
2255	u8 unused_1[4];
2256	};
2257
2258	/* hwrm_func_qstats_ext_output (size:1536b/192B) */
2259	struct hwrm_func_qstats_ext_output {
2260	__le16 error_code;
2261	__le16 req_type;
2262	__le16 seq_id;
2263	__le16 resp_len;
2264	__le64 rx_ucast_pkts;
2265	__le64 rx_mcast_pkts;
2266	__le64 rx_bcast_pkts;
2267	__le64 rx_discard_pkts;
2268	__le64 rx_error_pkts;
2269	__le64 rx_ucast_bytes;
2270	__le64 rx_mcast_bytes;
2271	__le64 rx_bcast_bytes;
2272	__le64 tx_ucast_pkts;
2273	__le64 tx_mcast_pkts;
2274	__le64 tx_bcast_pkts;
2275	__le64 tx_error_pkts;
2276	__le64 tx_discard_pkts;
2277	__le64 tx_ucast_bytes;
2278	__le64 tx_mcast_bytes;
2279	__le64 tx_bcast_bytes;
2280	__le64 rx_tpa_eligible_pkt;
2281	__le64 rx_tpa_eligible_bytes;
2282	__le64 rx_tpa_pkt;
2283	__le64 rx_tpa_bytes;
2284	__le64 rx_tpa_errors;
2285	__le64 rx_tpa_events;
2286	u8 unused_0[7];
2287	u8 valid;
2288	};
2289
2290	/* hwrm_func_clr_stats_input (size:192b/24B) */
2291	struct hwrm_func_clr_stats_input {
2292	__le16 req_type;
2293	__le16 cmpl_ring;
2294	__le16 seq_id;
2295	__le16 target_id;
2296	__le64 resp_addr;
2297	__le16 fid;
2298	u8 unused_0[6];
2299	};
2300
2301	/* hwrm_func_clr_stats_output (size:128b/16B) */
2302	struct hwrm_func_clr_stats_output {
2303	__le16 error_code;
2304	__le16 req_type;
2305	__le16 seq_id;
2306	__le16 resp_len;
2307	u8 unused_0[7];
2308	u8 valid;
2309	};
2310
2311	/* hwrm_func_vf_resc_free_input (size:192b/24B) */
2312	struct hwrm_func_vf_resc_free_input {
2313	__le16 req_type;
2314	__le16 cmpl_ring;
2315	__le16 seq_id;
2316	__le16 target_id;
2317	__le64 resp_addr;
2318	__le16 vf_id;
2319	u8 unused_0[6];
2320	};
2321
2322	/* hwrm_func_vf_resc_free_output (size:128b/16B) */
2323	struct hwrm_func_vf_resc_free_output {
2324	__le16 error_code;
2325	__le16 req_type;
2326	__le16 seq_id;
2327	__le16 resp_len;
2328	u8 unused_0[7];
2329	u8 valid;
2330	};
2331
2332	/* hwrm_func_drv_rgtr_input (size:896b/112B) */
2333	struct hwrm_func_drv_rgtr_input {
2334	__le16 req_type;
2335	__le16 cmpl_ring;
2336	__le16 seq_id;
2337	__le16 target_id;
2338	__le64 resp_addr;
2339	__le32 flags;
2340	#define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL
2341	#define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL
2342	#define FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE 0x4UL
2343	#define FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE 0x8UL
2344	#define FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT 0x10UL
2345	#define FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT 0x20UL
2346	#define FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT 0x40UL
2347	#define FUNC_DRV_RGTR_REQ_FLAGS_FAST_RESET_SUPPORT 0x80UL
2348	#define FUNC_DRV_RGTR_REQ_FLAGS_RSS_STRICT_HASH_TYPE_SUPPORT 0x100UL
2349	#define FUNC_DRV_RGTR_REQ_FLAGS_NPAR_1_2_SUPPORT 0x200UL
2350	#define FUNC_DRV_RGTR_REQ_FLAGS_ASYM_QUEUE_CFG_SUPPORT 0x400UL
2351	__le32 enables;
2352	#define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL
2353	#define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL
2354	#define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP 0x4UL
2355	#define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD 0x8UL
2356	#define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL
2357	__le16 os_type;
2358	#define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN 0x0UL
2359	#define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER 0x1UL
2360	#define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS 0xeUL
2361	#define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS 0x12UL
2362	#define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS 0x1dUL
2363	#define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX 0x24UL
2364	#define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD 0x2aUL
2365	#define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI 0x68UL
2366	#define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864 0x73UL
2367	#define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 0x74UL
2368	#define FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 0x8000UL
2369	#define FUNC_DRV_RGTR_REQ_OS_TYPE_LAST FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI
2370	u8 ver_maj_8b;
2371	u8 ver_min_8b;
2372	u8 ver_upd_8b;
2373	u8 unused_0[3];
2374	__le32 timestamp;
2375	u8 unused_1[4];
2376	__le32 vf_req_fwd[8];
2377	__le32 async_event_fwd[8];
2378	__le16 ver_maj;
2379	__le16 ver_min;
2380	__le16 ver_upd;
2381	__le16 ver_patch;
2382	};
2383
2384	/* hwrm_func_drv_rgtr_output (size:128b/16B) */
2385	struct hwrm_func_drv_rgtr_output {
2386	__le16 error_code;
2387	__le16 req_type;
2388	__le16 seq_id;
2389	__le16 resp_len;
2390	__le32 flags;
2391	#define FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED 0x1UL
2392	u8 unused_0[3];
2393	u8 valid;
2394	};
2395
2396	/* hwrm_func_drv_unrgtr_input (size:192b/24B) */
2397	struct hwrm_func_drv_unrgtr_input {
2398	__le16 req_type;
2399	__le16 cmpl_ring;
2400	__le16 seq_id;
2401	__le16 target_id;
2402	__le64 resp_addr;
2403	__le32 flags;
2404	#define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL
2405	u8 unused_0[4];
2406	};
2407
2408	/* hwrm_func_drv_unrgtr_output (size:128b/16B) */
2409	struct hwrm_func_drv_unrgtr_output {
2410	__le16 error_code;
2411	__le16 req_type;
2412	__le16 seq_id;
2413	__le16 resp_len;
2414	u8 unused_0[7];
2415	u8 valid;
2416	};
2417
2418	/* hwrm_func_buf_rgtr_input (size:1024b/128B) */
2419	struct hwrm_func_buf_rgtr_input {
2420	__le16 req_type;
2421	__le16 cmpl_ring;
2422	__le16 seq_id;
2423	__le16 target_id;
2424	__le64 resp_addr;
2425	__le32 enables;
2426	#define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID 0x1UL
2427	#define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR 0x2UL
2428	__le16 vf_id;
2429	__le16 req_buf_num_pages;
2430	__le16 req_buf_page_size;
2431	#define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B 0x4UL
2432	#define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K 0xcUL
2433	#define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K 0xdUL
2434	#define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K 0x10UL
2435	#define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M 0x15UL
2436	#define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M 0x16UL
2437	#define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 0x1eUL
2438	#define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_LAST FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G
2439	__le16 req_buf_len;
2440	__le16 resp_buf_len;
2441	u8 unused_0[2];
2442	__le64 req_buf_page_addr0;
2443	__le64 req_buf_page_addr1;
2444	__le64 req_buf_page_addr2;
2445	__le64 req_buf_page_addr3;
2446	__le64 req_buf_page_addr4;
2447	__le64 req_buf_page_addr5;
2448	__le64 req_buf_page_addr6;
2449	__le64 req_buf_page_addr7;
2450	__le64 req_buf_page_addr8;
2451	__le64 req_buf_page_addr9;
2452	__le64 error_buf_addr;
2453	__le64 resp_buf_addr;
2454	};
2455
2456	/* hwrm_func_buf_rgtr_output (size:128b/16B) */
2457	struct hwrm_func_buf_rgtr_output {
2458	__le16 error_code;
2459	__le16 req_type;
2460	__le16 seq_id;
2461	__le16 resp_len;
2462	u8 unused_0[7];
2463	u8 valid;
2464	};
2465
2466	/* hwrm_func_drv_qver_input (size:192b/24B) */
2467	struct hwrm_func_drv_qver_input {
2468	__le16 req_type;
2469	__le16 cmpl_ring;
2470	__le16 seq_id;
2471	__le16 target_id;
2472	__le64 resp_addr;
2473	__le32 reserved;
2474	__le16 fid;
2475	u8 driver_type;
2476	#define FUNC_DRV_QVER_REQ_DRIVER_TYPE_L2 0x0UL
2477	#define FUNC_DRV_QVER_REQ_DRIVER_TYPE_ROCE 0x1UL
2478	#define FUNC_DRV_QVER_REQ_DRIVER_TYPE_LAST FUNC_DRV_QVER_REQ_DRIVER_TYPE_ROCE
2479	u8 unused_0;
2480	};
2481
2482	/* hwrm_func_drv_qver_output (size:256b/32B) */
2483	struct hwrm_func_drv_qver_output {
2484	__le16 error_code;
2485	__le16 req_type;
2486	__le16 seq_id;
2487	__le16 resp_len;
2488	__le16 os_type;
2489	#define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN 0x0UL
2490	#define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER 0x1UL
2491	#define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS 0xeUL
2492	#define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS 0x12UL
2493	#define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS 0x1dUL
2494	#define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX 0x24UL
2495	#define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD 0x2aUL
2496	#define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI 0x68UL
2497	#define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864 0x73UL
2498	#define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 0x74UL
2499	#define FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 0x8000UL
2500	#define FUNC_DRV_QVER_RESP_OS_TYPE_LAST FUNC_DRV_QVER_RESP_OS_TYPE_UEFI
2501	u8 ver_maj_8b;
2502	u8 ver_min_8b;
2503	u8 ver_upd_8b;
2504	u8 unused_0[3];
2505	__le16 ver_maj;
2506	__le16 ver_min;
2507	__le16 ver_upd;
2508	__le16 ver_patch;
2509	u8 unused_1[7];
2510	u8 valid;
2511	};
2512
2513	/* hwrm_func_resource_qcaps_input (size:192b/24B) */
2514	struct hwrm_func_resource_qcaps_input {
2515	__le16 req_type;
2516	__le16 cmpl_ring;
2517	__le16 seq_id;
2518	__le16 target_id;
2519	__le64 resp_addr;
2520	__le16 fid;
2521	u8 unused_0[6];
2522	};
2523
2524	/* hwrm_func_resource_qcaps_output (size:704b/88B) */
2525	struct hwrm_func_resource_qcaps_output {
2526	__le16 error_code;
2527	__le16 req_type;
2528	__le16 seq_id;
2529	__le16 resp_len;
2530	__le16 max_vfs;
2531	__le16 max_msix;
2532	__le16 vf_reservation_strategy;
2533	#define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MAXIMAL 0x0UL
2534	#define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL 0x1UL
2535	#define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 0x2UL
2536	#define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_LAST FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC
2537	__le16 min_rsscos_ctx;
2538	__le16 max_rsscos_ctx;
2539	__le16 min_cmpl_rings;
2540	__le16 max_cmpl_rings;
2541	__le16 min_tx_rings;
2542	__le16 max_tx_rings;
2543	__le16 min_rx_rings;
2544	__le16 max_rx_rings;
2545	__le16 min_l2_ctxs;
2546	__le16 max_l2_ctxs;
2547	__le16 min_vnics;
2548	__le16 max_vnics;
2549	__le16 min_stat_ctx;
2550	__le16 max_stat_ctx;
2551	__le16 min_hw_ring_grps;
2552	__le16 max_hw_ring_grps;
2553	__le16 max_tx_scheduler_inputs;
2554	__le16 flags;
2555	#define FUNC_RESOURCE_QCAPS_RESP_FLAGS_MIN_GUARANTEED 0x1UL
2556	__le16 min_msix;
2557	__le32 min_ktls_tx_key_ctxs;
2558	__le32 max_ktls_tx_key_ctxs;
2559	__le32 min_ktls_rx_key_ctxs;
2560	__le32 max_ktls_rx_key_ctxs;
2561	__le32 min_quic_tx_key_ctxs;
2562	__le32 max_quic_tx_key_ctxs;
2563	__le32 min_quic_rx_key_ctxs;
2564	__le32 max_quic_rx_key_ctxs;
2565	u8 unused_0[3];
2566	u8 valid;
2567	};
2568
2569	/* hwrm_func_vf_resource_cfg_input (size:704b/88B) */
2570	struct hwrm_func_vf_resource_cfg_input {
2571	__le16 req_type;
2572	__le16 cmpl_ring;
2573	__le16 seq_id;
2574	__le16 target_id;
2575	__le64 resp_addr;
2576	__le16 vf_id;
2577	__le16 max_msix;
2578	__le16 min_rsscos_ctx;
2579	__le16 max_rsscos_ctx;
2580	__le16 min_cmpl_rings;
2581	__le16 max_cmpl_rings;
2582	__le16 min_tx_rings;
2583	__le16 max_tx_rings;
2584	__le16 min_rx_rings;
2585	__le16 max_rx_rings;
2586	__le16 min_l2_ctxs;
2587	__le16 max_l2_ctxs;
2588	__le16 min_vnics;
2589	__le16 max_vnics;
2590	__le16 min_stat_ctx;
2591	__le16 max_stat_ctx;
2592	__le16 min_hw_ring_grps;
2593	__le16 max_hw_ring_grps;
2594	__le16 flags;
2595	#define FUNC_VF_RESOURCE_CFG_REQ_FLAGS_MIN_GUARANTEED 0x1UL
2596	__le16 min_msix;
2597	__le32 min_ktls_tx_key_ctxs;
2598	__le32 max_ktls_tx_key_ctxs;
2599	__le32 min_ktls_rx_key_ctxs;
2600	__le32 max_ktls_rx_key_ctxs;
2601	__le32 min_quic_tx_key_ctxs;
2602	__le32 max_quic_tx_key_ctxs;
2603	__le32 min_quic_rx_key_ctxs;
2604	__le32 max_quic_rx_key_ctxs;
2605	};
2606
2607	/* hwrm_func_vf_resource_cfg_output (size:320b/40B) */
2608	struct hwrm_func_vf_resource_cfg_output {
2609	__le16 error_code;
2610	__le16 req_type;
2611	__le16 seq_id;
2612	__le16 resp_len;
2613	__le16 reserved_rsscos_ctx;
2614	__le16 reserved_cmpl_rings;
2615	__le16 reserved_tx_rings;
2616	__le16 reserved_rx_rings;
2617	__le16 reserved_l2_ctxs;
2618	__le16 reserved_vnics;
2619	__le16 reserved_stat_ctx;
2620	__le16 reserved_hw_ring_grps;
2621	__le32 reserved_tx_key_ctxs;
2622	__le32 reserved_rx_key_ctxs;
2623	u8 unused_0[7];
2624	u8 valid;
2625	};
2626
2627	/* hwrm_func_backing_store_qcaps_input (size:128b/16B) */
2628	struct hwrm_func_backing_store_qcaps_input {
2629	__le16 req_type;
2630	__le16 cmpl_ring;
2631	__le16 seq_id;
2632	__le16 target_id;
2633	__le64 resp_addr;
2634	};
2635
2636	/* hwrm_func_backing_store_qcaps_output (size:832b/104B) */
2637	struct hwrm_func_backing_store_qcaps_output {
2638	__le16 error_code;
2639	__le16 req_type;
2640	__le16 seq_id;
2641	__le16 resp_len;
2642	__le32 qp_max_entries;
2643	__le16 qp_min_qp1_entries;
2644	__le16 qp_max_l2_entries;
2645	__le16 qp_entry_size;
2646	__le16 srq_max_l2_entries;
2647	__le32 srq_max_entries;
2648	__le16 srq_entry_size;
2649	__le16 cq_max_l2_entries;
2650	__le32 cq_max_entries;
2651	__le16 cq_entry_size;
2652	__le16 vnic_max_vnic_entries;
2653	__le16 vnic_max_ring_table_entries;
2654	__le16 vnic_entry_size;
2655	__le32 stat_max_entries;
2656	__le16 stat_entry_size;
2657	__le16 tqm_entry_size;
2658	__le32 tqm_min_entries_per_ring;
2659	__le32 tqm_max_entries_per_ring;
2660	__le32 mrav_max_entries;
2661	__le16 mrav_entry_size;
2662	__le16 tim_entry_size;
2663	__le32 tim_max_entries;
2664	__le16 mrav_num_entries_units;
2665	u8 tqm_entries_multiple;
2666	u8 ctx_kind_initializer;
2667	__le16 ctx_init_mask;
2668	#define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_QP 0x1UL
2669	#define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_SRQ 0x2UL
2670	#define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_CQ 0x4UL
2671	#define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_VNIC 0x8UL
2672	#define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_STAT 0x10UL
2673	#define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_MRAV 0x20UL
2674	#define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_TKC 0x40UL
2675	#define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_RKC 0x80UL
2676	u8 qp_init_offset;
2677	u8 srq_init_offset;
2678	u8 cq_init_offset;
2679	u8 vnic_init_offset;
2680	u8 tqm_fp_rings_count;
2681	u8 stat_init_offset;
2682	u8 mrav_init_offset;
2683	u8 tqm_fp_rings_count_ext;
2684	u8 tkc_init_offset;
2685	u8 rkc_init_offset;
2686	__le16 tkc_entry_size;
2687	__le16 rkc_entry_size;
2688	__le32 tkc_max_entries;
2689	__le32 rkc_max_entries;
2690	__le16 fast_qpmd_qp_num_entries;
2691	u8 rsvd1[5];
2692	u8 valid;
2693	};
2694
2695	/* tqm_fp_ring_cfg (size:128b/16B) */
2696	struct tqm_fp_ring_cfg {
2697	u8 tqm_ring_pg_size_tqm_ring_lvl;
2698	#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_MASK 0xfUL
2699	#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_SFT 0
2700	#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_0 0x0UL
2701	#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_1 0x1UL
2702	#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2 0x2UL
2703	#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LAST TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2
2704	#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_MASK 0xf0UL
2705	#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_SFT 4
2706	#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4)
2707	#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4)
2708	#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4)
2709	#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4)
2710	#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4)
2711	#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4)
2712	#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_LAST TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G
2713	u8 unused[3];
2714	__le32 tqm_ring_num_entries;
2715	__le64 tqm_ring_page_dir;
2716	};
2717
2718	/* hwrm_func_backing_store_cfg_input (size:2688b/336B) */
2719	struct hwrm_func_backing_store_cfg_input {
2720	__le16 req_type;
2721	__le16 cmpl_ring;
2722	__le16 seq_id;
2723	__le16 target_id;
2724	__le64 resp_addr;
2725	__le32 flags;
2726	#define FUNC_BACKING_STORE_CFG_REQ_FLAGS_PREBOOT_MODE 0x1UL
2727	#define FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT 0x2UL
2728	__le32 enables;
2729	#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP 0x1UL
2730	#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ 0x2UL
2731	#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ 0x4UL
2732	#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC 0x8UL
2733	#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT 0x10UL
2734	#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP 0x20UL
2735	#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING0 0x40UL
2736	#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING1 0x80UL
2737	#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING2 0x100UL
2738	#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING3 0x200UL
2739	#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING4 0x400UL
2740	#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING5 0x800UL
2741	#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING6 0x1000UL
2742	#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING7 0x2000UL
2743	#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV 0x4000UL
2744	#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM 0x8000UL
2745	#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING8 0x10000UL
2746	#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING9 0x20000UL
2747	#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING10 0x40000UL
2748	#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TKC 0x80000UL
2749	#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_RKC 0x100000UL
2750	#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP_FAST_QPMD 0x200000UL
2751	u8 qpc_pg_size_qpc_lvl;
2752	#define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_MASK 0xfUL
2753	#define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_SFT 0
2754	#define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_0 0x0UL
2755	#define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_1 0x1UL
2756	#define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 0x2UL
2757	#define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2
2758	#define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_MASK 0xf0UL
2759	#define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_SFT 4
2760	#define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K (0x0UL << 4)
2761	#define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8K (0x1UL << 4)
2762	#define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K (0x2UL << 4)
2763	#define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_2M (0x3UL << 4)
2764	#define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8M (0x4UL << 4)
2765	#define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G (0x5UL << 4)
2766	#define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G
2767	u8 srq_pg_size_srq_lvl;
2768	#define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_MASK 0xfUL
2769	#define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_SFT 0
2770	#define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_0 0x0UL
2771	#define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_1 0x1UL
2772	#define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 0x2UL
2773	#define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2
2774	#define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_MASK 0xf0UL
2775	#define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_SFT 4
2776	#define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_4K (0x0UL << 4)
2777	#define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K (0x1UL << 4)
2778	#define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_64K (0x2UL << 4)
2779	#define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_2M (0x3UL << 4)
2780	#define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8M (0x4UL << 4)
2781	#define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G (0x5UL << 4)
2782	#define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G
2783	u8 cq_pg_size_cq_lvl;
2784	#define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_MASK 0xfUL
2785	#define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_SFT 0
2786	#define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_0 0x0UL
2787	#define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_1 0x1UL
2788	#define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 0x2UL
2789	#define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2
2790	#define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_MASK 0xf0UL
2791	#define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_SFT 4
2792	#define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_4K (0x0UL << 4)
2793	#define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8K (0x1UL << 4)
2794	#define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_64K (0x2UL << 4)
2795	#define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_2M (0x3UL << 4)
2796	#define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8M (0x4UL << 4)
2797	#define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G (0x5UL << 4)
2798	#define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G
2799	u8 vnic_pg_size_vnic_lvl;
2800	#define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_MASK 0xfUL
2801	#define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_SFT 0
2802	#define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_0 0x0UL
2803	#define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_1 0x1UL
2804	#define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 0x2UL
2805	#define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2
2806	#define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_MASK 0xf0UL
2807	#define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_SFT 4
2808	#define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_4K (0x0UL << 4)
2809	#define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8K (0x1UL << 4)
2810	#define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_64K (0x2UL << 4)
2811	#define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_2M (0x3UL << 4)
2812	#define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8M (0x4UL << 4)
2813	#define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G (0x5UL << 4)
2814	#define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G
2815	u8 stat_pg_size_stat_lvl;
2816	#define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_MASK 0xfUL
2817	#define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_SFT 0
2818	#define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_0 0x0UL
2819	#define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_1 0x1UL
2820	#define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 0x2UL
2821	#define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2
2822	#define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_MASK 0xf0UL
2823	#define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_SFT 4
2824	#define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_4K (0x0UL << 4)
2825	#define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8K (0x1UL << 4)
2826	#define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_64K (0x2UL << 4)
2827	#define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_2M (0x3UL << 4)
2828	#define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8M (0x4UL << 4)
2829	#define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G (0x5UL << 4)
2830	#define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G
2831	u8 tqm_sp_pg_size_tqm_sp_lvl;
2832	#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_MASK 0xfUL
2833	#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_SFT 0
2834	#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_0 0x0UL
2835	#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_1 0x1UL
2836	#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 0x2UL
2837	#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2
2838	#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_MASK 0xf0UL
2839	#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_SFT 4
2840	#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_4K (0x0UL << 4)
2841	#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8K (0x1UL << 4)
2842	#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_64K (0x2UL << 4)
2843	#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_2M (0x3UL << 4)
2844	#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8M (0x4UL << 4)
2845	#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G (0x5UL << 4)
2846	#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G
2847	u8 tqm_ring0_pg_size_tqm_ring0_lvl;
2848	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_MASK 0xfUL
2849	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_SFT 0
2850	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_0 0x0UL
2851	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_1 0x1UL
2852	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 0x2UL
2853	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2
2854	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_MASK 0xf0UL
2855	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_SFT 4
2856	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_4K (0x0UL << 4)
2857	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8K (0x1UL << 4)
2858	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_64K (0x2UL << 4)
2859	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_2M (0x3UL << 4)
2860	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8M (0x4UL << 4)
2861	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G (0x5UL << 4)
2862	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G
2863	u8 tqm_ring1_pg_size_tqm_ring1_lvl;
2864	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_MASK 0xfUL
2865	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_SFT 0
2866	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_0 0x0UL
2867	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_1 0x1UL
2868	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 0x2UL
2869	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2
2870	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_MASK 0xf0UL
2871	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_SFT 4
2872	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_4K (0x0UL << 4)
2873	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8K (0x1UL << 4)
2874	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_64K (0x2UL << 4)
2875	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_2M (0x3UL << 4)
2876	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8M (0x4UL << 4)
2877	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G (0x5UL << 4)
2878	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G
2879	u8 tqm_ring2_pg_size_tqm_ring2_lvl;
2880	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_MASK 0xfUL
2881	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_SFT 0
2882	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_0 0x0UL
2883	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_1 0x1UL
2884	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 0x2UL
2885	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2
2886	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_MASK 0xf0UL
2887	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_SFT 4
2888	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_4K (0x0UL << 4)
2889	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8K (0x1UL << 4)
2890	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_64K (0x2UL << 4)
2891	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_2M (0x3UL << 4)
2892	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8M (0x4UL << 4)
2893	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G (0x5UL << 4)
2894	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G
2895	u8 tqm_ring3_pg_size_tqm_ring3_lvl;
2896	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_MASK 0xfUL
2897	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_SFT 0
2898	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_0 0x0UL
2899	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_1 0x1UL
2900	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 0x2UL
2901	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2
2902	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_MASK 0xf0UL
2903	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_SFT 4
2904	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_4K (0x0UL << 4)
2905	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8K (0x1UL << 4)
2906	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_64K (0x2UL << 4)
2907	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_2M (0x3UL << 4)
2908	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8M (0x4UL << 4)
2909	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G (0x5UL << 4)
2910	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G
2911	u8 tqm_ring4_pg_size_tqm_ring4_lvl;
2912	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_MASK 0xfUL
2913	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_SFT 0
2914	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_0 0x0UL
2915	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_1 0x1UL
2916	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 0x2UL
2917	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2
2918	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_MASK 0xf0UL
2919	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_SFT 4
2920	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_4K (0x0UL << 4)
2921	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8K (0x1UL << 4)
2922	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_64K (0x2UL << 4)
2923	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_2M (0x3UL << 4)
2924	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8M (0x4UL << 4)
2925	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G (0x5UL << 4)
2926	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G
2927	u8 tqm_ring5_pg_size_tqm_ring5_lvl;
2928	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_MASK 0xfUL
2929	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_SFT 0
2930	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_0 0x0UL
2931	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_1 0x1UL
2932	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 0x2UL
2933	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2
2934	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_MASK 0xf0UL
2935	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_SFT 4
2936	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_4K (0x0UL << 4)
2937	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8K (0x1UL << 4)
2938	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_64K (0x2UL << 4)
2939	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_2M (0x3UL << 4)
2940	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8M (0x4UL << 4)
2941	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G (0x5UL << 4)
2942	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G
2943	u8 tqm_ring6_pg_size_tqm_ring6_lvl;
2944	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_MASK 0xfUL
2945	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_SFT 0
2946	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_0 0x0UL
2947	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_1 0x1UL
2948	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 0x2UL
2949	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2
2950	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_MASK 0xf0UL
2951	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_SFT 4
2952	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_4K (0x0UL << 4)
2953	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8K (0x1UL << 4)
2954	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_64K (0x2UL << 4)
2955	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_2M (0x3UL << 4)
2956	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8M (0x4UL << 4)
2957	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G (0x5UL << 4)
2958	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G
2959	u8 tqm_ring7_pg_size_tqm_ring7_lvl;
2960	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_MASK 0xfUL
2961	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_SFT 0
2962	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_0 0x0UL
2963	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_1 0x1UL
2964	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 0x2UL
2965	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2
2966	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_MASK 0xf0UL
2967	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_SFT 4
2968	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_4K (0x0UL << 4)
2969	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8K (0x1UL << 4)
2970	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_64K (0x2UL << 4)
2971	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_2M (0x3UL << 4)
2972	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8M (0x4UL << 4)
2973	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G (0x5UL << 4)
2974	#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G
2975	u8 mrav_pg_size_mrav_lvl;
2976	#define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_MASK 0xfUL
2977	#define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_SFT 0
2978	#define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_0 0x0UL
2979	#define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_1 0x1UL
2980	#define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 0x2UL
2981	#define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2
2982	#define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_MASK 0xf0UL
2983	#define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_SFT 4
2984	#define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_4K (0x0UL << 4)
2985	#define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8K (0x1UL << 4)
2986	#define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_64K (0x2UL << 4)
2987	#define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_2M (0x3UL << 4)
2988	#define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8M (0x4UL << 4)
2989	#define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G (0x5UL << 4)
2990	#define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G
2991	u8 tim_pg_size_tim_lvl;
2992	#define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_MASK 0xfUL
2993	#define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_SFT 0
2994	#define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_0 0x0UL
2995	#define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_1 0x1UL
2996	#define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 0x2UL
2997	#define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2
2998	#define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_MASK 0xf0UL
2999	#define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_SFT 4
3000	#define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_4K (0x0UL << 4)
3001	#define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8K (0x1UL << 4)
3002	#define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_64K (0x2UL << 4)
3003	#define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_2M (0x3UL << 4)
3004	#define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8M (0x4UL << 4)
3005	#define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G (0x5UL << 4)
3006	#define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G
3007	__le64 qpc_page_dir;
3008	__le64 srq_page_dir;
3009	__le64 cq_page_dir;
3010	__le64 vnic_page_dir;
3011	__le64 stat_page_dir;
3012	__le64 tqm_sp_page_dir;
3013	__le64 tqm_ring0_page_dir;
3014	__le64 tqm_ring1_page_dir;
3015	__le64 tqm_ring2_page_dir;
3016	__le64 tqm_ring3_page_dir;
3017	__le64 tqm_ring4_page_dir;
3018	__le64 tqm_ring5_page_dir;
3019	__le64 tqm_ring6_page_dir;
3020	__le64 tqm_ring7_page_dir;
3021	__le64 mrav_page_dir;
3022	__le64 tim_page_dir;
3023	__le32 qp_num_entries;
3024	__le32 srq_num_entries;
3025	__le32 cq_num_entries;
3026	__le32 stat_num_entries;
3027	__le32 tqm_sp_num_entries;
3028	__le32 tqm_ring0_num_entries;
3029	__le32 tqm_ring1_num_entries;
3030	__le32 tqm_ring2_num_entries;
3031	__le32 tqm_ring3_num_entries;
3032	__le32 tqm_ring4_num_entries;
3033	__le32 tqm_ring5_num_entries;
3034	__le32 tqm_ring6_num_entries;
3035	__le32 tqm_ring7_num_entries;
3036	__le32 mrav_num_entries;
3037	__le32 tim_num_entries;
3038	__le16 qp_num_qp1_entries;
3039	__le16 qp_num_l2_entries;
3040	__le16 qp_entry_size;
3041	__le16 srq_num_l2_entries;
3042	__le16 srq_entry_size;
3043	__le16 cq_num_l2_entries;
3044	__le16 cq_entry_size;
3045	__le16 vnic_num_vnic_entries;
3046	__le16 vnic_num_ring_table_entries;
3047	__le16 vnic_entry_size;
3048	__le16 stat_entry_size;
3049	__le16 tqm_entry_size;
3050	__le16 mrav_entry_size;
3051	__le16 tim_entry_size;
3052	u8 tqm_ring8_pg_size_tqm_ring_lvl;
3053	#define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_MASK 0xfUL
3054	#define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_SFT 0
3055	#define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_0 0x0UL
3056	#define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_1 0x1UL
3057	#define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_2 0x2UL
3058	#define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_2
3059	#define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_MASK 0xf0UL
3060	#define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_SFT 4
3061	#define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4)
3062	#define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4)
3063	#define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4)
3064	#define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4)
3065	#define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4)
3066	#define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4)
3067	#define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_1G
3068	u8 ring8_unused[3];
3069	__le32 tqm_ring8_num_entries;
3070	__le64 tqm_ring8_page_dir;
3071	u8 tqm_ring9_pg_size_tqm_ring_lvl;
3072	#define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_MASK 0xfUL
3073	#define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_SFT 0
3074	#define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_0 0x0UL
3075	#define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_1 0x1UL
3076	#define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_2 0x2UL
3077	#define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_2
3078	#define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_MASK 0xf0UL
3079	#define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_SFT 4
3080	#define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4)
3081	#define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4)
3082	#define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4)
3083	#define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4)
3084	#define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4)
3085	#define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4)
3086	#define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_1G
3087	u8 ring9_unused[3];
3088	__le32 tqm_ring9_num_entries;
3089	__le64 tqm_ring9_page_dir;
3090	u8 tqm_ring10_pg_size_tqm_ring_lvl;
3091	#define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_MASK 0xfUL
3092	#define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_SFT 0
3093	#define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_0 0x0UL
3094	#define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_1 0x1UL
3095	#define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_2 0x2UL
3096	#define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_2
3097	#define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_MASK 0xf0UL
3098	#define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_SFT 4
3099	#define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4)
3100	#define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4)
3101	#define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4)
3102	#define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4)
3103	#define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4)
3104	#define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4)
3105	#define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_1G
3106	u8 ring10_unused[3];
3107	__le32 tqm_ring10_num_entries;
3108	__le64 tqm_ring10_page_dir;
3109	__le32 tkc_num_entries;
3110	__le32 rkc_num_entries;
3111	__le64 tkc_page_dir;
3112	__le64 rkc_page_dir;
3113	__le16 tkc_entry_size;
3114	__le16 rkc_entry_size;
3115	u8 tkc_pg_size_tkc_lvl;
3116	#define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_MASK 0xfUL
3117	#define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_SFT 0
3118	#define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_0 0x0UL
3119	#define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_1 0x1UL
3120	#define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_2 0x2UL
3121	#define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_2
3122	#define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_MASK 0xf0UL
3123	#define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_SFT 4
3124	#define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_4K (0x0UL << 4)
3125	#define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_8K (0x1UL << 4)
3126	#define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_64K (0x2UL << 4)
3127	#define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_2M (0x3UL << 4)
3128	#define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_8M (0x4UL << 4)
3129	#define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_1G (0x5UL << 4)
3130	#define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_1G
3131	u8 rkc_pg_size_rkc_lvl;
3132	#define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_MASK 0xfUL
3133	#define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_SFT 0
3134	#define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_0 0x0UL
3135	#define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_1 0x1UL
3136	#define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_2 0x2UL
3137	#define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_2
3138	#define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_MASK 0xf0UL
3139	#define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_SFT 4
3140	#define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_4K (0x0UL << 4)
3141	#define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_8K (0x1UL << 4)
3142	#define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_64K (0x2UL << 4)
3143	#define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_2M (0x3UL << 4)
3144	#define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_8M (0x4UL << 4)
3145	#define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_1G (0x5UL << 4)
3146	#define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_1G
3147	__le16 qp_num_fast_qpmd_entries;
3148	};
3149
3150	/* hwrm_func_backing_store_cfg_output (size:128b/16B) */
3151	struct hwrm_func_backing_store_cfg_output {
3152	__le16 error_code;
3153	__le16 req_type;
3154	__le16 seq_id;
3155	__le16 resp_len;
3156	u8 unused_0[7];
3157	u8 valid;
3158	};
3159
3160	/* hwrm_error_recovery_qcfg_input (size:192b/24B) */
3161	struct hwrm_error_recovery_qcfg_input {
3162	__le16 req_type;
3163	__le16 cmpl_ring;
3164	__le16 seq_id;
3165	__le16 target_id;
3166	__le64 resp_addr;
3167	u8 unused_0[8];
3168	};
3169
3170	/* hwrm_error_recovery_qcfg_output (size:1664b/208B) */
3171	struct hwrm_error_recovery_qcfg_output {
3172	__le16 error_code;
3173	__le16 req_type;
3174	__le16 seq_id;
3175	__le16 resp_len;
3176	__le32 flags;
3177	#define ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST 0x1UL
3178	#define ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU 0x2UL
3179	__le32 driver_polling_freq;
3180	__le32 master_func_wait_period;
3181	__le32 normal_func_wait_period;
3182	__le32 master_func_wait_period_after_reset;
3183	__le32 max_bailout_time_after_reset;
3184	__le32 fw_health_status_reg;
3185	#define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK 0x3UL
3186	#define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT 0
3187	#define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG 0x0UL
3188	#define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC 0x1UL
3189	#define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 0x2UL
3190	#define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 0x3UL
3191	#define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1
3192	#define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_MASK 0xfffffffcUL
3193	#define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SFT 2
3194	__le32 fw_heartbeat_reg;
3195	#define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_MASK 0x3UL
3196	#define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_SFT 0
3197	#define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG 0x0UL
3198	#define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_GRC 0x1UL
3199	#define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 0x2UL
3200	#define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 0x3UL
3201	#define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1
3202	#define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_MASK 0xfffffffcUL
3203	#define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SFT 2
3204	__le32 fw_reset_cnt_reg;
3205	#define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_MASK 0x3UL
3206	#define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_SFT 0
3207	#define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG 0x0UL
3208	#define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_GRC 0x1UL
3209	#define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 0x2UL
3210	#define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 0x3UL
3211	#define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1
3212	#define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_MASK 0xfffffffcUL
3213	#define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SFT 2
3214	__le32 reset_inprogress_reg;
3215	#define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_MASK 0x3UL
3216	#define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_SFT 0
3217	#define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG 0x0UL
3218	#define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_GRC 0x1UL
3219	#define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 0x2UL
3220	#define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 0x3UL
3221	#define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1
3222	#define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_MASK 0xfffffffcUL
3223	#define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SFT 2
3224	__le32 reset_inprogress_reg_mask;
3225	u8 unused_0[3];
3226	u8 reg_array_cnt;
3227	__le32 reset_reg[16];
3228	#define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_MASK 0x3UL
3229	#define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_SFT 0
3230	#define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_PCIE_CFG 0x0UL
3231	#define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_GRC 0x1UL
3232	#define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR0 0x2UL
3233	#define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1 0x3UL
3234	#define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1
3235	#define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_MASK 0xfffffffcUL
3236	#define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SFT 2
3237	__le32 reset_reg_val[16];
3238	u8 delay_after_reset[16];
3239	__le32 err_recovery_cnt_reg;
3240	#define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_MASK 0x3UL
3241	#define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_SFT 0
3242	#define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_PCIE_CFG 0x0UL
3243	#define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_GRC 0x1UL
3244	#define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR0 0x2UL
3245	#define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 0x3UL
3246	#define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1
3247	#define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_MASK 0xfffffffcUL
3248	#define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SFT 2
3249	u8 unused_1[3];
3250	u8 valid;
3251	};
3252
3253	/* hwrm_func_echo_response_input (size:192b/24B) */
3254	struct hwrm_func_echo_response_input {
3255	__le16 req_type;
3256	__le16 cmpl_ring;
3257	__le16 seq_id;
3258	__le16 target_id;
3259	__le64 resp_addr;
3260	__le32 event_data1;
3261	__le32 event_data2;
3262	};
3263
3264	/* hwrm_func_echo_response_output (size:128b/16B) */
3265	struct hwrm_func_echo_response_output {
3266	__le16 error_code;
3267	__le16 req_type;
3268	__le16 seq_id;
3269	__le16 resp_len;
3270	u8 unused_0[7];
3271	u8 valid;
3272	};
3273
3274	/* hwrm_func_ptp_pin_qcfg_input (size:192b/24B) */
3275	struct hwrm_func_ptp_pin_qcfg_input {
3276	__le16 req_type;
3277	__le16 cmpl_ring;
3278	__le16 seq_id;
3279	__le16 target_id;
3280	__le64 resp_addr;
3281	u8 unused_0[8];
3282	};
3283
3284	/* hwrm_func_ptp_pin_qcfg_output (size:128b/16B) */
3285	struct hwrm_func_ptp_pin_qcfg_output {
3286	__le16 error_code;
3287	__le16 req_type;
3288	__le16 seq_id;
3289	__le16 resp_len;
3290	u8 num_pins;
3291	u8 state;
3292	#define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN0_ENABLED 0x1UL
3293	#define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN1_ENABLED 0x2UL
3294	#define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN2_ENABLED 0x4UL
3295	#define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN3_ENABLED 0x8UL
3296	u8 pin0_usage;
3297	#define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_NONE 0x0UL
3298	#define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_PPS_IN 0x1UL
3299	#define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_PPS_OUT 0x2UL
3300	#define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_IN 0x3UL
3301	#define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_OUT 0x4UL
3302	#define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_OUT
3303	u8 pin1_usage;
3304	#define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_NONE 0x0UL
3305	#define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_PPS_IN 0x1UL
3306	#define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_PPS_OUT 0x2UL
3307	#define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_IN 0x3UL
3308	#define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_OUT 0x4UL
3309	#define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_OUT
3310	u8 pin2_usage;
3311	#define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_NONE 0x0UL
3312	#define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_PPS_IN 0x1UL
3313	#define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_PPS_OUT 0x2UL
3314	#define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNC_IN 0x3UL
3315	#define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNC_OUT 0x4UL
3316	#define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNCE_PRIMARY_CLOCK_OUT 0x5UL
3317	#define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT 0x6UL
3318	#define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT
3319	u8 pin3_usage;
3320	#define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_NONE 0x0UL
3321	#define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_PPS_IN 0x1UL
3322	#define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_PPS_OUT 0x2UL
3323	#define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNC_IN 0x3UL
3324	#define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNC_OUT 0x4UL
3325	#define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNCE_PRIMARY_CLOCK_OUT 0x5UL
3326	#define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT 0x6UL
3327	#define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT
3328	u8 unused_0;
3329	u8 valid;
3330	};
3331
3332	/* hwrm_func_ptp_pin_cfg_input (size:256b/32B) */
3333	struct hwrm_func_ptp_pin_cfg_input {
3334	__le16 req_type;
3335	__le16 cmpl_ring;
3336	__le16 seq_id;
3337	__le16 target_id;
3338	__le64 resp_addr;
3339	__le32 enables;
3340	#define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_STATE 0x1UL
3341	#define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_USAGE 0x2UL
3342	#define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN1_STATE 0x4UL
3343	#define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN1_USAGE 0x8UL
3344	#define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN2_STATE 0x10UL
3345	#define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN2_USAGE 0x20UL
3346	#define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN3_STATE 0x40UL
3347	#define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN3_USAGE 0x80UL
3348	u8 pin0_state;
3349	#define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_DISABLED 0x0UL
3350	#define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_ENABLED 0x1UL
3351	#define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_ENABLED
3352	u8 pin0_usage;
3353	#define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_NONE 0x0UL
3354	#define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_PPS_IN 0x1UL
3355	#define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_PPS_OUT 0x2UL
3356	#define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_IN 0x3UL
3357	#define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_OUT 0x4UL
3358	#define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_OUT
3359	u8 pin1_state;
3360	#define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_DISABLED 0x0UL
3361	#define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_ENABLED 0x1UL
3362	#define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_ENABLED
3363	u8 pin1_usage;
3364	#define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_NONE 0x0UL
3365	#define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_PPS_IN 0x1UL
3366	#define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_PPS_OUT 0x2UL
3367	#define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_IN 0x3UL
3368	#define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_OUT 0x4UL
3369	#define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_OUT
3370	u8 pin2_state;
3371	#define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_DISABLED 0x0UL
3372	#define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_ENABLED 0x1UL
3373	#define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_ENABLED
3374	u8 pin2_usage;
3375	#define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_NONE 0x0UL
3376	#define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_PPS_IN 0x1UL
3377	#define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_PPS_OUT 0x2UL
3378	#define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNC_IN 0x3UL
3379	#define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNC_OUT 0x4UL
3380	#define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNCE_PRIMARY_CLOCK_OUT 0x5UL
3381	#define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT 0x6UL
3382	#define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT
3383	u8 pin3_state;
3384	#define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_DISABLED 0x0UL
3385	#define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_ENABLED 0x1UL
3386	#define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_ENABLED
3387	u8 pin3_usage;
3388	#define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_NONE 0x0UL
3389	#define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_PPS_IN 0x1UL
3390	#define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_PPS_OUT 0x2UL
3391	#define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNC_IN 0x3UL
3392	#define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNC_OUT 0x4UL
3393	#define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNCE_PRIMARY_CLOCK_OUT 0x5UL
3394	#define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT 0x6UL
3395	#define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT
3396	u8 unused_0[4];
3397	};
3398
3399	/* hwrm_func_ptp_pin_cfg_output (size:128b/16B) */
3400	struct hwrm_func_ptp_pin_cfg_output {
3401	__le16 error_code;
3402	__le16 req_type;
3403	__le16 seq_id;
3404	__le16 resp_len;
3405	u8 unused_0[7];
3406	u8 valid;
3407	};
3408
3409	/* hwrm_func_ptp_cfg_input (size:384b/48B) */
3410	struct hwrm_func_ptp_cfg_input {
3411	__le16 req_type;
3412	__le16 cmpl_ring;
3413	__le16 seq_id;
3414	__le16 target_id;
3415	__le64 resp_addr;
3416	__le16 enables;
3417	#define FUNC_PTP_CFG_REQ_ENABLES_PTP_PPS_EVENT 0x1UL
3418	#define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_DLL_SOURCE 0x2UL
3419	#define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_DLL_PHASE 0x4UL
3420	#define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PERIOD 0x8UL
3421	#define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_UP 0x10UL
3422	#define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PHASE 0x20UL
3423	#define FUNC_PTP_CFG_REQ_ENABLES_PTP_SET_TIME 0x40UL
3424	u8 ptp_pps_event;
3425	#define FUNC_PTP_CFG_REQ_PTP_PPS_EVENT_INTERNAL 0x1UL
3426	#define FUNC_PTP_CFG_REQ_PTP_PPS_EVENT_EXTERNAL 0x2UL
3427	u8 ptp_freq_adj_dll_source;
3428	#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_NONE 0x0UL
3429	#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_0 0x1UL
3430	#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_1 0x2UL
3431	#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_2 0x3UL
3432	#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_3 0x4UL
3433	#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_0 0x5UL
3434	#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_1 0x6UL
3435	#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_2 0x7UL
3436	#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_3 0x8UL
3437	#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_INVALID 0xffUL
3438	#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_LAST FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_INVALID
3439	u8 ptp_freq_adj_dll_phase;
3440	#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_NONE 0x0UL
3441	#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_4K 0x1UL
3442	#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_8K 0x2UL
3443	#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_10M 0x3UL
3444	#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_LAST FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_10M
3445	u8 unused_0[3];
3446	__le32 ptp_freq_adj_ext_period;
3447	__le32 ptp_freq_adj_ext_up;
3448	__le32 ptp_freq_adj_ext_phase_lower;
3449	__le32 ptp_freq_adj_ext_phase_upper;
3450	__le64 ptp_set_time;
3451	};
3452
3453	/* hwrm_func_ptp_cfg_output (size:128b/16B) */
3454	struct hwrm_func_ptp_cfg_output {
3455	__le16 error_code;
3456	__le16 req_type;
3457	__le16 seq_id;
3458	__le16 resp_len;
3459	u8 unused_0[7];
3460	u8 valid;
3461	};
3462
3463	/* hwrm_func_ptp_ts_query_input (size:192b/24B) */
3464	struct hwrm_func_ptp_ts_query_input {
3465	__le16 req_type;
3466	__le16 cmpl_ring;
3467	__le16 seq_id;
3468	__le16 target_id;
3469	__le64 resp_addr;
3470	__le32 flags;
3471	#define FUNC_PTP_TS_QUERY_REQ_FLAGS_PPS_TIME 0x1UL
3472	#define FUNC_PTP_TS_QUERY_REQ_FLAGS_PTM_TIME 0x2UL
3473	u8 unused_0[4];
3474	};
3475
3476	/* hwrm_func_ptp_ts_query_output (size:320b/40B) */
3477	struct hwrm_func_ptp_ts_query_output {
3478	__le16 error_code;
3479	__le16 req_type;
3480	__le16 seq_id;
3481	__le16 resp_len;
3482	__le64 pps_event_ts;
3483	__le64 ptm_local_ts;
3484	__le64 ptm_system_ts;
3485	__le32 ptm_link_delay;
3486	u8 unused_0[3];
3487	u8 valid;
3488	};
3489
3490	/* hwrm_func_ptp_ext_cfg_input (size:256b/32B) */
3491	struct hwrm_func_ptp_ext_cfg_input {
3492	__le16 req_type;
3493	__le16 cmpl_ring;
3494	__le16 seq_id;
3495	__le16 target_id;
3496	__le64 resp_addr;
3497	__le16 enables;
3498	#define FUNC_PTP_EXT_CFG_REQ_ENABLES_PHC_MASTER_FID 0x1UL
3499	#define FUNC_PTP_EXT_CFG_REQ_ENABLES_PHC_SEC_FID 0x2UL
3500	#define FUNC_PTP_EXT_CFG_REQ_ENABLES_PHC_SEC_MODE 0x4UL
3501	#define FUNC_PTP_EXT_CFG_REQ_ENABLES_FAILOVER_TIMER 0x8UL
3502	__le16 phc_master_fid;
3503	__le16 phc_sec_fid;
3504	u8 phc_sec_mode;
3505	#define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_SWITCH 0x0UL
3506	#define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_ALL 0x1UL
3507	#define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_PF_ONLY 0x2UL
3508	#define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_LAST FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_PF_ONLY
3509	u8 unused_0;
3510	__le32 failover_timer;
3511	u8 unused_1[4];
3512	};
3513
3514	/* hwrm_func_ptp_ext_cfg_output (size:128b/16B) */
3515	struct hwrm_func_ptp_ext_cfg_output {
3516	__le16 error_code;
3517	__le16 req_type;
3518	__le16 seq_id;
3519	__le16 resp_len;
3520	u8 unused_0[7];
3521	u8 valid;
3522	};
3523
3524	/* hwrm_func_ptp_ext_qcfg_input (size:192b/24B) */
3525	struct hwrm_func_ptp_ext_qcfg_input {
3526	__le16 req_type;
3527	__le16 cmpl_ring;
3528	__le16 seq_id;
3529	__le16 target_id;
3530	__le64 resp_addr;
3531	u8 unused_0[8];
3532	};
3533
3534	/* hwrm_func_ptp_ext_qcfg_output (size:256b/32B) */
3535	struct hwrm_func_ptp_ext_qcfg_output {
3536	__le16 error_code;
3537	__le16 req_type;
3538	__le16 seq_id;
3539	__le16 resp_len;
3540	__le16 phc_master_fid;
3541	__le16 phc_sec_fid;
3542	__le16 phc_active_fid0;
3543	__le16 phc_active_fid1;
3544	__le32 last_failover_event;
3545	__le16 from_fid;
3546	__le16 to_fid;
3547	u8 unused_0[7];
3548	u8 valid;
3549	};
3550
3551	/* hwrm_func_backing_store_cfg_v2_input (size:448b/56B) */
3552	struct hwrm_func_backing_store_cfg_v2_input {
3553	__le16 req_type;
3554	__le16 cmpl_ring;
3555	__le16 seq_id;
3556	__le16 target_id;
3557	__le64 resp_addr;
3558	__le16 type;
3559	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_QP 0x0UL
3560	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SRQ 0x1UL
3561	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CQ 0x2UL
3562	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_VNIC 0x3UL
3563	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_STAT 0x4UL
3564	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SP_TQM_RING 0x5UL
3565	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_FP_TQM_RING 0x6UL
3566	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_MRAV 0xeUL
3567	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TIM 0xfUL
3568	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TKC 0x13UL
3569	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RKC 0x14UL
3570	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_MP_TQM_RING 0x15UL
3571	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SQ_DB_SHADOW 0x16UL
3572	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RQ_DB_SHADOW 0x17UL
3573	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SRQ_DB_SHADOW 0x18UL
3574	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CQ_DB_SHADOW 0x19UL
3575	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_QUIC_TKC 0x1aUL
3576	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_QUIC_RKC 0x1bUL
3577	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TBL_SCOPE 0x1cUL
3578	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_XID_PARTITION 0x1dUL
3579	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_INVALID 0xffffUL
3580	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_INVALID
3581	__le16 instance;
3582	__le32 flags;
3583	#define FUNC_BACKING_STORE_CFG_V2_REQ_FLAGS_PREBOOT_MODE 0x1UL
3584	#define FUNC_BACKING_STORE_CFG_V2_REQ_FLAGS_BS_CFG_ALL_DONE 0x2UL
3585	#define FUNC_BACKING_STORE_CFG_V2_REQ_FLAGS_BS_EXTEND 0x4UL
3586	__le64 page_dir;
3587	__le32 num_entries;
3588	__le16 entry_size;
3589	u8 page_size_pbl_level;
3590	#define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_MASK 0xfUL
3591	#define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_SFT 0
3592	#define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_0 0x0UL
3593	#define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_1 0x1UL
3594	#define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_2 0x2UL
3595	#define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LAST FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_2
3596	#define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_MASK 0xf0UL
3597	#define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_SFT 4
3598	#define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_4K (0x0UL << 4)
3599	#define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_8K (0x1UL << 4)
3600	#define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_64K (0x2UL << 4)
3601	#define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_2M (0x3UL << 4)
3602	#define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_8M (0x4UL << 4)
3603	#define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_1G (0x5UL << 4)
3604	#define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_LAST FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_1G
3605	u8 subtype_valid_cnt;
3606	__le32 split_entry_0;
3607	__le32 split_entry_1;
3608	__le32 split_entry_2;
3609	__le32 split_entry_3;
3610	};
3611
3612	/* hwrm_func_backing_store_cfg_v2_output (size:128b/16B) */
3613	struct hwrm_func_backing_store_cfg_v2_output {
3614	__le16 error_code;
3615	__le16 req_type;
3616	__le16 seq_id;
3617	__le16 resp_len;
3618	u8 rsvd0[7];
3619	u8 valid;
3620	};
3621
3622	/* hwrm_func_backing_store_qcfg_v2_input (size:192b/24B) */
3623	struct hwrm_func_backing_store_qcfg_v2_input {
3624	__le16 req_type;
3625	__le16 cmpl_ring;
3626	__le16 seq_id;
3627	__le16 target_id;
3628	__le64 resp_addr;
3629	__le16 type;
3630	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_QP 0x0UL
3631	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SRQ 0x1UL
3632	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CQ 0x2UL
3633	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_VNIC 0x3UL
3634	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_STAT 0x4UL
3635	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SP_TQM_RING 0x5UL
3636	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_FP_TQM_RING 0x6UL
3637	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_MRAV 0xeUL
3638	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TIM 0xfUL
3639	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TKC 0x13UL
3640	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RKC 0x14UL
3641	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_MP_TQM_RING 0x15UL
3642	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SQ_DB_SHADOW 0x16UL
3643	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RQ_DB_SHADOW 0x17UL
3644	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SRQ_DB_SHADOW 0x18UL
3645	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CQ_DB_SHADOW 0x19UL
3646	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_QUIC_TKC 0x1aUL
3647	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_QUIC_RKC 0x1bUL
3648	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TBL_SCOPE 0x1cUL
3649	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_XID_PARTITION 0x1dUL
3650	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_INVALID 0xffffUL
3651	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_INVALID
3652	__le16 instance;
3653	u8 rsvd[4];
3654	};
3655
3656	/* hwrm_func_backing_store_qcfg_v2_output (size:448b/56B) */
3657	struct hwrm_func_backing_store_qcfg_v2_output {
3658	__le16 error_code;
3659	__le16 req_type;
3660	__le16 seq_id;
3661	__le16 resp_len;
3662	__le16 type;
3663	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_QP 0x0UL
3664	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_SRQ 0x1UL
3665	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CQ 0x2UL
3666	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_VNIC 0x3UL
3667	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_STAT 0x4UL
3668	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_SP_TQM_RING 0x5UL
3669	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_FP_TQM_RING 0x6UL
3670	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_MRAV 0xeUL
3671	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TIM 0xfUL
3672	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TKC 0x13UL
3673	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_RKC 0x14UL
3674	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_MP_TQM_RING 0x15UL
3675	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_QUIC_TKC 0x1aUL
3676	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_QUIC_RKC 0x1bUL
3677	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TBL_SCOPE 0x1cUL
3678	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_XID_PARTITION 0x1dUL
3679	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_INVALID 0xffffUL
3680	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_LAST FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_INVALID
3681	__le16 instance;
3682	__le32 flags;
3683	__le64 page_dir;
3684	__le32 num_entries;
3685	u8 page_size_pbl_level;
3686	#define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_MASK 0xfUL
3687	#define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_SFT 0
3688	#define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_0 0x0UL
3689	#define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_1 0x1UL
3690	#define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_2 0x2UL
3691	#define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LAST FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_2
3692	#define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_MASK 0xf0UL
3693	#define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_SFT 4
3694	#define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_4K (0x0UL << 4)
3695	#define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_8K (0x1UL << 4)
3696	#define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_64K (0x2UL << 4)
3697	#define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_2M (0x3UL << 4)
3698	#define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_8M (0x4UL << 4)
3699	#define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_1G (0x5UL << 4)
3700	#define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_LAST FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_1G
3701	u8 subtype_valid_cnt;
3702	u8 rsvd[2];
3703	__le32 split_entry_0;
3704	__le32 split_entry_1;
3705	__le32 split_entry_2;
3706	__le32 split_entry_3;
3707	u8 rsvd2[7];
3708	u8 valid;
3709	};
3710
3711	/* qpc_split_entries (size:128b/16B) */
3712	struct qpc_split_entries {
3713	__le32 qp_num_l2_entries;
3714	__le32 qp_num_qp1_entries;
3715	__le32 qp_num_fast_qpmd_entries;
3716	__le32 rsvd;
3717	};
3718
3719	/* srq_split_entries (size:128b/16B) */
3720	struct srq_split_entries {
3721	__le32 srq_num_l2_entries;
3722	__le32 rsvd;
3723	__le32 rsvd2[2];
3724	};
3725
3726	/* cq_split_entries (size:128b/16B) */
3727	struct cq_split_entries {
3728	__le32 cq_num_l2_entries;
3729	__le32 rsvd;
3730	__le32 rsvd2[2];
3731	};
3732
3733	/* vnic_split_entries (size:128b/16B) */
3734	struct vnic_split_entries {
3735	__le32 vnic_num_vnic_entries;
3736	__le32 rsvd;
3737	__le32 rsvd2[2];
3738	};
3739
3740	/* mrav_split_entries (size:128b/16B) */
3741	struct mrav_split_entries {
3742	__le32 mrav_num_av_entries;
3743	__le32 rsvd;
3744	__le32 rsvd2[2];
3745	};
3746
3747	/* hwrm_func_backing_store_qcaps_v2_input (size:192b/24B) */
3748	struct hwrm_func_backing_store_qcaps_v2_input {
3749	__le16 req_type;
3750	__le16 cmpl_ring;
3751	__le16 seq_id;
3752	__le16 target_id;
3753	__le64 resp_addr;
3754	__le16 type;
3755	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QP 0x0UL
3756	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ 0x1UL
3757	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ 0x2UL
3758	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_VNIC 0x3UL
3759	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_STAT 0x4UL
3760	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SP_TQM_RING 0x5UL
3761	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_FP_TQM_RING 0x6UL
3762	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MRAV 0xeUL
3763	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TIM 0xfUL
3764	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TKC 0x13UL
3765	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RKC 0x14UL
3766	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MP_TQM_RING 0x15UL
3767	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SQ_DB_SHADOW 0x16UL
3768	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RQ_DB_SHADOW 0x17UL
3769	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ_DB_SHADOW 0x18UL
3770	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ_DB_SHADOW 0x19UL
3771	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QUIC_TKC 0x1aUL
3772	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QUIC_RKC 0x1bUL
3773	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TBL_SCOPE 0x1cUL
3774	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_XID_PARTITION 0x1dUL
3775	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_INVALID 0xffffUL
3776	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_INVALID
3777	u8 rsvd[6];
3778	};
3779
3780	/* hwrm_func_backing_store_qcaps_v2_output (size:448b/56B) */
3781	struct hwrm_func_backing_store_qcaps_v2_output {
3782	__le16 error_code;
3783	__le16 req_type;
3784	__le16 seq_id;
3785	__le16 resp_len;
3786	__le16 type;
3787	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_QP 0x0UL
3788	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SRQ 0x1UL
3789	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CQ 0x2UL
3790	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_VNIC 0x3UL
3791	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_STAT 0x4UL
3792	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SP_TQM_RING 0x5UL
3793	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_FP_TQM_RING 0x6UL
3794	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_MRAV 0xeUL
3795	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TIM 0xfUL
3796	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TKC 0x13UL
3797	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RKC 0x14UL
3798	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_MP_TQM_RING 0x15UL
3799	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SQ_DB_SHADOW 0x16UL
3800	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RQ_DB_SHADOW 0x17UL
3801	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SRQ_DB_SHADOW 0x18UL
3802	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CQ_DB_SHADOW 0x19UL
3803	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_QUIC_TKC 0x1aUL
3804	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_QUIC_RKC 0x1bUL
3805	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TBL_SCOPE 0x1cUL
3806	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_XID_PARTITION 0x1dUL
3807	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_INVALID 0xffffUL
3808	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_LAST FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_INVALID
3809	__le16 entry_size;
3810	__le32 flags;
3811	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_ENABLE_CTX_KIND_INIT 0x1UL
3812	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_TYPE_VALID 0x2UL
3813	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_DRIVER_MANAGED_MEMORY 0x4UL
3814	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_ROCE_QP_PSEUDO_STATIC_ALLOC 0x8UL
3815	__le32 instance_bit_map;
3816	u8 ctx_init_value;
3817	u8 ctx_init_offset;
3818	u8 entry_multiple;
3819	u8 rsvd;
3820	__le32 max_num_entries;
3821	__le32 min_num_entries;
3822	__le16 next_valid_type;
3823	u8 subtype_valid_cnt;
3824	u8 exact_cnt_bit_map;
3825	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_0_EXACT 0x1UL
3826	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_1_EXACT 0x2UL
3827	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_2_EXACT 0x4UL
3828	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_3_EXACT 0x8UL
3829	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_EXACT_CNT_BIT_MAP_UNUSED_MASK 0xf0UL
3830	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_EXACT_CNT_BIT_MAP_UNUSED_SFT 4
3831	__le32 split_entry_0;
3832	__le32 split_entry_1;
3833	__le32 split_entry_2;
3834	__le32 split_entry_3;
3835	u8 rsvd3[3];
3836	u8 valid;
3837	};
3838
3839	/* hwrm_func_dbr_pacing_qcfg_input (size:128b/16B) */
3840	struct hwrm_func_dbr_pacing_qcfg_input {
3841	__le16 req_type;
3842	__le16 cmpl_ring;
3843	__le16 seq_id;
3844	__le16 target_id;
3845	__le64 resp_addr;
3846	};
3847
3848	/* hwrm_func_dbr_pacing_qcfg_output (size:512b/64B) */
3849	struct hwrm_func_dbr_pacing_qcfg_output {
3850	__le16 error_code;
3851	__le16 req_type;
3852	__le16 seq_id;
3853	__le16 resp_len;
3854	u8 flags;
3855	#define FUNC_DBR_PACING_QCFG_RESP_FLAGS_DBR_NQ_EVENT_ENABLED 0x1UL
3856	u8 unused_0[7];
3857	__le32 dbr_stat_db_fifo_reg;
3858	#define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_MASK 0x3UL
3859	#define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_SFT 0
3860	#define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_PCIE_CFG 0x0UL
3861	#define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_GRC 0x1UL
3862	#define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_BAR0 0x2UL
3863	#define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_BAR1 0x3UL
3864	#define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_LAST \
3865	FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_BAR1
3866	#define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_MASK 0xfffffffcUL
3867	#define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SFT 2
3868	__le32 dbr_stat_db_fifo_reg_watermark_mask;
3869	u8 dbr_stat_db_fifo_reg_watermark_shift;
3870	u8 unused_1[3];
3871	__le32 dbr_stat_db_fifo_reg_fifo_room_mask;
3872	u8 dbr_stat_db_fifo_reg_fifo_room_shift;
3873	u8 unused_2[3];
3874	__le32 dbr_throttling_aeq_arm_reg;
3875	#define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_MASK 0x3UL
3876	#define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_SFT 0
3877	#define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_PCIE_CFG 0x0UL
3878	#define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_GRC 0x1UL
3879	#define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_BAR0 0x2UL
3880	#define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_BAR1 0x3UL
3881	#define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_LAST \
3882	FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_BAR1
3883	#define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_MASK 0xfffffffcUL
3884	#define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SFT 2
3885	u8 dbr_throttling_aeq_arm_reg_val;
3886	u8 unused_3[7];
3887	__le32 primary_nq_id;
3888	__le32 pacing_threshold;
3889	u8 unused_4[7];
3890	u8 valid;
3891	};
3892
3893	/* hwrm_func_drv_if_change_input (size:192b/24B) */
3894	struct hwrm_func_drv_if_change_input {
3895	__le16 req_type;
3896	__le16 cmpl_ring;
3897	__le16 seq_id;
3898	__le16 target_id;
3899	__le64 resp_addr;
3900	__le32 flags;
3901	#define FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP 0x1UL
3902	__le32 unused;
3903	};
3904
3905	/* hwrm_func_drv_if_change_output (size:128b/16B) */
3906	struct hwrm_func_drv_if_change_output {
3907	__le16 error_code;
3908	__le16 req_type;
3909	__le16 seq_id;
3910	__le16 resp_len;
3911	__le32 flags;
3912	#define FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE 0x1UL
3913	#define FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE 0x2UL
3914	u8 unused_0[3];
3915	u8 valid;
3916	};
3917
3918	/* hwrm_port_phy_cfg_input (size:448b/56B) */
3919	struct hwrm_port_phy_cfg_input {
3920	__le16 req_type;
3921	__le16 cmpl_ring;
3922	__le16 seq_id;
3923	__le16 target_id;
3924	__le64 resp_addr;
3925	__le32 flags;
3926	#define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL
3927	#define PORT_PHY_CFG_REQ_FLAGS_DEPRECATED 0x2UL
3928	#define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL
3929	#define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 0x8UL
3930	#define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE 0x10UL
3931	#define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE 0x20UL
3932	#define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE 0x40UL
3933	#define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE 0x80UL
3934	#define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE 0x100UL
3935	#define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE 0x200UL
3936	#define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE 0x400UL
3937	#define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE 0x800UL
3938	#define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE 0x1000UL
3939	#define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE 0x2000UL
3940	#define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN 0x4000UL
3941	#define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_ENABLE 0x8000UL
3942	#define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_DISABLE 0x10000UL
3943	#define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_ENABLE 0x20000UL
3944	#define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_DISABLE 0x40000UL
3945	#define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_ENABLE 0x80000UL
3946	#define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_DISABLE 0x100000UL
3947	#define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_ENABLE 0x200000UL
3948	#define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_DISABLE 0x400000UL
3949	__le32 enables;
3950	#define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL
3951	#define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL
3952	#define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL
3953	#define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED 0x8UL
3954	#define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL
3955	#define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED 0x20UL
3956	#define PORT_PHY_CFG_REQ_ENABLES_LPBK 0x40UL
3957	#define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS 0x80UL
3958	#define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL
3959	#define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK 0x200UL
3960	#define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER 0x400UL
3961	#define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAM4_LINK_SPEED 0x800UL
3962	#define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAM4_LINK_SPEED_MASK 0x1000UL
3963	__le16 port_id;
3964	__le16 force_link_speed;
3965	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB 0x1UL
3966	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB 0xaUL
3967	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB 0x14UL
3968	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB 0x19UL
3969	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB 0x64UL
3970	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB 0xc8UL
3971	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB 0xfaUL
3972	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB 0x190UL
3973	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB 0x1f4UL
3974	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL
3975	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 0xffffUL
3976	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB
3977	u8 auto_mode;
3978	#define PORT_PHY_CFG_REQ_AUTO_MODE_NONE 0x0UL
3979	#define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS 0x1UL
3980	#define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED 0x2UL
3981	#define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW 0x3UL
3982	#define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 0x4UL
3983	#define PORT_PHY_CFG_REQ_AUTO_MODE_LAST PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK
3984	u8 auto_duplex;
3985	#define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF 0x0UL
3986	#define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL 0x1UL
3987	#define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL
3988	#define PORT_PHY_CFG_REQ_AUTO_DUPLEX_LAST PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH
3989	u8 auto_pause;
3990	#define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL
3991	#define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL
3992	#define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL
3993	u8 unused_0;
3994	__le16 auto_link_speed;
3995	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB 0x1UL
3996	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB 0xaUL
3997	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB 0x14UL
3998	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB 0x19UL
3999	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB 0x64UL
4000	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB 0xc8UL
4001	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB 0xfaUL
4002	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB 0x190UL
4003	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB 0x1f4UL
4004	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB 0x3e8UL
4005	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 0xffffUL
4006	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_LAST PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB
4007	__le16 auto_link_speed_mask;
4008	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL
4009	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL
4010	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL
4011	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL
4012	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB 0x10UL
4013	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL
4014	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL
4015	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB 0x80UL
4016	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL
4017	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL
4018	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL
4019	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB 0x800UL
4020	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL
4021	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB 0x2000UL
4022	u8 wirespeed;
4023	#define PORT_PHY_CFG_REQ_WIRESPEED_OFF 0x0UL
4024	#define PORT_PHY_CFG_REQ_WIRESPEED_ON 0x1UL
4025	#define PORT_PHY_CFG_REQ_WIRESPEED_LAST PORT_PHY_CFG_REQ_WIRESPEED_ON
4026	u8 lpbk;
4027	#define PORT_PHY_CFG_REQ_LPBK_NONE 0x0UL
4028	#define PORT_PHY_CFG_REQ_LPBK_LOCAL 0x1UL
4029	#define PORT_PHY_CFG_REQ_LPBK_REMOTE 0x2UL
4030	#define PORT_PHY_CFG_REQ_LPBK_EXTERNAL 0x3UL
4031	#define PORT_PHY_CFG_REQ_LPBK_LAST PORT_PHY_CFG_REQ_LPBK_EXTERNAL
4032	u8 force_pause;
4033	#define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX 0x1UL
4034	#define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX 0x2UL
4035	u8 unused_1;
4036	__le32 preemphasis;
4037	__le16 eee_link_speed_mask;
4038	#define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1 0x1UL
4039	#define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB 0x2UL
4040	#define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2 0x4UL
4041	#define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB 0x8UL
4042	#define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3 0x10UL
4043	#define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4 0x20UL
4044	#define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB 0x40UL
4045	__le16 force_pam4_link_speed;
4046	#define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB 0x1f4UL
4047	#define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL
4048	#define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL
4049	#define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB
4050	__le32 tx_lpi_timer;
4051	#define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL
4052	#define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0
4053	__le16 auto_link_pam4_speed_mask;
4054	#define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_50G 0x1UL
4055	#define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_100G 0x2UL
4056	#define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_200G 0x4UL
4057	u8 unused_2[2];
4058	};
4059
4060	/* hwrm_port_phy_cfg_output (size:128b/16B) */
4061	struct hwrm_port_phy_cfg_output {
4062	__le16 error_code;
4063	__le16 req_type;
4064	__le16 seq_id;
4065	__le16 resp_len;
4066	u8 unused_0[7];
4067	u8 valid;
4068	};
4069
4070	/* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */
4071	struct hwrm_port_phy_cfg_cmd_err {
4072	u8 code;
4073	#define PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL
4074	#define PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED 0x1UL
4075	#define PORT_PHY_CFG_CMD_ERR_CODE_RETRY 0x2UL
4076	#define PORT_PHY_CFG_CMD_ERR_CODE_LAST PORT_PHY_CFG_CMD_ERR_CODE_RETRY
4077	u8 unused_0[7];
4078	};
4079
4080	/* hwrm_port_phy_qcfg_input (size:192b/24B) */
4081	struct hwrm_port_phy_qcfg_input {
4082	__le16 req_type;
4083	__le16 cmpl_ring;
4084	__le16 seq_id;
4085	__le16 target_id;
4086	__le64 resp_addr;
4087	__le16 port_id;
4088	u8 unused_0[6];
4089	};
4090
4091	/* hwrm_port_phy_qcfg_output (size:832b/104B) */
4092	struct hwrm_port_phy_qcfg_output {
4093	__le16 error_code;
4094	__le16 req_type;
4095	__le16 seq_id;
4096	__le16 resp_len;
4097	u8 link;
4098	#define PORT_PHY_QCFG_RESP_LINK_NO_LINK 0x0UL
4099	#define PORT_PHY_QCFG_RESP_LINK_SIGNAL 0x1UL
4100	#define PORT_PHY_QCFG_RESP_LINK_LINK 0x2UL
4101	#define PORT_PHY_QCFG_RESP_LINK_LAST PORT_PHY_QCFG_RESP_LINK_LINK
4102	u8 active_fec_signal_mode;
4103	#define PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK 0xfUL
4104	#define PORT_PHY_QCFG_RESP_SIGNAL_MODE_SFT 0
4105	#define PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ 0x0UL
4106	#define PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4 0x1UL
4107	#define PORT_PHY_QCFG_RESP_SIGNAL_MODE_LAST PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4
4108	#define PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK 0xf0UL
4109	#define PORT_PHY_QCFG_RESP_ACTIVE_FEC_SFT 4
4110	#define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE (0x0UL << 4)
4111	#define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE (0x1UL << 4)
4112	#define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE (0x2UL << 4)
4113	#define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE (0x3UL << 4)
4114	#define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE (0x4UL << 4)
4115	#define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE (0x5UL << 4)
4116	#define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE (0x6UL << 4)
4117	#define PORT_PHY_QCFG_RESP_ACTIVE_FEC_LAST PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE
4118	__le16 link_speed;
4119	#define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL
4120	#define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 0xaUL
4121	#define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 0x14UL
4122	#define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL
4123	#define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 0x64UL
4124	#define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 0xc8UL
4125	#define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 0xfaUL
4126	#define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 0x190UL
4127	#define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 0x1f4UL
4128	#define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL
4129	#define PORT_PHY_QCFG_RESP_LINK_SPEED_200GB 0x7d0UL
4130	#define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 0xffffUL
4131	#define PORT_PHY_QCFG_RESP_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_LINK_SPEED_10MB
4132	u8 duplex_cfg;
4133	#define PORT_PHY_QCFG_RESP_DUPLEX_CFG_HALF 0x0UL
4134	#define PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 0x1UL
4135	#define PORT_PHY_QCFG_RESP_DUPLEX_CFG_LAST PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL
4136	u8 pause;
4137	#define PORT_PHY_QCFG_RESP_PAUSE_TX 0x1UL
4138	#define PORT_PHY_QCFG_RESP_PAUSE_RX 0x2UL
4139	__le16 support_speeds;
4140	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD 0x1UL
4141	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 0x2UL
4142	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD 0x4UL
4143	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 0x8UL
4144	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 0x10UL
4145	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 0x20UL
4146	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 0x40UL
4147	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 0x80UL
4148	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 0x100UL
4149	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 0x200UL
4150	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 0x400UL
4151	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 0x800UL
4152	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD 0x1000UL
4153	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB 0x2000UL
4154	__le16 force_link_speed;
4155	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB 0x1UL
4156	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB 0xaUL
4157	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB 0x14UL
4158	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB 0x19UL
4159	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB 0x64UL
4160	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB 0xc8UL
4161	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB 0xfaUL
4162	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB 0x190UL
4163	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB 0x1f4UL
4164	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB 0x3e8UL
4165	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 0xffffUL
4166	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB
4167	u8 auto_mode;
4168	#define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE 0x0UL
4169	#define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS 0x1UL
4170	#define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED 0x2UL
4171	#define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 0x3UL
4172	#define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 0x4UL
4173	#define PORT_PHY_QCFG_RESP_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK
4174	u8 auto_pause;
4175	#define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX 0x1UL
4176	#define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX 0x2UL
4177	#define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL
4178	__le16 auto_link_speed;
4179	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB 0x1UL
4180	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB 0xaUL
4181	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB 0x14UL
4182	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB 0x19UL
4183	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB 0x64UL
4184	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB 0xc8UL
4185	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB 0xfaUL
4186	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB 0x190UL
4187	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB 0x1f4UL
4188	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB 0x3e8UL
4189	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 0xffffUL
4190	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB
4191	__le16 auto_link_speed_mask;
4192	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL
4193	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB 0x2UL
4194	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL
4195	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB 0x8UL
4196	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB 0x10UL
4197	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL
4198	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB 0x40UL
4199	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB 0x80UL
4200	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB 0x100UL
4201	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB 0x200UL
4202	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB 0x400UL
4203	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB 0x800UL
4204	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL
4205	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB 0x2000UL
4206	u8 wirespeed;
4207	#define PORT_PHY_QCFG_RESP_WIRESPEED_OFF 0x0UL
4208	#define PORT_PHY_QCFG_RESP_WIRESPEED_ON 0x1UL
4209	#define PORT_PHY_QCFG_RESP_WIRESPEED_LAST PORT_PHY_QCFG_RESP_WIRESPEED_ON
4210	u8 lpbk;
4211	#define PORT_PHY_QCFG_RESP_LPBK_NONE 0x0UL
4212	#define PORT_PHY_QCFG_RESP_LPBK_LOCAL 0x1UL
4213	#define PORT_PHY_QCFG_RESP_LPBK_REMOTE 0x2UL
4214	#define PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 0x3UL
4215	#define PORT_PHY_QCFG_RESP_LPBK_LAST PORT_PHY_QCFG_RESP_LPBK_EXTERNAL
4216	u8 force_pause;
4217	#define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL
4218	#define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL
4219	u8 module_status;
4220	#define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE 0x0UL
4221	#define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX 0x1UL
4222	#define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG 0x2UL
4223	#define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN 0x3UL
4224	#define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED 0x4UL
4225	#define PORT_PHY_QCFG_RESP_MODULE_STATUS_CURRENTFAULT 0x5UL
4226	#define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 0xffUL
4227	#define PORT_PHY_QCFG_RESP_MODULE_STATUS_LAST PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE
4228	__le32 preemphasis;
4229	u8 phy_maj;
4230	u8 phy_min;
4231	u8 phy_bld;
4232	u8 phy_type;
4233	#define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN 0x0UL
4234	#define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR 0x1UL
4235	#define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4 0x2UL
4236	#define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR 0x3UL
4237	#define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR 0x4UL
4238	#define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2 0x5UL
4239	#define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX 0x6UL
4240	#define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR 0x7UL
4241	#define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET 0x8UL
4242	#define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE 0x9UL
4243	#define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY 0xaUL
4244	#define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L 0xbUL
4245	#define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S 0xcUL
4246	#define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N 0xdUL
4247	#define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR 0xeUL
4248	#define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4 0xfUL
4249	#define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4 0x10UL
4250	#define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4 0x11UL
4251	#define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4 0x12UL
4252	#define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10 0x13UL
4253	#define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4 0x14UL
4254	#define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4 0x15UL
4255	#define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4 0x16UL
4256	#define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4 0x17UL
4257	#define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE 0x18UL
4258	#define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET 0x19UL
4259	#define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX 0x1aUL
4260	#define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX 0x1bUL
4261	#define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4 0x1cUL
4262	#define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4 0x1dUL
4263	#define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4 0x1eUL
4264	#define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4 0x1fUL
4265	#define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASECR 0x20UL
4266	#define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASESR 0x21UL
4267	#define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASELR 0x22UL
4268	#define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASEER 0x23UL
4269	#define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR2 0x24UL
4270	#define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR2 0x25UL
4271	#define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR2 0x26UL
4272	#define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER2 0x27UL
4273	#define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER2
4274	u8 media_type;
4275	#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL
4276	#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP 0x1UL
4277	#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC 0x2UL
4278	#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 0x3UL
4279	#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_LAST PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE
4280	u8 xcvr_pkg_type;
4281	#define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL 0x1UL
4282	#define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 0x2UL
4283	#define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL
4284	u8 eee_config_phy_addr;
4285	#define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK 0x1fUL
4286	#define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT 0
4287	#define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK 0xe0UL
4288	#define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT 5
4289	#define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED 0x20UL
4290	#define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE 0x40UL
4291	#define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI 0x80UL
4292	u8 parallel_detect;
4293	#define PORT_PHY_QCFG_RESP_PARALLEL_DETECT 0x1UL
4294	__le16 link_partner_adv_speeds;
4295	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD 0x1UL
4296	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB 0x2UL
4297	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD 0x4UL
4298	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB 0x8UL
4299	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB 0x10UL
4300	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB 0x20UL
4301	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB 0x40UL
4302	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB 0x80UL
4303	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB 0x100UL
4304	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB 0x200UL
4305	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB 0x400UL
4306	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB 0x800UL
4307	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD 0x1000UL
4308	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB 0x2000UL
4309	u8 link_partner_adv_auto_mode;
4310	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE 0x0UL
4311	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS 0x1UL
4312	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED 0x2UL
4313	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW 0x3UL
4314	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 0x4UL
4315	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK
4316	u8 link_partner_adv_pause;
4317	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX 0x1UL
4318	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX 0x2UL
4319	__le16 adv_eee_link_speed_mask;
4320	#define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL
4321	#define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL
4322	#define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL
4323	#define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL
4324	#define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL
4325	#define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL
4326	#define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL
4327	__le16 link_partner_adv_eee_link_speed_mask;
4328	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL
4329	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL
4330	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL
4331	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL
4332	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL
4333	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL
4334	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL
4335	__le32 xcvr_identifier_type_tx_lpi_timer;
4336	#define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK 0xffffffUL
4337	#define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT 0
4338	#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK 0xff000000UL
4339	#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT 24
4340	#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN (0x0UL << 24)
4341	#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP (0x3UL << 24)
4342	#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP (0xcUL << 24)
4343	#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS (0xdUL << 24)
4344	#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 (0x11UL << 24)
4345	#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28
4346	__le16 fec_cfg;
4347	#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED 0x1UL
4348	#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED 0x2UL
4349	#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED 0x4UL
4350	#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED 0x8UL
4351	#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 0x10UL
4352	#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED 0x20UL
4353	#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED 0x40UL
4354	#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_SUPPORTED 0x80UL
4355	#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_ENABLED 0x100UL
4356	#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_SUPPORTED 0x200UL
4357	#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_ENABLED 0x400UL
4358	#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_SUPPORTED 0x800UL
4359	#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_ENABLED 0x1000UL
4360	#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_SUPPORTED 0x2000UL
4361	#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_ENABLED 0x4000UL
4362	u8 duplex_state;
4363	#define PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF 0x0UL
4364	#define PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 0x1UL
4365	#define PORT_PHY_QCFG_RESP_DUPLEX_STATE_LAST PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL
4366	u8 option_flags;
4367	#define PORT_PHY_QCFG_RESP_OPTION_FLAGS_MEDIA_AUTO_DETECT 0x1UL
4368	#define PORT_PHY_QCFG_RESP_OPTION_FLAGS_SIGNAL_MODE_KNOWN 0x2UL
4369	char phy_vendor_name[16];
4370	char phy_vendor_partnumber[16];
4371	__le16 support_pam4_speeds;
4372	#define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G 0x1UL
4373	#define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G 0x2UL
4374	#define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G 0x4UL
4375	__le16 force_pam4_link_speed;
4376	#define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_50GB 0x1f4UL
4377	#define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL
4378	#define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL
4379	#define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB
4380	__le16 auto_pam4_link_speed_mask;
4381	#define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_50G 0x1UL
4382	#define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_100G 0x2UL
4383	#define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_200G 0x4UL
4384	u8 link_partner_pam4_adv_speeds;
4385	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_50GB 0x1UL
4386	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_100GB 0x2UL
4387	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_200GB 0x4UL
4388	u8 link_down_reason;
4389	#define PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_RF 0x1UL
4390	u8 unused_0[7];
4391	u8 valid;
4392	};
4393
4394	/* hwrm_port_mac_cfg_input (size:448b/56B) */
4395	struct hwrm_port_mac_cfg_input {
4396	__le16 req_type;
4397	__le16 cmpl_ring;
4398	__le16 seq_id;
4399	__le16 target_id;
4400	__le64 resp_addr;
4401	__le32 flags;
4402	#define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK 0x1UL
4403	#define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_ENABLE 0x2UL
4404	#define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE 0x4UL
4405	#define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE 0x8UL
4406	#define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE 0x10UL
4407	#define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE 0x20UL
4408	#define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE 0x40UL
4409	#define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE 0x80UL
4410	#define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE 0x100UL
4411	#define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE 0x200UL
4412	#define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE 0x400UL
4413	#define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE 0x800UL
4414	#define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE 0x1000UL
4415	#define PORT_MAC_CFG_REQ_FLAGS_PTP_ONE_STEP_TX_TS 0x2000UL
4416	#define PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE 0x4000UL
4417	#define PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_DISABLE 0x8000UL
4418	__le32 enables;
4419	#define PORT_MAC_CFG_REQ_ENABLES_IPG 0x1UL
4420	#define PORT_MAC_CFG_REQ_ENABLES_LPBK 0x2UL
4421	#define PORT_MAC_CFG_REQ_ENABLES_VLAN_PRI2COS_MAP_PRI 0x4UL
4422	#define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI 0x10UL
4423	#define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI 0x20UL
4424	#define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE 0x40UL
4425	#define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE 0x80UL
4426	#define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG 0x100UL
4427	#define PORT_MAC_CFG_REQ_ENABLES_PTP_FREQ_ADJ_PPB 0x200UL
4428	#define PORT_MAC_CFG_REQ_ENABLES_PTP_ADJ_PHASE 0x400UL
4429	__le16 port_id;
4430	u8 ipg;
4431	u8 lpbk;
4432	#define PORT_MAC_CFG_REQ_LPBK_NONE 0x0UL
4433	#define PORT_MAC_CFG_REQ_LPBK_LOCAL 0x1UL
4434	#define PORT_MAC_CFG_REQ_LPBK_REMOTE 0x2UL
4435	#define PORT_MAC_CFG_REQ_LPBK_LAST PORT_MAC_CFG_REQ_LPBK_REMOTE
4436	u8 vlan_pri2cos_map_pri;
4437	u8 reserved1;
4438	u8 tunnel_pri2cos_map_pri;
4439	u8 dscp2pri_map_pri;
4440	__le16 rx_ts_capture_ptp_msg_type;
4441	__le16 tx_ts_capture_ptp_msg_type;
4442	u8 cos_field_cfg;
4443	#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_RSVD1 0x1UL
4444	#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_MASK 0x6UL
4445	#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_SFT 1
4446	#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (0x0UL << 1)
4447	#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (0x1UL << 1)
4448	#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (0x2UL << 1)
4449	#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 1)
4450	#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
4451	#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK 0x18UL
4452	#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT 3
4453	#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (0x0UL << 3)
4454	#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (0x1UL << 3)
4455	#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (0x2UL << 3)
4456	#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 3)
4457	#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
4458	#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK 0xe0UL
4459	#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT 5
4460	u8 unused_0[3];
4461	__le32 ptp_freq_adj_ppb;
4462	u8 unused_1[4];
4463	__le64 ptp_adj_phase;
4464	};
4465
4466	/* hwrm_port_mac_cfg_output (size:128b/16B) */
4467	struct hwrm_port_mac_cfg_output {
4468	__le16 error_code;
4469	__le16 req_type;
4470	__le16 seq_id;
4471	__le16 resp_len;
4472	__le16 mru;
4473	__le16 mtu;
4474	u8 ipg;
4475	u8 lpbk;
4476	#define PORT_MAC_CFG_RESP_LPBK_NONE 0x0UL
4477	#define PORT_MAC_CFG_RESP_LPBK_LOCAL 0x1UL
4478	#define PORT_MAC_CFG_RESP_LPBK_REMOTE 0x2UL
4479	#define PORT_MAC_CFG_RESP_LPBK_LAST PORT_MAC_CFG_RESP_LPBK_REMOTE
4480	u8 unused_0;
4481	u8 valid;
4482	};
4483
4484	/* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */
4485	struct hwrm_port_mac_ptp_qcfg_input {
4486	__le16 req_type;
4487	__le16 cmpl_ring;
4488	__le16 seq_id;
4489	__le16 target_id;
4490	__le64 resp_addr;
4491	__le16 port_id;
4492	u8 unused_0[6];
4493	};
4494
4495	/* hwrm_port_mac_ptp_qcfg_output (size:704b/88B) */
4496	struct hwrm_port_mac_ptp_qcfg_output {
4497	__le16 error_code;
4498	__le16 req_type;
4499	__le16 seq_id;
4500	__le16 resp_len;
4501	u8 flags;
4502	#define PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS 0x1UL
4503	#define PORT_MAC_PTP_QCFG_RESP_FLAGS_ONE_STEP_TX_TS 0x4UL
4504	#define PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS 0x8UL
4505	#define PORT_MAC_PTP_QCFG_RESP_FLAGS_PARTIAL_DIRECT_ACCESS_REF_CLOCK 0x10UL
4506	#define PORT_MAC_PTP_QCFG_RESP_FLAGS_RTC_CONFIGURED 0x20UL
4507	u8 unused_0[3];
4508	__le32 rx_ts_reg_off_lower;
4509	__le32 rx_ts_reg_off_upper;
4510	__le32 rx_ts_reg_off_seq_id;
4511	__le32 rx_ts_reg_off_src_id_0;
4512	__le32 rx_ts_reg_off_src_id_1;
4513	__le32 rx_ts_reg_off_src_id_2;
4514	__le32 rx_ts_reg_off_domain_id;
4515	__le32 rx_ts_reg_off_fifo;
4516	__le32 rx_ts_reg_off_fifo_adv;
4517	__le32 rx_ts_reg_off_granularity;
4518	__le32 tx_ts_reg_off_lower;
4519	__le32 tx_ts_reg_off_upper;
4520	__le32 tx_ts_reg_off_seq_id;
4521	__le32 tx_ts_reg_off_fifo;
4522	__le32 tx_ts_reg_off_granularity;
4523	__le32 ts_ref_clock_reg_lower;
4524	__le32 ts_ref_clock_reg_upper;
4525	u8 unused_1[7];
4526	u8 valid;
4527	};
4528
4529	/* tx_port_stats (size:3264b/408B) */
4530	struct tx_port_stats {
4531	__le64 tx_64b_frames;
4532	__le64 tx_65b_127b_frames;
4533	__le64 tx_128b_255b_frames;
4534	__le64 tx_256b_511b_frames;
4535	__le64 tx_512b_1023b_frames;
4536	__le64 tx_1024b_1518b_frames;
4537	__le64 tx_good_vlan_frames;
4538	__le64 tx_1519b_2047b_frames;
4539	__le64 tx_2048b_4095b_frames;
4540	__le64 tx_4096b_9216b_frames;
4541	__le64 tx_9217b_16383b_frames;
4542	__le64 tx_good_frames;
4543	__le64 tx_total_frames;
4544	__le64 tx_ucast_frames;
4545	__le64 tx_mcast_frames;
4546	__le64 tx_bcast_frames;
4547	__le64 tx_pause_frames;
4548	__le64 tx_pfc_frames;
4549	__le64 tx_jabber_frames;
4550	__le64 tx_fcs_err_frames;
4551	__le64 tx_control_frames;
4552	__le64 tx_oversz_frames;
4553	__le64 tx_single_dfrl_frames;
4554	__le64 tx_multi_dfrl_frames;
4555	__le64 tx_single_coll_frames;
4556	__le64 tx_multi_coll_frames;
4557	__le64 tx_late_coll_frames;
4558	__le64 tx_excessive_coll_frames;
4559	__le64 tx_frag_frames;
4560	__le64 tx_err;
4561	__le64 tx_tagged_frames;
4562	__le64 tx_dbl_tagged_frames;
4563	__le64 tx_runt_frames;
4564	__le64 tx_fifo_underruns;
4565	__le64 tx_pfc_ena_frames_pri0;
4566	__le64 tx_pfc_ena_frames_pri1;
4567	__le64 tx_pfc_ena_frames_pri2;
4568	__le64 tx_pfc_ena_frames_pri3;
4569	__le64 tx_pfc_ena_frames_pri4;
4570	__le64 tx_pfc_ena_frames_pri5;
4571	__le64 tx_pfc_ena_frames_pri6;
4572	__le64 tx_pfc_ena_frames_pri7;
4573	__le64 tx_eee_lpi_events;
4574	__le64 tx_eee_lpi_duration;
4575	__le64 tx_llfc_logical_msgs;
4576	__le64 tx_hcfc_msgs;
4577	__le64 tx_total_collisions;
4578	__le64 tx_bytes;
4579	__le64 tx_xthol_frames;
4580	__le64 tx_stat_discard;
4581	__le64 tx_stat_error;
4582	};
4583
4584	/* rx_port_stats (size:4224b/528B) */
4585	struct rx_port_stats {
4586	__le64 rx_64b_frames;
4587	__le64 rx_65b_127b_frames;
4588	__le64 rx_128b_255b_frames;
4589	__le64 rx_256b_511b_frames;
4590	__le64 rx_512b_1023b_frames;
4591	__le64 rx_1024b_1518b_frames;
4592	__le64 rx_good_vlan_frames;
4593	__le64 rx_1519b_2047b_frames;
4594	__le64 rx_2048b_4095b_frames;
4595	__le64 rx_4096b_9216b_frames;
4596	__le64 rx_9217b_16383b_frames;
4597	__le64 rx_total_frames;
4598	__le64 rx_ucast_frames;
4599	__le64 rx_mcast_frames;
4600	__le64 rx_bcast_frames;
4601	__le64 rx_fcs_err_frames;
4602	__le64 rx_ctrl_frames;
4603	__le64 rx_pause_frames;
4604	__le64 rx_pfc_frames;
4605	__le64 rx_unsupported_opcode_frames;
4606	__le64 rx_unsupported_da_pausepfc_frames;
4607	__le64 rx_wrong_sa_frames;
4608	__le64 rx_align_err_frames;
4609	__le64 rx_oor_len_frames;
4610	__le64 rx_code_err_frames;
4611	__le64 rx_false_carrier_frames;
4612	__le64 rx_ovrsz_frames;
4613	__le64 rx_jbr_frames;
4614	__le64 rx_mtu_err_frames;
4615	__le64 rx_match_crc_frames;
4616	__le64 rx_promiscuous_frames;
4617	__le64 rx_tagged_frames;
4618	__le64 rx_double_tagged_frames;
4619	__le64 rx_trunc_frames;
4620	__le64 rx_good_frames;
4621	__le64 rx_pfc_xon2xoff_frames_pri0;
4622	__le64 rx_pfc_xon2xoff_frames_pri1;
4623	__le64 rx_pfc_xon2xoff_frames_pri2;
4624	__le64 rx_pfc_xon2xoff_frames_pri3;
4625	__le64 rx_pfc_xon2xoff_frames_pri4;
4626	__le64 rx_pfc_xon2xoff_frames_pri5;
4627	__le64 rx_pfc_xon2xoff_frames_pri6;
4628	__le64 rx_pfc_xon2xoff_frames_pri7;
4629	__le64 rx_pfc_ena_frames_pri0;
4630	__le64 rx_pfc_ena_frames_pri1;
4631	__le64 rx_pfc_ena_frames_pri2;
4632	__le64 rx_pfc_ena_frames_pri3;
4633	__le64 rx_pfc_ena_frames_pri4;
4634	__le64 rx_pfc_ena_frames_pri5;
4635	__le64 rx_pfc_ena_frames_pri6;
4636	__le64 rx_pfc_ena_frames_pri7;
4637	__le64 rx_sch_crc_err_frames;
4638	__le64 rx_undrsz_frames;
4639	__le64 rx_frag_frames;
4640	__le64 rx_eee_lpi_events;
4641	__le64 rx_eee_lpi_duration;
4642	__le64 rx_llfc_physical_msgs;
4643	__le64 rx_llfc_logical_msgs;
4644	__le64 rx_llfc_msgs_with_crc_err;
4645	__le64 rx_hcfc_msgs;
4646	__le64 rx_hcfc_msgs_with_crc_err;
4647	__le64 rx_bytes;
4648	__le64 rx_runt_bytes;
4649	__le64 rx_runt_frames;
4650	__le64 rx_stat_discard;
4651	__le64 rx_stat_err;
4652	};
4653
4654	/* hwrm_port_qstats_input (size:320b/40B) */
4655	struct hwrm_port_qstats_input {
4656	__le16 req_type;
4657	__le16 cmpl_ring;
4658	__le16 seq_id;
4659	__le16 target_id;
4660	__le64 resp_addr;
4661	__le16 port_id;
4662	u8 flags;
4663	#define PORT_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL
4664	u8 unused_0[5];
4665	__le64 tx_stat_host_addr;
4666	__le64 rx_stat_host_addr;
4667	};
4668
4669	/* hwrm_port_qstats_output (size:128b/16B) */
4670	struct hwrm_port_qstats_output {
4671	__le16 error_code;
4672	__le16 req_type;
4673	__le16 seq_id;
4674	__le16 resp_len;
4675	__le16 tx_stat_size;
4676	__le16 rx_stat_size;
4677	u8 unused_0[3];
4678	u8 valid;
4679	};
4680
4681	/* tx_port_stats_ext (size:2048b/256B) */
4682	struct tx_port_stats_ext {
4683	__le64 tx_bytes_cos0;
4684	__le64 tx_bytes_cos1;
4685	__le64 tx_bytes_cos2;
4686	__le64 tx_bytes_cos3;
4687	__le64 tx_bytes_cos4;
4688	__le64 tx_bytes_cos5;
4689	__le64 tx_bytes_cos6;
4690	__le64 tx_bytes_cos7;
4691	__le64 tx_packets_cos0;
4692	__le64 tx_packets_cos1;
4693	__le64 tx_packets_cos2;
4694	__le64 tx_packets_cos3;
4695	__le64 tx_packets_cos4;
4696	__le64 tx_packets_cos5;
4697	__le64 tx_packets_cos6;
4698	__le64 tx_packets_cos7;
4699	__le64 pfc_pri0_tx_duration_us;
4700	__le64 pfc_pri0_tx_transitions;
4701	__le64 pfc_pri1_tx_duration_us;
4702	__le64 pfc_pri1_tx_transitions;
4703	__le64 pfc_pri2_tx_duration_us;
4704	__le64 pfc_pri2_tx_transitions;
4705	__le64 pfc_pri3_tx_duration_us;
4706	__le64 pfc_pri3_tx_transitions;
4707	__le64 pfc_pri4_tx_duration_us;
4708	__le64 pfc_pri4_tx_transitions;
4709	__le64 pfc_pri5_tx_duration_us;
4710	__le64 pfc_pri5_tx_transitions;
4711	__le64 pfc_pri6_tx_duration_us;
4712	__le64 pfc_pri6_tx_transitions;
4713	__le64 pfc_pri7_tx_duration_us;
4714	__le64 pfc_pri7_tx_transitions;
4715	};
4716
4717	/* rx_port_stats_ext (size:3904b/488B) */
4718	struct rx_port_stats_ext {
4719	__le64 link_down_events;
4720	__le64 continuous_pause_events;
4721	__le64 resume_pause_events;
4722	__le64 continuous_roce_pause_events;
4723	__le64 resume_roce_pause_events;
4724	__le64 rx_bytes_cos0;
4725	__le64 rx_bytes_cos1;
4726	__le64 rx_bytes_cos2;
4727	__le64 rx_bytes_cos3;
4728	__le64 rx_bytes_cos4;
4729	__le64 rx_bytes_cos5;
4730	__le64 rx_bytes_cos6;
4731	__le64 rx_bytes_cos7;
4732	__le64 rx_packets_cos0;
4733	__le64 rx_packets_cos1;
4734	__le64 rx_packets_cos2;
4735	__le64 rx_packets_cos3;
4736	__le64 rx_packets_cos4;
4737	__le64 rx_packets_cos5;
4738	__le64 rx_packets_cos6;
4739	__le64 rx_packets_cos7;
4740	__le64 pfc_pri0_rx_duration_us;
4741	__le64 pfc_pri0_rx_transitions;
4742	__le64 pfc_pri1_rx_duration_us;
4743	__le64 pfc_pri1_rx_transitions;
4744	__le64 pfc_pri2_rx_duration_us;
4745	__le64 pfc_pri2_rx_transitions;
4746	__le64 pfc_pri3_rx_duration_us;
4747	__le64 pfc_pri3_rx_transitions;
4748	__le64 pfc_pri4_rx_duration_us;
4749	__le64 pfc_pri4_rx_transitions;
4750	__le64 pfc_pri5_rx_duration_us;
4751	__le64 pfc_pri5_rx_transitions;
4752	__le64 pfc_pri6_rx_duration_us;
4753	__le64 pfc_pri6_rx_transitions;
4754	__le64 pfc_pri7_rx_duration_us;
4755	__le64 pfc_pri7_rx_transitions;
4756	__le64 rx_bits;
4757	__le64 rx_buffer_passed_threshold;
4758	__le64 rx_pcs_symbol_err;
4759	__le64 rx_corrected_bits;
4760	__le64 rx_discard_bytes_cos0;
4761	__le64 rx_discard_bytes_cos1;
4762	__le64 rx_discard_bytes_cos2;
4763	__le64 rx_discard_bytes_cos3;
4764	__le64 rx_discard_bytes_cos4;
4765	__le64 rx_discard_bytes_cos5;
4766	__le64 rx_discard_bytes_cos6;
4767	__le64 rx_discard_bytes_cos7;
4768	__le64 rx_discard_packets_cos0;
4769	__le64 rx_discard_packets_cos1;
4770	__le64 rx_discard_packets_cos2;
4771	__le64 rx_discard_packets_cos3;
4772	__le64 rx_discard_packets_cos4;
4773	__le64 rx_discard_packets_cos5;
4774	__le64 rx_discard_packets_cos6;
4775	__le64 rx_discard_packets_cos7;
4776	__le64 rx_fec_corrected_blocks;
4777	__le64 rx_fec_uncorrectable_blocks;
4778	__le64 rx_filter_miss;
4779	__le64 rx_fec_symbol_err;
4780	};
4781
4782	/* hwrm_port_qstats_ext_input (size:320b/40B) */
4783	struct hwrm_port_qstats_ext_input {
4784	__le16 req_type;
4785	__le16 cmpl_ring;
4786	__le16 seq_id;
4787	__le16 target_id;
4788	__le64 resp_addr;
4789	__le16 port_id;
4790	__le16 tx_stat_size;
4791	__le16 rx_stat_size;
4792	u8 flags;
4793	#define PORT_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 0x1UL
4794	u8 unused_0;
4795	__le64 tx_stat_host_addr;
4796	__le64 rx_stat_host_addr;
4797	};
4798
4799	/* hwrm_port_qstats_ext_output (size:128b/16B) */
4800	struct hwrm_port_qstats_ext_output {
4801	__le16 error_code;
4802	__le16 req_type;
4803	__le16 seq_id;
4804	__le16 resp_len;
4805	__le16 tx_stat_size;
4806	__le16 rx_stat_size;
4807	__le16 total_active_cos_queues;
4808	u8 flags;
4809	#define PORT_QSTATS_EXT_RESP_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED 0x1UL
4810	u8 valid;
4811	};
4812
4813	/* hwrm_port_lpbk_qstats_input (size:128b/16B) */
4814	struct hwrm_port_lpbk_qstats_input {
4815	__le16 req_type;
4816	__le16 cmpl_ring;
4817	__le16 seq_id;
4818	__le16 target_id;
4819	__le64 resp_addr;
4820	};
4821
4822	/* hwrm_port_lpbk_qstats_output (size:768b/96B) */
4823	struct hwrm_port_lpbk_qstats_output {
4824	__le16 error_code;
4825	__le16 req_type;
4826	__le16 seq_id;
4827	__le16 resp_len;
4828	__le64 lpbk_ucast_frames;
4829	__le64 lpbk_mcast_frames;
4830	__le64 lpbk_bcast_frames;
4831	__le64 lpbk_ucast_bytes;
4832	__le64 lpbk_mcast_bytes;
4833	__le64 lpbk_bcast_bytes;
4834	__le64 tx_stat_discard;
4835	__le64 tx_stat_error;
4836	__le64 rx_stat_discard;
4837	__le64 rx_stat_error;
4838	u8 unused_0[7];
4839	u8 valid;
4840	};
4841
4842	/* hwrm_port_ecn_qstats_input (size:256b/32B) */
4843	struct hwrm_port_ecn_qstats_input {
4844	__le16 req_type;
4845	__le16 cmpl_ring;
4846	__le16 seq_id;
4847	__le16 target_id;
4848	__le64 resp_addr;
4849	__le16 port_id;
4850	__le16 ecn_stat_buf_size;
4851	u8 flags;
4852	#define PORT_ECN_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL
4853	u8 unused_0[3];
4854	__le64 ecn_stat_host_addr;
4855	};
4856
4857	/* hwrm_port_ecn_qstats_output (size:128b/16B) */
4858	struct hwrm_port_ecn_qstats_output {
4859	__le16 error_code;
4860	__le16 req_type;
4861	__le16 seq_id;
4862	__le16 resp_len;
4863	__le16 ecn_stat_buf_size;
4864	u8 mark_en;
4865	u8 unused_0[4];
4866	u8 valid;
4867	};
4868
4869	/* port_stats_ecn (size:512b/64B) */
4870	struct port_stats_ecn {
4871	__le64 mark_cnt_cos0;
4872	__le64 mark_cnt_cos1;
4873	__le64 mark_cnt_cos2;
4874	__le64 mark_cnt_cos3;
4875	__le64 mark_cnt_cos4;
4876	__le64 mark_cnt_cos5;
4877	__le64 mark_cnt_cos6;
4878	__le64 mark_cnt_cos7;
4879	};
4880
4881	/* hwrm_port_clr_stats_input (size:192b/24B) */
4882	struct hwrm_port_clr_stats_input {
4883	__le16 req_type;
4884	__le16 cmpl_ring;
4885	__le16 seq_id;
4886	__le16 target_id;
4887	__le64 resp_addr;
4888	__le16 port_id;
4889	u8 flags;
4890	#define PORT_CLR_STATS_REQ_FLAGS_ROCE_COUNTERS 0x1UL
4891	u8 unused_0[5];
4892	};
4893
4894	/* hwrm_port_clr_stats_output (size:128b/16B) */
4895	struct hwrm_port_clr_stats_output {
4896	__le16 error_code;
4897	__le16 req_type;
4898	__le16 seq_id;
4899	__le16 resp_len;
4900	u8 unused_0[7];
4901	u8 valid;
4902	};
4903
4904	/* hwrm_port_lpbk_clr_stats_input (size:128b/16B) */
4905	struct hwrm_port_lpbk_clr_stats_input {
4906	__le16 req_type;
4907	__le16 cmpl_ring;
4908	__le16 seq_id;
4909	__le16 target_id;
4910	__le64 resp_addr;
4911	};
4912
4913	/* hwrm_port_lpbk_clr_stats_output (size:128b/16B) */
4914	struct hwrm_port_lpbk_clr_stats_output {
4915	__le16 error_code;
4916	__le16 req_type;
4917	__le16 seq_id;
4918	__le16 resp_len;
4919	u8 unused_0[7];
4920	u8 valid;
4921	};
4922
4923	/* hwrm_port_ts_query_input (size:320b/40B) */
4924	struct hwrm_port_ts_query_input {
4925	__le16 req_type;
4926	__le16 cmpl_ring;
4927	__le16 seq_id;
4928	__le16 target_id;
4929	__le64 resp_addr;
4930	__le32 flags;
4931	#define PORT_TS_QUERY_REQ_FLAGS_PATH 0x1UL
4932	#define PORT_TS_QUERY_REQ_FLAGS_PATH_TX 0x0UL
4933	#define PORT_TS_QUERY_REQ_FLAGS_PATH_RX 0x1UL
4934	#define PORT_TS_QUERY_REQ_FLAGS_PATH_LAST PORT_TS_QUERY_REQ_FLAGS_PATH_RX
4935	#define PORT_TS_QUERY_REQ_FLAGS_CURRENT_TIME 0x2UL
4936	__le16 port_id;
4937	u8 unused_0[2];
4938	__le16 enables;
4939	#define PORT_TS_QUERY_REQ_ENABLES_TS_REQ_TIMEOUT 0x1UL
4940	#define PORT_TS_QUERY_REQ_ENABLES_PTP_SEQ_ID 0x2UL
4941	#define PORT_TS_QUERY_REQ_ENABLES_PTP_HDR_OFFSET 0x4UL
4942	__le16 ts_req_timeout;
4943	__le32 ptp_seq_id;
4944	__le16 ptp_hdr_offset;
4945	u8 unused_1[6];
4946	};
4947
4948	/* hwrm_port_ts_query_output (size:192b/24B) */
4949	struct hwrm_port_ts_query_output {
4950	__le16 error_code;
4951	__le16 req_type;
4952	__le16 seq_id;
4953	__le16 resp_len;
4954	__le64 ptp_msg_ts;
4955	__le16 ptp_msg_seqid;
4956	u8 unused_0[5];
4957	u8 valid;
4958	};
4959
4960	/* hwrm_port_phy_qcaps_input (size:192b/24B) */
4961	struct hwrm_port_phy_qcaps_input {
4962	__le16 req_type;
4963	__le16 cmpl_ring;
4964	__le16 seq_id;
4965	__le16 target_id;
4966	__le64 resp_addr;
4967	__le16 port_id;
4968	u8 unused_0[6];
4969	};
4970
4971	/* hwrm_port_phy_qcaps_output (size:256b/32B) */
4972	struct hwrm_port_phy_qcaps_output {
4973	__le16 error_code;
4974	__le16 req_type;
4975	__le16 seq_id;
4976	__le16 resp_len;
4977	u8 flags;
4978	#define PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED 0x1UL
4979	#define PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED 0x2UL
4980	#define PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED 0x4UL
4981	#define PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED 0x8UL
4982	#define PORT_PHY_QCAPS_RESP_FLAGS_CUMULATIVE_COUNTERS_ON_RESET 0x10UL
4983	#define PORT_PHY_QCAPS_RESP_FLAGS_LOCAL_LPBK_NOT_SUPPORTED 0x20UL
4984	#define PORT_PHY_QCAPS_RESP_FLAGS_FW_MANAGED_LINK_DOWN 0x40UL
4985	#define PORT_PHY_QCAPS_RESP_FLAGS_NO_FCS 0x80UL
4986	u8 port_cnt;
4987	#define PORT_PHY_QCAPS_RESP_PORT_CNT_UNKNOWN 0x0UL
4988	#define PORT_PHY_QCAPS_RESP_PORT_CNT_1 0x1UL
4989	#define PORT_PHY_QCAPS_RESP_PORT_CNT_2 0x2UL
4990	#define PORT_PHY_QCAPS_RESP_PORT_CNT_3 0x3UL
4991	#define PORT_PHY_QCAPS_RESP_PORT_CNT_4 0x4UL
4992	#define PORT_PHY_QCAPS_RESP_PORT_CNT_12 0xcUL
4993	#define PORT_PHY_QCAPS_RESP_PORT_CNT_LAST PORT_PHY_QCAPS_RESP_PORT_CNT_12
4994	__le16 supported_speeds_force_mode;
4995	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD 0x1UL
4996	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB 0x2UL
4997	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD 0x4UL
4998	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB 0x8UL
4999	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB 0x10UL
5000	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB 0x20UL
5001	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB 0x40UL
5002	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB 0x80UL
5003	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB 0x100UL
5004	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB 0x200UL
5005	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB 0x400UL
5006	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB 0x800UL
5007	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD 0x1000UL
5008	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB 0x2000UL
5009	__le16 supported_speeds_auto_mode;
5010	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD 0x1UL
5011	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB 0x2UL
5012	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD 0x4UL
5013	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB 0x8UL
5014	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB 0x10UL
5015	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB 0x20UL
5016	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB 0x40UL
5017	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB 0x80UL
5018	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB 0x100UL
5019	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB 0x200UL
5020	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB 0x400UL
5021	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB 0x800UL
5022	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD 0x1000UL
5023	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB 0x2000UL
5024	__le16 supported_speeds_eee_mode;
5025	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 0x1UL
5026	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB 0x2UL
5027	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 0x4UL
5028	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB 0x8UL
5029	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 0x10UL
5030	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 0x20UL
5031	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB 0x40UL
5032	__le32 tx_lpi_timer_low;
5033	#define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK 0xffffffUL
5034	#define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT 0
5035	#define PORT_PHY_QCAPS_RESP_RSVD2_MASK 0xff000000UL
5036	#define PORT_PHY_QCAPS_RESP_RSVD2_SFT 24
5037	__le32 valid_tx_lpi_timer_high;
5038	#define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK 0xffffffUL
5039	#define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 0
5040	#define PORT_PHY_QCAPS_RESP_RSVD_MASK 0xff000000UL
5041	#define PORT_PHY_QCAPS_RESP_RSVD_SFT 24
5042	__le16 supported_pam4_speeds_auto_mode;
5043	#define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_50G 0x1UL
5044	#define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_100G 0x2UL
5045	#define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_200G 0x4UL
5046	__le16 supported_pam4_speeds_force_mode;
5047	#define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_50G 0x1UL
5048	#define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_100G 0x2UL
5049	#define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_200G 0x4UL
5050	__le16 flags2;
5051	#define PORT_PHY_QCAPS_RESP_FLAGS2_PAUSE_UNSUPPORTED 0x1UL
5052	#define PORT_PHY_QCAPS_RESP_FLAGS2_PFC_UNSUPPORTED 0x2UL
5053	#define PORT_PHY_QCAPS_RESP_FLAGS2_BANK_ADDR_SUPPORTED 0x4UL
5054	u8 internal_port_cnt;
5055	u8 valid;
5056	};
5057
5058	/* hwrm_port_phy_i2c_read_input (size:320b/40B) */
5059	struct hwrm_port_phy_i2c_read_input {
5060	__le16 req_type;
5061	__le16 cmpl_ring;
5062	__le16 seq_id;
5063	__le16 target_id;
5064	__le64 resp_addr;
5065	__le32 flags;
5066	__le32 enables;
5067	#define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET 0x1UL
5068	#define PORT_PHY_I2C_READ_REQ_ENABLES_BANK_NUMBER 0x2UL
5069	__le16 port_id;
5070	u8 i2c_slave_addr;
5071	u8 bank_number;
5072	__le16 page_number;
5073	__le16 page_offset;
5074	u8 data_length;
5075	u8 unused_1[7];
5076	};
5077
5078	/* hwrm_port_phy_i2c_read_output (size:640b/80B) */
5079	struct hwrm_port_phy_i2c_read_output {
5080	__le16 error_code;
5081	__le16 req_type;
5082	__le16 seq_id;
5083	__le16 resp_len;
5084	__le32 data[16];
5085	u8 unused_0[7];
5086	u8 valid;
5087	};
5088
5089	/* hwrm_port_phy_mdio_write_input (size:320b/40B) */
5090	struct hwrm_port_phy_mdio_write_input {
5091	__le16 req_type;
5092	__le16 cmpl_ring;
5093	__le16 seq_id;
5094	__le16 target_id;
5095	__le64 resp_addr;
5096	__le32 unused_0[2];
5097	__le16 port_id;
5098	u8 phy_addr;
5099	u8 dev_addr;
5100	__le16 reg_addr;
5101	__le16 reg_data;
5102	u8 cl45_mdio;
5103	u8 unused_1[7];
5104	};
5105
5106	/* hwrm_port_phy_mdio_write_output (size:128b/16B) */
5107	struct hwrm_port_phy_mdio_write_output {
5108	__le16 error_code;
5109	__le16 req_type;
5110	__le16 seq_id;
5111	__le16 resp_len;
5112	u8 unused_0[7];
5113	u8 valid;
5114	};
5115
5116	/* hwrm_port_phy_mdio_read_input (size:256b/32B) */
5117	struct hwrm_port_phy_mdio_read_input {
5118	__le16 req_type;
5119	__le16 cmpl_ring;
5120	__le16 seq_id;
5121	__le16 target_id;
5122	__le64 resp_addr;
5123	__le32 unused_0[2];
5124	__le16 port_id;
5125	u8 phy_addr;
5126	u8 dev_addr;
5127	__le16 reg_addr;
5128	u8 cl45_mdio;
5129	u8 unused_1;
5130	};
5131
5132	/* hwrm_port_phy_mdio_read_output (size:128b/16B) */
5133	struct hwrm_port_phy_mdio_read_output {
5134	__le16 error_code;
5135	__le16 req_type;
5136	__le16 seq_id;
5137	__le16 resp_len;
5138	__le16 reg_data;
5139	u8 unused_0[5];
5140	u8 valid;
5141	};
5142
5143	/* hwrm_port_led_cfg_input (size:512b/64B) */
5144	struct hwrm_port_led_cfg_input {
5145	__le16 req_type;
5146	__le16 cmpl_ring;
5147	__le16 seq_id;
5148	__le16 target_id;
5149	__le64 resp_addr;
5150	__le32 enables;
5151	#define PORT_LED_CFG_REQ_ENABLES_LED0_ID 0x1UL
5152	#define PORT_LED_CFG_REQ_ENABLES_LED0_STATE 0x2UL
5153	#define PORT_LED_CFG_REQ_ENABLES_LED0_COLOR 0x4UL
5154	#define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_ON 0x8UL
5155	#define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_OFF 0x10UL
5156	#define PORT_LED_CFG_REQ_ENABLES_LED0_GROUP_ID 0x20UL
5157	#define PORT_LED_CFG_REQ_ENABLES_LED1_ID 0x40UL
5158	#define PORT_LED_CFG_REQ_ENABLES_LED1_STATE 0x80UL
5159	#define PORT_LED_CFG_REQ_ENABLES_LED1_COLOR 0x100UL
5160	#define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_ON 0x200UL
5161	#define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_OFF 0x400UL
5162	#define PORT_LED_CFG_REQ_ENABLES_LED1_GROUP_ID 0x800UL
5163	#define PORT_LED_CFG_REQ_ENABLES_LED2_ID 0x1000UL
5164	#define PORT_LED_CFG_REQ_ENABLES_LED2_STATE 0x2000UL
5165	#define PORT_LED_CFG_REQ_ENABLES_LED2_COLOR 0x4000UL
5166	#define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_ON 0x8000UL
5167	#define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_OFF 0x10000UL
5168	#define PORT_LED_CFG_REQ_ENABLES_LED2_GROUP_ID 0x20000UL
5169	#define PORT_LED_CFG_REQ_ENABLES_LED3_ID 0x40000UL
5170	#define PORT_LED_CFG_REQ_ENABLES_LED3_STATE 0x80000UL
5171	#define PORT_LED_CFG_REQ_ENABLES_LED3_COLOR 0x100000UL
5172	#define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_ON 0x200000UL
5173	#define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_OFF 0x400000UL
5174	#define PORT_LED_CFG_REQ_ENABLES_LED3_GROUP_ID 0x800000UL
5175	__le16 port_id;
5176	u8 num_leds;
5177	u8 rsvd;
5178	u8 led0_id;
5179	u8 led0_state;
5180	#define PORT_LED_CFG_REQ_LED0_STATE_DEFAULT 0x0UL
5181	#define PORT_LED_CFG_REQ_LED0_STATE_OFF 0x1UL
5182	#define PORT_LED_CFG_REQ_LED0_STATE_ON 0x2UL
5183	#define PORT_LED_CFG_REQ_LED0_STATE_BLINK 0x3UL
5184	#define PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 0x4UL
5185	#define PORT_LED_CFG_REQ_LED0_STATE_LAST PORT_LED_CFG_REQ_LED0_STATE_BLINKALT
5186	u8 led0_color;
5187	#define PORT_LED_CFG_REQ_LED0_COLOR_DEFAULT 0x0UL
5188	#define PORT_LED_CFG_REQ_LED0_COLOR_AMBER 0x1UL
5189	#define PORT_LED_CFG_REQ_LED0_COLOR_GREEN 0x2UL
5190	#define PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 0x3UL
5191	#define PORT_LED_CFG_REQ_LED0_COLOR_LAST PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER
5192	u8 unused_0;
5193	__le16 led0_blink_on;
5194	__le16 led0_blink_off;
5195	u8 led0_group_id;
5196	u8 rsvd0;
5197	u8 led1_id;
5198	u8 led1_state;
5199	#define PORT_LED_CFG_REQ_LED1_STATE_DEFAULT 0x0UL
5200	#define PORT_LED_CFG_REQ_LED1_STATE_OFF 0x1UL
5201	#define PORT_LED_CFG_REQ_LED1_STATE_ON 0x2UL
5202	#define PORT_LED_CFG_REQ_LED1_STATE_BLINK 0x3UL
5203	#define PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 0x4UL
5204	#define PORT_LED_CFG_REQ_LED1_STATE_LAST PORT_LED_CFG_REQ_LED1_STATE_BLINKALT
5205	u8 led1_color;
5206	#define PORT_LED_CFG_REQ_LED1_COLOR_DEFAULT 0x0UL
5207	#define PORT_LED_CFG_REQ_LED1_COLOR_AMBER 0x1UL
5208	#define PORT_LED_CFG_REQ_LED1_COLOR_GREEN 0x2UL
5209	#define PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 0x3UL
5210	#define PORT_LED_CFG_REQ_LED1_COLOR_LAST PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER
5211	u8 unused_1;
5212	__le16 led1_blink_on;
5213	__le16 led1_blink_off;
5214	u8 led1_group_id;
5215	u8 rsvd1;
5216	u8 led2_id;
5217	u8 led2_state;
5218	#define PORT_LED_CFG_REQ_LED2_STATE_DEFAULT 0x0UL
5219	#define PORT_LED_CFG_REQ_LED2_STATE_OFF 0x1UL
5220	#define PORT_LED_CFG_REQ_LED2_STATE_ON 0x2UL
5221	#define PORT_LED_CFG_REQ_LED2_STATE_BLINK 0x3UL
5222	#define PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 0x4UL
5223	#define PORT_LED_CFG_REQ_LED2_STATE_LAST PORT_LED_CFG_REQ_LED2_STATE_BLINKALT
5224	u8 led2_color;
5225	#define PORT_LED_CFG_REQ_LED2_COLOR_DEFAULT 0x0UL
5226	#define PORT_LED_CFG_REQ_LED2_COLOR_AMBER 0x1UL
5227	#define PORT_LED_CFG_REQ_LED2_COLOR_GREEN 0x2UL
5228	#define PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 0x3UL
5229	#define PORT_LED_CFG_REQ_LED2_COLOR_LAST PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER
5230	u8 unused_2;
5231	__le16 led2_blink_on;
5232	__le16 led2_blink_off;
5233	u8 led2_group_id;
5234	u8 rsvd2;
5235	u8 led3_id;
5236	u8 led3_state;
5237	#define PORT_LED_CFG_REQ_LED3_STATE_DEFAULT 0x0UL
5238	#define PORT_LED_CFG_REQ_LED3_STATE_OFF 0x1UL
5239	#define PORT_LED_CFG_REQ_LED3_STATE_ON 0x2UL
5240	#define PORT_LED_CFG_REQ_LED3_STATE_BLINK 0x3UL
5241	#define PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 0x4UL
5242	#define PORT_LED_CFG_REQ_LED3_STATE_LAST PORT_LED_CFG_REQ_LED3_STATE_BLINKALT
5243	u8 led3_color;
5244	#define PORT_LED_CFG_REQ_LED3_COLOR_DEFAULT 0x0UL
5245	#define PORT_LED_CFG_REQ_LED3_COLOR_AMBER 0x1UL
5246	#define PORT_LED_CFG_REQ_LED3_COLOR_GREEN 0x2UL
5247	#define PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 0x3UL
5248	#define PORT_LED_CFG_REQ_LED3_COLOR_LAST PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER
5249	u8 unused_3;
5250	__le16 led3_blink_on;
5251	__le16 led3_blink_off;
5252	u8 led3_group_id;
5253	u8 rsvd3;
5254	};
5255
5256	/* hwrm_port_led_cfg_output (size:128b/16B) */
5257	struct hwrm_port_led_cfg_output {
5258	__le16 error_code;
5259	__le16 req_type;
5260	__le16 seq_id;
5261	__le16 resp_len;
5262	u8 unused_0[7];
5263	u8 valid;
5264	};
5265
5266	/* hwrm_port_led_qcfg_input (size:192b/24B) */
5267	struct hwrm_port_led_qcfg_input {
5268	__le16 req_type;
5269	__le16 cmpl_ring;
5270	__le16 seq_id;
5271	__le16 target_id;
5272	__le64 resp_addr;
5273	__le16 port_id;
5274	u8 unused_0[6];
5275	};
5276
5277	/* hwrm_port_led_qcfg_output (size:448b/56B) */
5278	struct hwrm_port_led_qcfg_output {
5279	__le16 error_code;
5280	__le16 req_type;
5281	__le16 seq_id;
5282	__le16 resp_len;
5283	u8 num_leds;
5284	u8 led0_id;
5285	u8 led0_type;
5286	#define PORT_LED_QCFG_RESP_LED0_TYPE_SPEED 0x0UL
5287	#define PORT_LED_QCFG_RESP_LED0_TYPE_ACTIVITY 0x1UL
5288	#define PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 0xffUL
5289	#define PORT_LED_QCFG_RESP_LED0_TYPE_LAST PORT_LED_QCFG_RESP_LED0_TYPE_INVALID
5290	u8 led0_state;
5291	#define PORT_LED_QCFG_RESP_LED0_STATE_DEFAULT 0x0UL
5292	#define PORT_LED_QCFG_RESP_LED0_STATE_OFF 0x1UL
5293	#define PORT_LED_QCFG_RESP_LED0_STATE_ON 0x2UL
5294	#define PORT_LED_QCFG_RESP_LED0_STATE_BLINK 0x3UL
5295	#define PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 0x4UL
5296	#define PORT_LED_QCFG_RESP_LED0_STATE_LAST PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT
5297	u8 led0_color;
5298	#define PORT_LED_QCFG_RESP_LED0_COLOR_DEFAULT 0x0UL
5299	#define PORT_LED_QCFG_RESP_LED0_COLOR_AMBER 0x1UL
5300	#define PORT_LED_QCFG_RESP_LED0_COLOR_GREEN 0x2UL
5301	#define PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 0x3UL
5302	#define PORT_LED_QCFG_RESP_LED0_COLOR_LAST PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER
5303	u8 unused_0;
5304	__le16 led0_blink_on;
5305	__le16 led0_blink_off;
5306	u8 led0_group_id;
5307	u8 led1_id;
5308	u8 led1_type;
5309	#define PORT_LED_QCFG_RESP_LED1_TYPE_SPEED 0x0UL
5310	#define PORT_LED_QCFG_RESP_LED1_TYPE_ACTIVITY 0x1UL
5311	#define PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 0xffUL
5312	#define PORT_LED_QCFG_RESP_LED1_TYPE_LAST PORT_LED_QCFG_RESP_LED1_TYPE_INVALID
5313	u8 led1_state;
5314	#define PORT_LED_QCFG_RESP_LED1_STATE_DEFAULT 0x0UL
5315	#define PORT_LED_QCFG_RESP_LED1_STATE_OFF 0x1UL
5316	#define PORT_LED_QCFG_RESP_LED1_STATE_ON 0x2UL
5317	#define PORT_LED_QCFG_RESP_LED1_STATE_BLINK 0x3UL
5318	#define PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 0x4UL
5319	#define PORT_LED_QCFG_RESP_LED1_STATE_LAST PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT
5320	u8 led1_color;
5321	#define PORT_LED_QCFG_RESP_LED1_COLOR_DEFAULT 0x0UL
5322	#define PORT_LED_QCFG_RESP_LED1_COLOR_AMBER 0x1UL
5323	#define PORT_LED_QCFG_RESP_LED1_COLOR_GREEN 0x2UL
5324	#define PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 0x3UL
5325	#define PORT_LED_QCFG_RESP_LED1_COLOR_LAST PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER
5326	u8 unused_1;
5327	__le16 led1_blink_on;
5328	__le16 led1_blink_off;
5329	u8 led1_group_id;
5330	u8 led2_id;
5331	u8 led2_type;
5332	#define PORT_LED_QCFG_RESP_LED2_TYPE_SPEED 0x0UL
5333	#define PORT_LED_QCFG_RESP_LED2_TYPE_ACTIVITY 0x1UL
5334	#define PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 0xffUL
5335	#define PORT_LED_QCFG_RESP_LED2_TYPE_LAST PORT_LED_QCFG_RESP_LED2_TYPE_INVALID
5336	u8 led2_state;
5337	#define PORT_LED_QCFG_RESP_LED2_STATE_DEFAULT 0x0UL
5338	#define PORT_LED_QCFG_RESP_LED2_STATE_OFF 0x1UL
5339	#define PORT_LED_QCFG_RESP_LED2_STATE_ON 0x2UL
5340	#define PORT_LED_QCFG_RESP_LED2_STATE_BLINK 0x3UL
5341	#define PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 0x4UL
5342	#define PORT_LED_QCFG_RESP_LED2_STATE_LAST PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT
5343	u8 led2_color;
5344	#define PORT_LED_QCFG_RESP_LED2_COLOR_DEFAULT 0x0UL
5345	#define PORT_LED_QCFG_RESP_LED2_COLOR_AMBER 0x1UL
5346	#define PORT_LED_QCFG_RESP_LED2_COLOR_GREEN 0x2UL
5347	#define PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 0x3UL
5348	#define PORT_LED_QCFG_RESP_LED2_COLOR_LAST PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER
5349	u8 unused_2;
5350	__le16 led2_blink_on;
5351	__le16 led2_blink_off;
5352	u8 led2_group_id;
5353	u8 led3_id;
5354	u8 led3_type;
5355	#define PORT_LED_QCFG_RESP_LED3_TYPE_SPEED 0x0UL
5356	#define PORT_LED_QCFG_RESP_LED3_TYPE_ACTIVITY 0x1UL
5357	#define PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 0xffUL
5358	#define PORT_LED_QCFG_RESP_LED3_TYPE_LAST PORT_LED_QCFG_RESP_LED3_TYPE_INVALID
5359	u8 led3_state;
5360	#define PORT_LED_QCFG_RESP_LED3_STATE_DEFAULT 0x0UL
5361	#define PORT_LED_QCFG_RESP_LED3_STATE_OFF 0x1UL
5362	#define PORT_LED_QCFG_RESP_LED3_STATE_ON 0x2UL
5363	#define PORT_LED_QCFG_RESP_LED3_STATE_BLINK 0x3UL
5364	#define PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 0x4UL
5365	#define PORT_LED_QCFG_RESP_LED3_STATE_LAST PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT
5366	u8 led3_color;
5367	#define PORT_LED_QCFG_RESP_LED3_COLOR_DEFAULT 0x0UL
5368	#define PORT_LED_QCFG_RESP_LED3_COLOR_AMBER 0x1UL
5369	#define PORT_LED_QCFG_RESP_LED3_COLOR_GREEN 0x2UL
5370	#define PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 0x3UL
5371	#define PORT_LED_QCFG_RESP_LED3_COLOR_LAST PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER
5372	u8 unused_3;
5373	__le16 led3_blink_on;
5374	__le16 led3_blink_off;
5375	u8 led3_group_id;
5376	u8 unused_4[6];
5377	u8 valid;
5378	};
5379
5380	/* hwrm_port_led_qcaps_input (size:192b/24B) */
5381	struct hwrm_port_led_qcaps_input {
5382	__le16 req_type;
5383	__le16 cmpl_ring;
5384	__le16 seq_id;
5385	__le16 target_id;
5386	__le64 resp_addr;
5387	__le16 port_id;
5388	u8 unused_0[6];
5389	};
5390
5391	/* hwrm_port_led_qcaps_output (size:384b/48B) */
5392	struct hwrm_port_led_qcaps_output {
5393	__le16 error_code;
5394	__le16 req_type;
5395	__le16 seq_id;
5396	__le16 resp_len;
5397	u8 num_leds;
5398	u8 unused[3];
5399	u8 led0_id;
5400	u8 led0_type;
5401	#define PORT_LED_QCAPS_RESP_LED0_TYPE_SPEED 0x0UL
5402	#define PORT_LED_QCAPS_RESP_LED0_TYPE_ACTIVITY 0x1UL
5403	#define PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 0xffUL
5404	#define PORT_LED_QCAPS_RESP_LED0_TYPE_LAST PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID
5405	u8 led0_group_id;
5406	u8 unused_0;
5407	__le16 led0_state_caps;
5408	#define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ENABLED 0x1UL
5409	#define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_OFF_SUPPORTED 0x2UL
5410	#define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ON_SUPPORTED 0x4UL
5411	#define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_SUPPORTED 0x8UL
5412	#define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL
5413	__le16 led0_color_caps;
5414	#define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_RSVD 0x1UL
5415	#define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_AMBER_SUPPORTED 0x2UL
5416	#define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GREEN_SUPPORTED 0x4UL
5417	u8 led1_id;
5418	u8 led1_type;
5419	#define PORT_LED_QCAPS_RESP_LED1_TYPE_SPEED 0x0UL
5420	#define PORT_LED_QCAPS_RESP_LED1_TYPE_ACTIVITY 0x1UL
5421	#define PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 0xffUL
5422	#define PORT_LED_QCAPS_RESP_LED1_TYPE_LAST PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID
5423	u8 led1_group_id;
5424	u8 unused_1;
5425	__le16 led1_state_caps;
5426	#define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ENABLED 0x1UL
5427	#define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_OFF_SUPPORTED 0x2UL
5428	#define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ON_SUPPORTED 0x4UL
5429	#define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_SUPPORTED 0x8UL
5430	#define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL
5431	__le16 led1_color_caps;
5432	#define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_RSVD 0x1UL
5433	#define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_AMBER_SUPPORTED 0x2UL
5434	#define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GREEN_SUPPORTED 0x4UL
5435	u8 led2_id;
5436	u8 led2_type;
5437	#define PORT_LED_QCAPS_RESP_LED2_TYPE_SPEED 0x0UL
5438	#define PORT_LED_QCAPS_RESP_LED2_TYPE_ACTIVITY 0x1UL
5439	#define PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 0xffUL
5440	#define PORT_LED_QCAPS_RESP_LED2_TYPE_LAST PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID
5441	u8 led2_group_id;
5442	u8 unused_2;
5443	__le16 led2_state_caps;
5444	#define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ENABLED 0x1UL
5445	#define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_OFF_SUPPORTED 0x2UL
5446	#define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ON_SUPPORTED 0x4UL
5447	#define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_SUPPORTED 0x8UL
5448	#define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL
5449	__le16 led2_color_caps;
5450	#define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_RSVD 0x1UL
5451	#define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_AMBER_SUPPORTED 0x2UL
5452	#define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GREEN_SUPPORTED 0x4UL
5453	u8 led3_id;
5454	u8 led3_type;
5455	#define PORT_LED_QCAPS_RESP_LED3_TYPE_SPEED 0x0UL
5456	#define PORT_LED_QCAPS_RESP_LED3_TYPE_ACTIVITY 0x1UL
5457	#define PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 0xffUL
5458	#define PORT_LED_QCAPS_RESP_LED3_TYPE_LAST PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID
5459	u8 led3_group_id;
5460	u8 unused_3;
5461	__le16 led3_state_caps;
5462	#define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ENABLED 0x1UL
5463	#define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_OFF_SUPPORTED 0x2UL
5464	#define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ON_SUPPORTED 0x4UL
5465	#define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_SUPPORTED 0x8UL
5466	#define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL
5467	__le16 led3_color_caps;
5468	#define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_RSVD 0x1UL
5469	#define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_AMBER_SUPPORTED 0x2UL
5470	#define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GREEN_SUPPORTED 0x4UL
5471	u8 unused_4[3];
5472	u8 valid;
5473	};
5474
5475	/* hwrm_queue_qportcfg_input (size:192b/24B) */
5476	struct hwrm_queue_qportcfg_input {
5477	__le16 req_type;
5478	__le16 cmpl_ring;
5479	__le16 seq_id;
5480	__le16 target_id;
5481	__le64 resp_addr;
5482	__le32 flags;
5483	#define QUEUE_QPORTCFG_REQ_FLAGS_PATH 0x1UL
5484	#define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX 0x0UL
5485	#define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 0x1UL
5486	#define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX
5487	__le16 port_id;
5488	u8 drv_qmap_cap;
5489	#define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_DISABLED 0x0UL
5490	#define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 0x1UL
5491	#define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_LAST QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED
5492	u8 unused_0;
5493	};
5494
5495	/* hwrm_queue_qportcfg_output (size:1344b/168B) */
5496	struct hwrm_queue_qportcfg_output {
5497	__le16 error_code;
5498	__le16 req_type;
5499	__le16 seq_id;
5500	__le16 resp_len;
5501	u8 max_configurable_queues;
5502	u8 max_configurable_lossless_queues;
5503	u8 queue_cfg_allowed;
5504	u8 queue_cfg_info;
5505	#define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL
5506	#define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_USE_PROFILE_TYPE 0x2UL
5507	u8 queue_pfcenable_cfg_allowed;
5508	u8 queue_pri2cos_cfg_allowed;
5509	u8 queue_cos2bw_cfg_allowed;
5510	u8 queue_id0;
5511	u8 queue_id0_service_profile;
5512	#define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY 0x0UL
5513	#define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS 0x1UL
5514	#define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
5515	#define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
5516	#define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
5517	#define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 0xffUL
5518	#define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN
5519	u8 queue_id1;
5520	u8 queue_id1_service_profile;
5521	#define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY 0x0UL
5522	#define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS 0x1UL
5523	#define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
5524	#define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
5525	#define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
5526	#define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 0xffUL
5527	#define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN
5528	u8 queue_id2;
5529	u8 queue_id2_service_profile;
5530	#define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY 0x0UL
5531	#define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS 0x1UL
5532	#define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
5533	#define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
5534	#define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
5535	#define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 0xffUL
5536	#define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN
5537	u8 queue_id3;
5538	u8 queue_id3_service_profile;
5539	#define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY 0x0UL
5540	#define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS 0x1UL
5541	#define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
5542	#define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
5543	#define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
5544	#define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 0xffUL
5545	#define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN
5546	u8 queue_id4;
5547	u8 queue_id4_service_profile;
5548	#define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY 0x0UL
5549	#define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS 0x1UL
5550	#define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
5551	#define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
5552	#define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
5553	#define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 0xffUL
5554	#define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN
5555	u8 queue_id5;
5556	u8 queue_id5_service_profile;
5557	#define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY 0x0UL
5558	#define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS 0x1UL
5559	#define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
5560	#define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
5561	#define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
5562	#define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 0xffUL
5563	#define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN
5564	u8 queue_id6;
5565	u8 queue_id6_service_profile;
5566	#define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY 0x0UL
5567	#define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS 0x1UL
5568	#define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
5569	#define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
5570	#define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
5571	#define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 0xffUL
5572	#define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN
5573	u8 queue_id7;
5574	u8 queue_id7_service_profile;
5575	#define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY 0x0UL
5576	#define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS 0x1UL
5577	#define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
5578	#define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
5579	#define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
5580	#define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 0xffUL
5581	#define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN
5582	u8 queue_id0_service_profile_type;
5583	#define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_ROCE 0x1UL
5584	#define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_NIC 0x2UL
5585	#define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_CNP 0x4UL
5586	char qid0_name[16];
5587	char qid1_name[16];
5588	char qid2_name[16];
5589	char qid3_name[16];
5590	char qid4_name[16];
5591	char qid5_name[16];
5592	char qid6_name[16];
5593	char qid7_name[16];
5594	u8 queue_id1_service_profile_type;
5595	#define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_ROCE 0x1UL
5596	#define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_NIC 0x2UL
5597	#define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_CNP 0x4UL
5598	u8 queue_id2_service_profile_type;
5599	#define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_ROCE 0x1UL
5600	#define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_NIC 0x2UL
5601	#define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_CNP 0x4UL
5602	u8 queue_id3_service_profile_type;
5603	#define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_ROCE 0x1UL
5604	#define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_NIC 0x2UL
5605	#define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_CNP 0x4UL
5606	u8 queue_id4_service_profile_type;
5607	#define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_ROCE 0x1UL
5608	#define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_NIC 0x2UL
5609	#define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_CNP 0x4UL
5610	u8 queue_id5_service_profile_type;
5611	#define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_ROCE 0x1UL
5612	#define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_NIC 0x2UL
5613	#define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_CNP 0x4UL
5614	u8 queue_id6_service_profile_type;
5615	#define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_ROCE 0x1UL
5616	#define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_NIC 0x2UL
5617	#define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_CNP 0x4UL
5618	u8 queue_id7_service_profile_type;
5619	#define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_ROCE 0x1UL
5620	#define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_NIC 0x2UL
5621	#define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_CNP 0x4UL
5622	u8 valid;
5623	};
5624
5625	/* hwrm_queue_qcfg_input (size:192b/24B) */
5626	struct hwrm_queue_qcfg_input {
5627	__le16 req_type;
5628	__le16 cmpl_ring;
5629	__le16 seq_id;
5630	__le16 target_id;
5631	__le64 resp_addr;
5632	__le32 flags;
5633	#define QUEUE_QCFG_REQ_FLAGS_PATH 0x1UL
5634	#define QUEUE_QCFG_REQ_FLAGS_PATH_TX 0x0UL
5635	#define QUEUE_QCFG_REQ_FLAGS_PATH_RX 0x1UL
5636	#define QUEUE_QCFG_REQ_FLAGS_PATH_LAST QUEUE_QCFG_REQ_FLAGS_PATH_RX
5637	__le32 queue_id;
5638	};
5639
5640	/* hwrm_queue_qcfg_output (size:128b/16B) */
5641	struct hwrm_queue_qcfg_output {
5642	__le16 error_code;
5643	__le16 req_type;
5644	__le16 seq_id;
5645	__le16 resp_len;
5646	__le32 queue_len;
5647	u8 service_profile;
5648	#define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSY 0x0UL
5649	#define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSLESS 0x1UL
5650	#define QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN 0xffUL
5651	#define QUEUE_QCFG_RESP_SERVICE_PROFILE_LAST QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN
5652	u8 queue_cfg_info;
5653	#define QUEUE_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL
5654	u8 unused_0;
5655	u8 valid;
5656	};
5657
5658	/* hwrm_queue_cfg_input (size:320b/40B) */
5659	struct hwrm_queue_cfg_input {
5660	__le16 req_type;
5661	__le16 cmpl_ring;
5662	__le16 seq_id;
5663	__le16 target_id;
5664	__le64 resp_addr;
5665	__le32 flags;
5666	#define QUEUE_CFG_REQ_FLAGS_PATH_MASK 0x3UL
5667	#define QUEUE_CFG_REQ_FLAGS_PATH_SFT 0
5668	#define QUEUE_CFG_REQ_FLAGS_PATH_TX 0x0UL
5669	#define QUEUE_CFG_REQ_FLAGS_PATH_RX 0x1UL
5670	#define QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL
5671	#define QUEUE_CFG_REQ_FLAGS_PATH_LAST QUEUE_CFG_REQ_FLAGS_PATH_BIDIR
5672	__le32 enables;
5673	#define QUEUE_CFG_REQ_ENABLES_DFLT_LEN 0x1UL
5674	#define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE 0x2UL
5675	__le32 queue_id;
5676	__le32 dflt_len;
5677	u8 service_profile;
5678	#define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY 0x0UL
5679	#define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS 0x1UL
5680	#define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 0xffUL
5681	#define QUEUE_CFG_REQ_SERVICE_PROFILE_LAST QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN
5682	u8 unused_0[7];
5683	};
5684
5685	/* hwrm_queue_cfg_output (size:128b/16B) */
5686	struct hwrm_queue_cfg_output {
5687	__le16 error_code;
5688	__le16 req_type;
5689	__le16 seq_id;
5690	__le16 resp_len;
5691	u8 unused_0[7];
5692	u8 valid;
5693	};
5694
5695	/* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */
5696	struct hwrm_queue_pfcenable_qcfg_input {
5697	__le16 req_type;
5698	__le16 cmpl_ring;
5699	__le16 seq_id;
5700	__le16 target_id;
5701	__le64 resp_addr;
5702	__le16 port_id;
5703	u8 unused_0[6];
5704	};
5705
5706	/* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */
5707	struct hwrm_queue_pfcenable_qcfg_output {
5708	__le16 error_code;
5709	__le16 req_type;
5710	__le16 seq_id;
5711	__le16 resp_len;
5712	__le32 flags;
5713	#define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_ENABLED 0x1UL
5714	#define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_ENABLED 0x2UL
5715	#define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_ENABLED 0x4UL
5716	#define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_ENABLED 0x8UL
5717	#define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_ENABLED 0x10UL
5718	#define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_ENABLED 0x20UL
5719	#define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_ENABLED 0x40UL
5720	#define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_ENABLED 0x80UL
5721	#define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_WATCHDOG_ENABLED 0x100UL
5722	#define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_WATCHDOG_ENABLED 0x200UL
5723	#define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_WATCHDOG_ENABLED 0x400UL
5724	#define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_WATCHDOG_ENABLED 0x800UL
5725	#define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_WATCHDOG_ENABLED 0x1000UL
5726	#define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_WATCHDOG_ENABLED 0x2000UL
5727	#define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_WATCHDOG_ENABLED 0x4000UL
5728	#define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_WATCHDOG_ENABLED 0x8000UL
5729	u8 unused_0[3];
5730	u8 valid;
5731	};
5732
5733	/* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */
5734	struct hwrm_queue_pfcenable_cfg_input {
5735	__le16 req_type;
5736	__le16 cmpl_ring;
5737	__le16 seq_id;
5738	__le16 target_id;
5739	__le64 resp_addr;
5740	__le32 flags;
5741	#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED 0x1UL
5742	#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED 0x2UL
5743	#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED 0x4UL
5744	#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED 0x8UL
5745	#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED 0x10UL
5746	#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED 0x20UL
5747	#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED 0x40UL
5748	#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED 0x80UL
5749	#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_WATCHDOG_ENABLED 0x100UL
5750	#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_WATCHDOG_ENABLED 0x200UL
5751	#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_WATCHDOG_ENABLED 0x400UL
5752	#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_WATCHDOG_ENABLED 0x800UL
5753	#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_WATCHDOG_ENABLED 0x1000UL
5754	#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_WATCHDOG_ENABLED 0x2000UL
5755	#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_WATCHDOG_ENABLED 0x4000UL
5756	#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_WATCHDOG_ENABLED 0x8000UL
5757	__le16 port_id;
5758	u8 unused_0[2];
5759	};
5760
5761	/* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */
5762	struct hwrm_queue_pfcenable_cfg_output {
5763	__le16 error_code;
5764	__le16 req_type;
5765	__le16 seq_id;
5766	__le16 resp_len;
5767	u8 unused_0[7];
5768	u8 valid;
5769	};
5770
5771	/* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */
5772	struct hwrm_queue_pri2cos_qcfg_input {
5773	__le16 req_type;
5774	__le16 cmpl_ring;
5775	__le16 seq_id;
5776	__le16 target_id;
5777	__le64 resp_addr;
5778	__le32 flags;
5779	#define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH 0x1UL
5780	#define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_TX 0x0UL
5781	#define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 0x1UL
5782	#define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX
5783	#define QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN 0x2UL
5784	u8 port_id;
5785	u8 unused_0[3];
5786	};
5787
5788	/* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */
5789	struct hwrm_queue_pri2cos_qcfg_output {
5790	__le16 error_code;
5791	__le16 req_type;
5792	__le16 seq_id;
5793	__le16 resp_len;
5794	u8 pri0_cos_queue_id;
5795	u8 pri1_cos_queue_id;
5796	u8 pri2_cos_queue_id;
5797	u8 pri3_cos_queue_id;
5798	u8 pri4_cos_queue_id;
5799	u8 pri5_cos_queue_id;
5800	u8 pri6_cos_queue_id;
5801	u8 pri7_cos_queue_id;
5802	u8 queue_cfg_info;
5803	#define QUEUE_PRI2COS_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL
5804	u8 unused_0[6];
5805	u8 valid;
5806	};
5807
5808	/* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */
5809	struct hwrm_queue_pri2cos_cfg_input {
5810	__le16 req_type;
5811	__le16 cmpl_ring;
5812	__le16 seq_id;
5813	__le16 target_id;
5814	__le64 resp_addr;
5815	__le32 flags;
5816	#define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_MASK 0x3UL
5817	#define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_SFT 0
5818	#define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX 0x0UL
5819	#define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX 0x1UL
5820	#define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL
5821	#define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR
5822	#define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN 0x4UL
5823	__le32 enables;
5824	#define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI0_COS_QUEUE_ID 0x1UL
5825	#define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI1_COS_QUEUE_ID 0x2UL
5826	#define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI2_COS_QUEUE_ID 0x4UL
5827	#define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI3_COS_QUEUE_ID 0x8UL
5828	#define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI4_COS_QUEUE_ID 0x10UL
5829	#define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI5_COS_QUEUE_ID 0x20UL
5830	#define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI6_COS_QUEUE_ID 0x40UL
5831	#define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI7_COS_QUEUE_ID 0x80UL
5832	u8 port_id;
5833	u8 pri0_cos_queue_id;
5834	u8 pri1_cos_queue_id;
5835	u8 pri2_cos_queue_id;
5836	u8 pri3_cos_queue_id;
5837	u8 pri4_cos_queue_id;
5838	u8 pri5_cos_queue_id;
5839	u8 pri6_cos_queue_id;
5840	u8 pri7_cos_queue_id;
5841	u8 unused_0[7];
5842	};
5843
5844	/* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */
5845	struct hwrm_queue_pri2cos_cfg_output {
5846	__le16 error_code;
5847	__le16 req_type;
5848	__le16 seq_id;
5849	__le16 resp_len;
5850	u8 unused_0[7];
5851	u8 valid;
5852	};
5853
5854	/* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */
5855	struct hwrm_queue_cos2bw_qcfg_input {
5856	__le16 req_type;
5857	__le16 cmpl_ring;
5858	__le16 seq_id;
5859	__le16 target_id;
5860	__le64 resp_addr;
5861	__le16 port_id;
5862	u8 unused_0[6];
5863	};
5864
5865	/* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */
5866	struct hwrm_queue_cos2bw_qcfg_output {
5867	__le16 error_code;
5868	__le16 req_type;
5869	__le16 seq_id;
5870	__le16 resp_len;
5871	u8 queue_id0;
5872	u8 unused_0;
5873	__le16 unused_1;
5874	__le32 queue_id0_min_bw;
5875	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL
5876	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0
5877	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL
5878	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28)
5879	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28)
5880	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES
5881	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
5882	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29
5883	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
5884	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
5885	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
5886	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
5887	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
5888	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
5889	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
5890	__le32 queue_id0_max_bw;
5891	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL
5892	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0
5893	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL
5894	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28)
5895	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28)
5896	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES
5897	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
5898	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29
5899	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
5900	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
5901	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
5902	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
5903	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
5904	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
5905	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
5906	u8 queue_id0_tsa_assign;
5907	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL
5908	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL
5909	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL
5910	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL
5911	u8 queue_id0_pri_lvl;
5912	u8 queue_id0_bw_weight;
5913	struct {
5914	u8 queue_id;
5915	__le32 queue_id_min_bw;
5916	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_MASK 0xfffffffUL
5917	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_SFT 0
5918	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_SCALE 0x10000000UL
5919	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_SCALE_BITS (0x0UL << 28)
5920	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_SCALE_BYTES (0x1UL << 28)
5921	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_SCALE_BYTES
5922	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
5923	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_SFT 29
5924	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
5925	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
5926	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
5927	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
5928	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
5929	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
5930	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_INVALID
5931	__le32 queue_id_max_bw;
5932	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_MASK 0xfffffffUL
5933	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_SFT 0
5934	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_SCALE 0x10000000UL
5935	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_SCALE_BITS (0x0UL << 28)
5936	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_SCALE_BYTES (0x1UL << 28)
5937	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_SCALE_BYTES
5938	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
5939	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_SFT 29
5940	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
5941	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
5942	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
5943	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
5944	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
5945	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
5946	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_INVALID
5947	u8 queue_id_tsa_assign;
5948	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_TSA_ASSIGN_SP 0x0UL
5949	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_TSA_ASSIGN_ETS 0x1UL
5950	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_TSA_ASSIGN_RESERVED_FIRST 0x2UL
5951	#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_TSA_ASSIGN_RESERVED_LAST 0xffUL
5952	u8 queue_id_pri_lvl;
5953	u8 queue_id_bw_weight;
5954	} __packed cfg[7];
5955	u8 unused_2[4];
5956	u8 valid;
5957	};
5958
5959	/* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */
5960	struct hwrm_queue_cos2bw_cfg_input {
5961	__le16 req_type;
5962	__le16 cmpl_ring;
5963	__le16 seq_id;
5964	__le16 target_id;
5965	__le64 resp_addr;
5966	__le32 flags;
5967	__le32 enables;
5968	#define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID 0x1UL
5969	#define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID 0x2UL
5970	#define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID 0x4UL
5971	#define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID 0x8UL
5972	#define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID 0x10UL
5973	#define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID 0x20UL
5974	#define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID 0x40UL
5975	#define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID 0x80UL
5976	__le16 port_id;
5977	u8 queue_id0;
5978	u8 unused_0;
5979	__le32 queue_id0_min_bw;
5980	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL
5981	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0
5982	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL
5983	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28)
5984	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28)
5985	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES
5986	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
5987	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29
5988	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
5989	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
5990	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
5991	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
5992	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
5993	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
5994	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
5995	__le32 queue_id0_max_bw;
5996	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL
5997	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0
5998	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL
5999	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28)
6000	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28)
6001	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES
6002	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
6003	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29
6004	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
6005	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
6006	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
6007	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
6008	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
6009	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
6010	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
6011	u8 queue_id0_tsa_assign;
6012	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL
6013	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL
6014	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL
6015	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL
6016	u8 queue_id0_pri_lvl;
6017	u8 queue_id0_bw_weight;
6018	struct {
6019	u8 queue_id;
6020	__le32 queue_id_min_bw;
6021	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_MASK 0xfffffffUL
6022	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_SFT 0
6023	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_SCALE 0x10000000UL
6024	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_SCALE_BITS (0x0UL << 28)
6025	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_SCALE_BYTES (0x1UL << 28)
6026	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_SCALE_BYTES
6027	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
6028	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_SFT 29
6029	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
6030	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
6031	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
6032	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
6033	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
6034	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
6035	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_INVALID
6036	__le32 queue_id_max_bw;
6037	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_MASK 0xfffffffUL
6038	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_SFT 0
6039	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_SCALE 0x10000000UL
6040	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_SCALE_BITS (0x0UL << 28)
6041	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_SCALE_BYTES (0x1UL << 28)
6042	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_SCALE_BYTES
6043	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
6044	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_SFT 29
6045	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
6046	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
6047	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
6048	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
6049	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
6050	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
6051	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_INVALID
6052	u8 queue_id_tsa_assign;
6053	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_TSA_ASSIGN_SP 0x0UL
6054	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_TSA_ASSIGN_ETS 0x1UL
6055	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_TSA_ASSIGN_RESERVED_FIRST 0x2UL
6056	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_TSA_ASSIGN_RESERVED_LAST 0xffUL
6057	u8 queue_id_pri_lvl;
6058	u8 queue_id_bw_weight;
6059	} __packed cfg[7];
6060	u8 unused_1[5];
6061	};
6062
6063	/* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */
6064	struct hwrm_queue_cos2bw_cfg_output {
6065	__le16 error_code;
6066	__le16 req_type;
6067	__le16 seq_id;
6068	__le16 resp_len;
6069	u8 unused_0[7];
6070	u8 valid;
6071	};
6072
6073	/* hwrm_queue_dscp_qcaps_input (size:192b/24B) */
6074	struct hwrm_queue_dscp_qcaps_input {
6075	__le16 req_type;
6076	__le16 cmpl_ring;
6077	__le16 seq_id;
6078	__le16 target_id;
6079	__le64 resp_addr;
6080	u8 port_id;
6081	u8 unused_0[7];
6082	};
6083
6084	/* hwrm_queue_dscp_qcaps_output (size:128b/16B) */
6085	struct hwrm_queue_dscp_qcaps_output {
6086	__le16 error_code;
6087	__le16 req_type;
6088	__le16 seq_id;
6089	__le16 resp_len;
6090	u8 num_dscp_bits;
6091	u8 unused_0;
6092	__le16 max_entries;
6093	u8 unused_1[3];
6094	u8 valid;
6095	};
6096
6097	/* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */
6098	struct hwrm_queue_dscp2pri_qcfg_input {
6099	__le16 req_type;
6100	__le16 cmpl_ring;
6101	__le16 seq_id;
6102	__le16 target_id;
6103	__le64 resp_addr;
6104	__le64 dest_data_addr;
6105	u8 port_id;
6106	u8 unused_0;
6107	__le16 dest_data_buffer_size;
6108	u8 unused_1[4];
6109	};
6110
6111	/* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */
6112	struct hwrm_queue_dscp2pri_qcfg_output {
6113	__le16 error_code;
6114	__le16 req_type;
6115	__le16 seq_id;
6116	__le16 resp_len;
6117	__le16 entry_cnt;
6118	u8 default_pri;
6119	u8 unused_0[4];
6120	u8 valid;
6121	};
6122
6123	/* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */
6124	struct hwrm_queue_dscp2pri_cfg_input {
6125	__le16 req_type;
6126	__le16 cmpl_ring;
6127	__le16 seq_id;
6128	__le16 target_id;
6129	__le64 resp_addr;
6130	__le64 src_data_addr;
6131	__le32 flags;
6132	#define QUEUE_DSCP2PRI_CFG_REQ_FLAGS_USE_HW_DEFAULT_PRI 0x1UL
6133	__le32 enables;
6134	#define QUEUE_DSCP2PRI_CFG_REQ_ENABLES_DEFAULT_PRI 0x1UL
6135	u8 port_id;
6136	u8 default_pri;
6137	__le16 entry_cnt;
6138	u8 unused_0[4];
6139	};
6140
6141	/* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */
6142	struct hwrm_queue_dscp2pri_cfg_output {
6143	__le16 error_code;
6144	__le16 req_type;
6145	__le16 seq_id;
6146	__le16 resp_len;
6147	u8 unused_0[7];
6148	u8 valid;
6149	};
6150
6151	/* hwrm_vnic_alloc_input (size:192b/24B) */
6152	struct hwrm_vnic_alloc_input {
6153	__le16 req_type;
6154	__le16 cmpl_ring;
6155	__le16 seq_id;
6156	__le16 target_id;
6157	__le64 resp_addr;
6158	__le32 flags;
6159	#define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL
6160	#define VNIC_ALLOC_REQ_FLAGS_VIRTIO_NET_FID_VALID 0x2UL
6161	__le16 virtio_net_fid;
6162	u8 unused_0[2];
6163	};
6164
6165	/* hwrm_vnic_alloc_output (size:128b/16B) */
6166	struct hwrm_vnic_alloc_output {
6167	__le16 error_code;
6168	__le16 req_type;
6169	__le16 seq_id;
6170	__le16 resp_len;
6171	__le32 vnic_id;
6172	u8 unused_0[3];
6173	u8 valid;
6174	};
6175
6176	/* hwrm_vnic_free_input (size:192b/24B) */
6177	struct hwrm_vnic_free_input {
6178	__le16 req_type;
6179	__le16 cmpl_ring;
6180	__le16 seq_id;
6181	__le16 target_id;
6182	__le64 resp_addr;
6183	__le32 vnic_id;
6184	u8 unused_0[4];
6185	};
6186
6187	/* hwrm_vnic_free_output (size:128b/16B) */
6188	struct hwrm_vnic_free_output {
6189	__le16 error_code;
6190	__le16 req_type;
6191	__le16 seq_id;
6192	__le16 resp_len;
6193	u8 unused_0[7];
6194	u8 valid;
6195	};
6196
6197	/* hwrm_vnic_cfg_input (size:384b/48B) */
6198	struct hwrm_vnic_cfg_input {
6199	__le16 req_type;
6200	__le16 cmpl_ring;
6201	__le16 seq_id;
6202	__le16 target_id;
6203	__le64 resp_addr;
6204	__le32 flags;
6205	#define VNIC_CFG_REQ_FLAGS_DEFAULT 0x1UL
6206	#define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE 0x2UL
6207	#define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE 0x4UL
6208	#define VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE 0x8UL
6209	#define VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE 0x10UL
6210	#define VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE 0x20UL
6211	#define VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE 0x40UL
6212	#define VNIC_CFG_REQ_FLAGS_PORTCOS_MAPPING_MODE 0x80UL
6213	__le32 enables;
6214	#define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL
6215	#define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL
6216	#define VNIC_CFG_REQ_ENABLES_COS_RULE 0x4UL
6217	#define VNIC_CFG_REQ_ENABLES_LB_RULE 0x8UL
6218	#define VNIC_CFG_REQ_ENABLES_MRU 0x10UL
6219	#define VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID 0x20UL
6220	#define VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID 0x40UL
6221	#define VNIC_CFG_REQ_ENABLES_QUEUE_ID 0x80UL
6222	#define VNIC_CFG_REQ_ENABLES_RX_CSUM_V2_MODE 0x100UL
6223	#define VNIC_CFG_REQ_ENABLES_L2_CQE_MODE 0x200UL
6224	__le16 vnic_id;
6225	__le16 dflt_ring_grp;
6226	__le16 rss_rule;
6227	__le16 cos_rule;
6228	__le16 lb_rule;
6229	__le16 mru;
6230	__le16 default_rx_ring_id;
6231	__le16 default_cmpl_ring_id;
6232	__le16 queue_id;
6233	u8 rx_csum_v2_mode;
6234	#define VNIC_CFG_REQ_RX_CSUM_V2_MODE_DEFAULT 0x0UL
6235	#define VNIC_CFG_REQ_RX_CSUM_V2_MODE_ALL_OK 0x1UL
6236	#define VNIC_CFG_REQ_RX_CSUM_V2_MODE_MAX 0x2UL
6237	#define VNIC_CFG_REQ_RX_CSUM_V2_MODE_LAST VNIC_CFG_REQ_RX_CSUM_V2_MODE_MAX
6238	u8 l2_cqe_mode;
6239	#define VNIC_CFG_REQ_L2_CQE_MODE_DEFAULT 0x0UL
6240	#define VNIC_CFG_REQ_L2_CQE_MODE_COMPRESSED 0x1UL
6241	#define VNIC_CFG_REQ_L2_CQE_MODE_MIXED 0x2UL
6242	#define VNIC_CFG_REQ_L2_CQE_MODE_LAST VNIC_CFG_REQ_L2_CQE_MODE_MIXED
6243	u8 unused0[4];
6244	};
6245
6246	/* hwrm_vnic_cfg_output (size:128b/16B) */
6247	struct hwrm_vnic_cfg_output {
6248	__le16 error_code;
6249	__le16 req_type;
6250	__le16 seq_id;
6251	__le16 resp_len;
6252	u8 unused_0[7];
6253	u8 valid;
6254	};
6255
6256	/* hwrm_vnic_qcaps_input (size:192b/24B) */
6257	struct hwrm_vnic_qcaps_input {
6258	__le16 req_type;
6259	__le16 cmpl_ring;
6260	__le16 seq_id;
6261	__le16 target_id;
6262	__le64 resp_addr;
6263	__le32 enables;
6264	u8 unused_0[4];
6265	};
6266
6267	/* hwrm_vnic_qcaps_output (size:192b/24B) */
6268	struct hwrm_vnic_qcaps_output {
6269	__le16 error_code;
6270	__le16 req_type;
6271	__le16 seq_id;
6272	__le16 resp_len;
6273	__le16 mru;
6274	u8 unused_0[2];
6275	__le32 flags;
6276	#define VNIC_QCAPS_RESP_FLAGS_UNUSED 0x1UL
6277	#define VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP 0x2UL
6278	#define VNIC_QCAPS_RESP_FLAGS_BD_STALL_CAP 0x4UL
6279	#define VNIC_QCAPS_RESP_FLAGS_ROCE_DUAL_VNIC_CAP 0x8UL
6280	#define VNIC_QCAPS_RESP_FLAGS_ROCE_ONLY_VNIC_CAP 0x10UL
6281	#define VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP 0x20UL
6282	#define VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP 0x40UL
6283	#define VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_CAP 0x80UL
6284	#define VNIC_QCAPS_RESP_FLAGS_COS_ASSIGNMENT_CAP 0x100UL
6285	#define VNIC_QCAPS_RESP_FLAGS_RX_CMPL_V2_CAP 0x200UL
6286	#define VNIC_QCAPS_RESP_FLAGS_VNIC_STATE_CAP 0x400UL
6287	#define VNIC_QCAPS_RESP_FLAGS_VIRTIO_NET_VNIC_ALLOC_CAP 0x800UL
6288	#define VNIC_QCAPS_RESP_FLAGS_METADATA_FORMAT_CAP 0x1000UL
6289	#define VNIC_QCAPS_RESP_FLAGS_RSS_STRICT_HASH_TYPE_CAP 0x2000UL
6290	#define VNIC_QCAPS_RESP_FLAGS_RSS_HASH_TYPE_DELTA_CAP 0x4000UL
6291	#define VNIC_QCAPS_RESP_FLAGS_RING_SELECT_MODE_TOEPLITZ_CAP 0x8000UL
6292	#define VNIC_QCAPS_RESP_FLAGS_RING_SELECT_MODE_XOR_CAP 0x10000UL
6293	#define VNIC_QCAPS_RESP_FLAGS_RING_SELECT_MODE_TOEPLITZ_CHKSM_CAP 0x20000UL
6294	#define VNIC_QCAPS_RESP_FLAGS_RSS_IPV6_FLOW_LABEL_CAP 0x40000UL
6295	#define VNIC_QCAPS_RESP_FLAGS_RX_CMPL_V3_CAP 0x80000UL
6296	#define VNIC_QCAPS_RESP_FLAGS_L2_CQE_MODE_CAP 0x100000UL
6297	#define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_AH_SPI_IPV4_CAP 0x200000UL
6298	#define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_ESP_SPI_IPV4_CAP 0x400000UL
6299	#define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_AH_SPI_IPV6_CAP 0x800000UL
6300	#define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_ESP_SPI_IPV6_CAP 0x1000000UL
6301	#define VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_TRUSTED_VF_CAP 0x2000000UL
6302	#define VNIC_QCAPS_RESP_FLAGS_PORTCOS_MAPPING_MODE 0x4000000UL
6303	#define VNIC_QCAPS_RESP_FLAGS_RSS_PROF_TCAM_MODE_ENABLED 0x8000000UL
6304	#define VNIC_QCAPS_RESP_FLAGS_VNIC_RSS_HASH_MODE_CAP 0x10000000UL
6305	#define VNIC_QCAPS_RESP_FLAGS_HW_TUNNEL_TPA_CAP 0x20000000UL
6306	__le16 max_aggs_supported;
6307	u8 unused_1[5];
6308	u8 valid;
6309	};
6310
6311	/* hwrm_vnic_tpa_cfg_input (size:384b/48B) */
6312	struct hwrm_vnic_tpa_cfg_input {
6313	__le16 req_type;
6314	__le16 cmpl_ring;
6315	__le16 seq_id;
6316	__le16 target_id;
6317	__le64 resp_addr;
6318	__le32 flags;
6319	#define VNIC_TPA_CFG_REQ_FLAGS_TPA 0x1UL
6320	#define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA 0x2UL
6321	#define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE 0x4UL
6322	#define VNIC_TPA_CFG_REQ_FLAGS_GRO 0x8UL
6323	#define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN 0x10UL
6324	#define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL
6325	#define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK 0x40UL
6326	#define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK 0x80UL
6327	#define VNIC_TPA_CFG_REQ_FLAGS_AGG_PACK_AS_GRO 0x100UL
6328	__le32 enables;
6329	#define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS 0x1UL
6330	#define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS 0x2UL
6331	#define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER 0x4UL
6332	#define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN 0x8UL
6333	#define VNIC_TPA_CFG_REQ_ENABLES_TNL_TPA_EN 0x10UL
6334	__le16 vnic_id;
6335	__le16 max_agg_segs;
6336	#define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1 0x0UL
6337	#define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2 0x1UL
6338	#define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4 0x2UL
6339	#define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8 0x3UL
6340	#define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 0x1fUL
6341	#define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_LAST VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX
6342	__le16 max_aggs;
6343	#define VNIC_TPA_CFG_REQ_MAX_AGGS_1 0x0UL
6344	#define VNIC_TPA_CFG_REQ_MAX_AGGS_2 0x1UL
6345	#define VNIC_TPA_CFG_REQ_MAX_AGGS_4 0x2UL
6346	#define VNIC_TPA_CFG_REQ_MAX_AGGS_8 0x3UL
6347	#define VNIC_TPA_CFG_REQ_MAX_AGGS_16 0x4UL
6348	#define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 0x7UL
6349	#define VNIC_TPA_CFG_REQ_MAX_AGGS_LAST VNIC_TPA_CFG_REQ_MAX_AGGS_MAX
6350	u8 unused_0[2];
6351	__le32 max_agg_timer;
6352	__le32 min_agg_len;
6353	__le32 tnl_tpa_en_bitmap;
6354	#define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_VXLAN 0x1UL
6355	#define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_GENEVE 0x2UL
6356	#define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_NVGRE 0x4UL
6357	#define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_GRE 0x8UL
6358	#define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_IPV4 0x10UL
6359	#define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_IPV6 0x20UL
6360	#define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_VXLAN_GPE 0x40UL
6361	#define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_VXLAN_CUST1 0x80UL
6362	#define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_GRE_CUST1 0x100UL
6363	#define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR1 0x200UL
6364	#define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR2 0x400UL
6365	#define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR3 0x800UL
6366	#define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR4 0x1000UL
6367	#define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR5 0x2000UL
6368	#define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR6 0x4000UL
6369	#define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR7 0x8000UL
6370	#define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR8 0x10000UL
6371	u8 unused_1[4];
6372	};
6373
6374	/* hwrm_vnic_tpa_cfg_output (size:128b/16B) */
6375	struct hwrm_vnic_tpa_cfg_output {
6376	__le16 error_code;
6377	__le16 req_type;
6378	__le16 seq_id;
6379	__le16 resp_len;
6380	u8 unused_0[7];
6381	u8 valid;
6382	};
6383
6384	/* hwrm_vnic_tpa_qcfg_input (size:192b/24B) */
6385	struct hwrm_vnic_tpa_qcfg_input {
6386	__le16 req_type;
6387	__le16 cmpl_ring;
6388	__le16 seq_id;
6389	__le16 target_id;
6390	__le64 resp_addr;
6391	__le16 vnic_id;
6392	u8 unused_0[6];
6393	};
6394
6395	/* hwrm_vnic_tpa_qcfg_output (size:256b/32B) */
6396	struct hwrm_vnic_tpa_qcfg_output {
6397	__le16 error_code;
6398	__le16 req_type;
6399	__le16 seq_id;
6400	__le16 resp_len;
6401	__le32 flags;
6402	#define VNIC_TPA_QCFG_RESP_FLAGS_TPA 0x1UL
6403	#define VNIC_TPA_QCFG_RESP_FLAGS_ENCAP_TPA 0x2UL
6404	#define VNIC_TPA_QCFG_RESP_FLAGS_RSC_WND_UPDATE 0x4UL
6405	#define VNIC_TPA_QCFG_RESP_FLAGS_GRO 0x8UL
6406	#define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_ECN 0x10UL
6407	#define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL
6408	#define VNIC_TPA_QCFG_RESP_FLAGS_GRO_IPID_CHECK 0x40UL
6409	#define VNIC_TPA_QCFG_RESP_FLAGS_GRO_TTL_CHECK 0x80UL
6410	__le16 max_agg_segs;
6411	#define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_1 0x0UL
6412	#define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_2 0x1UL
6413	#define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_4 0x2UL
6414	#define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_8 0x3UL
6415	#define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 0x1fUL
6416	#define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX
6417	__le16 max_aggs;
6418	#define VNIC_TPA_QCFG_RESP_MAX_AGGS_1 0x0UL
6419	#define VNIC_TPA_QCFG_RESP_MAX_AGGS_2 0x1UL
6420	#define VNIC_TPA_QCFG_RESP_MAX_AGGS_4 0x2UL
6421	#define VNIC_TPA_QCFG_RESP_MAX_AGGS_8 0x3UL
6422	#define VNIC_TPA_QCFG_RESP_MAX_AGGS_16 0x4UL
6423	#define VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 0x7UL
6424	#define VNIC_TPA_QCFG_RESP_MAX_AGGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX
6425	__le32 max_agg_timer;
6426	__le32 min_agg_len;
6427	__le32 tnl_tpa_en_bitmap;
6428	#define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_VXLAN 0x1UL
6429	#define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_GENEVE 0x2UL
6430	#define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_NVGRE 0x4UL
6431	#define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_GRE 0x8UL
6432	#define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_IPV4 0x10UL
6433	#define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_IPV6 0x20UL
6434	#define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_VXLAN_GPE 0x40UL
6435	#define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_VXLAN_CUST1 0x80UL
6436	#define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_GRE_CUST1 0x100UL
6437	#define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR1 0x200UL
6438	#define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR2 0x400UL
6439	#define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR3 0x800UL
6440	#define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR4 0x1000UL
6441	#define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR5 0x2000UL
6442	#define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR6 0x4000UL
6443	#define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR7 0x8000UL
6444	#define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR8 0x10000UL
6445	u8 unused_0[3];
6446	u8 valid;
6447	};
6448
6449	/* hwrm_vnic_rss_cfg_input (size:384b/48B) */
6450	struct hwrm_vnic_rss_cfg_input {
6451	__le16 req_type;
6452	__le16 cmpl_ring;
6453	__le16 seq_id;
6454	__le16 target_id;
6455	__le64 resp_addr;
6456	__le32 hash_type;
6457	#define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 0x1UL
6458	#define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 0x2UL
6459	#define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 0x4UL
6460	#define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL
6461	#define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL
6462	#define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL
6463	#define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6_FLOW_LABEL 0x40UL
6464	#define VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV4 0x80UL
6465	#define VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV4 0x100UL
6466	#define VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV6 0x200UL
6467	#define VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV6 0x400UL
6468	__le16 vnic_id;
6469	u8 ring_table_pair_index;
6470	u8 hash_mode_flags;
6471	#define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT 0x1UL
6472	#define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_4 0x2UL
6473	#define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_2 0x4UL
6474	#define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_4 0x8UL
6475	#define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_2 0x10UL
6476	__le64 ring_grp_tbl_addr;
6477	__le64 hash_key_tbl_addr;
6478	__le16 rss_ctx_idx;
6479	u8 flags;
6480	#define VNIC_RSS_CFG_REQ_FLAGS_HASH_TYPE_INCLUDE 0x1UL
6481	#define VNIC_RSS_CFG_REQ_FLAGS_HASH_TYPE_EXCLUDE 0x2UL
6482	#define VNIC_RSS_CFG_REQ_FLAGS_IPSEC_HASH_TYPE_CFG_SUPPORT 0x4UL
6483	u8 ring_select_mode;
6484	#define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_TOEPLITZ 0x0UL
6485	#define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_XOR 0x1UL
6486	#define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_TOEPLITZ_CHECKSUM 0x2UL
6487	#define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_LAST VNIC_RSS_CFG_REQ_RING_SELECT_MODE_TOEPLITZ_CHECKSUM
6488	u8 unused_1[4];
6489	};
6490
6491	/* hwrm_vnic_rss_cfg_output (size:128b/16B) */
6492	struct hwrm_vnic_rss_cfg_output {
6493	__le16 error_code;
6494	__le16 req_type;
6495	__le16 seq_id;
6496	__le16 resp_len;
6497	u8 unused_0[7];
6498	u8 valid;
6499	};
6500
6501	/* hwrm_vnic_rss_cfg_cmd_err (size:64b/8B) */
6502	struct hwrm_vnic_rss_cfg_cmd_err {
6503	u8 code;
6504	#define VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL
6505	#define VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY 0x1UL
6506	#define VNIC_RSS_CFG_CMD_ERR_CODE_LAST VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY
6507	u8 unused_0[7];
6508	};
6509
6510	/* hwrm_vnic_rss_qcfg_input (size:192b/24B) */
6511	struct hwrm_vnic_rss_qcfg_input {
6512	__le16 req_type;
6513	__le16 cmpl_ring;
6514	__le16 seq_id;
6515	__le16 target_id;
6516	__le64 resp_addr;
6517	__le16 rss_ctx_idx;
6518	__le16 vnic_id;
6519	u8 unused_0[4];
6520	};
6521
6522	/* hwrm_vnic_rss_qcfg_output (size:512b/64B) */
6523	struct hwrm_vnic_rss_qcfg_output {
6524	__le16 error_code;
6525	__le16 req_type;
6526	__le16 seq_id;
6527	__le16 resp_len;
6528	__le32 hash_type;
6529	#define VNIC_RSS_QCFG_RESP_HASH_TYPE_IPV4 0x1UL
6530	#define VNIC_RSS_QCFG_RESP_HASH_TYPE_TCP_IPV4 0x2UL
6531	#define VNIC_RSS_QCFG_RESP_HASH_TYPE_UDP_IPV4 0x4UL
6532	#define VNIC_RSS_QCFG_RESP_HASH_TYPE_IPV6 0x8UL
6533	#define VNIC_RSS_QCFG_RESP_HASH_TYPE_TCP_IPV6 0x10UL
6534	#define VNIC_RSS_QCFG_RESP_HASH_TYPE_UDP_IPV6 0x20UL
6535	#define VNIC_RSS_QCFG_RESP_HASH_TYPE_IPV6_FLOW_LABEL 0x40UL
6536	#define VNIC_RSS_QCFG_RESP_HASH_TYPE_AH_SPI_IPV4 0x80UL
6537	#define VNIC_RSS_QCFG_RESP_HASH_TYPE_ESP_SPI_IPV4 0x100UL
6538	#define VNIC_RSS_QCFG_RESP_HASH_TYPE_AH_SPI_IPV6 0x200UL
6539	#define VNIC_RSS_QCFG_RESP_HASH_TYPE_ESP_SPI_IPV6 0x400UL
6540	u8 unused_0[4];
6541	__le32 hash_key[10];
6542	u8 hash_mode_flags;
6543	#define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_DEFAULT 0x1UL
6544	#define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_INNERMOST_4 0x2UL
6545	#define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_INNERMOST_2 0x4UL
6546	#define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_OUTERMOST_4 0x8UL
6547	#define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_OUTERMOST_2 0x10UL
6548	u8 ring_select_mode;
6549	#define VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_TOEPLITZ 0x0UL
6550	#define VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_XOR 0x1UL
6551	#define VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_TOEPLITZ_CHECKSUM 0x2UL
6552	#define VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_LAST VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_TOEPLITZ_CHECKSUM
6553	u8 unused_1[5];
6554	u8 valid;
6555	};
6556
6557	/* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */
6558	struct hwrm_vnic_plcmodes_cfg_input {
6559	__le16 req_type;
6560	__le16 cmpl_ring;
6561	__le16 seq_id;
6562	__le16 target_id;
6563	__le64 resp_addr;
6564	__le32 flags;
6565	#define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT 0x1UL
6566	#define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT 0x2UL
6567	#define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 0x4UL
6568	#define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6 0x8UL
6569	#define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE 0x10UL
6570	#define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE 0x20UL
6571	#define VNIC_PLCMODES_CFG_REQ_FLAGS_VIRTIO_PLACEMENT 0x40UL
6572	__le32 enables;
6573	#define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID 0x1UL
6574	#define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID 0x2UL
6575	#define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID 0x4UL
6576	#define VNIC_PLCMODES_CFG_REQ_ENABLES_MAX_BDS_VALID 0x8UL
6577	__le32 vnic_id;
6578	__le16 jumbo_thresh;
6579	__le16 hds_offset;
6580	__le16 hds_threshold;
6581	__le16 max_bds;
6582	u8 unused_0[4];
6583	};
6584
6585	/* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */
6586	struct hwrm_vnic_plcmodes_cfg_output {
6587	__le16 error_code;
6588	__le16 req_type;
6589	__le16 seq_id;
6590	__le16 resp_len;
6591	u8 unused_0[7];
6592	u8 valid;
6593	};
6594
6595	/* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */
6596	struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {
6597	__le16 req_type;
6598	__le16 cmpl_ring;
6599	__le16 seq_id;
6600	__le16 target_id;
6601	__le64 resp_addr;
6602	};
6603
6604	/* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */
6605	struct hwrm_vnic_rss_cos_lb_ctx_alloc_output {
6606	__le16 error_code;
6607	__le16 req_type;
6608	__le16 seq_id;
6609	__le16 resp_len;
6610	__le16 rss_cos_lb_ctx_id;
6611	u8 unused_0[5];
6612	u8 valid;
6613	};
6614
6615	/* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */
6616	struct hwrm_vnic_rss_cos_lb_ctx_free_input {
6617	__le16 req_type;
6618	__le16 cmpl_ring;
6619	__le16 seq_id;
6620	__le16 target_id;
6621	__le64 resp_addr;
6622	__le16 rss_cos_lb_ctx_id;
6623	u8 unused_0[6];
6624	};
6625
6626	/* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */
6627	struct hwrm_vnic_rss_cos_lb_ctx_free_output {
6628	__le16 error_code;
6629	__le16 req_type;
6630	__le16 seq_id;
6631	__le16 resp_len;
6632	u8 unused_0[7];
6633	u8 valid;
6634	};
6635
6636	/* hwrm_ring_alloc_input (size:704b/88B) */
6637	struct hwrm_ring_alloc_input {
6638	__le16 req_type;
6639	__le16 cmpl_ring;
6640	__le16 seq_id;
6641	__le16 target_id;
6642	__le64 resp_addr;
6643	__le32 enables;
6644	#define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG 0x2UL
6645	#define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL
6646	#define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL
6647	#define RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID 0x40UL
6648	#define RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID 0x80UL
6649	#define RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID 0x100UL
6650	#define RING_ALLOC_REQ_ENABLES_SCHQ_ID 0x200UL
6651	#define RING_ALLOC_REQ_ENABLES_MPC_CHNLS_TYPE 0x400UL
6652	#define RING_ALLOC_REQ_ENABLES_STEERING_TAG_VALID 0x800UL
6653	u8 ring_type;
6654	#define RING_ALLOC_REQ_RING_TYPE_L2_CMPL 0x0UL
6655	#define RING_ALLOC_REQ_RING_TYPE_TX 0x1UL
6656	#define RING_ALLOC_REQ_RING_TYPE_RX 0x2UL
6657	#define RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL 0x3UL
6658	#define RING_ALLOC_REQ_RING_TYPE_RX_AGG 0x4UL
6659	#define RING_ALLOC_REQ_RING_TYPE_NQ 0x5UL
6660	#define RING_ALLOC_REQ_RING_TYPE_LAST RING_ALLOC_REQ_RING_TYPE_NQ
6661	u8 cmpl_coal_cnt;
6662	#define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_OFF 0x0UL
6663	#define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_4 0x1UL
6664	#define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_8 0x2UL
6665	#define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_12 0x3UL
6666	#define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_16 0x4UL
6667	#define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_24 0x5UL
6668	#define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_32 0x6UL
6669	#define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_48 0x7UL
6670	#define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_64 0x8UL
6671	#define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_96 0x9UL
6672	#define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_128 0xaUL
6673	#define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_192 0xbUL
6674	#define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_256 0xcUL
6675	#define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_320 0xdUL
6676	#define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_384 0xeUL
6677	#define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_MAX 0xfUL
6678	#define RING_ALLOC_REQ_CMPL_COAL_CNT_LAST RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_MAX
6679	__le16 flags;
6680	#define RING_ALLOC_REQ_FLAGS_RX_SOP_PAD 0x1UL
6681	#define RING_ALLOC_REQ_FLAGS_DISABLE_CQ_OVERFLOW_DETECTION 0x2UL
6682	#define RING_ALLOC_REQ_FLAGS_NQ_DBR_PACING 0x4UL
6683	#define RING_ALLOC_REQ_FLAGS_TX_PKT_TS_CMPL_ENABLE 0x8UL
6684	__le64 page_tbl_addr;
6685	__le32 fbo;
6686	u8 page_size;
6687	u8 page_tbl_depth;
6688	__le16 schq_id;
6689	__le32 length;
6690	__le16 logical_id;
6691	__le16 cmpl_ring_id;
6692	__le16 queue_id;
6693	__le16 rx_buf_size;
6694	__le16 rx_ring_id;
6695	__le16 nq_ring_id;
6696	__le16 ring_arb_cfg;
6697	#define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_MASK 0xfUL
6698	#define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SFT 0
6699	#define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SP 0x1UL
6700	#define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 0x2UL
6701	#define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_LAST RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ
6702	#define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_MASK 0xf0UL
6703	#define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_SFT 4
6704	#define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_MASK 0xff00UL
6705	#define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8
6706	__le16 steering_tag;
6707	__le32 reserved3;
6708	__le32 stat_ctx_id;
6709	__le32 reserved4;
6710	__le32 max_bw;
6711	#define RING_ALLOC_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL
6712	#define RING_ALLOC_REQ_MAX_BW_BW_VALUE_SFT 0
6713	#define RING_ALLOC_REQ_MAX_BW_SCALE 0x10000000UL
6714	#define RING_ALLOC_REQ_MAX_BW_SCALE_BITS (0x0UL << 28)
6715	#define RING_ALLOC_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28)
6716	#define RING_ALLOC_REQ_MAX_BW_SCALE_LAST RING_ALLOC_REQ_MAX_BW_SCALE_BYTES
6717	#define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
6718	#define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29
6719	#define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
6720	#define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
6721	#define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
6722	#define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
6723	#define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
6724	#define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
6725	#define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_LAST RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID
6726	u8 int_mode;
6727	#define RING_ALLOC_REQ_INT_MODE_LEGACY 0x0UL
6728	#define RING_ALLOC_REQ_INT_MODE_RSVD 0x1UL
6729	#define RING_ALLOC_REQ_INT_MODE_MSIX 0x2UL
6730	#define RING_ALLOC_REQ_INT_MODE_POLL 0x3UL
6731	#define RING_ALLOC_REQ_INT_MODE_LAST RING_ALLOC_REQ_INT_MODE_POLL
6732	u8 mpc_chnls_type;
6733	#define RING_ALLOC_REQ_MPC_CHNLS_TYPE_TCE 0x0UL
6734	#define RING_ALLOC_REQ_MPC_CHNLS_TYPE_RCE 0x1UL
6735	#define RING_ALLOC_REQ_MPC_CHNLS_TYPE_TE_CFA 0x2UL
6736	#define RING_ALLOC_REQ_MPC_CHNLS_TYPE_RE_CFA 0x3UL
6737	#define RING_ALLOC_REQ_MPC_CHNLS_TYPE_PRIMATE 0x4UL
6738	#define RING_ALLOC_REQ_MPC_CHNLS_TYPE_LAST RING_ALLOC_REQ_MPC_CHNLS_TYPE_PRIMATE
6739	u8 unused_4[2];
6740	__le64 cq_handle;
6741	};
6742
6743	/* hwrm_ring_alloc_output (size:128b/16B) */
6744	struct hwrm_ring_alloc_output {
6745	__le16 error_code;
6746	__le16 req_type;
6747	__le16 seq_id;
6748	__le16 resp_len;
6749	__le16 ring_id;
6750	__le16 logical_ring_id;
6751	u8 push_buffer_index;
6752	#define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PING_BUFFER 0x0UL
6753	#define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 0x1UL
6754	#define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_LAST RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER
6755	u8 unused_0[2];
6756	u8 valid;
6757	};
6758
6759	/* hwrm_ring_free_input (size:256b/32B) */
6760	struct hwrm_ring_free_input {
6761	__le16 req_type;
6762	__le16 cmpl_ring;
6763	__le16 seq_id;
6764	__le16 target_id;
6765	__le64 resp_addr;
6766	u8 ring_type;
6767	#define RING_FREE_REQ_RING_TYPE_L2_CMPL 0x0UL
6768	#define RING_FREE_REQ_RING_TYPE_TX 0x1UL
6769	#define RING_FREE_REQ_RING_TYPE_RX 0x2UL
6770	#define RING_FREE_REQ_RING_TYPE_ROCE_CMPL 0x3UL
6771	#define RING_FREE_REQ_RING_TYPE_RX_AGG 0x4UL
6772	#define RING_FREE_REQ_RING_TYPE_NQ 0x5UL
6773	#define RING_FREE_REQ_RING_TYPE_LAST RING_FREE_REQ_RING_TYPE_NQ
6774	u8 flags;
6775	#define RING_FREE_REQ_FLAGS_VIRTIO_RING_VALID 0x1UL
6776	#define RING_FREE_REQ_FLAGS_LAST RING_FREE_REQ_FLAGS_VIRTIO_RING_VALID
6777	__le16 ring_id;
6778	__le32 prod_idx;
6779	__le32 opaque;
6780	__le32 unused_1;
6781	};
6782
6783	/* hwrm_ring_free_output (size:128b/16B) */
6784	struct hwrm_ring_free_output {
6785	__le16 error_code;
6786	__le16 req_type;
6787	__le16 seq_id;
6788	__le16 resp_len;
6789	u8 unused_0[7];
6790	u8 valid;
6791	};
6792
6793	/* hwrm_ring_reset_input (size:192b/24B) */
6794	struct hwrm_ring_reset_input {
6795	__le16 req_type;
6796	__le16 cmpl_ring;
6797	__le16 seq_id;
6798	__le16 target_id;
6799	__le64 resp_addr;
6800	u8 ring_type;
6801	#define RING_RESET_REQ_RING_TYPE_L2_CMPL 0x0UL
6802	#define RING_RESET_REQ_RING_TYPE_TX 0x1UL
6803	#define RING_RESET_REQ_RING_TYPE_RX 0x2UL
6804	#define RING_RESET_REQ_RING_TYPE_ROCE_CMPL 0x3UL
6805	#define RING_RESET_REQ_RING_TYPE_RX_RING_GRP 0x6UL
6806	#define RING_RESET_REQ_RING_TYPE_LAST RING_RESET_REQ_RING_TYPE_RX_RING_GRP
6807	u8 unused_0;
6808	__le16 ring_id;
6809	u8 unused_1[4];
6810	};
6811
6812	/* hwrm_ring_reset_output (size:128b/16B) */
6813	struct hwrm_ring_reset_output {
6814	__le16 error_code;
6815	__le16 req_type;
6816	__le16 seq_id;
6817	__le16 resp_len;
6818	u8 push_buffer_index;
6819	#define RING_RESET_RESP_PUSH_BUFFER_INDEX_PING_BUFFER 0x0UL
6820	#define RING_RESET_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 0x1UL
6821	#define RING_RESET_RESP_PUSH_BUFFER_INDEX_LAST RING_RESET_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER
6822	u8 unused_0[3];
6823	u8 consumer_idx[3];
6824	u8 valid;
6825	};
6826
6827	/* hwrm_ring_aggint_qcaps_input (size:128b/16B) */
6828	struct hwrm_ring_aggint_qcaps_input {
6829	__le16 req_type;
6830	__le16 cmpl_ring;
6831	__le16 seq_id;
6832	__le16 target_id;
6833	__le64 resp_addr;
6834	};
6835
6836	/* hwrm_ring_aggint_qcaps_output (size:384b/48B) */
6837	struct hwrm_ring_aggint_qcaps_output {
6838	__le16 error_code;
6839	__le16 req_type;
6840	__le16 seq_id;
6841	__le16 resp_len;
6842	__le32 cmpl_params;
6843	#define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN 0x1UL
6844	#define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX 0x2UL
6845	#define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET 0x4UL
6846	#define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE 0x8UL
6847	#define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR 0x10UL
6848	#define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT 0x20UL
6849	#define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR 0x40UL
6850	#define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT 0x80UL
6851	#define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT 0x100UL
6852	__le32 nq_params;
6853	#define RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN 0x1UL
6854	__le16 num_cmpl_dma_aggr_min;
6855	__le16 num_cmpl_dma_aggr_max;
6856	__le16 num_cmpl_dma_aggr_during_int_min;
6857	__le16 num_cmpl_dma_aggr_during_int_max;
6858	__le16 cmpl_aggr_dma_tmr_min;
6859	__le16 cmpl_aggr_dma_tmr_max;
6860	__le16 cmpl_aggr_dma_tmr_during_int_min;
6861	__le16 cmpl_aggr_dma_tmr_during_int_max;
6862	__le16 int_lat_tmr_min_min;
6863	__le16 int_lat_tmr_min_max;
6864	__le16 int_lat_tmr_max_min;
6865	__le16 int_lat_tmr_max_max;
6866	__le16 num_cmpl_aggr_int_min;
6867	__le16 num_cmpl_aggr_int_max;
6868	__le16 timer_units;
6869	u8 unused_0[1];
6870	u8 valid;
6871	};
6872
6873	/* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */
6874	struct hwrm_ring_cmpl_ring_qaggint_params_input {
6875	__le16 req_type;
6876	__le16 cmpl_ring;
6877	__le16 seq_id;
6878	__le16 target_id;
6879	__le64 resp_addr;
6880	__le16 ring_id;
6881	__le16 flags;
6882	#define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_UNUSED_0_MASK 0x3UL
6883	#define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_UNUSED_0_SFT 0
6884	#define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL
6885	u8 unused_0[4];
6886	};
6887
6888	/* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */
6889	struct hwrm_ring_cmpl_ring_qaggint_params_output {
6890	__le16 error_code;
6891	__le16 req_type;
6892	__le16 seq_id;
6893	__le16 resp_len;
6894	__le16 flags;
6895	#define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET 0x1UL
6896	#define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE 0x2UL
6897	__le16 num_cmpl_dma_aggr;
6898	__le16 num_cmpl_dma_aggr_during_int;
6899	__le16 cmpl_aggr_dma_tmr;
6900	__le16 cmpl_aggr_dma_tmr_during_int;
6901	__le16 int_lat_tmr_min;
6902	__le16 int_lat_tmr_max;
6903	__le16 num_cmpl_aggr_int;
6904	u8 unused_0[7];
6905	u8 valid;
6906	};
6907
6908	/* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */
6909	struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {
6910	__le16 req_type;
6911	__le16 cmpl_ring;
6912	__le16 seq_id;
6913	__le16 target_id;
6914	__le64 resp_addr;
6915	__le16 ring_id;
6916	__le16 flags;
6917	#define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET 0x1UL
6918	#define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE 0x2UL
6919	#define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL
6920	__le16 num_cmpl_dma_aggr;
6921	__le16 num_cmpl_dma_aggr_during_int;
6922	__le16 cmpl_aggr_dma_tmr;
6923	__le16 cmpl_aggr_dma_tmr_during_int;
6924	__le16 int_lat_tmr_min;
6925	__le16 int_lat_tmr_max;
6926	__le16 num_cmpl_aggr_int;
6927	__le16 enables;
6928	#define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR 0x1UL
6929	#define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT 0x2UL
6930	#define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR 0x4UL
6931	#define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN 0x8UL
6932	#define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX 0x10UL
6933	#define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT 0x20UL
6934	u8 unused_0[4];
6935	};
6936
6937	/* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */
6938	struct hwrm_ring_cmpl_ring_cfg_aggint_params_output {
6939	__le16 error_code;
6940	__le16 req_type;
6941	__le16 seq_id;
6942	__le16 resp_len;
6943	u8 unused_0[7];
6944	u8 valid;
6945	};
6946
6947	/* hwrm_ring_grp_alloc_input (size:192b/24B) */
6948	struct hwrm_ring_grp_alloc_input {
6949	__le16 req_type;
6950	__le16 cmpl_ring;
6951	__le16 seq_id;
6952	__le16 target_id;
6953	__le64 resp_addr;
6954	__le16 cr;
6955	__le16 rr;
6956	__le16 ar;
6957	__le16 sc;
6958	};
6959
6960	/* hwrm_ring_grp_alloc_output (size:128b/16B) */
6961	struct hwrm_ring_grp_alloc_output {
6962	__le16 error_code;
6963	__le16 req_type;
6964	__le16 seq_id;
6965	__le16 resp_len;
6966	__le32 ring_group_id;
6967	u8 unused_0[3];
6968	u8 valid;
6969	};
6970
6971	/* hwrm_ring_grp_free_input (size:192b/24B) */
6972	struct hwrm_ring_grp_free_input {
6973	__le16 req_type;
6974	__le16 cmpl_ring;
6975	__le16 seq_id;
6976	__le16 target_id;
6977	__le64 resp_addr;
6978	__le32 ring_group_id;
6979	u8 unused_0[4];
6980	};
6981
6982	/* hwrm_ring_grp_free_output (size:128b/16B) */
6983	struct hwrm_ring_grp_free_output {
6984	__le16 error_code;
6985	__le16 req_type;
6986	__le16 seq_id;
6987	__le16 resp_len;
6988	u8 unused_0[7];
6989	u8 valid;
6990	};
6991
6992	#define DEFAULT_FLOW_ID 0xFFFFFFFFUL
6993	#define ROCEV1_FLOW_ID 0xFFFFFFFEUL
6994	#define ROCEV2_FLOW_ID 0xFFFFFFFDUL
6995	#define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL
6996
6997	/* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */
6998	struct hwrm_cfa_l2_filter_alloc_input {
6999	__le16 req_type;
7000	__le16 cmpl_ring;
7001	__le16 seq_id;
7002	__le16 target_id;
7003	__le64 resp_addr;
7004	__le32 flags;
7005	#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL
7006	#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX 0x0UL
7007	#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 0x1UL
7008	#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX
7009	#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL
7010	#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL
7011	#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL
7012	#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_MASK 0x30UL
7013	#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_SFT 4
7014	#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 4)
7015	#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 4)
7016	#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 4)
7017	#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE
7018	#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_XDP_DISABLE 0x40UL
7019	#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_SOURCE_VALID 0x80UL
7020	__le32 enables;
7021	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL
7022	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL
7023	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN 0x4UL
7024	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK 0x8UL
7025	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x10UL
7026	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK 0x20UL
7027	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR 0x40UL
7028	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK 0x80UL
7029	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN 0x100UL
7030	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK 0x200UL
7031	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN 0x400UL
7032	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK 0x800UL
7033	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE 0x1000UL
7034	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID 0x2000UL
7035	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4000UL
7036	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL
7037	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL
7038	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_NUM_VLANS 0x20000UL
7039	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_NUM_VLANS 0x40000UL
7040	u8 l2_addr[6];
7041	u8 num_vlans;
7042	u8 t_num_vlans;
7043	u8 l2_addr_mask[6];
7044	__le16 l2_ovlan;
7045	__le16 l2_ovlan_mask;
7046	__le16 l2_ivlan;
7047	__le16 l2_ivlan_mask;
7048	u8 unused_1[2];
7049	u8 t_l2_addr[6];
7050	u8 unused_2[2];
7051	u8 t_l2_addr_mask[6];
7052	__le16 t_l2_ovlan;
7053	__le16 t_l2_ovlan_mask;
7054	__le16 t_l2_ivlan;
7055	__le16 t_l2_ivlan_mask;
7056	u8 src_type;
7057	#define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT 0x0UL
7058	#define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF 0x1UL
7059	#define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF 0x2UL
7060	#define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC 0x3UL
7061	#define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG 0x4UL
7062	#define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE 0x5UL
7063	#define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO 0x6UL
7064	#define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 0x7UL
7065	#define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG
7066	u8 unused_3;
7067	__le32 src_id;
7068	u8 tunnel_type;
7069	#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
7070	#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
7071	#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
7072	#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL
7073	#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL
7074	#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
7075	#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL
7076	#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
7077	#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
7078	#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
7079	#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
7080	#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
7081	#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
7082	#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL
7083	#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
7084	#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
7085	u8 unused_4;
7086	__le16 dst_id;
7087	__le16 mirror_vnic_id;
7088	u8 pri_hint;
7089	#define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL
7090	#define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER 0x1UL
7091	#define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER 0x2UL
7092	#define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX 0x3UL
7093	#define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 0x4UL
7094	#define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN
7095	u8 unused_5;
7096	__le32 unused_6;
7097	__le64 l2_filter_id_hint;
7098	};
7099
7100	/* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */
7101	struct hwrm_cfa_l2_filter_alloc_output {
7102	__le16 error_code;
7103	__le16 req_type;
7104	__le16 seq_id;
7105	__le16 resp_len;
7106	__le64 l2_filter_id;
7107	__le32 flow_id;
7108	#define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL
7109	#define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0
7110	#define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL
7111	#define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30)
7112	#define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30)
7113	#define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT
7114	#define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL
7115	#define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31)
7116	#define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31)
7117	#define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX
7118	u8 unused_0[3];
7119	u8 valid;
7120	};
7121
7122	/* hwrm_cfa_l2_filter_free_input (size:192b/24B) */
7123	struct hwrm_cfa_l2_filter_free_input {
7124	__le16 req_type;
7125	__le16 cmpl_ring;
7126	__le16 seq_id;
7127	__le16 target_id;
7128	__le64 resp_addr;
7129	__le64 l2_filter_id;
7130	};
7131
7132	/* hwrm_cfa_l2_filter_free_output (size:128b/16B) */
7133	struct hwrm_cfa_l2_filter_free_output {
7134	__le16 error_code;
7135	__le16 req_type;
7136	__le16 seq_id;
7137	__le16 resp_len;
7138	u8 unused_0[7];
7139	u8 valid;
7140	};
7141
7142	/* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */
7143	struct hwrm_cfa_l2_filter_cfg_input {
7144	__le16 req_type;
7145	__le16 cmpl_ring;
7146	__le16 seq_id;
7147	__le16 target_id;
7148	__le64 resp_addr;
7149	__le32 flags;
7150	#define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL
7151	#define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX 0x0UL
7152	#define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 0x1UL
7153	#define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX
7154	#define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL
7155	#define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_MASK 0xcUL
7156	#define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_SFT 2
7157	#define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 2)
7158	#define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 2)
7159	#define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 2)
7160	#define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE
7161	__le32 enables;
7162	#define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID 0x1UL
7163	#define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL
7164	__le64 l2_filter_id;
7165	__le32 dst_id;
7166	__le32 new_mirror_vnic_id;
7167	};
7168
7169	/* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */
7170	struct hwrm_cfa_l2_filter_cfg_output {
7171	__le16 error_code;
7172	__le16 req_type;
7173	__le16 seq_id;
7174	__le16 resp_len;
7175	u8 unused_0[7];
7176	u8 valid;
7177	};
7178
7179	/* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */
7180	struct hwrm_cfa_l2_set_rx_mask_input {
7181	__le16 req_type;
7182	__le16 cmpl_ring;
7183	__le16 seq_id;
7184	__le16 target_id;
7185	__le64 resp_addr;
7186	__le32 vnic_id;
7187	__le32 mask;
7188	#define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL
7189	#define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL
7190	#define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL
7191	#define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL
7192	#define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST 0x20UL
7193	#define CFA_L2_SET_RX_MASK_REQ_MASK_VLANONLY 0x40UL
7194	#define CFA_L2_SET_RX_MASK_REQ_MASK_VLAN_NONVLAN 0x80UL
7195	#define CFA_L2_SET_RX_MASK_REQ_MASK_ANYVLAN_NONVLAN 0x100UL
7196	__le64 mc_tbl_addr;
7197	__le32 num_mc_entries;
7198	u8 unused_0[4];
7199	__le64 vlan_tag_tbl_addr;
7200	__le32 num_vlan_tags;
7201	u8 unused_1[4];
7202	};
7203
7204	/* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */
7205	struct hwrm_cfa_l2_set_rx_mask_output {
7206	__le16 error_code;
7207	__le16 req_type;
7208	__le16 seq_id;
7209	__le16 resp_len;
7210	u8 unused_0[7];
7211	u8 valid;
7212	};
7213
7214	/* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */
7215	struct hwrm_cfa_l2_set_rx_mask_cmd_err {
7216	u8 code;
7217	#define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN 0x0UL
7218	#define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 0x1UL
7219	#define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR
7220	u8 unused_0[7];
7221	};
7222
7223	/* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */
7224	struct hwrm_cfa_tunnel_filter_alloc_input {
7225	__le16 req_type;
7226	__le16 cmpl_ring;
7227	__le16 seq_id;
7228	__le16 target_id;
7229	__le64 resp_addr;
7230	__le32 flags;
7231	#define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL
7232	__le32 enables;
7233	#define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL
7234	#define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x2UL
7235	#define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x4UL
7236	#define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR 0x8UL
7237	#define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE 0x10UL
7238	#define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE 0x20UL
7239	#define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR 0x40UL
7240	#define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x80UL
7241	#define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI 0x100UL
7242	#define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x200UL
7243	#define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x400UL
7244	__le64 l2_filter_id;
7245	u8 l2_addr[6];
7246	__le16 l2_ivlan;
7247	__le32 l3_addr[4];
7248	__le32 t_l3_addr[4];
7249	u8 l3_addr_type;
7250	u8 t_l3_addr_type;
7251	u8 tunnel_type;
7252	#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
7253	#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
7254	#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
7255	#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL
7256	#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL
7257	#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
7258	#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL
7259	#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
7260	#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
7261	#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
7262	#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
7263	#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
7264	#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
7265	#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL
7266	#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
7267	#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
7268	u8 tunnel_flags;
7269	#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR 0x1UL
7270	#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 0x2UL
7271	#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 0x4UL
7272	__le32 vni;
7273	__le32 dst_vnic_id;
7274	__le32 mirror_vnic_id;
7275	};
7276
7277	/* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */
7278	struct hwrm_cfa_tunnel_filter_alloc_output {
7279	__le16 error_code;
7280	__le16 req_type;
7281	__le16 seq_id;
7282	__le16 resp_len;
7283	__le64 tunnel_filter_id;
7284	__le32 flow_id;
7285	#define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL
7286	#define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0
7287	#define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL
7288	#define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30)
7289	#define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30)
7290	#define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT
7291	#define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL
7292	#define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31)
7293	#define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31)
7294	#define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX
7295	u8 unused_0[3];
7296	u8 valid;
7297	};
7298
7299	/* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */
7300	struct hwrm_cfa_tunnel_filter_free_input {
7301	__le16 req_type;
7302	__le16 cmpl_ring;
7303	__le16 seq_id;
7304	__le16 target_id;
7305	__le64 resp_addr;
7306	__le64 tunnel_filter_id;
7307	};
7308
7309	/* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */
7310	struct hwrm_cfa_tunnel_filter_free_output {
7311	__le16 error_code;
7312	__le16 req_type;
7313	__le16 seq_id;
7314	__le16 resp_len;
7315	u8 unused_0[7];
7316	u8 valid;
7317	};
7318
7319	/* hwrm_vxlan_ipv4_hdr (size:128b/16B) */
7320	struct hwrm_vxlan_ipv4_hdr {
7321	u8 ver_hlen;
7322	#define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK 0xfUL
7323	#define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0
7324	#define VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK 0xf0UL
7325	#define VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4
7326	u8 tos;
7327	__be16 ip_id;
7328	__be16 flags_frag_offset;
7329	u8 ttl;
7330	u8 protocol;
7331	__be32 src_ip_addr;
7332	__be32 dest_ip_addr;
7333	};
7334
7335	/* hwrm_vxlan_ipv6_hdr (size:320b/40B) */
7336	struct hwrm_vxlan_ipv6_hdr {
7337	__be32 ver_tc_flow_label;
7338	#define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT 0x1cUL
7339	#define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK 0xf0000000UL
7340	#define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT 0x14UL
7341	#define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK 0xff00000UL
7342	#define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT 0x0UL
7343	#define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 0xfffffUL
7344	#define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK
7345	__be16 payload_len;
7346	u8 next_hdr;
7347	u8 ttl;
7348	__be32 src_ip_addr[4];
7349	__be32 dest_ip_addr[4];
7350	};
7351
7352	/* hwrm_cfa_encap_data_vxlan (size:640b/80B) */
7353	struct hwrm_cfa_encap_data_vxlan {
7354	u8 src_mac_addr[6];
7355	__le16 unused_0;
7356	u8 dst_mac_addr[6];
7357	u8 num_vlan_tags;
7358	u8 unused_1;
7359	__be16 ovlan_tpid;
7360	__be16 ovlan_tci;
7361	__be16 ivlan_tpid;
7362	__be16 ivlan_tci;
7363	__le32 l3[10];
7364	#define CFA_ENCAP_DATA_VXLAN_L3_VER_MASK 0xfUL
7365	#define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 0x4UL
7366	#define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 0x6UL
7367	#define CFA_ENCAP_DATA_VXLAN_L3_LAST CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6
7368	__be16 src_port;
7369	__be16 dst_port;
7370	__be32 vni;
7371	u8 hdr_rsvd0[3];
7372	u8 hdr_rsvd1;
7373	u8 hdr_flags;
7374	u8 unused[3];
7375	};
7376
7377	/* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */
7378	struct hwrm_cfa_encap_record_alloc_input {
7379	__le16 req_type;
7380	__le16 cmpl_ring;
7381	__le16 seq_id;
7382	__le16 target_id;
7383	__le64 resp_addr;
7384	__le32 flags;
7385	#define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL
7386	#define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_EXTERNAL 0x2UL
7387	u8 encap_type;
7388	#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN 0x1UL
7389	#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE 0x2UL
7390	#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE 0x3UL
7391	#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP 0x4UL
7392	#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE 0x5UL
7393	#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS 0x6UL
7394	#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN 0x7UL
7395	#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE 0x8UL
7396	#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_V4 0x9UL
7397	#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE_V1 0xaUL
7398	#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2_ETYPE 0xbUL
7399	#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6 0xcUL
7400	#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE 0x10UL
7401	#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_LAST CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE
7402	u8 unused_0[3];
7403	__le32 encap_data[20];
7404	};
7405
7406	/* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */
7407	struct hwrm_cfa_encap_record_alloc_output {
7408	__le16 error_code;
7409	__le16 req_type;
7410	__le16 seq_id;
7411	__le16 resp_len;
7412	__le32 encap_record_id;
7413	u8 unused_0[3];
7414	u8 valid;
7415	};
7416
7417	/* hwrm_cfa_encap_record_free_input (size:192b/24B) */
7418	struct hwrm_cfa_encap_record_free_input {
7419	__le16 req_type;
7420	__le16 cmpl_ring;
7421	__le16 seq_id;
7422	__le16 target_id;
7423	__le64 resp_addr;
7424	__le32 encap_record_id;
7425	u8 unused_0[4];
7426	};
7427
7428	/* hwrm_cfa_encap_record_free_output (size:128b/16B) */
7429	struct hwrm_cfa_encap_record_free_output {
7430	__le16 error_code;
7431	__le16 req_type;
7432	__le16 seq_id;
7433	__le16 resp_len;
7434	u8 unused_0[7];
7435	u8 valid;
7436	};
7437
7438	/* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */
7439	struct hwrm_cfa_ntuple_filter_alloc_input {
7440	__le16 req_type;
7441	__le16 cmpl_ring;
7442	__le16 seq_id;
7443	__le16 target_id;
7444	__le64 resp_addr;
7445	__le32 flags;
7446	#define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL
7447	#define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP 0x2UL
7448	#define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_METER 0x4UL
7449	#define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_FID 0x8UL
7450	#define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_ARP_REPLY 0x10UL
7451	#define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_RFS_RING_IDX 0x20UL
7452	#define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_NO_L2_CONTEXT 0x40UL
7453	__le32 enables;
7454	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL
7455	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x2UL
7456	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4UL
7457	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x8UL
7458	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x10UL
7459	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x20UL
7460	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK 0x40UL
7461	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x80UL
7462	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK 0x100UL
7463	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x200UL
7464	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x400UL
7465	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK 0x800UL
7466	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x1000UL
7467	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK 0x2000UL
7468	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT 0x4000UL
7469	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID 0x8000UL
7470	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x10000UL
7471	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x20000UL
7472	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x40000UL
7473	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_RFS_RING_TBL_IDX 0x80000UL
7474	__le64 l2_filter_id;
7475	u8 src_macaddr[6];
7476	__be16 ethertype;
7477	u8 ip_addr_type;
7478	#define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL
7479	#define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL
7480	#define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL
7481	#define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6
7482	u8 ip_protocol;
7483	#define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL
7484	#define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL
7485	#define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL
7486	#define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_ICMP 0x1UL
7487	#define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_ICMPV6 0x3aUL
7488	#define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_RSVD 0xffUL
7489	#define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_RSVD
7490	__le16 dst_id;
7491	__le16 mirror_vnic_id;
7492	u8 tunnel_type;
7493	#define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
7494	#define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
7495	#define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
7496	#define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL
7497	#define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL
7498	#define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
7499	#define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL
7500	#define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
7501	#define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
7502	#define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
7503	#define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
7504	#define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
7505	#define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
7506	#define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL
7507	#define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
7508	#define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
7509	u8 pri_hint;
7510	#define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL
7511	#define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE 0x1UL
7512	#define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW 0x2UL
7513	#define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST 0x3UL
7514	#define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 0x4UL
7515	#define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST
7516	__be32 src_ipaddr[4];
7517	__be32 src_ipaddr_mask[4];
7518	__be32 dst_ipaddr[4];
7519	__be32 dst_ipaddr_mask[4];
7520	__be16 src_port;
7521	__be16 src_port_mask;
7522	__be16 dst_port;
7523	__be16 dst_port_mask;
7524	__le64 ntuple_filter_id_hint;
7525	};
7526
7527	/* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */
7528	struct hwrm_cfa_ntuple_filter_alloc_output {
7529	__le16 error_code;
7530	__le16 req_type;
7531	__le16 seq_id;
7532	__le16 resp_len;
7533	__le64 ntuple_filter_id;
7534	__le32 flow_id;
7535	#define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL
7536	#define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0
7537	#define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL
7538	#define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30)
7539	#define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30)
7540	#define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT
7541	#define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL
7542	#define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31)
7543	#define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31)
7544	#define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX
7545	u8 unused_0[3];
7546	u8 valid;
7547	};
7548
7549	/* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */
7550	struct hwrm_cfa_ntuple_filter_alloc_cmd_err {
7551	u8 code;
7552	#define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL
7553	#define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 0x1UL
7554	#define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR
7555	u8 unused_0[7];
7556	};
7557
7558	/* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */
7559	struct hwrm_cfa_ntuple_filter_free_input {
7560	__le16 req_type;
7561	__le16 cmpl_ring;
7562	__le16 seq_id;
7563	__le16 target_id;
7564	__le64 resp_addr;
7565	__le64 ntuple_filter_id;
7566	};
7567
7568	/* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */
7569	struct hwrm_cfa_ntuple_filter_free_output {
7570	__le16 error_code;
7571	__le16 req_type;
7572	__le16 seq_id;
7573	__le16 resp_len;
7574	u8 unused_0[7];
7575	u8 valid;
7576	};
7577
7578	/* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */
7579	struct hwrm_cfa_ntuple_filter_cfg_input {
7580	__le16 req_type;
7581	__le16 cmpl_ring;
7582	__le16 seq_id;
7583	__le16 target_id;
7584	__le64 resp_addr;
7585	__le32 enables;
7586	#define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID 0x1UL
7587	#define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL
7588	#define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_METER_INSTANCE_ID 0x4UL
7589	__le32 flags;
7590	#define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_FID 0x1UL
7591	#define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_RFS_RING_IDX 0x2UL
7592	#define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_NO_L2_CONTEXT 0x4UL
7593	__le64 ntuple_filter_id;
7594	__le32 new_dst_id;
7595	__le32 new_mirror_vnic_id;
7596	__le16 new_meter_instance_id;
7597	#define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 0xffffUL
7598	#define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_LAST CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID
7599	u8 unused_1[6];
7600	};
7601
7602	/* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */
7603	struct hwrm_cfa_ntuple_filter_cfg_output {
7604	__le16 error_code;
7605	__le16 req_type;
7606	__le16 seq_id;
7607	__le16 resp_len;
7608	u8 unused_0[7];
7609	u8 valid;
7610	};
7611
7612	/* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
7613	struct hwrm_cfa_decap_filter_alloc_input {
7614	__le16 req_type;
7615	__le16 cmpl_ring;
7616	__le16 seq_id;
7617	__le16 target_id;
7618	__le64 resp_addr;
7619	__le32 flags;
7620	#define CFA_DECAP_FILTER_ALLOC_REQ_FLAGS_OVS_TUNNEL 0x1UL
7621	__le32 enables;
7622	#define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x1UL
7623	#define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_ID 0x2UL
7624	#define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x4UL
7625	#define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x8UL
7626	#define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_OVLAN_VID 0x10UL
7627	#define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IVLAN_VID 0x20UL
7628	#define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_OVLAN_VID 0x40UL
7629	#define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_IVLAN_VID 0x80UL
7630	#define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x100UL
7631	#define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x200UL
7632	#define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x400UL
7633	#define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x800UL
7634	#define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x1000UL
7635	#define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x2000UL
7636	#define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x4000UL
7637	#define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL
7638	#define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL
7639	__be32 tunnel_id;
7640	u8 tunnel_type;
7641	#define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
7642	#define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
7643	#define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
7644	#define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL
7645	#define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL
7646	#define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
7647	#define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL
7648	#define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
7649	#define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
7650	#define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
7651	#define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
7652	#define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
7653	#define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
7654	#define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL
7655	#define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
7656	#define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
7657	u8 unused_0;
7658	__le16 unused_1;
7659	u8 src_macaddr[6];
7660	u8 unused_2[2];
7661	u8 dst_macaddr[6];
7662	__be16 ovlan_vid;
7663	__be16 ivlan_vid;
7664	__be16 t_ovlan_vid;
7665	__be16 t_ivlan_vid;
7666	__be16 ethertype;
7667	u8 ip_addr_type;
7668	#define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL
7669	#define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL
7670	#define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL
7671	#define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6
7672	u8 ip_protocol;
7673	#define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL
7674	#define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL
7675	#define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL
7676	#define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP
7677	__le16 unused_3;
7678	__le32 unused_4;
7679	__be32 src_ipaddr[4];
7680	__be32 dst_ipaddr[4];
7681	__be16 src_port;
7682	__be16 dst_port;
7683	__le16 dst_id;
7684	__le16 l2_ctxt_ref_id;
7685	};
7686
7687	/* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */
7688	struct hwrm_cfa_decap_filter_alloc_output {
7689	__le16 error_code;
7690	__le16 req_type;
7691	__le16 seq_id;
7692	__le16 resp_len;
7693	__le32 decap_filter_id;
7694	u8 unused_0[3];
7695	u8 valid;
7696	};
7697
7698	/* hwrm_cfa_decap_filter_free_input (size:192b/24B) */
7699	struct hwrm_cfa_decap_filter_free_input {
7700	__le16 req_type;
7701	__le16 cmpl_ring;
7702	__le16 seq_id;
7703	__le16 target_id;
7704	__le64 resp_addr;
7705	__le32 decap_filter_id;
7706	u8 unused_0[4];
7707	};
7708
7709	/* hwrm_cfa_decap_filter_free_output (size:128b/16B) */
7710	struct hwrm_cfa_decap_filter_free_output {
7711	__le16 error_code;
7712	__le16 req_type;
7713	__le16 seq_id;
7714	__le16 resp_len;
7715	u8 unused_0[7];
7716	u8 valid;
7717	};
7718
7719	/* hwrm_cfa_flow_alloc_input (size:1024b/128B) */
7720	struct hwrm_cfa_flow_alloc_input {
7721	__le16 req_type;
7722	__le16 cmpl_ring;
7723	__le16 seq_id;
7724	__le16 target_id;
7725	__le64 resp_addr;
7726	__le16 flags;
7727	#define CFA_FLOW_ALLOC_REQ_FLAGS_TUNNEL 0x1UL
7728	#define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_MASK 0x6UL
7729	#define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_SFT 1
7730	#define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_NONE (0x0UL << 1)
7731	#define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_ONE (0x1UL << 1)
7732	#define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO (0x2UL << 1)
7733	#define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_LAST CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO
7734	#define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_MASK 0x38UL
7735	#define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_SFT 3
7736	#define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_L2 (0x0UL << 3)
7737	#define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV4 (0x1UL << 3)
7738	#define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 (0x2UL << 3)
7739	#define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_LAST CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6
7740	#define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_TX 0x40UL
7741	#define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_RX 0x80UL
7742	#define CFA_FLOW_ALLOC_REQ_FLAGS_MATCH_VXLAN_IP_VNI 0x100UL
7743	#define CFA_FLOW_ALLOC_REQ_FLAGS_VHOST_ID_USE_VLAN 0x200UL
7744	__le16 src_fid;
7745	__le32 tunnel_handle;
7746	__le16 action_flags;
7747	#define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FWD 0x1UL
7748	#define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_RECYCLE 0x2UL
7749	#define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_DROP 0x4UL
7750	#define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_METER 0x8UL
7751	#define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL 0x10UL
7752	#define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_SRC 0x20UL
7753	#define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_DEST 0x40UL
7754	#define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_IPV4_ADDRESS 0x80UL
7755	#define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_L2_HEADER_REWRITE 0x100UL
7756	#define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TTL_DECREMENT 0x200UL
7757	#define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL_IP 0x400UL
7758	#define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FLOW_AGING_ENABLED 0x800UL
7759	#define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_PRI_HINT 0x1000UL
7760	#define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC 0x2000UL
7761	__le16 dst_fid;
7762	__be16 l2_rewrite_vlan_tpid;
7763	__be16 l2_rewrite_vlan_tci;
7764	__le16 act_meter_id;
7765	__le16 ref_flow_handle;
7766	__be16 ethertype;
7767	__be16 outer_vlan_tci;
7768	__be16 dmac[3];
7769	__be16 inner_vlan_tci;
7770	__be16 smac[3];
7771	u8 ip_dst_mask_len;
7772	u8 ip_src_mask_len;
7773	__be32 ip_dst[4];
7774	__be32 ip_src[4];
7775	__be16 l4_src_port;
7776	__be16 l4_src_port_mask;
7777	__be16 l4_dst_port;
7778	__be16 l4_dst_port_mask;
7779	__be32 nat_ip_address[4];
7780	__be16 l2_rewrite_dmac[3];
7781	__be16 nat_port;
7782	__be16 l2_rewrite_smac[3];
7783	u8 ip_proto;
7784	u8 tunnel_type;
7785	#define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
7786	#define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
7787	#define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
7788	#define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL
7789	#define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL
7790	#define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
7791	#define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL
7792	#define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
7793	#define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
7794	#define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
7795	#define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
7796	#define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
7797	#define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
7798	#define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL
7799	#define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
7800	#define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
7801	};
7802
7803	/* hwrm_cfa_flow_alloc_output (size:256b/32B) */
7804	struct hwrm_cfa_flow_alloc_output {
7805	__le16 error_code;
7806	__le16 req_type;
7807	__le16 seq_id;
7808	__le16 resp_len;
7809	__le16 flow_handle;
7810	u8 unused_0[2];
7811	__le32 flow_id;
7812	#define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL
7813	#define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_SFT 0
7814	#define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL
7815	#define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30)
7816	#define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30)
7817	#define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT
7818	#define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL
7819	#define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31)
7820	#define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31)
7821	#define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX
7822	__le64 ext_flow_handle;
7823	__le32 flow_counter_id;
7824	u8 unused_1[3];
7825	u8 valid;
7826	};
7827
7828	/* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */
7829	struct hwrm_cfa_flow_alloc_cmd_err {
7830	u8 code;
7831	#define CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL
7832	#define CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM 0x1UL
7833	#define CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD 0x2UL
7834	#define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER 0x3UL
7835	#define CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM 0x4UL
7836	#define CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION 0x5UL
7837	#define CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS 0x6UL
7838	#define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB 0x7UL
7839	#define CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB
7840	u8 unused_0[7];
7841	};
7842
7843	/* hwrm_cfa_flow_free_input (size:256b/32B) */
7844	struct hwrm_cfa_flow_free_input {
7845	__le16 req_type;
7846	__le16 cmpl_ring;
7847	__le16 seq_id;
7848	__le16 target_id;
7849	__le64 resp_addr;
7850	__le16 flow_handle;
7851	__le16 unused_0;
7852	__le32 flow_counter_id;
7853	__le64 ext_flow_handle;
7854	};
7855
7856	/* hwrm_cfa_flow_free_output (size:256b/32B) */
7857	struct hwrm_cfa_flow_free_output {
7858	__le16 error_code;
7859	__le16 req_type;
7860	__le16 seq_id;
7861	__le16 resp_len;
7862	__le64 packet;
7863	__le64 byte;
7864	u8 unused_0[7];
7865	u8 valid;
7866	};
7867
7868	/* hwrm_cfa_flow_info_input (size:256b/32B) */
7869	struct hwrm_cfa_flow_info_input {
7870	__le16 req_type;
7871	__le16 cmpl_ring;
7872	__le16 seq_id;
7873	__le16 target_id;
7874	__le64 resp_addr;
7875	__le16 flow_handle;
7876	#define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_MASK 0xfffUL
7877	#define CFA_FLOW_INFO_REQ_FLOW_HANDLE_CNP_CNT 0x1000UL
7878	#define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV1_CNT 0x2000UL
7879	#define CFA_FLOW_INFO_REQ_FLOW_HANDLE_NIC_TX 0x3000UL
7880	#define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT 0x4000UL
7881	#define CFA_FLOW_INFO_REQ_FLOW_HANDLE_DIR_RX 0x8000UL
7882	#define CFA_FLOW_INFO_REQ_FLOW_HANDLE_CNP_CNT_RX 0x9000UL
7883	#define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV1_CNT_RX 0xa000UL
7884	#define CFA_FLOW_INFO_REQ_FLOW_HANDLE_NIC_RX 0xb000UL
7885	#define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT_RX 0xc000UL
7886	#define CFA_FLOW_INFO_REQ_FLOW_HANDLE_LAST CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT_RX
7887	u8 unused_0[6];
7888	__le64 ext_flow_handle;
7889	};
7890
7891	/* hwrm_cfa_flow_info_output (size:5632b/704B) */
7892	struct hwrm_cfa_flow_info_output {
7893	__le16 error_code;
7894	__le16 req_type;
7895	__le16 seq_id;
7896	__le16 resp_len;
7897	u8 flags;
7898	#define CFA_FLOW_INFO_RESP_FLAGS_PATH_TX 0x1UL
7899	#define CFA_FLOW_INFO_RESP_FLAGS_PATH_RX 0x2UL
7900	u8 profile;
7901	__le16 src_fid;
7902	__le16 dst_fid;
7903	__le16 l2_ctxt_id;
7904	__le64 em_info;
7905	__le64 tcam_info;
7906	__le64 vfp_tcam_info;
7907	__le16 ar_id;
7908	__le16 flow_handle;
7909	__le32 tunnel_handle;
7910	__le16 flow_timer;
7911	u8 unused_0[6];
7912	__le32 flow_key_data[130];
7913	__le32 flow_action_info[30];
7914	u8 unused_1[7];
7915	u8 valid;
7916	};
7917
7918	/* hwrm_cfa_flow_stats_input (size:640b/80B) */
7919	struct hwrm_cfa_flow_stats_input {
7920	__le16 req_type;
7921	__le16 cmpl_ring;
7922	__le16 seq_id;
7923	__le16 target_id;
7924	__le64 resp_addr;
7925	__le16 num_flows;
7926	__le16 flow_handle_0;
7927	__le16 flow_handle_1;
7928	__le16 flow_handle_2;
7929	__le16 flow_handle_3;
7930	__le16 flow_handle_4;
7931	__le16 flow_handle_5;
7932	__le16 flow_handle_6;
7933	__le16 flow_handle_7;
7934	__le16 flow_handle_8;
7935	__le16 flow_handle_9;
7936	u8 unused_0[2];
7937	__le32 flow_id_0;
7938	__le32 flow_id_1;
7939	__le32 flow_id_2;
7940	__le32 flow_id_3;
7941	__le32 flow_id_4;
7942	__le32 flow_id_5;
7943	__le32 flow_id_6;
7944	__le32 flow_id_7;
7945	__le32 flow_id_8;
7946	__le32 flow_id_9;
7947	};
7948
7949	/* hwrm_cfa_flow_stats_output (size:1408b/176B) */
7950	struct hwrm_cfa_flow_stats_output {
7951	__le16 error_code;
7952	__le16 req_type;
7953	__le16 seq_id;
7954	__le16 resp_len;
7955	__le64 packet_0;
7956	__le64 packet_1;
7957	__le64 packet_2;
7958	__le64 packet_3;
7959	__le64 packet_4;
7960	__le64 packet_5;
7961	__le64 packet_6;
7962	__le64 packet_7;
7963	__le64 packet_8;
7964	__le64 packet_9;
7965	__le64 byte_0;
7966	__le64 byte_1;
7967	__le64 byte_2;
7968	__le64 byte_3;
7969	__le64 byte_4;
7970	__le64 byte_5;
7971	__le64 byte_6;
7972	__le64 byte_7;
7973	__le64 byte_8;
7974	__le64 byte_9;
7975	__le16 flow_hits;
7976	u8 unused_0[5];
7977	u8 valid;
7978	};
7979
7980	/* hwrm_cfa_vfr_alloc_input (size:448b/56B) */
7981	struct hwrm_cfa_vfr_alloc_input {
7982	__le16 req_type;
7983	__le16 cmpl_ring;
7984	__le16 seq_id;
7985	__le16 target_id;
7986	__le64 resp_addr;
7987	__le16 vf_id;
7988	__le16 reserved;
7989	u8 unused_0[4];
7990	char vfr_name[32];
7991	};
7992
7993	/* hwrm_cfa_vfr_alloc_output (size:128b/16B) */
7994	struct hwrm_cfa_vfr_alloc_output {
7995	__le16 error_code;
7996	__le16 req_type;
7997	__le16 seq_id;
7998	__le16 resp_len;
7999	__le16 rx_cfa_code;
8000	__le16 tx_cfa_action;
8001	u8 unused_0[3];
8002	u8 valid;
8003	};
8004
8005	/* hwrm_cfa_vfr_free_input (size:448b/56B) */
8006	struct hwrm_cfa_vfr_free_input {
8007	__le16 req_type;
8008	__le16 cmpl_ring;
8009	__le16 seq_id;
8010	__le16 target_id;
8011	__le64 resp_addr;
8012	char vfr_name[32];
8013	__le16 vf_id;
8014	__le16 reserved;
8015	u8 unused_0[4];
8016	};
8017
8018	/* hwrm_cfa_vfr_free_output (size:128b/16B) */
8019	struct hwrm_cfa_vfr_free_output {
8020	__le16 error_code;
8021	__le16 req_type;
8022	__le16 seq_id;
8023	__le16 resp_len;
8024	u8 unused_0[7];
8025	u8 valid;
8026	};
8027
8028	/* hwrm_cfa_eem_qcaps_input (size:192b/24B) */
8029	struct hwrm_cfa_eem_qcaps_input {
8030	__le16 req_type;
8031	__le16 cmpl_ring;
8032	__le16 seq_id;
8033	__le16 target_id;
8034	__le64 resp_addr;
8035	__le32 flags;
8036	#define CFA_EEM_QCAPS_REQ_FLAGS_PATH_TX 0x1UL
8037	#define CFA_EEM_QCAPS_REQ_FLAGS_PATH_RX 0x2UL
8038	#define CFA_EEM_QCAPS_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL
8039	__le32 unused_0;
8040	};
8041
8042	/* hwrm_cfa_eem_qcaps_output (size:320b/40B) */
8043	struct hwrm_cfa_eem_qcaps_output {
8044	__le16 error_code;
8045	__le16 req_type;
8046	__le16 seq_id;
8047	__le16 resp_len;
8048	__le32 flags;
8049	#define CFA_EEM_QCAPS_RESP_FLAGS_PATH_TX 0x1UL
8050	#define CFA_EEM_QCAPS_RESP_FLAGS_PATH_RX 0x2UL
8051	#define CFA_EEM_QCAPS_RESP_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED 0x4UL
8052	#define CFA_EEM_QCAPS_RESP_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED 0x8UL
8053	__le32 unused_0;
8054	__le32 supported;
8055	#define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY0_TABLE 0x1UL
8056	#define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY1_TABLE 0x2UL
8057	#define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_RECORD_TABLE 0x4UL
8058	#define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE 0x8UL
8059	#define CFA_EEM_QCAPS_RESP_SUPPORTED_FID_TABLE 0x10UL
8060	__le32 max_entries_supported;
8061	__le16 key_entry_size;
8062	__le16 record_entry_size;
8063	__le16 efc_entry_size;
8064	__le16 fid_entry_size;
8065	u8 unused_1[7];
8066	u8 valid;
8067	};
8068
8069	/* hwrm_cfa_eem_cfg_input (size:384b/48B) */
8070	struct hwrm_cfa_eem_cfg_input {
8071	__le16 req_type;
8072	__le16 cmpl_ring;
8073	__le16 seq_id;
8074	__le16 target_id;
8075	__le64 resp_addr;
8076	__le32 flags;
8077	#define CFA_EEM_CFG_REQ_FLAGS_PATH_TX 0x1UL
8078	#define CFA_EEM_CFG_REQ_FLAGS_PATH_RX 0x2UL
8079	#define CFA_EEM_CFG_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL
8080	#define CFA_EEM_CFG_REQ_FLAGS_SECONDARY_PF 0x8UL
8081	__le16 group_id;
8082	__le16 unused_0;
8083	__le32 num_entries;
8084	__le32 unused_1;
8085	__le16 key0_ctx_id;
8086	__le16 key1_ctx_id;
8087	__le16 record_ctx_id;
8088	__le16 efc_ctx_id;
8089	__le16 fid_ctx_id;
8090	__le16 unused_2;
8091	__le32 unused_3;
8092	};
8093
8094	/* hwrm_cfa_eem_cfg_output (size:128b/16B) */
8095	struct hwrm_cfa_eem_cfg_output {
8096	__le16 error_code;
8097	__le16 req_type;
8098	__le16 seq_id;
8099	__le16 resp_len;
8100	u8 unused_0[7];
8101	u8 valid;
8102	};
8103
8104	/* hwrm_cfa_eem_qcfg_input (size:192b/24B) */
8105	struct hwrm_cfa_eem_qcfg_input {
8106	__le16 req_type;
8107	__le16 cmpl_ring;
8108	__le16 seq_id;
8109	__le16 target_id;
8110	__le64 resp_addr;
8111	__le32 flags;
8112	#define CFA_EEM_QCFG_REQ_FLAGS_PATH_TX 0x1UL
8113	#define CFA_EEM_QCFG_REQ_FLAGS_PATH_RX 0x2UL
8114	__le32 unused_0;
8115	};
8116
8117	/* hwrm_cfa_eem_qcfg_output (size:256b/32B) */
8118	struct hwrm_cfa_eem_qcfg_output {
8119	__le16 error_code;
8120	__le16 req_type;
8121	__le16 seq_id;
8122	__le16 resp_len;
8123	__le32 flags;
8124	#define CFA_EEM_QCFG_RESP_FLAGS_PATH_TX 0x1UL
8125	#define CFA_EEM_QCFG_RESP_FLAGS_PATH_RX 0x2UL
8126	#define CFA_EEM_QCFG_RESP_FLAGS_PREFERRED_OFFLOAD 0x4UL
8127	__le32 num_entries;
8128	__le16 key0_ctx_id;
8129	__le16 key1_ctx_id;
8130	__le16 record_ctx_id;
8131	__le16 efc_ctx_id;
8132	__le16 fid_ctx_id;
8133	u8 unused_2[5];
8134	u8 valid;
8135	};
8136
8137	/* hwrm_cfa_eem_op_input (size:192b/24B) */
8138	struct hwrm_cfa_eem_op_input {
8139	__le16 req_type;
8140	__le16 cmpl_ring;
8141	__le16 seq_id;
8142	__le16 target_id;
8143	__le64 resp_addr;
8144	__le32 flags;
8145	#define CFA_EEM_OP_REQ_FLAGS_PATH_TX 0x1UL
8146	#define CFA_EEM_OP_REQ_FLAGS_PATH_RX 0x2UL
8147	__le16 unused_0;
8148	__le16 op;
8149	#define CFA_EEM_OP_REQ_OP_RESERVED 0x0UL
8150	#define CFA_EEM_OP_REQ_OP_EEM_DISABLE 0x1UL
8151	#define CFA_EEM_OP_REQ_OP_EEM_ENABLE 0x2UL
8152	#define CFA_EEM_OP_REQ_OP_EEM_CLEANUP 0x3UL
8153	#define CFA_EEM_OP_REQ_OP_LAST CFA_EEM_OP_REQ_OP_EEM_CLEANUP
8154	};
8155
8156	/* hwrm_cfa_eem_op_output (size:128b/16B) */
8157	struct hwrm_cfa_eem_op_output {
8158	__le16 error_code;
8159	__le16 req_type;
8160	__le16 seq_id;
8161	__le16 resp_len;
8162	u8 unused_0[7];
8163	u8 valid;
8164	};
8165
8166	/* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */
8167	struct hwrm_cfa_adv_flow_mgnt_qcaps_input {
8168	__le16 req_type;
8169	__le16 cmpl_ring;
8170	__le16 seq_id;
8171	__le16 target_id;
8172	__le64 resp_addr;
8173	__le32 unused_0[4];
8174	};
8175
8176	/* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */
8177	struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
8178	__le16 error_code;
8179	__le16 req_type;
8180	__le16 seq_id;
8181	__le16 resp_len;
8182	__le32 flags;
8183	#define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_16BIT_SUPPORTED 0x1UL
8184	#define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_64BIT_SUPPORTED 0x2UL
8185	#define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_BATCH_DELETE_SUPPORTED 0x4UL
8186	#define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_RESET_ALL_SUPPORTED 0x8UL
8187	#define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED 0x10UL
8188	#define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_TX_EEM_FLOW_SUPPORTED 0x20UL
8189	#define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RX_EEM_FLOW_SUPPORTED 0x40UL
8190	#define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED 0x80UL
8191	#define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_SUPPORTED 0x100UL
8192	#define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_UNTAGGED_VLAN_SUPPORTED 0x200UL
8193	#define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_XDP_SUPPORTED 0x400UL
8194	#define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED 0x800UL
8195	#define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED 0x1000UL
8196	#define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED 0x2000UL
8197	#define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED 0x4000UL
8198	#define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_TRUFLOW_CAPABLE 0x8000UL
8199	#define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_L2_FILTER_TRAFFIC_TYPE_L2_ROCE_SUPPORTED 0x10000UL
8200	#define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_LAG_SUPPORTED 0x20000UL
8201	#define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_NO_L2CTX_SUPPORTED 0x40000UL
8202	#define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NIC_FLOW_STATS_SUPPORTED 0x80000UL
8203	#define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_EXT_IP_PROTO_SUPPORTED 0x100000UL
8204	u8 unused_0[3];
8205	u8 valid;
8206	};
8207
8208	/* hwrm_tunnel_dst_port_query_input (size:192b/24B) */
8209	struct hwrm_tunnel_dst_port_query_input {
8210	__le16 req_type;
8211	__le16 cmpl_ring;
8212	__le16 seq_id;
8213	__le16 target_id;
8214	__le64 resp_addr;
8215	u8 tunnel_type;
8216	#define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN 0x1UL
8217	#define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE 0x5UL
8218	#define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
8219	#define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
8220	#define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
8221	#define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
8222	#define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_CUSTOM_GRE 0xdUL
8223	#define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ECPRI 0xeUL
8224	#define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_SRV6 0xfUL
8225	#define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL
8226	#define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE
8227	u8 tunnel_next_proto;
8228	u8 unused_0[6];
8229	};
8230
8231	/* hwrm_tunnel_dst_port_query_output (size:128b/16B) */
8232	struct hwrm_tunnel_dst_port_query_output {
8233	__le16 error_code;
8234	__le16 req_type;
8235	__le16 seq_id;
8236	__le16 resp_len;
8237	__le16 tunnel_dst_port_id;
8238	__be16 tunnel_dst_port_val;
8239	u8 upar_in_use;
8240	#define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR0 0x1UL
8241	#define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR1 0x2UL
8242	#define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR2 0x4UL
8243	#define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR3 0x8UL
8244	#define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR4 0x10UL
8245	#define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR5 0x20UL
8246	#define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR6 0x40UL
8247	#define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR7 0x80UL
8248	u8 unused_0[2];
8249	u8 valid;
8250	};
8251
8252	/* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */
8253	struct hwrm_tunnel_dst_port_alloc_input {
8254	__le16 req_type;
8255	__le16 cmpl_ring;
8256	__le16 seq_id;
8257	__le16 target_id;
8258	__le64 resp_addr;
8259	u8 tunnel_type;
8260	#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
8261	#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
8262	#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
8263	#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
8264	#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
8265	#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
8266	#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_CUSTOM_GRE 0xdUL
8267	#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ECPRI 0xeUL
8268	#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_SRV6 0xfUL
8269	#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL
8270	#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE
8271	u8 tunnel_next_proto;
8272	__be16 tunnel_dst_port_val;
8273	u8 unused_0[4];
8274	};
8275
8276	/* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */
8277	struct hwrm_tunnel_dst_port_alloc_output {
8278	__le16 error_code;
8279	__le16 req_type;
8280	__le16 seq_id;
8281	__le16 resp_len;
8282	__le16 tunnel_dst_port_id;
8283	u8 error_info;
8284	#define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_SUCCESS 0x0UL
8285	#define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_ERR_ALLOCATED 0x1UL
8286	#define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_ERR_NO_RESOURCE 0x2UL
8287	#define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_LAST TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_ERR_NO_RESOURCE
8288	u8 upar_in_use;
8289	#define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR0 0x1UL
8290	#define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR1 0x2UL
8291	#define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR2 0x4UL
8292	#define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR3 0x8UL
8293	#define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR4 0x10UL
8294	#define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR5 0x20UL
8295	#define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR6 0x40UL
8296	#define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR7 0x80UL
8297	u8 unused_0[3];
8298	u8 valid;
8299	};
8300
8301	/* hwrm_tunnel_dst_port_free_input (size:192b/24B) */
8302	struct hwrm_tunnel_dst_port_free_input {
8303	__le16 req_type;
8304	__le16 cmpl_ring;
8305	__le16 seq_id;
8306	__le16 target_id;
8307	__le64 resp_addr;
8308	u8 tunnel_type;
8309	#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN 0x1UL
8310	#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE 0x5UL
8311	#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
8312	#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
8313	#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
8314	#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
8315	#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_CUSTOM_GRE 0xdUL
8316	#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ECPRI 0xeUL
8317	#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_SRV6 0xfUL
8318	#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL
8319	#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE
8320	u8 tunnel_next_proto;
8321	__le16 tunnel_dst_port_id;
8322	u8 unused_0[4];
8323	};
8324
8325	/* hwrm_tunnel_dst_port_free_output (size:128b/16B) */
8326	struct hwrm_tunnel_dst_port_free_output {
8327	__le16 error_code;
8328	__le16 req_type;
8329	__le16 seq_id;
8330	__le16 resp_len;
8331	u8 error_info;
8332	#define TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_SUCCESS 0x0UL
8333	#define TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_ERR_NOT_OWNER 0x1UL
8334	#define TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_ERR_NOT_ALLOCATED 0x2UL
8335	#define TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_LAST TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_ERR_NOT_ALLOCATED
8336	u8 unused_1[6];
8337	u8 valid;
8338	};
8339
8340	/* ctx_hw_stats (size:1280b/160B) */
8341	struct ctx_hw_stats {
8342	__le64 rx_ucast_pkts;
8343	__le64 rx_mcast_pkts;
8344	__le64 rx_bcast_pkts;
8345	__le64 rx_discard_pkts;
8346	__le64 rx_error_pkts;
8347	__le64 rx_ucast_bytes;
8348	__le64 rx_mcast_bytes;
8349	__le64 rx_bcast_bytes;
8350	__le64 tx_ucast_pkts;
8351	__le64 tx_mcast_pkts;
8352	__le64 tx_bcast_pkts;
8353	__le64 tx_error_pkts;
8354	__le64 tx_discard_pkts;
8355	__le64 tx_ucast_bytes;
8356	__le64 tx_mcast_bytes;
8357	__le64 tx_bcast_bytes;
8358	__le64 tpa_pkts;
8359	__le64 tpa_bytes;
8360	__le64 tpa_events;
8361	__le64 tpa_aborts;
8362	};
8363
8364	/* ctx_hw_stats_ext (size:1408b/176B) */
8365	struct ctx_hw_stats_ext {
8366	__le64 rx_ucast_pkts;
8367	__le64 rx_mcast_pkts;
8368	__le64 rx_bcast_pkts;
8369	__le64 rx_discard_pkts;
8370	__le64 rx_error_pkts;
8371	__le64 rx_ucast_bytes;
8372	__le64 rx_mcast_bytes;
8373	__le64 rx_bcast_bytes;
8374	__le64 tx_ucast_pkts;
8375	__le64 tx_mcast_pkts;
8376	__le64 tx_bcast_pkts;
8377	__le64 tx_error_pkts;
8378	__le64 tx_discard_pkts;
8379	__le64 tx_ucast_bytes;
8380	__le64 tx_mcast_bytes;
8381	__le64 tx_bcast_bytes;
8382	__le64 rx_tpa_eligible_pkt;
8383	__le64 rx_tpa_eligible_bytes;
8384	__le64 rx_tpa_pkt;
8385	__le64 rx_tpa_bytes;
8386	__le64 rx_tpa_errors;
8387	__le64 rx_tpa_events;
8388	};
8389
8390	/* hwrm_stat_ctx_alloc_input (size:320b/40B) */
8391	struct hwrm_stat_ctx_alloc_input {
8392	__le16 req_type;
8393	__le16 cmpl_ring;
8394	__le16 seq_id;
8395	__le16 target_id;
8396	__le64 resp_addr;
8397	__le64 stats_dma_addr;
8398	__le32 update_period_ms;
8399	u8 stat_ctx_flags;
8400	#define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE 0x1UL
8401	u8 unused_0;
8402	__le16 stats_dma_length;
8403	__le16 flags;
8404	#define STAT_CTX_ALLOC_REQ_FLAGS_STEERING_TAG_VALID 0x1UL
8405	__le16 steering_tag;
8406	__le32 unused_1;
8407	};
8408
8409	/* hwrm_stat_ctx_alloc_output (size:128b/16B) */
8410	struct hwrm_stat_ctx_alloc_output {
8411	__le16 error_code;
8412	__le16 req_type;
8413	__le16 seq_id;
8414	__le16 resp_len;
8415	__le32 stat_ctx_id;
8416	u8 unused_0[3];
8417	u8 valid;
8418	};
8419
8420	/* hwrm_stat_ctx_free_input (size:192b/24B) */
8421	struct hwrm_stat_ctx_free_input {
8422	__le16 req_type;
8423	__le16 cmpl_ring;
8424	__le16 seq_id;
8425	__le16 target_id;
8426	__le64 resp_addr;
8427	__le32 stat_ctx_id;
8428	u8 unused_0[4];
8429	};
8430
8431	/* hwrm_stat_ctx_free_output (size:128b/16B) */
8432	struct hwrm_stat_ctx_free_output {
8433	__le16 error_code;
8434	__le16 req_type;
8435	__le16 seq_id;
8436	__le16 resp_len;
8437	__le32 stat_ctx_id;
8438	u8 unused_0[3];
8439	u8 valid;
8440	};
8441
8442	/* hwrm_stat_ctx_query_input (size:192b/24B) */
8443	struct hwrm_stat_ctx_query_input {
8444	__le16 req_type;
8445	__le16 cmpl_ring;
8446	__le16 seq_id;
8447	__le16 target_id;
8448	__le64 resp_addr;
8449	__le32 stat_ctx_id;
8450	u8 flags;
8451	#define STAT_CTX_QUERY_REQ_FLAGS_COUNTER_MASK 0x1UL
8452	u8 unused_0[3];
8453	};
8454
8455	/* hwrm_stat_ctx_query_output (size:1408b/176B) */
8456	struct hwrm_stat_ctx_query_output {
8457	__le16 error_code;
8458	__le16 req_type;
8459	__le16 seq_id;
8460	__le16 resp_len;
8461	__le64 tx_ucast_pkts;
8462	__le64 tx_mcast_pkts;
8463	__le64 tx_bcast_pkts;
8464	__le64 tx_discard_pkts;
8465	__le64 tx_error_pkts;
8466	__le64 tx_ucast_bytes;
8467	__le64 tx_mcast_bytes;
8468	__le64 tx_bcast_bytes;
8469	__le64 rx_ucast_pkts;
8470	__le64 rx_mcast_pkts;
8471	__le64 rx_bcast_pkts;
8472	__le64 rx_discard_pkts;
8473	__le64 rx_error_pkts;
8474	__le64 rx_ucast_bytes;
8475	__le64 rx_mcast_bytes;
8476	__le64 rx_bcast_bytes;
8477	__le64 rx_agg_pkts;
8478	__le64 rx_agg_bytes;
8479	__le64 rx_agg_events;
8480	__le64 rx_agg_aborts;
8481	u8 unused_0[7];
8482	u8 valid;
8483	};
8484
8485	/* hwrm_stat_ext_ctx_query_input (size:192b/24B) */
8486	struct hwrm_stat_ext_ctx_query_input {
8487	__le16 req_type;
8488	__le16 cmpl_ring;
8489	__le16 seq_id;
8490	__le16 target_id;
8491	__le64 resp_addr;
8492	__le32 stat_ctx_id;
8493	u8 flags;
8494	#define STAT_EXT_CTX_QUERY_REQ_FLAGS_COUNTER_MASK 0x1UL
8495	u8 unused_0[3];
8496	};
8497
8498	/* hwrm_stat_ext_ctx_query_output (size:1536b/192B) */
8499	struct hwrm_stat_ext_ctx_query_output {
8500	__le16 error_code;
8501	__le16 req_type;
8502	__le16 seq_id;
8503	__le16 resp_len;
8504	__le64 rx_ucast_pkts;
8505	__le64 rx_mcast_pkts;
8506	__le64 rx_bcast_pkts;
8507	__le64 rx_discard_pkts;
8508	__le64 rx_error_pkts;
8509	__le64 rx_ucast_bytes;
8510	__le64 rx_mcast_bytes;
8511	__le64 rx_bcast_bytes;
8512	__le64 tx_ucast_pkts;
8513	__le64 tx_mcast_pkts;
8514	__le64 tx_bcast_pkts;
8515	__le64 tx_error_pkts;
8516	__le64 tx_discard_pkts;
8517	__le64 tx_ucast_bytes;
8518	__le64 tx_mcast_bytes;
8519	__le64 tx_bcast_bytes;
8520	__le64 rx_tpa_eligible_pkt;
8521	__le64 rx_tpa_eligible_bytes;
8522	__le64 rx_tpa_pkt;
8523	__le64 rx_tpa_bytes;
8524	__le64 rx_tpa_errors;
8525	__le64 rx_tpa_events;
8526	u8 unused_0[7];
8527	u8 valid;
8528	};
8529
8530	/* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */
8531	struct hwrm_stat_ctx_clr_stats_input {
8532	__le16 req_type;
8533	__le16 cmpl_ring;
8534	__le16 seq_id;
8535	__le16 target_id;
8536	__le64 resp_addr;
8537	__le32 stat_ctx_id;
8538	u8 unused_0[4];
8539	};
8540
8541	/* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */
8542	struct hwrm_stat_ctx_clr_stats_output {
8543	__le16 error_code;
8544	__le16 req_type;
8545	__le16 seq_id;
8546	__le16 resp_len;
8547	u8 unused_0[7];
8548	u8 valid;
8549	};
8550
8551	/* hwrm_pcie_qstats_input (size:256b/32B) */
8552	struct hwrm_pcie_qstats_input {
8553	__le16 req_type;
8554	__le16 cmpl_ring;
8555	__le16 seq_id;
8556	__le16 target_id;
8557	__le64 resp_addr;
8558	__le16 pcie_stat_size;
8559	u8 unused_0[6];
8560	__le64 pcie_stat_host_addr;
8561	};
8562
8563	/* hwrm_pcie_qstats_output (size:128b/16B) */
8564	struct hwrm_pcie_qstats_output {
8565	__le16 error_code;
8566	__le16 req_type;
8567	__le16 seq_id;
8568	__le16 resp_len;
8569	__le16 pcie_stat_size;
8570	u8 unused_0[5];
8571	u8 valid;
8572	};
8573
8574	/* pcie_ctx_hw_stats (size:768b/96B) */
8575	struct pcie_ctx_hw_stats {
8576	__le64 pcie_pl_signal_integrity;
8577	__le64 pcie_dl_signal_integrity;
8578	__le64 pcie_tl_signal_integrity;
8579	__le64 pcie_link_integrity;
8580	__le64 pcie_tx_traffic_rate;
8581	__le64 pcie_rx_traffic_rate;
8582	__le64 pcie_tx_dllp_statistics;
8583	__le64 pcie_rx_dllp_statistics;
8584	__le64 pcie_equalization_time;
8585	__le32 pcie_ltssm_histogram[4];
8586	__le64 pcie_recovery_histogram;
8587	};
8588
8589	/* hwrm_stat_generic_qstats_input (size:256b/32B) */
8590	struct hwrm_stat_generic_qstats_input {
8591	__le16 req_type;
8592	__le16 cmpl_ring;
8593	__le16 seq_id;
8594	__le16 target_id;
8595	__le64 resp_addr;
8596	__le16 generic_stat_size;
8597	u8 flags;
8598	#define STAT_GENERIC_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL
8599	u8 unused_0[5];
8600	__le64 generic_stat_host_addr;
8601	};
8602
8603	/* hwrm_stat_generic_qstats_output (size:128b/16B) */
8604	struct hwrm_stat_generic_qstats_output {
8605	__le16 error_code;
8606	__le16 req_type;
8607	__le16 seq_id;
8608	__le16 resp_len;
8609	__le16 generic_stat_size;
8610	u8 unused_0[5];
8611	u8 valid;
8612	};
8613
8614	/* generic_sw_hw_stats (size:1408b/176B) */
8615	struct generic_sw_hw_stats {
8616	__le64 pcie_statistics_tx_tlp;
8617	__le64 pcie_statistics_rx_tlp;
8618	__le64 pcie_credit_fc_hdr_posted;
8619	__le64 pcie_credit_fc_hdr_nonposted;
8620	__le64 pcie_credit_fc_hdr_cmpl;
8621	__le64 pcie_credit_fc_data_posted;
8622	__le64 pcie_credit_fc_data_nonposted;
8623	__le64 pcie_credit_fc_data_cmpl;
8624	__le64 pcie_credit_fc_tgt_nonposted;
8625	__le64 pcie_credit_fc_tgt_data_posted;
8626	__le64 pcie_credit_fc_tgt_hdr_posted;
8627	__le64 pcie_credit_fc_cmpl_hdr_posted;
8628	__le64 pcie_credit_fc_cmpl_data_posted;
8629	__le64 pcie_cmpl_longest;
8630	__le64 pcie_cmpl_shortest;
8631	__le64 cache_miss_count_cfcq;
8632	__le64 cache_miss_count_cfcs;
8633	__le64 cache_miss_count_cfcc;
8634	__le64 cache_miss_count_cfcm;
8635	__le64 hw_db_recov_dbs_dropped;
8636	__le64 hw_db_recov_drops_serviced;
8637	__le64 hw_db_recov_dbs_recovered;
8638	};
8639
8640	/* hwrm_fw_reset_input (size:192b/24B) */
8641	struct hwrm_fw_reset_input {
8642	__le16 req_type;
8643	__le16 cmpl_ring;
8644	__le16 seq_id;
8645	__le16 target_id;
8646	__le64 resp_addr;
8647	u8 embedded_proc_type;
8648	#define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL
8649	#define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL
8650	#define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL
8651	#define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL
8652	#define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL
8653	#define FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL
8654	#define FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL
8655	#define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT 0x7UL
8656	#define FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION 0x8UL
8657	#define FW_RESET_REQ_EMBEDDED_PROC_TYPE_LAST FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION
8658	u8 selfrst_status;
8659	#define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE 0x0UL
8660	#define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP 0x1UL
8661	#define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST 0x2UL
8662	#define FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL
8663	#define FW_RESET_REQ_SELFRST_STATUS_LAST FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE
8664	u8 host_idx;
8665	u8 flags;
8666	#define FW_RESET_REQ_FLAGS_RESET_GRACEFUL 0x1UL
8667	#define FW_RESET_REQ_FLAGS_FW_ACTIVATION 0x2UL
8668	u8 unused_0[4];
8669	};
8670
8671	/* hwrm_fw_reset_output (size:128b/16B) */
8672	struct hwrm_fw_reset_output {
8673	__le16 error_code;
8674	__le16 req_type;
8675	__le16 seq_id;
8676	__le16 resp_len;
8677	u8 selfrst_status;
8678	#define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL
8679	#define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL
8680	#define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL
8681	#define FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL
8682	#define FW_RESET_RESP_SELFRST_STATUS_LAST FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE
8683	u8 unused_0[6];
8684	u8 valid;
8685	};
8686
8687	/* hwrm_fw_qstatus_input (size:192b/24B) */
8688	struct hwrm_fw_qstatus_input {
8689	__le16 req_type;
8690	__le16 cmpl_ring;
8691	__le16 seq_id;
8692	__le16 target_id;
8693	__le64 resp_addr;
8694	u8 embedded_proc_type;
8695	#define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL
8696	#define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL
8697	#define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL
8698	#define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL
8699	#define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL
8700	#define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL
8701	#define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL
8702	#define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_LAST FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP
8703	u8 unused_0[7];
8704	};
8705
8706	/* hwrm_fw_qstatus_output (size:128b/16B) */
8707	struct hwrm_fw_qstatus_output {
8708	__le16 error_code;
8709	__le16 req_type;
8710	__le16 seq_id;
8711	__le16 resp_len;
8712	u8 selfrst_status;
8713	#define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL
8714	#define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL
8715	#define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL
8716	#define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER 0x3UL
8717	#define FW_QSTATUS_RESP_SELFRST_STATUS_LAST FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER
8718	u8 nvm_option_action_status;
8719	#define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_NONE 0x0UL
8720	#define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_HOTRESET 0x1UL
8721	#define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_WARMBOOT 0x2UL
8722	#define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_COLDBOOT 0x3UL
8723	#define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_LAST FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_COLDBOOT
8724	u8 unused_0[5];
8725	u8 valid;
8726	};
8727
8728	/* hwrm_fw_set_time_input (size:256b/32B) */
8729	struct hwrm_fw_set_time_input {
8730	__le16 req_type;
8731	__le16 cmpl_ring;
8732	__le16 seq_id;
8733	__le16 target_id;
8734	__le64 resp_addr;
8735	__le16 year;
8736	#define FW_SET_TIME_REQ_YEAR_UNKNOWN 0x0UL
8737	#define FW_SET_TIME_REQ_YEAR_LAST FW_SET_TIME_REQ_YEAR_UNKNOWN
8738	u8 month;
8739	u8 day;
8740	u8 hour;
8741	u8 minute;
8742	u8 second;
8743	u8 unused_0;
8744	__le16 millisecond;
8745	__le16 zone;
8746	#define FW_SET_TIME_REQ_ZONE_UTC 0
8747	#define FW_SET_TIME_REQ_ZONE_UNKNOWN 65535
8748	#define FW_SET_TIME_REQ_ZONE_LAST FW_SET_TIME_REQ_ZONE_UNKNOWN
8749	u8 unused_1[4];
8750	};
8751
8752	/* hwrm_fw_set_time_output (size:128b/16B) */
8753	struct hwrm_fw_set_time_output {
8754	__le16 error_code;
8755	__le16 req_type;
8756	__le16 seq_id;
8757	__le16 resp_len;
8758	u8 unused_0[7];
8759	u8 valid;
8760	};
8761
8762	/* hwrm_struct_hdr (size:128b/16B) */
8763	struct hwrm_struct_hdr {
8764	__le16 struct_id;
8765	#define STRUCT_HDR_STRUCT_ID_LLDP_CFG 0x41bUL
8766	#define STRUCT_HDR_STRUCT_ID_DCBX_ETS 0x41dUL
8767	#define STRUCT_HDR_STRUCT_ID_DCBX_PFC 0x41fUL
8768	#define STRUCT_HDR_STRUCT_ID_DCBX_APP 0x421UL
8769	#define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL
8770	#define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC 0x424UL
8771	#define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE 0x426UL
8772	#define STRUCT_HDR_STRUCT_ID_POWER_BKUP 0x427UL
8773	#define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE 0x1UL
8774	#define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION 0xaUL
8775	#define STRUCT_HDR_STRUCT_ID_RSS_V2 0x64UL
8776	#define STRUCT_HDR_STRUCT_ID_MSIX_PER_VF 0xc8UL
8777	#define STRUCT_HDR_STRUCT_ID_LAST STRUCT_HDR_STRUCT_ID_MSIX_PER_VF
8778	__le16 len;
8779	u8 version;
8780	u8 count;
8781	__le16 subtype;
8782	__le16 next_offset;
8783	#define STRUCT_HDR_NEXT_OFFSET_LAST 0x0UL
8784	u8 unused_0[6];
8785	};
8786
8787	/* hwrm_struct_data_dcbx_app (size:64b/8B) */
8788	struct hwrm_struct_data_dcbx_app {
8789	__be16 protocol_id;
8790	u8 protocol_selector;
8791	#define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE 0x1UL
8792	#define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT 0x2UL
8793	#define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT 0x3UL
8794	#define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 0x4UL
8795	#define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_LAST STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT
8796	u8 priority;
8797	u8 valid;
8798	u8 unused_0[3];
8799	};
8800
8801	/* hwrm_fw_set_structured_data_input (size:256b/32B) */
8802	struct hwrm_fw_set_structured_data_input {
8803	__le16 req_type;
8804	__le16 cmpl_ring;
8805	__le16 seq_id;
8806	__le16 target_id;
8807	__le64 resp_addr;
8808	__le64 src_data_addr;
8809	__le16 data_len;
8810	u8 hdr_cnt;
8811	u8 unused_0[5];
8812	};
8813
8814	/* hwrm_fw_set_structured_data_output (size:128b/16B) */
8815	struct hwrm_fw_set_structured_data_output {
8816	__le16 error_code;
8817	__le16 req_type;
8818	__le16 seq_id;
8819	__le16 resp_len;
8820	u8 unused_0[7];
8821	u8 valid;
8822	};
8823
8824	/* hwrm_fw_set_structured_data_cmd_err (size:64b/8B) */
8825	struct hwrm_fw_set_structured_data_cmd_err {
8826	u8 code;
8827	#define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL
8828	#define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_HDR_CNT 0x1UL
8829	#define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_FMT 0x2UL
8830	#define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL
8831	#define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID
8832	u8 unused_0[7];
8833	};
8834
8835	/* hwrm_fw_get_structured_data_input (size:256b/32B) */
8836	struct hwrm_fw_get_structured_data_input {
8837	__le16 req_type;
8838	__le16 cmpl_ring;
8839	__le16 seq_id;
8840	__le16 target_id;
8841	__le64 resp_addr;
8842	__le64 dest_data_addr;
8843	__le16 data_len;
8844	__le16 structure_id;
8845	__le16 subtype;
8846	#define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_UNUSED 0x0UL
8847	#define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_ALL 0xffffUL
8848	#define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_ADMIN 0x100UL
8849	#define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_PEER 0x101UL
8850	#define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_OPERATIONAL 0x102UL
8851	#define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_ADMIN 0x200UL
8852	#define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_PEER 0x201UL
8853	#define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_OPERATIONAL 0x202UL
8854	#define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 0x300UL
8855	#define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_LAST FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL
8856	u8 count;
8857	u8 unused_0;
8858	};
8859
8860	/* hwrm_fw_get_structured_data_output (size:128b/16B) */
8861	struct hwrm_fw_get_structured_data_output {
8862	__le16 error_code;
8863	__le16 req_type;
8864	__le16 seq_id;
8865	__le16 resp_len;
8866	u8 hdr_cnt;
8867	u8 unused_0[6];
8868	u8 valid;
8869	};
8870
8871	/* hwrm_fw_get_structured_data_cmd_err (size:64b/8B) */
8872	struct hwrm_fw_get_structured_data_cmd_err {
8873	u8 code;
8874	#define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL
8875	#define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL
8876	#define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID
8877	u8 unused_0[7];
8878	};
8879
8880	/* hwrm_fw_livepatch_query_input (size:192b/24B) */
8881	struct hwrm_fw_livepatch_query_input {
8882	__le16 req_type;
8883	__le16 cmpl_ring;
8884	__le16 seq_id;
8885	__le16 target_id;
8886	__le64 resp_addr;
8887	u8 fw_target;
8888	#define FW_LIVEPATCH_QUERY_REQ_FW_TARGET_COMMON_FW 0x1UL
8889	#define FW_LIVEPATCH_QUERY_REQ_FW_TARGET_SECURE_FW 0x2UL
8890	#define FW_LIVEPATCH_QUERY_REQ_FW_TARGET_LAST FW_LIVEPATCH_QUERY_REQ_FW_TARGET_SECURE_FW
8891	u8 unused_0[7];
8892	};
8893
8894	/* hwrm_fw_livepatch_query_output (size:640b/80B) */
8895	struct hwrm_fw_livepatch_query_output {
8896	__le16 error_code;
8897	__le16 req_type;
8898	__le16 seq_id;
8899	__le16 resp_len;
8900	char install_ver[32];
8901	char active_ver[32];
8902	__le16 status_flags;
8903	#define FW_LIVEPATCH_QUERY_RESP_STATUS_FLAGS_INSTALL 0x1UL
8904	#define FW_LIVEPATCH_QUERY_RESP_STATUS_FLAGS_ACTIVE 0x2UL
8905	u8 unused_0[5];
8906	u8 valid;
8907	};
8908
8909	/* hwrm_fw_livepatch_input (size:256b/32B) */
8910	struct hwrm_fw_livepatch_input {
8911	__le16 req_type;
8912	__le16 cmpl_ring;
8913	__le16 seq_id;
8914	__le16 target_id;
8915	__le64 resp_addr;
8916	u8 opcode;
8917	#define FW_LIVEPATCH_REQ_OPCODE_ACTIVATE 0x1UL
8918	#define FW_LIVEPATCH_REQ_OPCODE_DEACTIVATE 0x2UL
8919	#define FW_LIVEPATCH_REQ_OPCODE_LAST FW_LIVEPATCH_REQ_OPCODE_DEACTIVATE
8920	u8 fw_target;
8921	#define FW_LIVEPATCH_REQ_FW_TARGET_COMMON_FW 0x1UL
8922	#define FW_LIVEPATCH_REQ_FW_TARGET_SECURE_FW 0x2UL
8923	#define FW_LIVEPATCH_REQ_FW_TARGET_LAST FW_LIVEPATCH_REQ_FW_TARGET_SECURE_FW
8924	u8 loadtype;
8925	#define FW_LIVEPATCH_REQ_LOADTYPE_NVM_INSTALL 0x1UL
8926	#define FW_LIVEPATCH_REQ_LOADTYPE_MEMORY_DIRECT 0x2UL
8927	#define FW_LIVEPATCH_REQ_LOADTYPE_LAST FW_LIVEPATCH_REQ_LOADTYPE_MEMORY_DIRECT
8928	u8 flags;
8929	__le32 patch_len;
8930	__le64 host_addr;
8931	};
8932
8933	/* hwrm_fw_livepatch_output (size:128b/16B) */
8934	struct hwrm_fw_livepatch_output {
8935	__le16 error_code;
8936	__le16 req_type;
8937	__le16 seq_id;
8938	__le16 resp_len;
8939	u8 unused_0[7];
8940	u8 valid;
8941	};
8942
8943	/* hwrm_fw_livepatch_cmd_err (size:64b/8B) */
8944	struct hwrm_fw_livepatch_cmd_err {
8945	u8 code;
8946	#define FW_LIVEPATCH_CMD_ERR_CODE_UNKNOWN 0x0UL
8947	#define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_OPCODE 0x1UL
8948	#define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_TARGET 0x2UL
8949	#define FW_LIVEPATCH_CMD_ERR_CODE_NOT_SUPPORTED 0x3UL
8950	#define FW_LIVEPATCH_CMD_ERR_CODE_NOT_INSTALLED 0x4UL
8951	#define FW_LIVEPATCH_CMD_ERR_CODE_NOT_PATCHED 0x5UL
8952	#define FW_LIVEPATCH_CMD_ERR_CODE_AUTH_FAIL 0x6UL
8953	#define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_HEADER 0x7UL
8954	#define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_SIZE 0x8UL
8955	#define FW_LIVEPATCH_CMD_ERR_CODE_ALREADY_PATCHED 0x9UL
8956	#define FW_LIVEPATCH_CMD_ERR_CODE_LAST FW_LIVEPATCH_CMD_ERR_CODE_ALREADY_PATCHED
8957	u8 unused_0[7];
8958	};
8959
8960	/* hwrm_exec_fwd_resp_input (size:1024b/128B) */
8961	struct hwrm_exec_fwd_resp_input {
8962	__le16 req_type;
8963	__le16 cmpl_ring;
8964	__le16 seq_id;
8965	__le16 target_id;
8966	__le64 resp_addr;
8967	__le32 encap_request[26];
8968	__le16 encap_resp_target_id;
8969	u8 unused_0[6];
8970	};
8971
8972	/* hwrm_exec_fwd_resp_output (size:128b/16B) */
8973	struct hwrm_exec_fwd_resp_output {
8974	__le16 error_code;
8975	__le16 req_type;
8976	__le16 seq_id;
8977	__le16 resp_len;
8978	u8 unused_0[7];
8979	u8 valid;
8980	};
8981
8982	/* hwrm_reject_fwd_resp_input (size:1024b/128B) */
8983	struct hwrm_reject_fwd_resp_input {
8984	__le16 req_type;
8985	__le16 cmpl_ring;
8986	__le16 seq_id;
8987	__le16 target_id;
8988	__le64 resp_addr;
8989	__le32 encap_request[26];
8990	__le16 encap_resp_target_id;
8991	u8 unused_0[6];
8992	};
8993
8994	/* hwrm_reject_fwd_resp_output (size:128b/16B) */
8995	struct hwrm_reject_fwd_resp_output {
8996	__le16 error_code;
8997	__le16 req_type;
8998	__le16 seq_id;
8999	__le16 resp_len;
9000	u8 unused_0[7];
9001	u8 valid;
9002	};
9003
9004	/* hwrm_fwd_resp_input (size:1024b/128B) */
9005	struct hwrm_fwd_resp_input {
9006	__le16 req_type;
9007	__le16 cmpl_ring;
9008	__le16 seq_id;
9009	__le16 target_id;
9010	__le64 resp_addr;
9011	__le16 encap_resp_target_id;
9012	__le16 encap_resp_cmpl_ring;
9013	__le16 encap_resp_len;
9014	u8 unused_0;
9015	u8 unused_1;
9016	__le64 encap_resp_addr;
9017	__le32 encap_resp[24];
9018	};
9019
9020	/* hwrm_fwd_resp_output (size:128b/16B) */
9021	struct hwrm_fwd_resp_output {
9022	__le16 error_code;
9023	__le16 req_type;
9024	__le16 seq_id;
9025	__le16 resp_len;
9026	u8 unused_0[7];
9027	u8 valid;
9028	};
9029
9030	/* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */
9031	struct hwrm_fwd_async_event_cmpl_input {
9032	__le16 req_type;
9033	__le16 cmpl_ring;
9034	__le16 seq_id;
9035	__le16 target_id;
9036	__le64 resp_addr;
9037	__le16 encap_async_event_target_id;
9038	u8 unused_0[6];
9039	__le32 encap_async_event_cmpl[4];
9040	};
9041
9042	/* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */
9043	struct hwrm_fwd_async_event_cmpl_output {
9044	__le16 error_code;
9045	__le16 req_type;
9046	__le16 seq_id;
9047	__le16 resp_len;
9048	u8 unused_0[7];
9049	u8 valid;
9050	};
9051
9052	/* hwrm_temp_monitor_query_input (size:128b/16B) */
9053	struct hwrm_temp_monitor_query_input {
9054	__le16 req_type;
9055	__le16 cmpl_ring;
9056	__le16 seq_id;
9057	__le16 target_id;
9058	__le64 resp_addr;
9059	};
9060
9061	/* hwrm_temp_monitor_query_output (size:192b/24B) */
9062	struct hwrm_temp_monitor_query_output {
9063	__le16 error_code;
9064	__le16 req_type;
9065	__le16 seq_id;
9066	__le16 resp_len;
9067	u8 temp;
9068	u8 phy_temp;
9069	u8 om_temp;
9070	u8 flags;
9071	#define TEMP_MONITOR_QUERY_RESP_FLAGS_TEMP_NOT_AVAILABLE 0x1UL
9072	#define TEMP_MONITOR_QUERY_RESP_FLAGS_PHY_TEMP_NOT_AVAILABLE 0x2UL
9073	#define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_NOT_PRESENT 0x4UL
9074	#define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_TEMP_NOT_AVAILABLE 0x8UL
9075	#define TEMP_MONITOR_QUERY_RESP_FLAGS_EXT_TEMP_FIELDS_AVAILABLE 0x10UL
9076	#define TEMP_MONITOR_QUERY_RESP_FLAGS_THRESHOLD_VALUES_AVAILABLE 0x20UL
9077	u8 temp2;
9078	u8 phy_temp2;
9079	u8 om_temp2;
9080	u8 warn_threshold;
9081	u8 critical_threshold;
9082	u8 fatal_threshold;
9083	u8 shutdown_threshold;
9084	u8 unused_0[4];
9085	u8 valid;
9086	};
9087
9088	/* hwrm_wol_filter_alloc_input (size:512b/64B) */
9089	struct hwrm_wol_filter_alloc_input {
9090	__le16 req_type;
9091	__le16 cmpl_ring;
9092	__le16 seq_id;
9093	__le16 target_id;
9094	__le64 resp_addr;
9095	__le32 flags;
9096	__le32 enables;
9097	#define WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS 0x1UL
9098	#define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_OFFSET 0x2UL
9099	#define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_SIZE 0x4UL
9100	#define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_ADDR 0x8UL
9101	#define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_ADDR 0x10UL
9102	#define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_SIZE 0x20UL
9103	__le16 port_id;
9104	u8 wol_type;
9105	#define WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT 0x0UL
9106	#define WOL_FILTER_ALLOC_REQ_WOL_TYPE_BMP 0x1UL
9107	#define WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 0xffUL
9108	#define WOL_FILTER_ALLOC_REQ_WOL_TYPE_LAST WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID
9109	u8 unused_0[5];
9110	u8 mac_address[6];
9111	__le16 pattern_offset;
9112	__le16 pattern_buf_size;
9113	__le16 pattern_mask_size;
9114	u8 unused_1[4];
9115	__le64 pattern_buf_addr;
9116	__le64 pattern_mask_addr;
9117	};
9118
9119	/* hwrm_wol_filter_alloc_output (size:128b/16B) */
9120	struct hwrm_wol_filter_alloc_output {
9121	__le16 error_code;
9122	__le16 req_type;
9123	__le16 seq_id;
9124	__le16 resp_len;
9125	u8 wol_filter_id;
9126	u8 unused_0[6];
9127	u8 valid;
9128	};
9129
9130	/* hwrm_wol_filter_free_input (size:256b/32B) */
9131	struct hwrm_wol_filter_free_input {
9132	__le16 req_type;
9133	__le16 cmpl_ring;
9134	__le16 seq_id;
9135	__le16 target_id;
9136	__le64 resp_addr;
9137	__le32 flags;
9138	#define WOL_FILTER_FREE_REQ_FLAGS_FREE_ALL_WOL_FILTERS 0x1UL
9139	__le32 enables;
9140	#define WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID 0x1UL
9141	__le16 port_id;
9142	u8 wol_filter_id;
9143	u8 unused_0[5];
9144	};
9145
9146	/* hwrm_wol_filter_free_output (size:128b/16B) */
9147	struct hwrm_wol_filter_free_output {
9148	__le16 error_code;
9149	__le16 req_type;
9150	__le16 seq_id;
9151	__le16 resp_len;
9152	u8 unused_0[7];
9153	u8 valid;
9154	};
9155
9156	/* hwrm_wol_filter_qcfg_input (size:448b/56B) */
9157	struct hwrm_wol_filter_qcfg_input {
9158	__le16 req_type;
9159	__le16 cmpl_ring;
9160	__le16 seq_id;
9161	__le16 target_id;
9162	__le64 resp_addr;
9163	__le16 port_id;
9164	__le16 handle;
9165	u8 unused_0[4];
9166	__le64 pattern_buf_addr;
9167	__le16 pattern_buf_size;
9168	u8 unused_1[6];
9169	__le64 pattern_mask_addr;
9170	__le16 pattern_mask_size;
9171	u8 unused_2[6];
9172	};
9173
9174	/* hwrm_wol_filter_qcfg_output (size:256b/32B) */
9175	struct hwrm_wol_filter_qcfg_output {
9176	__le16 error_code;
9177	__le16 req_type;
9178	__le16 seq_id;
9179	__le16 resp_len;
9180	__le16 next_handle;
9181	u8 wol_filter_id;
9182	u8 wol_type;
9183	#define WOL_FILTER_QCFG_RESP_WOL_TYPE_MAGICPKT 0x0UL
9184	#define WOL_FILTER_QCFG_RESP_WOL_TYPE_BMP 0x1UL
9185	#define WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 0xffUL
9186	#define WOL_FILTER_QCFG_RESP_WOL_TYPE_LAST WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID
9187	__le32 unused_0;
9188	u8 mac_address[6];
9189	__le16 pattern_offset;
9190	__le16 pattern_size;
9191	__le16 pattern_mask_size;
9192	u8 unused_1[3];
9193	u8 valid;
9194	};
9195
9196	/* hwrm_wol_reason_qcfg_input (size:320b/40B) */
9197	struct hwrm_wol_reason_qcfg_input {
9198	__le16 req_type;
9199	__le16 cmpl_ring;
9200	__le16 seq_id;
9201	__le16 target_id;
9202	__le64 resp_addr;
9203	__le16 port_id;
9204	u8 unused_0[6];
9205	__le64 wol_pkt_buf_addr;
9206	__le16 wol_pkt_buf_size;
9207	u8 unused_1[6];
9208	};
9209
9210	/* hwrm_wol_reason_qcfg_output (size:128b/16B) */
9211	struct hwrm_wol_reason_qcfg_output {
9212	__le16 error_code;
9213	__le16 req_type;
9214	__le16 seq_id;
9215	__le16 resp_len;
9216	u8 wol_filter_id;
9217	u8 wol_reason;
9218	#define WOL_REASON_QCFG_RESP_WOL_REASON_MAGICPKT 0x0UL
9219	#define WOL_REASON_QCFG_RESP_WOL_REASON_BMP 0x1UL
9220	#define WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 0xffUL
9221	#define WOL_REASON_QCFG_RESP_WOL_REASON_LAST WOL_REASON_QCFG_RESP_WOL_REASON_INVALID
9222	u8 wol_pkt_len;
9223	u8 unused_0[4];
9224	u8 valid;
9225	};
9226
9227	/* hwrm_dbg_read_direct_input (size:256b/32B) */
9228	struct hwrm_dbg_read_direct_input {
9229	__le16 req_type;
9230	__le16 cmpl_ring;
9231	__le16 seq_id;
9232	__le16 target_id;
9233	__le64 resp_addr;
9234	__le64 host_dest_addr;
9235	__le32 read_addr;
9236	__le32 read_len32;
9237	};
9238
9239	/* hwrm_dbg_read_direct_output (size:128b/16B) */
9240	struct hwrm_dbg_read_direct_output {
9241	__le16 error_code;
9242	__le16 req_type;
9243	__le16 seq_id;
9244	__le16 resp_len;
9245	__le32 crc32;
9246	u8 unused_0[3];
9247	u8 valid;
9248	};
9249
9250	/* hwrm_dbg_qcaps_input (size:192b/24B) */
9251	struct hwrm_dbg_qcaps_input {
9252	__le16 req_type;
9253	__le16 cmpl_ring;
9254	__le16 seq_id;
9255	__le16 target_id;
9256	__le64 resp_addr;
9257	__le16 fid;
9258	u8 unused_0[6];
9259	};
9260
9261	/* hwrm_dbg_qcaps_output (size:192b/24B) */
9262	struct hwrm_dbg_qcaps_output {
9263	__le16 error_code;
9264	__le16 req_type;
9265	__le16 seq_id;
9266	__le16 resp_len;
9267	__le16 fid;
9268	u8 unused_0[2];
9269	__le32 coredump_component_disable_caps;
9270	#define DBG_QCAPS_RESP_COREDUMP_COMPONENT_DISABLE_CAPS_NVRAM 0x1UL
9271	__le32 flags;
9272	#define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_NVM 0x1UL
9273	#define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_HOST_DDR 0x2UL
9274	#define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_SOC_DDR 0x4UL
9275	#define DBG_QCAPS_RESP_FLAGS_USEQ 0x8UL
9276	u8 unused_1[3];
9277	u8 valid;
9278	};
9279
9280	/* hwrm_dbg_qcfg_input (size:192b/24B) */
9281	struct hwrm_dbg_qcfg_input {
9282	__le16 req_type;
9283	__le16 cmpl_ring;
9284	__le16 seq_id;
9285	__le16 target_id;
9286	__le64 resp_addr;
9287	__le16 fid;
9288	__le16 flags;
9289	#define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_MASK 0x3UL
9290	#define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_SFT 0
9291	#define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_NVM 0x0UL
9292	#define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_HOST_DDR 0x1UL
9293	#define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR 0x2UL
9294	#define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_LAST DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR
9295	__le32 coredump_component_disable_flags;
9296	#define DBG_QCFG_REQ_COREDUMP_COMPONENT_DISABLE_FLAGS_NVRAM 0x1UL
9297	};
9298
9299	/* hwrm_dbg_qcfg_output (size:256b/32B) */
9300	struct hwrm_dbg_qcfg_output {
9301	__le16 error_code;
9302	__le16 req_type;
9303	__le16 seq_id;
9304	__le16 resp_len;
9305	__le16 fid;
9306	u8 unused_0[2];
9307	__le32 coredump_size;
9308	__le32 flags;
9309	#define DBG_QCFG_RESP_FLAGS_UART_LOG 0x1UL
9310	#define DBG_QCFG_RESP_FLAGS_UART_LOG_SECONDARY 0x2UL
9311	#define DBG_QCFG_RESP_FLAGS_FW_TRACE 0x4UL
9312	#define DBG_QCFG_RESP_FLAGS_FW_TRACE_SECONDARY 0x8UL
9313	#define DBG_QCFG_RESP_FLAGS_DEBUG_NOTIFY 0x10UL
9314	#define DBG_QCFG_RESP_FLAGS_JTAG_DEBUG 0x20UL
9315	__le16 async_cmpl_ring;
9316	u8 unused_2[2];
9317	__le32 crashdump_size;
9318	u8 unused_3[3];
9319	u8 valid;
9320	};
9321
9322	/* hwrm_dbg_crashdump_medium_cfg_input (size:320b/40B) */
9323	struct hwrm_dbg_crashdump_medium_cfg_input {
9324	__le16 req_type;
9325	__le16 cmpl_ring;
9326	__le16 seq_id;
9327	__le16 target_id;
9328	__le64 resp_addr;
9329	__le16 output_dest_flags;
9330	#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_TYPE_DDR 0x1UL
9331	__le16 pg_size_lvl;
9332	#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_MASK 0x3UL
9333	#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_SFT 0
9334	#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_0 0x0UL
9335	#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_1 0x1UL
9336	#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_2 0x2UL
9337	#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LAST DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_2
9338	#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_MASK 0x1cUL
9339	#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_SFT 2
9340	#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_4K (0x0UL << 2)
9341	#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_8K (0x1UL << 2)
9342	#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_64K (0x2UL << 2)
9343	#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_2M (0x3UL << 2)
9344	#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_8M (0x4UL << 2)
9345	#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_1G (0x5UL << 2)
9346	#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_LAST DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_1G
9347	#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_UNUSED11_MASK 0xffe0UL
9348	#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_UNUSED11_SFT 5
9349	__le32 size;
9350	__le32 coredump_component_disable_flags;
9351	#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_NVRAM 0x1UL
9352	__le32 unused_0;
9353	__le64 pbl;
9354	};
9355
9356	/* hwrm_dbg_crashdump_medium_cfg_output (size:128b/16B) */
9357	struct hwrm_dbg_crashdump_medium_cfg_output {
9358	__le16 error_code;
9359	__le16 req_type;
9360	__le16 seq_id;
9361	__le16 resp_len;
9362	u8 unused_1[7];
9363	u8 valid;
9364	};
9365
9366	/* coredump_segment_record (size:128b/16B) */
9367	struct coredump_segment_record {
9368	__le16 component_id;
9369	__le16 segment_id;
9370	__le16 max_instances;
9371	u8 version_hi;
9372	u8 version_low;
9373	u8 seg_flags;
9374	u8 compress_flags;
9375	#define SFLAG_COMPRESSED_ZLIB 0x1UL
9376	u8 unused_0[2];
9377	__le32 segment_len;
9378	};
9379
9380	/* hwrm_dbg_coredump_list_input (size:256b/32B) */
9381	struct hwrm_dbg_coredump_list_input {
9382	__le16 req_type;
9383	__le16 cmpl_ring;
9384	__le16 seq_id;
9385	__le16 target_id;
9386	__le64 resp_addr;
9387	__le64 host_dest_addr;
9388	__le32 host_buf_len;
9389	__le16 seq_no;
9390	u8 flags;
9391	#define DBG_COREDUMP_LIST_REQ_FLAGS_CRASHDUMP 0x1UL
9392	u8 unused_0[1];
9393	};
9394
9395	/* hwrm_dbg_coredump_list_output (size:128b/16B) */
9396	struct hwrm_dbg_coredump_list_output {
9397	__le16 error_code;
9398	__le16 req_type;
9399	__le16 seq_id;
9400	__le16 resp_len;
9401	u8 flags;
9402	#define DBG_COREDUMP_LIST_RESP_FLAGS_MORE 0x1UL
9403	u8 unused_0;
9404	__le16 total_segments;
9405	__le16 data_len;
9406	u8 unused_1;
9407	u8 valid;
9408	};
9409
9410	/* hwrm_dbg_coredump_initiate_input (size:256b/32B) */
9411	struct hwrm_dbg_coredump_initiate_input {
9412	__le16 req_type;
9413	__le16 cmpl_ring;
9414	__le16 seq_id;
9415	__le16 target_id;
9416	__le64 resp_addr;
9417	__le16 component_id;
9418	__le16 segment_id;
9419	__le16 instance;
9420	__le16 unused_0;
9421	u8 seg_flags;
9422	u8 unused_1[7];
9423	};
9424
9425	/* hwrm_dbg_coredump_initiate_output (size:128b/16B) */
9426	struct hwrm_dbg_coredump_initiate_output {
9427	__le16 error_code;
9428	__le16 req_type;
9429	__le16 seq_id;
9430	__le16 resp_len;
9431	u8 unused_0[7];
9432	u8 valid;
9433	};
9434
9435	/* coredump_data_hdr (size:128b/16B) */
9436	struct coredump_data_hdr {
9437	__le32 address;
9438	__le32 flags_length;
9439	#define COREDUMP_DATA_HDR_FLAGS_LENGTH_ACTUAL_LEN_MASK 0xffffffUL
9440	#define COREDUMP_DATA_HDR_FLAGS_LENGTH_ACTUAL_LEN_SFT 0
9441	#define COREDUMP_DATA_HDR_FLAGS_LENGTH_INDIRECT_ACCESS 0x1000000UL
9442	__le32 instance;
9443	__le32 next_offset;
9444	};
9445
9446	/* hwrm_dbg_coredump_retrieve_input (size:448b/56B) */
9447	struct hwrm_dbg_coredump_retrieve_input {
9448	__le16 req_type;
9449	__le16 cmpl_ring;
9450	__le16 seq_id;
9451	__le16 target_id;
9452	__le64 resp_addr;
9453	__le64 host_dest_addr;
9454	__le32 host_buf_len;
9455	__le32 unused_0;
9456	__le16 component_id;
9457	__le16 segment_id;
9458	__le16 instance;
9459	__le16 unused_1;
9460	u8 seg_flags;
9461	u8 unused_2;
9462	__le16 unused_3;
9463	__le32 unused_4;
9464	__le32 seq_no;
9465	__le32 unused_5;
9466	};
9467
9468	/* hwrm_dbg_coredump_retrieve_output (size:128b/16B) */
9469	struct hwrm_dbg_coredump_retrieve_output {
9470	__le16 error_code;
9471	__le16 req_type;
9472	__le16 seq_id;
9473	__le16 resp_len;
9474	u8 flags;
9475	#define DBG_COREDUMP_RETRIEVE_RESP_FLAGS_MORE 0x1UL
9476	u8 unused_0;
9477	__le16 data_len;
9478	u8 unused_1[3];
9479	u8 valid;
9480	};
9481
9482	/* hwrm_dbg_ring_info_get_input (size:192b/24B) */
9483	struct hwrm_dbg_ring_info_get_input {
9484	__le16 req_type;
9485	__le16 cmpl_ring;
9486	__le16 seq_id;
9487	__le16 target_id;
9488	__le64 resp_addr;
9489	u8 ring_type;
9490	#define DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL 0x0UL
9491	#define DBG_RING_INFO_GET_REQ_RING_TYPE_TX 0x1UL
9492	#define DBG_RING_INFO_GET_REQ_RING_TYPE_RX 0x2UL
9493	#define DBG_RING_INFO_GET_REQ_RING_TYPE_NQ 0x3UL
9494	#define DBG_RING_INFO_GET_REQ_RING_TYPE_LAST DBG_RING_INFO_GET_REQ_RING_TYPE_NQ
9495	u8 unused_0[3];
9496	__le32 fw_ring_id;
9497	};
9498
9499	/* hwrm_dbg_ring_info_get_output (size:192b/24B) */
9500	struct hwrm_dbg_ring_info_get_output {
9501	__le16 error_code;
9502	__le16 req_type;
9503	__le16 seq_id;
9504	__le16 resp_len;
9505	__le32 producer_index;
9506	__le32 consumer_index;
9507	__le32 cag_vector_ctrl;
9508	__le16 st_tag;
9509	u8 unused_0;
9510	u8 valid;
9511	};
9512
9513	/* hwrm_nvm_read_input (size:320b/40B) */
9514	struct hwrm_nvm_read_input {
9515	__le16 req_type;
9516	__le16 cmpl_ring;
9517	__le16 seq_id;
9518	__le16 target_id;
9519	__le64 resp_addr;
9520	__le64 host_dest_addr;
9521	__le16 dir_idx;
9522	u8 unused_0[2];
9523	__le32 offset;
9524	__le32 len;
9525	u8 unused_1[4];
9526	};
9527
9528	/* hwrm_nvm_read_output (size:128b/16B) */
9529	struct hwrm_nvm_read_output {
9530	__le16 error_code;
9531	__le16 req_type;
9532	__le16 seq_id;
9533	__le16 resp_len;
9534	u8 unused_0[7];
9535	u8 valid;
9536	};
9537
9538	/* hwrm_nvm_get_dir_entries_input (size:192b/24B) */
9539	struct hwrm_nvm_get_dir_entries_input {
9540	__le16 req_type;
9541	__le16 cmpl_ring;
9542	__le16 seq_id;
9543	__le16 target_id;
9544	__le64 resp_addr;
9545	__le64 host_dest_addr;
9546	};
9547
9548	/* hwrm_nvm_get_dir_entries_output (size:128b/16B) */
9549	struct hwrm_nvm_get_dir_entries_output {
9550	__le16 error_code;
9551	__le16 req_type;
9552	__le16 seq_id;
9553	__le16 resp_len;
9554	u8 unused_0[7];
9555	u8 valid;
9556	};
9557
9558	/* hwrm_nvm_get_dir_info_input (size:128b/16B) */
9559	struct hwrm_nvm_get_dir_info_input {
9560	__le16 req_type;
9561	__le16 cmpl_ring;
9562	__le16 seq_id;
9563	__le16 target_id;
9564	__le64 resp_addr;
9565	};
9566
9567	/* hwrm_nvm_get_dir_info_output (size:192b/24B) */
9568	struct hwrm_nvm_get_dir_info_output {
9569	__le16 error_code;
9570	__le16 req_type;
9571	__le16 seq_id;
9572	__le16 resp_len;
9573	__le32 entries;
9574	__le32 entry_length;
9575	u8 unused_0[7];
9576	u8 valid;
9577	};
9578
9579	/* hwrm_nvm_write_input (size:448b/56B) */
9580	struct hwrm_nvm_write_input {
9581	__le16 req_type;
9582	__le16 cmpl_ring;
9583	__le16 seq_id;
9584	__le16 target_id;
9585	__le64 resp_addr;
9586	__le64 host_src_addr;
9587	__le16 dir_type;
9588	__le16 dir_ordinal;
9589	__le16 dir_ext;
9590	__le16 dir_attr;
9591	__le32 dir_data_length;
9592	__le16 option;
9593	__le16 flags;
9594	#define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG 0x1UL
9595	#define NVM_WRITE_REQ_FLAGS_BATCH_MODE 0x2UL
9596	#define NVM_WRITE_REQ_FLAGS_BATCH_LAST 0x4UL
9597	__le32 dir_item_length;
9598	__le32 offset;
9599	__le32 len;
9600	__le32 unused_0;
9601	};
9602
9603	/* hwrm_nvm_write_output (size:128b/16B) */
9604	struct hwrm_nvm_write_output {
9605	__le16 error_code;
9606	__le16 req_type;
9607	__le16 seq_id;
9608	__le16 resp_len;
9609	__le32 dir_item_length;
9610	__le16 dir_idx;
9611	u8 unused_0;
9612	u8 valid;
9613	};
9614
9615	/* hwrm_nvm_write_cmd_err (size:64b/8B) */
9616	struct hwrm_nvm_write_cmd_err {
9617	u8 code;
9618	#define NVM_WRITE_CMD_ERR_CODE_UNKNOWN 0x0UL
9619	#define NVM_WRITE_CMD_ERR_CODE_FRAG_ERR 0x1UL
9620	#define NVM_WRITE_CMD_ERR_CODE_NO_SPACE 0x2UL
9621	#define NVM_WRITE_CMD_ERR_CODE_LAST NVM_WRITE_CMD_ERR_CODE_NO_SPACE
9622	u8 unused_0[7];
9623	};
9624
9625	/* hwrm_nvm_modify_input (size:320b/40B) */
9626	struct hwrm_nvm_modify_input {
9627	__le16 req_type;
9628	__le16 cmpl_ring;
9629	__le16 seq_id;
9630	__le16 target_id;
9631	__le64 resp_addr;
9632	__le64 host_src_addr;
9633	__le16 dir_idx;
9634	__le16 flags;
9635	#define NVM_MODIFY_REQ_FLAGS_BATCH_MODE 0x1UL
9636	#define NVM_MODIFY_REQ_FLAGS_BATCH_LAST 0x2UL
9637	__le32 offset;
9638	__le32 len;
9639	u8 unused_1[4];
9640	};
9641
9642	/* hwrm_nvm_modify_output (size:128b/16B) */
9643	struct hwrm_nvm_modify_output {
9644	__le16 error_code;
9645	__le16 req_type;
9646	__le16 seq_id;
9647	__le16 resp_len;
9648	u8 unused_0[7];
9649	u8 valid;
9650	};
9651
9652	/* hwrm_nvm_find_dir_entry_input (size:256b/32B) */
9653	struct hwrm_nvm_find_dir_entry_input {
9654	__le16 req_type;
9655	__le16 cmpl_ring;
9656	__le16 seq_id;
9657	__le16 target_id;
9658	__le64 resp_addr;
9659	__le32 enables;
9660	#define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID 0x1UL
9661	__le16 dir_idx;
9662	__le16 dir_type;
9663	__le16 dir_ordinal;
9664	__le16 dir_ext;
9665	u8 opt_ordinal;
9666	#define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL
9667	#define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0
9668	#define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ 0x0UL
9669	#define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE 0x1UL
9670	#define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 0x2UL
9671	#define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_LAST NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT
9672	u8 unused_0[3];
9673	};
9674
9675	/* hwrm_nvm_find_dir_entry_output (size:256b/32B) */
9676	struct hwrm_nvm_find_dir_entry_output {
9677	__le16 error_code;
9678	__le16 req_type;
9679	__le16 seq_id;
9680	__le16 resp_len;
9681	__le32 dir_item_length;
9682	__le32 dir_data_length;
9683	__le32 fw_ver;
9684	__le16 dir_ordinal;
9685	__le16 dir_idx;
9686	u8 unused_0[7];
9687	u8 valid;
9688	};
9689
9690	/* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */
9691	struct hwrm_nvm_erase_dir_entry_input {
9692	__le16 req_type;
9693	__le16 cmpl_ring;
9694	__le16 seq_id;
9695	__le16 target_id;
9696	__le64 resp_addr;
9697	__le16 dir_idx;
9698	u8 unused_0[6];
9699	};
9700
9701	/* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */
9702	struct hwrm_nvm_erase_dir_entry_output {
9703	__le16 error_code;
9704	__le16 req_type;
9705	__le16 seq_id;
9706	__le16 resp_len;
9707	u8 unused_0[7];
9708	u8 valid;
9709	};
9710
9711	/* hwrm_nvm_get_dev_info_input (size:128b/16B) */
9712	struct hwrm_nvm_get_dev_info_input {
9713	__le16 req_type;
9714	__le16 cmpl_ring;
9715	__le16 seq_id;
9716	__le16 target_id;
9717	__le64 resp_addr;
9718	};
9719
9720	/* hwrm_nvm_get_dev_info_output (size:640b/80B) */
9721	struct hwrm_nvm_get_dev_info_output {
9722	__le16 error_code;
9723	__le16 req_type;
9724	__le16 seq_id;
9725	__le16 resp_len;
9726	__le16 manufacturer_id;
9727	__le16 device_id;
9728	__le32 sector_size;
9729	__le32 nvram_size;
9730	__le32 reserved_size;
9731	__le32 available_size;
9732	u8 nvm_cfg_ver_maj;
9733	u8 nvm_cfg_ver_min;
9734	u8 nvm_cfg_ver_upd;
9735	u8 flags;
9736	#define NVM_GET_DEV_INFO_RESP_FLAGS_FW_VER_VALID 0x1UL
9737	char pkg_name[16];
9738	__le16 hwrm_fw_major;
9739	__le16 hwrm_fw_minor;
9740	__le16 hwrm_fw_build;
9741	__le16 hwrm_fw_patch;
9742	__le16 mgmt_fw_major;
9743	__le16 mgmt_fw_minor;
9744	__le16 mgmt_fw_build;
9745	__le16 mgmt_fw_patch;
9746	__le16 roce_fw_major;
9747	__le16 roce_fw_minor;
9748	__le16 roce_fw_build;
9749	__le16 roce_fw_patch;
9750	u8 unused_0[7];
9751	u8 valid;
9752	};
9753
9754	/* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */
9755	struct hwrm_nvm_mod_dir_entry_input {
9756	__le16 req_type;
9757	__le16 cmpl_ring;
9758	__le16 seq_id;
9759	__le16 target_id;
9760	__le64 resp_addr;
9761	__le32 enables;
9762	#define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM 0x1UL
9763	__le16 dir_idx;
9764	__le16 dir_ordinal;
9765	__le16 dir_ext;
9766	__le16 dir_attr;
9767	__le32 checksum;
9768	};
9769
9770	/* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */
9771	struct hwrm_nvm_mod_dir_entry_output {
9772	__le16 error_code;
9773	__le16 req_type;
9774	__le16 seq_id;
9775	__le16 resp_len;
9776	u8 unused_0[7];
9777	u8 valid;
9778	};
9779
9780	/* hwrm_nvm_verify_update_input (size:192b/24B) */
9781	struct hwrm_nvm_verify_update_input {
9782	__le16 req_type;
9783	__le16 cmpl_ring;
9784	__le16 seq_id;
9785	__le16 target_id;
9786	__le64 resp_addr;
9787	__le16 dir_type;
9788	__le16 dir_ordinal;
9789	__le16 dir_ext;
9790	u8 unused_0[2];
9791	};
9792
9793	/* hwrm_nvm_verify_update_output (size:128b/16B) */
9794	struct hwrm_nvm_verify_update_output {
9795	__le16 error_code;
9796	__le16 req_type;
9797	__le16 seq_id;
9798	__le16 resp_len;
9799	u8 unused_0[7];
9800	u8 valid;
9801	};
9802
9803	/* hwrm_nvm_install_update_input (size:192b/24B) */
9804	struct hwrm_nvm_install_update_input {
9805	__le16 req_type;
9806	__le16 cmpl_ring;
9807	__le16 seq_id;
9808	__le16 target_id;
9809	__le64 resp_addr;
9810	__le32 install_type;
9811	#define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_NORMAL 0x0UL
9812	#define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 0xffffffffUL
9813	#define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_LAST NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL
9814	__le16 flags;
9815	#define NVM_INSTALL_UPDATE_REQ_FLAGS_ERASE_UNUSED_SPACE 0x1UL
9816	#define NVM_INSTALL_UPDATE_REQ_FLAGS_REMOVE_UNUSED_PKG 0x2UL
9817	#define NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG 0x4UL
9818	#define NVM_INSTALL_UPDATE_REQ_FLAGS_VERIFY_ONLY 0x8UL
9819	u8 unused_0[2];
9820	};
9821
9822	/* hwrm_nvm_install_update_output (size:192b/24B) */
9823	struct hwrm_nvm_install_update_output {
9824	__le16 error_code;
9825	__le16 req_type;
9826	__le16 seq_id;
9827	__le16 resp_len;
9828	__le64 installed_items;
9829	u8 result;
9830	#define NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 0x0UL
9831	#define NVM_INSTALL_UPDATE_RESP_RESULT_FAILURE 0xffUL
9832	#define NVM_INSTALL_UPDATE_RESP_RESULT_MALLOC_FAILURE 0xfdUL
9833	#define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_INDEX_PARAMETER 0xfbUL
9834	#define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TYPE_PARAMETER 0xf3UL
9835	#define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PREREQUISITE 0xf2UL
9836	#define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_FILE_HEADER 0xecUL
9837	#define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_SIGNATURE 0xebUL
9838	#define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_STREAM 0xeaUL
9839	#define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_LENGTH 0xe9UL
9840	#define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_MANIFEST 0xe8UL
9841	#define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TRAILER 0xe7UL
9842	#define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_CHECKSUM 0xe6UL
9843	#define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_ITEM_CHECKSUM 0xe5UL
9844	#define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DATA_LENGTH 0xe4UL
9845	#define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DIRECTIVE 0xe1UL
9846	#define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_CHIP_REV 0xceUL
9847	#define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_DEVICE_ID 0xcdUL
9848	#define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_VENDOR 0xccUL
9849	#define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_ID 0xcbUL
9850	#define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_PLATFORM 0xc5UL
9851	#define NVM_INSTALL_UPDATE_RESP_RESULT_DUPLICATE_ITEM 0xc4UL
9852	#define NVM_INSTALL_UPDATE_RESP_RESULT_ZERO_LENGTH_ITEM 0xc3UL
9853	#define NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_CHECKSUM_ERROR 0xb9UL
9854	#define NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_DATA_ERROR 0xb8UL
9855	#define NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_AUTHENTICATION_ERROR 0xb7UL
9856	#define NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_NOT_FOUND 0xb0UL
9857	#define NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_LOCKED 0xa7UL
9858	#define NVM_INSTALL_UPDATE_RESP_RESULT_LAST NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_LOCKED
9859	u8 problem_item;
9860	#define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_NONE 0x0UL
9861	#define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 0xffUL
9862	#define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_LAST NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE
9863	u8 reset_required;
9864	#define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_NONE 0x0UL
9865	#define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_PCI 0x1UL
9866	#define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 0x2UL
9867	#define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_LAST NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER
9868	u8 unused_0[4];
9869	u8 valid;
9870	};
9871
9872	/* hwrm_nvm_install_update_cmd_err (size:64b/8B) */
9873	struct hwrm_nvm_install_update_cmd_err {
9874	u8 code;
9875	#define NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN 0x0UL
9876	#define NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR 0x1UL
9877	#define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 0x2UL
9878	#define NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK 0x3UL
9879	#define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_VOLTREG_SUPPORT 0x4UL
9880	#define NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_VOLTREG_SUPPORT
9881	u8 unused_0[7];
9882	};
9883
9884	/* hwrm_nvm_get_variable_input (size:320b/40B) */
9885	struct hwrm_nvm_get_variable_input {
9886	__le16 req_type;
9887	__le16 cmpl_ring;
9888	__le16 seq_id;
9889	__le16 target_id;
9890	__le64 resp_addr;
9891	__le64 dest_data_addr;
9892	__le16 data_len;
9893	__le16 option_num;
9894	#define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL
9895	#define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL
9896	#define NVM_GET_VARIABLE_REQ_OPTION_NUM_LAST NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF
9897	__le16 dimensions;
9898	__le16 index_0;
9899	__le16 index_1;
9900	__le16 index_2;
9901	__le16 index_3;
9902	u8 flags;
9903	#define NVM_GET_VARIABLE_REQ_FLAGS_FACTORY_DFLT 0x1UL
9904	u8 unused_0;
9905	};
9906
9907	/* hwrm_nvm_get_variable_output (size:128b/16B) */
9908	struct hwrm_nvm_get_variable_output {
9909	__le16 error_code;
9910	__le16 req_type;
9911	__le16 seq_id;
9912	__le16 resp_len;
9913	__le16 data_len;
9914	__le16 option_num;
9915	#define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_0 0x0UL
9916	#define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 0xffffUL
9917	#define NVM_GET_VARIABLE_RESP_OPTION_NUM_LAST NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF
9918	u8 unused_0[3];
9919	u8 valid;
9920	};
9921
9922	/* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */
9923	struct hwrm_nvm_get_variable_cmd_err {
9924	u8 code;
9925	#define NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL
9926	#define NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL
9927	#define NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL
9928	#define NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 0x3UL
9929	#define NVM_GET_VARIABLE_CMD_ERR_CODE_LAST NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT
9930	u8 unused_0[7];
9931	};
9932
9933	/* hwrm_nvm_set_variable_input (size:320b/40B) */
9934	struct hwrm_nvm_set_variable_input {
9935	__le16 req_type;
9936	__le16 cmpl_ring;
9937	__le16 seq_id;
9938	__le16 target_id;
9939	__le64 resp_addr;
9940	__le64 src_data_addr;
9941	__le16 data_len;
9942	__le16 option_num;
9943	#define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL
9944	#define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL
9945	#define NVM_SET_VARIABLE_REQ_OPTION_NUM_LAST NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF
9946	__le16 dimensions;
9947	__le16 index_0;
9948	__le16 index_1;
9949	__le16 index_2;
9950	__le16 index_3;
9951	u8 flags;
9952	#define NVM_SET_VARIABLE_REQ_FLAGS_FORCE_FLUSH 0x1UL
9953	#define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_MASK 0xeUL
9954	#define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_SFT 1
9955	#define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_NONE (0x0UL << 1)
9956	#define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1 (0x1UL << 1)
9957	#define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_AES256 (0x2UL << 1)
9958	#define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH (0x3UL << 1)
9959	#define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_LAST NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH
9960	#define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_MASK 0x70UL
9961	#define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_SFT 4
9962	#define NVM_SET_VARIABLE_REQ_FLAGS_FACTORY_DEFAULT 0x80UL
9963	u8 unused_0;
9964	};
9965
9966	/* hwrm_nvm_set_variable_output (size:128b/16B) */
9967	struct hwrm_nvm_set_variable_output {
9968	__le16 error_code;
9969	__le16 req_type;
9970	__le16 seq_id;
9971	__le16 resp_len;
9972	u8 unused_0[7];
9973	u8 valid;
9974	};
9975
9976	/* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */
9977	struct hwrm_nvm_set_variable_cmd_err {
9978	u8 code;
9979	#define NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL
9980	#define NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL
9981	#define NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL
9982	#define NVM_SET_VARIABLE_CMD_ERR_CODE_LAST NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR
9983	u8 unused_0[7];
9984	};
9985
9986	/* hwrm_selftest_qlist_input (size:128b/16B) */
9987	struct hwrm_selftest_qlist_input {
9988	__le16 req_type;
9989	__le16 cmpl_ring;
9990	__le16 seq_id;
9991	__le16 target_id;
9992	__le64 resp_addr;
9993	};
9994
9995	/* hwrm_selftest_qlist_output (size:2240b/280B) */
9996	struct hwrm_selftest_qlist_output {
9997	__le16 error_code;
9998	__le16 req_type;
9999	__le16 seq_id;
10000	__le16 resp_len;
10001	u8 num_tests;
10002	u8 available_tests;
10003	#define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_NVM_TEST 0x1UL
10004	#define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_LINK_TEST 0x2UL
10005	#define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_REGISTER_TEST 0x4UL
10006	#define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_MEMORY_TEST 0x8UL
10007	#define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_PCIE_SERDES_TEST 0x10UL
10008	#define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_ETHERNET_SERDES_TEST 0x20UL
10009	u8 offline_tests;
10010	#define SELFTEST_QLIST_RESP_OFFLINE_TESTS_NVM_TEST 0x1UL
10011	#define SELFTEST_QLIST_RESP_OFFLINE_TESTS_LINK_TEST 0x2UL
10012	#define SELFTEST_QLIST_RESP_OFFLINE_TESTS_REGISTER_TEST 0x4UL
10013	#define SELFTEST_QLIST_RESP_OFFLINE_TESTS_MEMORY_TEST 0x8UL
10014	#define SELFTEST_QLIST_RESP_OFFLINE_TESTS_PCIE_SERDES_TEST 0x10UL
10015	#define SELFTEST_QLIST_RESP_OFFLINE_TESTS_ETHERNET_SERDES_TEST 0x20UL
10016	u8 unused_0;
10017	__le16 test_timeout;
10018	u8 unused_1[2];
10019	char test_name[8][32];
10020	u8 eyescope_target_BER_support;
10021	#define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E8_SUPPORTED 0x0UL
10022	#define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E9_SUPPORTED 0x1UL
10023	#define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E10_SUPPORTED 0x2UL
10024	#define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E11_SUPPORTED 0x3UL
10025	#define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED 0x4UL
10026	#define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_LAST SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED
10027	u8 unused_2[6];
10028	u8 valid;
10029	};
10030
10031	/* hwrm_selftest_exec_input (size:192b/24B) */
10032	struct hwrm_selftest_exec_input {
10033	__le16 req_type;
10034	__le16 cmpl_ring;
10035	__le16 seq_id;
10036	__le16 target_id;
10037	__le64 resp_addr;
10038	u8 flags;
10039	#define SELFTEST_EXEC_REQ_FLAGS_NVM_TEST 0x1UL
10040	#define SELFTEST_EXEC_REQ_FLAGS_LINK_TEST 0x2UL
10041	#define SELFTEST_EXEC_REQ_FLAGS_REGISTER_TEST 0x4UL
10042	#define SELFTEST_EXEC_REQ_FLAGS_MEMORY_TEST 0x8UL
10043	#define SELFTEST_EXEC_REQ_FLAGS_PCIE_SERDES_TEST 0x10UL
10044	#define SELFTEST_EXEC_REQ_FLAGS_ETHERNET_SERDES_TEST 0x20UL
10045	u8 unused_0[7];
10046	};
10047
10048	/* hwrm_selftest_exec_output (size:128b/16B) */
10049	struct hwrm_selftest_exec_output {
10050	__le16 error_code;
10051	__le16 req_type;
10052	__le16 seq_id;
10053	__le16 resp_len;
10054	u8 requested_tests;
10055	#define SELFTEST_EXEC_RESP_REQUESTED_TESTS_NVM_TEST 0x1UL
10056	#define SELFTEST_EXEC_RESP_REQUESTED_TESTS_LINK_TEST 0x2UL
10057	#define SELFTEST_EXEC_RESP_REQUESTED_TESTS_REGISTER_TEST 0x4UL
10058	#define SELFTEST_EXEC_RESP_REQUESTED_TESTS_MEMORY_TEST 0x8UL
10059	#define SELFTEST_EXEC_RESP_REQUESTED_TESTS_PCIE_SERDES_TEST 0x10UL
10060	#define SELFTEST_EXEC_RESP_REQUESTED_TESTS_ETHERNET_SERDES_TEST 0x20UL
10061	u8 test_success;
10062	#define SELFTEST_EXEC_RESP_TEST_SUCCESS_NVM_TEST 0x1UL
10063	#define SELFTEST_EXEC_RESP_TEST_SUCCESS_LINK_TEST 0x2UL
10064	#define SELFTEST_EXEC_RESP_TEST_SUCCESS_REGISTER_TEST 0x4UL
10065	#define SELFTEST_EXEC_RESP_TEST_SUCCESS_MEMORY_TEST 0x8UL
10066	#define SELFTEST_EXEC_RESP_TEST_SUCCESS_PCIE_SERDES_TEST 0x10UL
10067	#define SELFTEST_EXEC_RESP_TEST_SUCCESS_ETHERNET_SERDES_TEST 0x20UL
10068	u8 unused_0[5];
10069	u8 valid;
10070	};
10071
10072	/* hwrm_selftest_irq_input (size:128b/16B) */
10073	struct hwrm_selftest_irq_input {
10074	__le16 req_type;
10075	__le16 cmpl_ring;
10076	__le16 seq_id;
10077	__le16 target_id;
10078	__le64 resp_addr;
10079	};
10080
10081	/* hwrm_selftest_irq_output (size:128b/16B) */
10082	struct hwrm_selftest_irq_output {
10083	__le16 error_code;
10084	__le16 req_type;
10085	__le16 seq_id;
10086	__le16 resp_len;
10087	u8 unused_0[7];
10088	u8 valid;
10089	};
10090
10091	/* dbc_dbc (size:64b/8B) */
10092	struct dbc_dbc {
10093	u32 index;
10094	#define DBC_DBC_INDEX_MASK 0xffffffUL
10095	#define DBC_DBC_INDEX_SFT 0
10096	#define DBC_DBC_EPOCH 0x1000000UL
10097	#define DBC_DBC_TOGGLE_MASK 0x6000000UL
10098	#define DBC_DBC_TOGGLE_SFT 25
10099	u32 type_path_xid;
10100	#define DBC_DBC_XID_MASK 0xfffffUL
10101	#define DBC_DBC_XID_SFT 0
10102	#define DBC_DBC_PATH_MASK 0x3000000UL
10103	#define DBC_DBC_PATH_SFT 24
10104	#define DBC_DBC_PATH_ROCE (0x0UL << 24)
10105	#define DBC_DBC_PATH_L2 (0x1UL << 24)
10106	#define DBC_DBC_PATH_ENGINE (0x2UL << 24)
10107	#define DBC_DBC_PATH_LAST DBC_DBC_PATH_ENGINE
10108	#define DBC_DBC_VALID 0x4000000UL
10109	#define DBC_DBC_DEBUG_TRACE 0x8000000UL
10110	#define DBC_DBC_TYPE_MASK 0xf0000000UL
10111	#define DBC_DBC_TYPE_SFT 28
10112	#define DBC_DBC_TYPE_SQ (0x0UL << 28)
10113	#define DBC_DBC_TYPE_RQ (0x1UL << 28)
10114	#define DBC_DBC_TYPE_SRQ (0x2UL << 28)
10115	#define DBC_DBC_TYPE_SRQ_ARM (0x3UL << 28)
10116	#define DBC_DBC_TYPE_CQ (0x4UL << 28)
10117	#define DBC_DBC_TYPE_CQ_ARMSE (0x5UL << 28)
10118	#define DBC_DBC_TYPE_CQ_ARMALL (0x6UL << 28)
10119	#define DBC_DBC_TYPE_CQ_ARMENA (0x7UL << 28)
10120	#define DBC_DBC_TYPE_SRQ_ARMENA (0x8UL << 28)
10121	#define DBC_DBC_TYPE_CQ_CUTOFF_ACK (0x9UL << 28)
10122	#define DBC_DBC_TYPE_NQ (0xaUL << 28)
10123	#define DBC_DBC_TYPE_NQ_ARM (0xbUL << 28)
10124	#define DBC_DBC_TYPE_NQ_MASK (0xeUL << 28)
10125	#define DBC_DBC_TYPE_NULL (0xfUL << 28)
10126	#define DBC_DBC_TYPE_LAST DBC_DBC_TYPE_NULL
10127	};
10128
10129	/* db_push_start (size:64b/8B) */
10130	struct db_push_start {
10131	u64 db;
10132	#define DB_PUSH_START_DB_INDEX_MASK 0xffffffUL
10133	#define DB_PUSH_START_DB_INDEX_SFT 0
10134	#define DB_PUSH_START_DB_PI_LO_MASK 0xff000000UL
10135	#define DB_PUSH_START_DB_PI_LO_SFT 24
10136	#define DB_PUSH_START_DB_XID_MASK 0xfffff00000000ULL
10137	#define DB_PUSH_START_DB_XID_SFT 32
10138	#define DB_PUSH_START_DB_PI_HI_MASK 0xf0000000000000ULL
10139	#define DB_PUSH_START_DB_PI_HI_SFT 52
10140	#define DB_PUSH_START_DB_TYPE_MASK 0xf000000000000000ULL
10141	#define DB_PUSH_START_DB_TYPE_SFT 60
10142	#define DB_PUSH_START_DB_TYPE_PUSH_START (0xcULL << 60)
10143	#define DB_PUSH_START_DB_TYPE_PUSH_END (0xdULL << 60)
10144	#define DB_PUSH_START_DB_TYPE_LAST DB_PUSH_START_DB_TYPE_PUSH_END
10145	};
10146
10147	/* db_push_end (size:64b/8B) */
10148	struct db_push_end {
10149	u64 db;
10150	#define DB_PUSH_END_DB_INDEX_MASK 0xffffffUL
10151	#define DB_PUSH_END_DB_INDEX_SFT 0
10152	#define DB_PUSH_END_DB_PI_LO_MASK 0xff000000UL
10153	#define DB_PUSH_END_DB_PI_LO_SFT 24
10154	#define DB_PUSH_END_DB_XID_MASK 0xfffff00000000ULL
10155	#define DB_PUSH_END_DB_XID_SFT 32
10156	#define DB_PUSH_END_DB_PI_HI_MASK 0xf0000000000000ULL
10157	#define DB_PUSH_END_DB_PI_HI_SFT 52
10158	#define DB_PUSH_END_DB_PATH_MASK 0x300000000000000ULL
10159	#define DB_PUSH_END_DB_PATH_SFT 56
10160	#define DB_PUSH_END_DB_PATH_ROCE (0x0ULL << 56)
10161	#define DB_PUSH_END_DB_PATH_L2 (0x1ULL << 56)
10162	#define DB_PUSH_END_DB_PATH_ENGINE (0x2ULL << 56)
10163	#define DB_PUSH_END_DB_PATH_LAST DB_PUSH_END_DB_PATH_ENGINE
10164	#define DB_PUSH_END_DB_DEBUG_TRACE 0x800000000000000ULL
10165	#define DB_PUSH_END_DB_TYPE_MASK 0xf000000000000000ULL
10166	#define DB_PUSH_END_DB_TYPE_SFT 60
10167	#define DB_PUSH_END_DB_TYPE_PUSH_START (0xcULL << 60)
10168	#define DB_PUSH_END_DB_TYPE_PUSH_END (0xdULL << 60)
10169	#define DB_PUSH_END_DB_TYPE_LAST DB_PUSH_END_DB_TYPE_PUSH_END
10170	};
10171
10172	/* db_push_info (size:64b/8B) */
10173	struct db_push_info {
10174	u32 push_size_push_index;
10175	#define DB_PUSH_INFO_PUSH_INDEX_MASK 0xffffffUL
10176	#define DB_PUSH_INFO_PUSH_INDEX_SFT 0
10177	#define DB_PUSH_INFO_PUSH_SIZE_MASK 0x1f000000UL
10178	#define DB_PUSH_INFO_PUSH_SIZE_SFT 24
10179	u32 reserved32;
10180	};
10181
10182	/* fw_status_reg (size:32b/4B) */
10183	struct fw_status_reg {
10184	u32 fw_status;
10185	#define FW_STATUS_REG_CODE_MASK 0xffffUL
10186	#define FW_STATUS_REG_CODE_SFT 0
10187	#define FW_STATUS_REG_CODE_READY 0x8000UL
10188	#define FW_STATUS_REG_CODE_LAST FW_STATUS_REG_CODE_READY
10189	#define FW_STATUS_REG_IMAGE_DEGRADED 0x10000UL
10190	#define FW_STATUS_REG_RECOVERABLE 0x20000UL
10191	#define FW_STATUS_REG_CRASHDUMP_ONGOING 0x40000UL
10192	#define FW_STATUS_REG_CRASHDUMP_COMPLETE 0x80000UL
10193	#define FW_STATUS_REG_SHUTDOWN 0x100000UL
10194	#define FW_STATUS_REG_CRASHED_NO_MASTER 0x200000UL
10195	#define FW_STATUS_REG_RECOVERING 0x400000UL
10196	#define FW_STATUS_REG_MANU_DEBUG_STATUS 0x800000UL
10197	};
10198
10199	/* hcomm_status (size:64b/8B) */
10200	struct hcomm_status {
10201	u32 sig_ver;
10202	#define HCOMM_STATUS_VER_MASK 0xffUL
10203	#define HCOMM_STATUS_VER_SFT 0
10204	#define HCOMM_STATUS_VER_LATEST 0x1UL
10205	#define HCOMM_STATUS_VER_LAST HCOMM_STATUS_VER_LATEST
10206	#define HCOMM_STATUS_SIGNATURE_MASK 0xffffff00UL
10207	#define HCOMM_STATUS_SIGNATURE_SFT 8
10208	#define HCOMM_STATUS_SIGNATURE_VAL (0x484353UL << 8)
10209	#define HCOMM_STATUS_SIGNATURE_LAST HCOMM_STATUS_SIGNATURE_VAL
10210	u32 fw_status_loc;
10211	#define HCOMM_STATUS_TRUE_ADDR_SPACE_MASK 0x3UL
10212	#define HCOMM_STATUS_TRUE_ADDR_SPACE_SFT 0
10213	#define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_PCIE_CFG 0x0UL
10214	#define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_GRC 0x1UL
10215	#define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR0 0x2UL
10216	#define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 0x3UL
10217	#define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_LAST HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1
10218	#define HCOMM_STATUS_TRUE_OFFSET_MASK 0xfffffffcUL
10219	#define HCOMM_STATUS_TRUE_OFFSET_SFT 2
10220	};
10221	#define HCOMM_STATUS_STRUCT_LOC 0x31001F0UL
10222
10223	#endif /* _BNXT_HSI_H_ */
10224