1/*
2 * linux/drivers/net/ethernet/ethoc.c
3 *
4 * Copyright (C) 2007-2008 Avionic Design Development GmbH
5 * Copyright (C) 2008-2009 Avionic Design GmbH
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Written by Thierry Reding <thierry.reding@avionic-design.de>
12 */
13
14#include <linux/dma-mapping.h>
15#include <linux/etherdevice.h>
16#include <linux/clk.h>
17#include <linux/crc32.h>
18#include <linux/interrupt.h>
19#include <linux/io.h>
20#include <linux/mii.h>
21#include <linux/phy.h>
22#include <linux/platform_device.h>
23#include <linux/sched.h>
24#include <linux/slab.h>
25#include <linux/of.h>
26#include <linux/of_net.h>
27#include <linux/module.h>
28#include <net/ethoc.h>
29
30static int buffer_size = 0x8000; /* 32 KBytes */
31module_param(buffer_size, int, 0);
32MODULE_PARM_DESC(buffer_size, "DMA buffer allocation size");
33
34/* register offsets */
35#define MODER 0x00
36#define INT_SOURCE 0x04
37#define INT_MASK 0x08
38#define IPGT 0x0c
39#define IPGR1 0x10
40#define IPGR2 0x14
41#define PACKETLEN 0x18
42#define COLLCONF 0x1c
43#define TX_BD_NUM 0x20
44#define CTRLMODER 0x24
45#define MIIMODER 0x28
46#define MIICOMMAND 0x2c
47#define MIIADDRESS 0x30
48#define MIITX_DATA 0x34
49#define MIIRX_DATA 0x38
50#define MIISTATUS 0x3c
51#define MAC_ADDR0 0x40
52#define MAC_ADDR1 0x44
53#define ETH_HASH0 0x48
54#define ETH_HASH1 0x4c
55#define ETH_TXCTRL 0x50
56#define ETH_END 0x54
57
58/* mode register */
59#define MODER_RXEN (1 << 0) /* receive enable */
60#define MODER_TXEN (1 << 1) /* transmit enable */
61#define MODER_NOPRE (1 << 2) /* no preamble */
62#define MODER_BRO (1 << 3) /* broadcast address */
63#define MODER_IAM (1 << 4) /* individual address mode */
64#define MODER_PRO (1 << 5) /* promiscuous mode */
65#define MODER_IFG (1 << 6) /* interframe gap for incoming frames */
66#define MODER_LOOP (1 << 7) /* loopback */
67#define MODER_NBO (1 << 8) /* no back-off */
68#define MODER_EDE (1 << 9) /* excess defer enable */
69#define MODER_FULLD (1 << 10) /* full duplex */
70#define MODER_RESET (1 << 11) /* FIXME: reset (undocumented) */
71#define MODER_DCRC (1 << 12) /* delayed CRC enable */
72#define MODER_CRC (1 << 13) /* CRC enable */
73#define MODER_HUGE (1 << 14) /* huge packets enable */
74#define MODER_PAD (1 << 15) /* padding enabled */
75#define MODER_RSM (1 << 16) /* receive small packets */
76
77/* interrupt source and mask registers */
78#define INT_MASK_TXF (1 << 0) /* transmit frame */
79#define INT_MASK_TXE (1 << 1) /* transmit error */
80#define INT_MASK_RXF (1 << 2) /* receive frame */
81#define INT_MASK_RXE (1 << 3) /* receive error */
82#define INT_MASK_BUSY (1 << 4)
83#define INT_MASK_TXC (1 << 5) /* transmit control frame */
84#define INT_MASK_RXC (1 << 6) /* receive control frame */
85
86#define INT_MASK_TX (INT_MASK_TXF | INT_MASK_TXE)
87#define INT_MASK_RX (INT_MASK_RXF | INT_MASK_RXE)
88
89#define INT_MASK_ALL ( \
90 INT_MASK_TXF | INT_MASK_TXE | \
91 INT_MASK_RXF | INT_MASK_RXE | \
92 INT_MASK_TXC | INT_MASK_RXC | \
93 INT_MASK_BUSY \
94 )
95
96/* packet length register */
97#define PACKETLEN_MIN(min) (((min) & 0xffff) << 16)
98#define PACKETLEN_MAX(max) (((max) & 0xffff) << 0)
99#define PACKETLEN_MIN_MAX(min, max) (PACKETLEN_MIN(min) | \
100 PACKETLEN_MAX(max))
101
102/* transmit buffer number register */
103#define TX_BD_NUM_VAL(x) (((x) <= 0x80) ? (x) : 0x80)
104
105/* control module mode register */
106#define CTRLMODER_PASSALL (1 << 0) /* pass all receive frames */
107#define CTRLMODER_RXFLOW (1 << 1) /* receive control flow */
108#define CTRLMODER_TXFLOW (1 << 2) /* transmit control flow */
109
110/* MII mode register */
111#define MIIMODER_CLKDIV(x) ((x) & 0xfe) /* needs to be an even number */
112#define MIIMODER_NOPRE (1 << 8) /* no preamble */
113
114/* MII command register */
115#define MIICOMMAND_SCAN (1 << 0) /* scan status */
116#define MIICOMMAND_READ (1 << 1) /* read status */
117#define MIICOMMAND_WRITE (1 << 2) /* write control data */
118
119/* MII address register */
120#define MIIADDRESS_FIAD(x) (((x) & 0x1f) << 0)
121#define MIIADDRESS_RGAD(x) (((x) & 0x1f) << 8)
122#define MIIADDRESS_ADDR(phy, reg) (MIIADDRESS_FIAD(phy) | \
123 MIIADDRESS_RGAD(reg))
124
125/* MII transmit data register */
126#define MIITX_DATA_VAL(x) ((x) & 0xffff)
127
128/* MII receive data register */
129#define MIIRX_DATA_VAL(x) ((x) & 0xffff)
130
131/* MII status register */
132#define MIISTATUS_LINKFAIL (1 << 0)
133#define MIISTATUS_BUSY (1 << 1)
134#define MIISTATUS_INVALID (1 << 2)
135
136/* TX buffer descriptor */
137#define TX_BD_CS (1 << 0) /* carrier sense lost */
138#define TX_BD_DF (1 << 1) /* defer indication */
139#define TX_BD_LC (1 << 2) /* late collision */
140#define TX_BD_RL (1 << 3) /* retransmission limit */
141#define TX_BD_RETRY_MASK (0x00f0)
142#define TX_BD_RETRY(x) (((x) & 0x00f0) >> 4)
143#define TX_BD_UR (1 << 8) /* transmitter underrun */
144#define TX_BD_CRC (1 << 11) /* TX CRC enable */
145#define TX_BD_PAD (1 << 12) /* pad enable for short packets */
146#define TX_BD_WRAP (1 << 13)
147#define TX_BD_IRQ (1 << 14) /* interrupt request enable */
148#define TX_BD_READY (1 << 15) /* TX buffer ready */
149#define TX_BD_LEN(x) (((x) & 0xffff) << 16)
150#define TX_BD_LEN_MASK (0xffff << 16)
151
152#define TX_BD_STATS (TX_BD_CS | TX_BD_DF | TX_BD_LC | \
153 TX_BD_RL | TX_BD_RETRY_MASK | TX_BD_UR)
154
155/* RX buffer descriptor */
156#define RX_BD_LC (1 << 0) /* late collision */
157#define RX_BD_CRC (1 << 1) /* RX CRC error */
158#define RX_BD_SF (1 << 2) /* short frame */
159#define RX_BD_TL (1 << 3) /* too long */
160#define RX_BD_DN (1 << 4) /* dribble nibble */
161#define RX_BD_IS (1 << 5) /* invalid symbol */
162#define RX_BD_OR (1 << 6) /* receiver overrun */
163#define RX_BD_MISS (1 << 7)
164#define RX_BD_CF (1 << 8) /* control frame */
165#define RX_BD_WRAP (1 << 13)
166#define RX_BD_IRQ (1 << 14) /* interrupt request enable */
167#define RX_BD_EMPTY (1 << 15)
168#define RX_BD_LEN(x) (((x) & 0xffff) << 16)
169
170#define RX_BD_STATS (RX_BD_LC | RX_BD_CRC | RX_BD_SF | RX_BD_TL | \
171 RX_BD_DN | RX_BD_IS | RX_BD_OR | RX_BD_MISS)
172
173#define ETHOC_BUFSIZ 1536
174#define ETHOC_ZLEN 64
175#define ETHOC_BD_BASE 0x400
176#define ETHOC_TIMEOUT (HZ / 2)
177#define ETHOC_MII_TIMEOUT (1 + (HZ / 5))
178
179/**
180 * struct ethoc - driver-private device structure
181 * @iobase: pointer to I/O memory region
182 * @membase: pointer to buffer memory region
183 * @num_bd: number of buffer descriptors
184 * @num_tx: number of send buffers
185 * @cur_tx: last send buffer written
186 * @dty_tx: last buffer actually sent
187 * @num_rx: number of receive buffers
188 * @cur_rx: current receive buffer
189 * @vma: pointer to array of virtual memory addresses for buffers
190 * @netdev: pointer to network device structure
191 * @napi: NAPI structure
192 * @msg_enable: device state flags
193 * @lock: device lock
194 * @mdio: MDIO bus for PHY access
195 * @phy_id: address of attached PHY
196 */
197struct ethoc {
198 void __iomem *iobase;
199 void __iomem *membase;
200 bool big_endian;
201
202 unsigned int num_bd;
203 unsigned int num_tx;
204 unsigned int cur_tx;
205 unsigned int dty_tx;
206
207 unsigned int num_rx;
208 unsigned int cur_rx;
209
210 void **vma;
211
212 struct net_device *netdev;
213 struct napi_struct napi;
214 u32 msg_enable;
215
216 spinlock_t lock;
217
218 struct mii_bus *mdio;
219 struct clk *clk;
220 s8 phy_id;
221
222 int old_link;
223 int old_duplex;
224};
225
226/**
227 * struct ethoc_bd - buffer descriptor
228 * @stat: buffer statistics
229 * @addr: physical memory address
230 */
231struct ethoc_bd {
232 u32 stat;
233 u32 addr;
234};
235
236static inline u32 ethoc_read(struct ethoc *dev, loff_t offset)
237{
238 if (dev->big_endian)
239 return ioread32be(dev->iobase + offset);
240 else
241 return ioread32(dev->iobase + offset);
242}
243
244static inline void ethoc_write(struct ethoc *dev, loff_t offset, u32 data)
245{
246 if (dev->big_endian)
247 iowrite32be(data, dev->iobase + offset);
248 else
249 iowrite32(data, dev->iobase + offset);
250}
251
252static inline void ethoc_read_bd(struct ethoc *dev, int index,
253 struct ethoc_bd *bd)
254{
255 loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
256 bd->stat = ethoc_read(dev, offset + 0);
257 bd->addr = ethoc_read(dev, offset + 4);
258}
259
260static inline void ethoc_write_bd(struct ethoc *dev, int index,
261 const struct ethoc_bd *bd)
262{
263 loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
264 ethoc_write(dev, offset + 0, bd->stat);
265 ethoc_write(dev, offset + 4, bd->addr);
266}
267
268static inline void ethoc_enable_irq(struct ethoc *dev, u32 mask)
269{
270 u32 imask = ethoc_read(dev, INT_MASK);
271 imask |= mask;
272 ethoc_write(dev, INT_MASK, imask);
273}
274
275static inline void ethoc_disable_irq(struct ethoc *dev, u32 mask)
276{
277 u32 imask = ethoc_read(dev, INT_MASK);
278 imask &= ~mask;
279 ethoc_write(dev, INT_MASK, imask);
280}
281
282static inline void ethoc_ack_irq(struct ethoc *dev, u32 mask)
283{
284 ethoc_write(dev, INT_SOURCE, mask);
285}
286
287static inline void ethoc_enable_rx_and_tx(struct ethoc *dev)
288{
289 u32 mode = ethoc_read(dev, MODER);
290 mode |= MODER_RXEN | MODER_TXEN;
291 ethoc_write(dev, MODER, mode);
292}
293
294static inline void ethoc_disable_rx_and_tx(struct ethoc *dev)
295{
296 u32 mode = ethoc_read(dev, MODER);
297 mode &= ~(MODER_RXEN | MODER_TXEN);
298 ethoc_write(dev, MODER, mode);
299}
300
301static int ethoc_init_ring(struct ethoc *dev, unsigned long mem_start)
302{
303 struct ethoc_bd bd;
304 int i;
305 void *vma;
306
307 dev->cur_tx = 0;
308 dev->dty_tx = 0;
309 dev->cur_rx = 0;
310
311 ethoc_write(dev, TX_BD_NUM, dev->num_tx);
312
313 /* setup transmission buffers */
314 bd.addr = mem_start;
315 bd.stat = TX_BD_IRQ | TX_BD_CRC;
316 vma = dev->membase;
317
318 for (i = 0; i < dev->num_tx; i++) {
319 if (i == dev->num_tx - 1)
320 bd.stat |= TX_BD_WRAP;
321
322 ethoc_write_bd(dev, i, &bd);
323 bd.addr += ETHOC_BUFSIZ;
324
325 dev->vma[i] = vma;
326 vma += ETHOC_BUFSIZ;
327 }
328
329 bd.stat = RX_BD_EMPTY | RX_BD_IRQ;
330
331 for (i = 0; i < dev->num_rx; i++) {
332 if (i == dev->num_rx - 1)
333 bd.stat |= RX_BD_WRAP;
334
335 ethoc_write_bd(dev, dev->num_tx + i, &bd);
336 bd.addr += ETHOC_BUFSIZ;
337
338 dev->vma[dev->num_tx + i] = vma;
339 vma += ETHOC_BUFSIZ;
340 }
341
342 return 0;
343}
344
345static int ethoc_reset(struct ethoc *dev)
346{
347 u32 mode;
348
349 /* TODO: reset controller? */
350
351 ethoc_disable_rx_and_tx(dev);
352
353 /* TODO: setup registers */
354
355 /* enable FCS generation and automatic padding */
356 mode = ethoc_read(dev, MODER);
357 mode |= MODER_CRC | MODER_PAD;
358 ethoc_write(dev, MODER, mode);
359
360 /* set full-duplex mode */
361 mode = ethoc_read(dev, MODER);
362 mode |= MODER_FULLD;
363 ethoc_write(dev, MODER, mode);
364 ethoc_write(dev, IPGT, 0x15);
365
366 ethoc_ack_irq(dev, INT_MASK_ALL);
367 ethoc_enable_irq(dev, INT_MASK_ALL);
368 ethoc_enable_rx_and_tx(dev);
369 return 0;
370}
371
372static unsigned int ethoc_update_rx_stats(struct ethoc *dev,
373 struct ethoc_bd *bd)
374{
375 struct net_device *netdev = dev->netdev;
376 unsigned int ret = 0;
377
378 if (bd->stat & RX_BD_TL) {
379 dev_err(&netdev->dev, "RX: frame too long\n");
380 netdev->stats.rx_length_errors++;
381 ret++;
382 }
383
384 if (bd->stat & RX_BD_SF) {
385 dev_err(&netdev->dev, "RX: frame too short\n");
386 netdev->stats.rx_length_errors++;
387 ret++;
388 }
389
390 if (bd->stat & RX_BD_DN) {
391 dev_err(&netdev->dev, "RX: dribble nibble\n");
392 netdev->stats.rx_frame_errors++;
393 }
394
395 if (bd->stat & RX_BD_CRC) {
396 dev_err(&netdev->dev, "RX: wrong CRC\n");
397 netdev->stats.rx_crc_errors++;
398 ret++;
399 }
400
401 if (bd->stat & RX_BD_OR) {
402 dev_err(&netdev->dev, "RX: overrun\n");
403 netdev->stats.rx_over_errors++;
404 ret++;
405 }
406
407 if (bd->stat & RX_BD_MISS)
408 netdev->stats.rx_missed_errors++;
409
410 if (bd->stat & RX_BD_LC) {
411 dev_err(&netdev->dev, "RX: late collision\n");
412 netdev->stats.collisions++;
413 ret++;
414 }
415
416 return ret;
417}
418
419static int ethoc_rx(struct net_device *dev, int limit)
420{
421 struct ethoc *priv = netdev_priv(dev);
422 int count;
423
424 for (count = 0; count < limit; ++count) {
425 unsigned int entry;
426 struct ethoc_bd bd;
427
428 entry = priv->num_tx + priv->cur_rx;
429 ethoc_read_bd(priv, entry, &bd);
430 if (bd.stat & RX_BD_EMPTY) {
431 ethoc_ack_irq(priv, INT_MASK_RX);
432 /* If packet (interrupt) came in between checking
433 * BD_EMTPY and clearing the interrupt source, then we
434 * risk missing the packet as the RX interrupt won't
435 * trigger right away when we reenable it; hence, check
436 * BD_EMTPY here again to make sure there isn't such a
437 * packet waiting for us...
438 */
439 ethoc_read_bd(priv, entry, &bd);
440 if (bd.stat & RX_BD_EMPTY)
441 break;
442 }
443
444 if (ethoc_update_rx_stats(priv, &bd) == 0) {
445 int size = bd.stat >> 16;
446 struct sk_buff *skb;
447
448 size -= 4; /* strip the CRC */
449 skb = netdev_alloc_skb_ip_align(dev, size);
450
451 if (likely(skb)) {
452 void *src = priv->vma[entry];
453 memcpy_fromio(skb_put(skb, size), src, size);
454 skb->protocol = eth_type_trans(skb, dev);
455 dev->stats.rx_packets++;
456 dev->stats.rx_bytes += size;
457 netif_receive_skb(skb);
458 } else {
459 if (net_ratelimit())
460 dev_warn(&dev->dev,
461 "low on memory - packet dropped\n");
462
463 dev->stats.rx_dropped++;
464 break;
465 }
466 }
467
468 /* clear the buffer descriptor so it can be reused */
469 bd.stat &= ~RX_BD_STATS;
470 bd.stat |= RX_BD_EMPTY;
471 ethoc_write_bd(priv, entry, &bd);
472 if (++priv->cur_rx == priv->num_rx)
473 priv->cur_rx = 0;
474 }
475
476 return count;
477}
478
479static void ethoc_update_tx_stats(struct ethoc *dev, struct ethoc_bd *bd)
480{
481 struct net_device *netdev = dev->netdev;
482
483 if (bd->stat & TX_BD_LC) {
484 dev_err(&netdev->dev, "TX: late collision\n");
485 netdev->stats.tx_window_errors++;
486 }
487
488 if (bd->stat & TX_BD_RL) {
489 dev_err(&netdev->dev, "TX: retransmit limit\n");
490 netdev->stats.tx_aborted_errors++;
491 }
492
493 if (bd->stat & TX_BD_UR) {
494 dev_err(&netdev->dev, "TX: underrun\n");
495 netdev->stats.tx_fifo_errors++;
496 }
497
498 if (bd->stat & TX_BD_CS) {
499 dev_err(&netdev->dev, "TX: carrier sense lost\n");
500 netdev->stats.tx_carrier_errors++;
501 }
502
503 if (bd->stat & TX_BD_STATS)
504 netdev->stats.tx_errors++;
505
506 netdev->stats.collisions += (bd->stat >> 4) & 0xf;
507 netdev->stats.tx_bytes += bd->stat >> 16;
508 netdev->stats.tx_packets++;
509}
510
511static int ethoc_tx(struct net_device *dev, int limit)
512{
513 struct ethoc *priv = netdev_priv(dev);
514 int count;
515 struct ethoc_bd bd;
516
517 for (count = 0; count < limit; ++count) {
518 unsigned int entry;
519
520 entry = priv->dty_tx & (priv->num_tx-1);
521
522 ethoc_read_bd(priv, entry, &bd);
523
524 if (bd.stat & TX_BD_READY || (priv->dty_tx == priv->cur_tx)) {
525 ethoc_ack_irq(priv, INT_MASK_TX);
526 /* If interrupt came in between reading in the BD
527 * and clearing the interrupt source, then we risk
528 * missing the event as the TX interrupt won't trigger
529 * right away when we reenable it; hence, check
530 * BD_EMPTY here again to make sure there isn't such an
531 * event pending...
532 */
533 ethoc_read_bd(priv, entry, &bd);
534 if (bd.stat & TX_BD_READY ||
535 (priv->dty_tx == priv->cur_tx))
536 break;
537 }
538
539 ethoc_update_tx_stats(priv, &bd);
540 priv->dty_tx++;
541 }
542
543 if ((priv->cur_tx - priv->dty_tx) <= (priv->num_tx / 2))
544 netif_wake_queue(dev);
545
546 return count;
547}
548
549static irqreturn_t ethoc_interrupt(int irq, void *dev_id)
550{
551 struct net_device *dev = dev_id;
552 struct ethoc *priv = netdev_priv(dev);
553 u32 pending;
554 u32 mask;
555
556 /* Figure out what triggered the interrupt...
557 * The tricky bit here is that the interrupt source bits get
558 * set in INT_SOURCE for an event regardless of whether that
559 * event is masked or not. Thus, in order to figure out what
560 * triggered the interrupt, we need to remove the sources
561 * for all events that are currently masked. This behaviour
562 * is not particularly well documented but reasonable...
563 */
564 mask = ethoc_read(priv, INT_MASK);
565 pending = ethoc_read(priv, INT_SOURCE);
566 pending &= mask;
567
568 if (unlikely(pending == 0))
569 return IRQ_NONE;
570
571 ethoc_ack_irq(priv, pending);
572
573 /* We always handle the dropped packet interrupt */
574 if (pending & INT_MASK_BUSY) {
575 dev_dbg(&dev->dev, "packet dropped\n");
576 dev->stats.rx_dropped++;
577 }
578
579 /* Handle receive/transmit event by switching to polling */
580 if (pending & (INT_MASK_TX | INT_MASK_RX)) {
581 ethoc_disable_irq(priv, INT_MASK_TX | INT_MASK_RX);
582 napi_schedule(&priv->napi);
583 }
584
585 return IRQ_HANDLED;
586}
587
588static int ethoc_get_mac_address(struct net_device *dev, void *addr)
589{
590 struct ethoc *priv = netdev_priv(dev);
591 u8 *mac = (u8 *)addr;
592 u32 reg;
593
594 reg = ethoc_read(priv, MAC_ADDR0);
595 mac[2] = (reg >> 24) & 0xff;
596 mac[3] = (reg >> 16) & 0xff;
597 mac[4] = (reg >> 8) & 0xff;
598 mac[5] = (reg >> 0) & 0xff;
599
600 reg = ethoc_read(priv, MAC_ADDR1);
601 mac[0] = (reg >> 8) & 0xff;
602 mac[1] = (reg >> 0) & 0xff;
603
604 return 0;
605}
606
607static int ethoc_poll(struct napi_struct *napi, int budget)
608{
609 struct ethoc *priv = container_of(napi, struct ethoc, napi);
610 int rx_work_done = 0;
611 int tx_work_done = 0;
612
613 rx_work_done = ethoc_rx(priv->netdev, budget);
614 tx_work_done = ethoc_tx(priv->netdev, budget);
615
616 if (rx_work_done < budget && tx_work_done < budget) {
617 napi_complete_done(napi, rx_work_done);
618 ethoc_enable_irq(priv, INT_MASK_TX | INT_MASK_RX);
619 }
620
621 return rx_work_done;
622}
623
624static int ethoc_mdio_read(struct mii_bus *bus, int phy, int reg)
625{
626 struct ethoc *priv = bus->priv;
627 int i;
628
629 ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg));
630 ethoc_write(priv, MIICOMMAND, MIICOMMAND_READ);
631
632 for (i = 0; i < 5; i++) {
633 u32 status = ethoc_read(priv, MIISTATUS);
634 if (!(status & MIISTATUS_BUSY)) {
635 u32 data = ethoc_read(priv, MIIRX_DATA);
636 /* reset MII command register */
637 ethoc_write(priv, MIICOMMAND, 0);
638 return data;
639 }
640 usleep_range(100, 200);
641 }
642
643 return -EBUSY;
644}
645
646static int ethoc_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
647{
648 struct ethoc *priv = bus->priv;
649 int i;
650
651 ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg));
652 ethoc_write(priv, MIITX_DATA, val);
653 ethoc_write(priv, MIICOMMAND, MIICOMMAND_WRITE);
654
655 for (i = 0; i < 5; i++) {
656 u32 stat = ethoc_read(priv, MIISTATUS);
657 if (!(stat & MIISTATUS_BUSY)) {
658 /* reset MII command register */
659 ethoc_write(priv, MIICOMMAND, 0);
660 return 0;
661 }
662 usleep_range(100, 200);
663 }
664
665 return -EBUSY;
666}
667
668static void ethoc_mdio_poll(struct net_device *dev)
669{
670 struct ethoc *priv = netdev_priv(dev);
671 struct phy_device *phydev = dev->phydev;
672 bool changed = false;
673 u32 mode;
674
675 if (priv->old_link != phydev->link) {
676 changed = true;
677 priv->old_link = phydev->link;
678 }
679
680 if (priv->old_duplex != phydev->duplex) {
681 changed = true;
682 priv->old_duplex = phydev->duplex;
683 }
684
685 if (!changed)
686 return;
687
688 mode = ethoc_read(priv, MODER);
689 if (phydev->duplex == DUPLEX_FULL)
690 mode |= MODER_FULLD;
691 else
692 mode &= ~MODER_FULLD;
693 ethoc_write(priv, MODER, mode);
694
695 phy_print_status(phydev);
696}
697
698static int ethoc_mdio_probe(struct net_device *dev)
699{
700 struct ethoc *priv = netdev_priv(dev);
701 struct phy_device *phy;
702 int err;
703
704 if (priv->phy_id != -1)
705 phy = mdiobus_get_phy(priv->mdio, priv->phy_id);
706 else
707 phy = phy_find_first(priv->mdio);
708
709 if (!phy) {
710 dev_err(&dev->dev, "no PHY found\n");
711 return -ENXIO;
712 }
713
714 priv->old_duplex = -1;
715 priv->old_link = -1;
716
717 err = phy_connect_direct(dev, phy, ethoc_mdio_poll,
718 PHY_INTERFACE_MODE_GMII);
719 if (err) {
720 dev_err(&dev->dev, "could not attach to PHY\n");
721 return err;
722 }
723
724 phy_set_max_speed(phy, SPEED_100);
725
726 return 0;
727}
728
729static int ethoc_open(struct net_device *dev)
730{
731 struct ethoc *priv = netdev_priv(dev);
732 int ret;
733
734 ret = request_irq(dev->irq, ethoc_interrupt, IRQF_SHARED,
735 dev->name, dev);
736 if (ret)
737 return ret;
738
739 napi_enable(&priv->napi);
740
741 ethoc_init_ring(priv, dev->mem_start);
742 ethoc_reset(priv);
743
744 if (netif_queue_stopped(dev)) {
745 dev_dbg(&dev->dev, " resuming queue\n");
746 netif_wake_queue(dev);
747 } else {
748 dev_dbg(&dev->dev, " starting queue\n");
749 netif_start_queue(dev);
750 }
751
752 priv->old_link = -1;
753 priv->old_duplex = -1;
754
755 phy_start(dev->phydev);
756
757 if (netif_msg_ifup(priv)) {
758 dev_info(&dev->dev, "I/O: %08lx Memory: %08lx-%08lx\n",
759 dev->base_addr, dev->mem_start, dev->mem_end);
760 }
761
762 return 0;
763}
764
765static int ethoc_stop(struct net_device *dev)
766{
767 struct ethoc *priv = netdev_priv(dev);
768
769 napi_disable(&priv->napi);
770
771 if (dev->phydev)
772 phy_stop(dev->phydev);
773
774 ethoc_disable_rx_and_tx(priv);
775 free_irq(dev->irq, dev);
776
777 if (!netif_queue_stopped(dev))
778 netif_stop_queue(dev);
779
780 return 0;
781}
782
783static int ethoc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
784{
785 struct ethoc *priv = netdev_priv(dev);
786 struct mii_ioctl_data *mdio = if_mii(ifr);
787 struct phy_device *phy = NULL;
788
789 if (!netif_running(dev))
790 return -EINVAL;
791
792 if (cmd != SIOCGMIIPHY) {
793 if (mdio->phy_id >= PHY_MAX_ADDR)
794 return -ERANGE;
795
796 phy = mdiobus_get_phy(priv->mdio, mdio->phy_id);
797 if (!phy)
798 return -ENODEV;
799 } else {
800 phy = dev->phydev;
801 }
802
803 return phy_mii_ioctl(phy, ifr, cmd);
804}
805
806static void ethoc_do_set_mac_address(struct net_device *dev)
807{
808 struct ethoc *priv = netdev_priv(dev);
809 unsigned char *mac = dev->dev_addr;
810
811 ethoc_write(priv, MAC_ADDR0, (mac[2] << 24) | (mac[3] << 16) |
812 (mac[4] << 8) | (mac[5] << 0));
813 ethoc_write(priv, MAC_ADDR1, (mac[0] << 8) | (mac[1] << 0));
814}
815
816static int ethoc_set_mac_address(struct net_device *dev, void *p)
817{
818 const struct sockaddr *addr = p;
819
820 if (!is_valid_ether_addr(addr->sa_data))
821 return -EADDRNOTAVAIL;
822 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
823 ethoc_do_set_mac_address(dev);
824 return 0;
825}
826
827static void ethoc_set_multicast_list(struct net_device *dev)
828{
829 struct ethoc *priv = netdev_priv(dev);
830 u32 mode = ethoc_read(priv, MODER);
831 struct netdev_hw_addr *ha;
832 u32 hash[2] = { 0, 0 };
833
834 /* set loopback mode if requested */
835 if (dev->flags & IFF_LOOPBACK)
836 mode |= MODER_LOOP;
837 else
838 mode &= ~MODER_LOOP;
839
840 /* receive broadcast frames if requested */
841 if (dev->flags & IFF_BROADCAST)
842 mode &= ~MODER_BRO;
843 else
844 mode |= MODER_BRO;
845
846 /* enable promiscuous mode if requested */
847 if (dev->flags & IFF_PROMISC)
848 mode |= MODER_PRO;
849 else
850 mode &= ~MODER_PRO;
851
852 ethoc_write(priv, MODER, mode);
853
854 /* receive multicast frames */
855 if (dev->flags & IFF_ALLMULTI) {
856 hash[0] = 0xffffffff;
857 hash[1] = 0xffffffff;
858 } else {
859 netdev_for_each_mc_addr(ha, dev) {
860 u32 crc = ether_crc(ETH_ALEN, ha->addr);
861 int bit = (crc >> 26) & 0x3f;
862 hash[bit >> 5] |= 1 << (bit & 0x1f);
863 }
864 }
865
866 ethoc_write(priv, ETH_HASH0, hash[0]);
867 ethoc_write(priv, ETH_HASH1, hash[1]);
868}
869
870static int ethoc_change_mtu(struct net_device *dev, int new_mtu)
871{
872 return -ENOSYS;
873}
874
875static void ethoc_tx_timeout(struct net_device *dev)
876{
877 struct ethoc *priv = netdev_priv(dev);
878 u32 pending = ethoc_read(priv, INT_SOURCE);
879 if (likely(pending))
880 ethoc_interrupt(dev->irq, dev);
881}
882
883static netdev_tx_t ethoc_start_xmit(struct sk_buff *skb, struct net_device *dev)
884{
885 struct ethoc *priv = netdev_priv(dev);
886 struct ethoc_bd bd;
887 unsigned int entry;
888 void *dest;
889
890 if (skb_put_padto(skb, ETHOC_ZLEN)) {
891 dev->stats.tx_errors++;
892 goto out_no_free;
893 }
894
895 if (unlikely(skb->len > ETHOC_BUFSIZ)) {
896 dev->stats.tx_errors++;
897 goto out;
898 }
899
900 entry = priv->cur_tx % priv->num_tx;
901 spin_lock_irq(&priv->lock);
902 priv->cur_tx++;
903
904 ethoc_read_bd(priv, entry, &bd);
905 if (unlikely(skb->len < ETHOC_ZLEN))
906 bd.stat |= TX_BD_PAD;
907 else
908 bd.stat &= ~TX_BD_PAD;
909
910 dest = priv->vma[entry];
911 memcpy_toio(dest, skb->data, skb->len);
912
913 bd.stat &= ~(TX_BD_STATS | TX_BD_LEN_MASK);
914 bd.stat |= TX_BD_LEN(skb->len);
915 ethoc_write_bd(priv, entry, &bd);
916
917 bd.stat |= TX_BD_READY;
918 ethoc_write_bd(priv, entry, &bd);
919
920 if (priv->cur_tx == (priv->dty_tx + priv->num_tx)) {
921 dev_dbg(&dev->dev, "stopping queue\n");
922 netif_stop_queue(dev);
923 }
924
925 spin_unlock_irq(&priv->lock);
926 skb_tx_timestamp(skb);
927out:
928 dev_kfree_skb(skb);
929out_no_free:
930 return NETDEV_TX_OK;
931}
932
933static int ethoc_get_regs_len(struct net_device *netdev)
934{
935 return ETH_END;
936}
937
938static void ethoc_get_regs(struct net_device *dev, struct ethtool_regs *regs,
939 void *p)
940{
941 struct ethoc *priv = netdev_priv(dev);
942 u32 *regs_buff = p;
943 unsigned i;
944
945 regs->version = 0;
946 for (i = 0; i < ETH_END / sizeof(u32); ++i)
947 regs_buff[i] = ethoc_read(priv, i * sizeof(u32));
948}
949
950static void ethoc_get_ringparam(struct net_device *dev,
951 struct ethtool_ringparam *ring)
952{
953 struct ethoc *priv = netdev_priv(dev);
954
955 ring->rx_max_pending = priv->num_bd - 1;
956 ring->rx_mini_max_pending = 0;
957 ring->rx_jumbo_max_pending = 0;
958 ring->tx_max_pending = priv->num_bd - 1;
959
960 ring->rx_pending = priv->num_rx;
961 ring->rx_mini_pending = 0;
962 ring->rx_jumbo_pending = 0;
963 ring->tx_pending = priv->num_tx;
964}
965
966static int ethoc_set_ringparam(struct net_device *dev,
967 struct ethtool_ringparam *ring)
968{
969 struct ethoc *priv = netdev_priv(dev);
970
971 if (ring->tx_pending < 1 || ring->rx_pending < 1 ||
972 ring->tx_pending + ring->rx_pending > priv->num_bd)
973 return -EINVAL;
974 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
975 return -EINVAL;
976
977 if (netif_running(dev)) {
978 netif_tx_disable(dev);
979 ethoc_disable_rx_and_tx(priv);
980 ethoc_disable_irq(priv, INT_MASK_TX | INT_MASK_RX);
981 synchronize_irq(dev->irq);
982 }
983
984 priv->num_tx = rounddown_pow_of_two(ring->tx_pending);
985 priv->num_rx = ring->rx_pending;
986 ethoc_init_ring(priv, dev->mem_start);
987
988 if (netif_running(dev)) {
989 ethoc_enable_irq(priv, INT_MASK_TX | INT_MASK_RX);
990 ethoc_enable_rx_and_tx(priv);
991 netif_wake_queue(dev);
992 }
993 return 0;
994}
995
996static const struct ethtool_ops ethoc_ethtool_ops = {
997 .get_regs_len = ethoc_get_regs_len,
998 .get_regs = ethoc_get_regs,
999 .nway_reset = phy_ethtool_nway_reset,
1000 .get_link = ethtool_op_get_link,
1001 .get_ringparam = ethoc_get_ringparam,
1002 .set_ringparam = ethoc_set_ringparam,
1003 .get_ts_info = ethtool_op_get_ts_info,
1004 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1005 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1006};
1007
1008static const struct net_device_ops ethoc_netdev_ops = {
1009 .ndo_open = ethoc_open,
1010 .ndo_stop = ethoc_stop,
1011 .ndo_do_ioctl = ethoc_ioctl,
1012 .ndo_set_mac_address = ethoc_set_mac_address,
1013 .ndo_set_rx_mode = ethoc_set_multicast_list,
1014 .ndo_change_mtu = ethoc_change_mtu,
1015 .ndo_tx_timeout = ethoc_tx_timeout,
1016 .ndo_start_xmit = ethoc_start_xmit,
1017};
1018
1019/**
1020 * ethoc_probe - initialize OpenCores ethernet MAC
1021 * pdev: platform device
1022 */
1023static int ethoc_probe(struct platform_device *pdev)
1024{
1025 struct net_device *netdev = NULL;
1026 struct resource *res = NULL;
1027 struct resource *mmio = NULL;
1028 struct resource *mem = NULL;
1029 struct ethoc *priv = NULL;
1030 int num_bd;
1031 int ret = 0;
1032 struct ethoc_platform_data *pdata = dev_get_platdata(&pdev->dev);
1033 u32 eth_clkfreq = pdata ? pdata->eth_clkfreq : 0;
1034
1035 /* allocate networking device */
1036 netdev = alloc_etherdev(sizeof(struct ethoc));
1037 if (!netdev) {
1038 ret = -ENOMEM;
1039 goto out;
1040 }
1041
1042 SET_NETDEV_DEV(netdev, &pdev->dev);
1043 platform_set_drvdata(pdev, netdev);
1044
1045 /* obtain I/O memory space */
1046 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1047 if (!res) {
1048 dev_err(&pdev->dev, "cannot obtain I/O memory space\n");
1049 ret = -ENXIO;
1050 goto free;
1051 }
1052
1053 mmio = devm_request_mem_region(&pdev->dev, res->start,
1054 resource_size(res), res->name);
1055 if (!mmio) {
1056 dev_err(&pdev->dev, "cannot request I/O memory space\n");
1057 ret = -ENXIO;
1058 goto free;
1059 }
1060
1061 netdev->base_addr = mmio->start;
1062
1063 /* obtain buffer memory space */
1064 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1065 if (res) {
1066 mem = devm_request_mem_region(&pdev->dev, res->start,
1067 resource_size(res), res->name);
1068 if (!mem) {
1069 dev_err(&pdev->dev, "cannot request memory space\n");
1070 ret = -ENXIO;
1071 goto free;
1072 }
1073
1074 netdev->mem_start = mem->start;
1075 netdev->mem_end = mem->end;
1076 }
1077
1078
1079 /* obtain device IRQ number */
1080 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1081 if (!res) {
1082 dev_err(&pdev->dev, "cannot obtain IRQ\n");
1083 ret = -ENXIO;
1084 goto free;
1085 }
1086
1087 netdev->irq = res->start;
1088
1089 /* setup driver-private data */
1090 priv = netdev_priv(netdev);
1091 priv->netdev = netdev;
1092
1093 priv->iobase = devm_ioremap_nocache(&pdev->dev, netdev->base_addr,
1094 resource_size(mmio));
1095 if (!priv->iobase) {
1096 dev_err(&pdev->dev, "cannot remap I/O memory space\n");
1097 ret = -ENXIO;
1098 goto free;
1099 }
1100
1101 if (netdev->mem_end) {
1102 priv->membase = devm_ioremap_nocache(&pdev->dev,
1103 netdev->mem_start, resource_size(mem));
1104 if (!priv->membase) {
1105 dev_err(&pdev->dev, "cannot remap memory space\n");
1106 ret = -ENXIO;
1107 goto free;
1108 }
1109 } else {
1110 /* Allocate buffer memory */
1111 priv->membase = dmam_alloc_coherent(&pdev->dev,
1112 buffer_size, (void *)&netdev->mem_start,
1113 GFP_KERNEL);
1114 if (!priv->membase) {
1115 dev_err(&pdev->dev, "cannot allocate %dB buffer\n",
1116 buffer_size);
1117 ret = -ENOMEM;
1118 goto free;
1119 }
1120 netdev->mem_end = netdev->mem_start + buffer_size;
1121 }
1122
1123 priv->big_endian = pdata ? pdata->big_endian :
1124 of_device_is_big_endian(pdev->dev.of_node);
1125
1126 /* calculate the number of TX/RX buffers, maximum 128 supported */
1127 num_bd = min_t(unsigned int,
1128 128, (netdev->mem_end - netdev->mem_start + 1) / ETHOC_BUFSIZ);
1129 if (num_bd < 4) {
1130 ret = -ENODEV;
1131 goto free;
1132 }
1133 priv->num_bd = num_bd;
1134 /* num_tx must be a power of two */
1135 priv->num_tx = rounddown_pow_of_two(num_bd >> 1);
1136 priv->num_rx = num_bd - priv->num_tx;
1137
1138 dev_dbg(&pdev->dev, "ethoc: num_tx: %d num_rx: %d\n",
1139 priv->num_tx, priv->num_rx);
1140
1141 priv->vma = devm_kcalloc(&pdev->dev, num_bd, sizeof(void *),
1142 GFP_KERNEL);
1143 if (!priv->vma) {
1144 ret = -ENOMEM;
1145 goto free;
1146 }
1147
1148 /* Allow the platform setup code to pass in a MAC address. */
1149 if (pdata) {
1150 ether_addr_copy(netdev->dev_addr, pdata->hwaddr);
1151 priv->phy_id = pdata->phy_id;
1152 } else {
1153 const void *mac;
1154
1155 mac = of_get_mac_address(pdev->dev.of_node);
1156 if (mac)
1157 ether_addr_copy(netdev->dev_addr, mac);
1158 priv->phy_id = -1;
1159 }
1160
1161 /* Check that the given MAC address is valid. If it isn't, read the
1162 * current MAC from the controller.
1163 */
1164 if (!is_valid_ether_addr(netdev->dev_addr))
1165 ethoc_get_mac_address(netdev, netdev->dev_addr);
1166
1167 /* Check the MAC again for validity, if it still isn't choose and
1168 * program a random one.
1169 */
1170 if (!is_valid_ether_addr(netdev->dev_addr))
1171 eth_hw_addr_random(netdev);
1172
1173 ethoc_do_set_mac_address(netdev);
1174
1175 /* Allow the platform setup code to adjust MII management bus clock. */
1176 if (!eth_clkfreq) {
1177 struct clk *clk = devm_clk_get(&pdev->dev, NULL);
1178
1179 if (!IS_ERR(clk)) {
1180 priv->clk = clk;
1181 clk_prepare_enable(clk);
1182 eth_clkfreq = clk_get_rate(clk);
1183 }
1184 }
1185 if (eth_clkfreq) {
1186 u32 clkdiv = MIIMODER_CLKDIV(eth_clkfreq / 2500000 + 1);
1187
1188 if (!clkdiv)
1189 clkdiv = 2;
1190 dev_dbg(&pdev->dev, "setting MII clkdiv to %u\n", clkdiv);
1191 ethoc_write(priv, MIIMODER,
1192 (ethoc_read(priv, MIIMODER) & MIIMODER_NOPRE) |
1193 clkdiv);
1194 }
1195
1196 /* register MII bus */
1197 priv->mdio = mdiobus_alloc();
1198 if (!priv->mdio) {
1199 ret = -ENOMEM;
1200 goto free2;
1201 }
1202
1203 priv->mdio->name = "ethoc-mdio";
1204 snprintf(priv->mdio->id, MII_BUS_ID_SIZE, "%s-%d",
1205 priv->mdio->name, pdev->id);
1206 priv->mdio->read = ethoc_mdio_read;
1207 priv->mdio->write = ethoc_mdio_write;
1208 priv->mdio->priv = priv;
1209
1210 ret = mdiobus_register(priv->mdio);
1211 if (ret) {
1212 dev_err(&netdev->dev, "failed to register MDIO bus\n");
1213 goto free2;
1214 }
1215
1216 ret = ethoc_mdio_probe(netdev);
1217 if (ret) {
1218 dev_err(&netdev->dev, "failed to probe MDIO bus\n");
1219 goto error;
1220 }
1221
1222 /* setup the net_device structure */
1223 netdev->netdev_ops = &ethoc_netdev_ops;
1224 netdev->watchdog_timeo = ETHOC_TIMEOUT;
1225 netdev->features |= 0;
1226 netdev->ethtool_ops = &ethoc_ethtool_ops;
1227
1228 /* setup NAPI */
1229 netif_napi_add(netdev, &priv->napi, ethoc_poll, 64);
1230
1231 spin_lock_init(&priv->lock);
1232
1233 ret = register_netdev(netdev);
1234 if (ret < 0) {
1235 dev_err(&netdev->dev, "failed to register interface\n");
1236 goto error2;
1237 }
1238
1239 goto out;
1240
1241error2:
1242 netif_napi_del(&priv->napi);
1243error:
1244 mdiobus_unregister(priv->mdio);
1245 mdiobus_free(priv->mdio);
1246free2:
1247 clk_disable_unprepare(priv->clk);
1248free:
1249 free_netdev(netdev);
1250out:
1251 return ret;
1252}
1253
1254/**
1255 * ethoc_remove - shutdown OpenCores ethernet MAC
1256 * @pdev: platform device
1257 */
1258static int ethoc_remove(struct platform_device *pdev)
1259{
1260 struct net_device *netdev = platform_get_drvdata(pdev);
1261 struct ethoc *priv = netdev_priv(netdev);
1262
1263 if (netdev) {
1264 netif_napi_del(&priv->napi);
1265 phy_disconnect(netdev->phydev);
1266
1267 if (priv->mdio) {
1268 mdiobus_unregister(priv->mdio);
1269 mdiobus_free(priv->mdio);
1270 }
1271 clk_disable_unprepare(priv->clk);
1272 unregister_netdev(netdev);
1273 free_netdev(netdev);
1274 }
1275
1276 return 0;
1277}
1278
1279#ifdef CONFIG_PM
1280static int ethoc_suspend(struct platform_device *pdev, pm_message_t state)
1281{
1282 return -ENOSYS;
1283}
1284
1285static int ethoc_resume(struct platform_device *pdev)
1286{
1287 return -ENOSYS;
1288}
1289#else
1290# define ethoc_suspend NULL
1291# define ethoc_resume NULL
1292#endif
1293
1294static const struct of_device_id ethoc_match[] = {
1295 { .compatible = "opencores,ethoc", },
1296 {},
1297};
1298MODULE_DEVICE_TABLE(of, ethoc_match);
1299
1300static struct platform_driver ethoc_driver = {
1301 .probe = ethoc_probe,
1302 .remove = ethoc_remove,
1303 .suspend = ethoc_suspend,
1304 .resume = ethoc_resume,
1305 .driver = {
1306 .name = "ethoc",
1307 .of_match_table = ethoc_match,
1308 },
1309};
1310
1311module_platform_driver(ethoc_driver);
1312
1313MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
1314MODULE_DESCRIPTION("OpenCores Ethernet MAC driver");
1315MODULE_LICENSE("GPL v2");
1316
1317