1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * linux/drivers/net/ethernet/ethoc.c |
4 | * |
5 | * Copyright (C) 2007-2008 Avionic Design Development GmbH |
6 | * Copyright (C) 2008-2009 Avionic Design GmbH |
7 | * |
8 | * Written by Thierry Reding <thierry.reding@avionic-design.de> |
9 | */ |
10 | |
11 | #include <linux/dma-mapping.h> |
12 | #include <linux/etherdevice.h> |
13 | #include <linux/clk.h> |
14 | #include <linux/crc32.h> |
15 | #include <linux/interrupt.h> |
16 | #include <linux/io.h> |
17 | #include <linux/mii.h> |
18 | #include <linux/phy.h> |
19 | #include <linux/platform_device.h> |
20 | #include <linux/sched.h> |
21 | #include <linux/slab.h> |
22 | #include <linux/of.h> |
23 | #include <linux/of_net.h> |
24 | #include <linux/module.h> |
25 | #include <net/ethoc.h> |
26 | |
27 | static int buffer_size = 0x8000; /* 32 KBytes */ |
28 | module_param(buffer_size, int, 0); |
29 | MODULE_PARM_DESC(buffer_size, "DMA buffer allocation size" ); |
30 | |
31 | /* register offsets */ |
32 | #define MODER 0x00 |
33 | #define INT_SOURCE 0x04 |
34 | #define INT_MASK 0x08 |
35 | #define IPGT 0x0c |
36 | #define IPGR1 0x10 |
37 | #define IPGR2 0x14 |
38 | #define PACKETLEN 0x18 |
39 | #define COLLCONF 0x1c |
40 | #define TX_BD_NUM 0x20 |
41 | #define CTRLMODER 0x24 |
42 | #define MIIMODER 0x28 |
43 | #define MIICOMMAND 0x2c |
44 | #define MIIADDRESS 0x30 |
45 | #define MIITX_DATA 0x34 |
46 | #define MIIRX_DATA 0x38 |
47 | #define MIISTATUS 0x3c |
48 | #define MAC_ADDR0 0x40 |
49 | #define MAC_ADDR1 0x44 |
50 | #define ETH_HASH0 0x48 |
51 | #define ETH_HASH1 0x4c |
52 | #define ETH_TXCTRL 0x50 |
53 | #define ETH_END 0x54 |
54 | |
55 | /* mode register */ |
56 | #define MODER_RXEN (1 << 0) /* receive enable */ |
57 | #define MODER_TXEN (1 << 1) /* transmit enable */ |
58 | #define MODER_NOPRE (1 << 2) /* no preamble */ |
59 | #define MODER_BRO (1 << 3) /* broadcast address */ |
60 | #define MODER_IAM (1 << 4) /* individual address mode */ |
61 | #define MODER_PRO (1 << 5) /* promiscuous mode */ |
62 | #define MODER_IFG (1 << 6) /* interframe gap for incoming frames */ |
63 | #define MODER_LOOP (1 << 7) /* loopback */ |
64 | #define MODER_NBO (1 << 8) /* no back-off */ |
65 | #define MODER_EDE (1 << 9) /* excess defer enable */ |
66 | #define MODER_FULLD (1 << 10) /* full duplex */ |
67 | #define MODER_RESET (1 << 11) /* FIXME: reset (undocumented) */ |
68 | #define MODER_DCRC (1 << 12) /* delayed CRC enable */ |
69 | #define MODER_CRC (1 << 13) /* CRC enable */ |
70 | #define MODER_HUGE (1 << 14) /* huge packets enable */ |
71 | #define MODER_PAD (1 << 15) /* padding enabled */ |
72 | #define MODER_RSM (1 << 16) /* receive small packets */ |
73 | |
74 | /* interrupt source and mask registers */ |
75 | #define INT_MASK_TXF (1 << 0) /* transmit frame */ |
76 | #define INT_MASK_TXE (1 << 1) /* transmit error */ |
77 | #define INT_MASK_RXF (1 << 2) /* receive frame */ |
78 | #define INT_MASK_RXE (1 << 3) /* receive error */ |
79 | #define INT_MASK_BUSY (1 << 4) |
80 | #define INT_MASK_TXC (1 << 5) /* transmit control frame */ |
81 | #define INT_MASK_RXC (1 << 6) /* receive control frame */ |
82 | |
83 | #define INT_MASK_TX (INT_MASK_TXF | INT_MASK_TXE) |
84 | #define INT_MASK_RX (INT_MASK_RXF | INT_MASK_RXE) |
85 | |
86 | #define INT_MASK_ALL ( \ |
87 | INT_MASK_TXF | INT_MASK_TXE | \ |
88 | INT_MASK_RXF | INT_MASK_RXE | \ |
89 | INT_MASK_TXC | INT_MASK_RXC | \ |
90 | INT_MASK_BUSY \ |
91 | ) |
92 | |
93 | /* packet length register */ |
94 | #define PACKETLEN_MIN(min) (((min) & 0xffff) << 16) |
95 | #define PACKETLEN_MAX(max) (((max) & 0xffff) << 0) |
96 | #define PACKETLEN_MIN_MAX(min, max) (PACKETLEN_MIN(min) | \ |
97 | PACKETLEN_MAX(max)) |
98 | |
99 | /* transmit buffer number register */ |
100 | #define TX_BD_NUM_VAL(x) (((x) <= 0x80) ? (x) : 0x80) |
101 | |
102 | /* control module mode register */ |
103 | #define CTRLMODER_PASSALL (1 << 0) /* pass all receive frames */ |
104 | #define CTRLMODER_RXFLOW (1 << 1) /* receive control flow */ |
105 | #define CTRLMODER_TXFLOW (1 << 2) /* transmit control flow */ |
106 | |
107 | /* MII mode register */ |
108 | #define MIIMODER_CLKDIV(x) ((x) & 0xfe) /* needs to be an even number */ |
109 | #define MIIMODER_NOPRE (1 << 8) /* no preamble */ |
110 | |
111 | /* MII command register */ |
112 | #define MIICOMMAND_SCAN (1 << 0) /* scan status */ |
113 | #define MIICOMMAND_READ (1 << 1) /* read status */ |
114 | #define MIICOMMAND_WRITE (1 << 2) /* write control data */ |
115 | |
116 | /* MII address register */ |
117 | #define MIIADDRESS_FIAD(x) (((x) & 0x1f) << 0) |
118 | #define MIIADDRESS_RGAD(x) (((x) & 0x1f) << 8) |
119 | #define MIIADDRESS_ADDR(phy, reg) (MIIADDRESS_FIAD(phy) | \ |
120 | MIIADDRESS_RGAD(reg)) |
121 | |
122 | /* MII transmit data register */ |
123 | #define MIITX_DATA_VAL(x) ((x) & 0xffff) |
124 | |
125 | /* MII receive data register */ |
126 | #define MIIRX_DATA_VAL(x) ((x) & 0xffff) |
127 | |
128 | /* MII status register */ |
129 | #define MIISTATUS_LINKFAIL (1 << 0) |
130 | #define MIISTATUS_BUSY (1 << 1) |
131 | #define MIISTATUS_INVALID (1 << 2) |
132 | |
133 | /* TX buffer descriptor */ |
134 | #define TX_BD_CS (1 << 0) /* carrier sense lost */ |
135 | #define TX_BD_DF (1 << 1) /* defer indication */ |
136 | #define TX_BD_LC (1 << 2) /* late collision */ |
137 | #define TX_BD_RL (1 << 3) /* retransmission limit */ |
138 | #define TX_BD_RETRY_MASK (0x00f0) |
139 | #define TX_BD_RETRY(x) (((x) & 0x00f0) >> 4) |
140 | #define TX_BD_UR (1 << 8) /* transmitter underrun */ |
141 | #define TX_BD_CRC (1 << 11) /* TX CRC enable */ |
142 | #define TX_BD_PAD (1 << 12) /* pad enable for short packets */ |
143 | #define TX_BD_WRAP (1 << 13) |
144 | #define TX_BD_IRQ (1 << 14) /* interrupt request enable */ |
145 | #define TX_BD_READY (1 << 15) /* TX buffer ready */ |
146 | #define TX_BD_LEN(x) (((x) & 0xffff) << 16) |
147 | #define TX_BD_LEN_MASK (0xffff << 16) |
148 | |
149 | #define TX_BD_STATS (TX_BD_CS | TX_BD_DF | TX_BD_LC | \ |
150 | TX_BD_RL | TX_BD_RETRY_MASK | TX_BD_UR) |
151 | |
152 | /* RX buffer descriptor */ |
153 | #define RX_BD_LC (1 << 0) /* late collision */ |
154 | #define RX_BD_CRC (1 << 1) /* RX CRC error */ |
155 | #define RX_BD_SF (1 << 2) /* short frame */ |
156 | #define RX_BD_TL (1 << 3) /* too long */ |
157 | #define RX_BD_DN (1 << 4) /* dribble nibble */ |
158 | #define RX_BD_IS (1 << 5) /* invalid symbol */ |
159 | #define RX_BD_OR (1 << 6) /* receiver overrun */ |
160 | #define RX_BD_MISS (1 << 7) |
161 | #define RX_BD_CF (1 << 8) /* control frame */ |
162 | #define RX_BD_WRAP (1 << 13) |
163 | #define RX_BD_IRQ (1 << 14) /* interrupt request enable */ |
164 | #define RX_BD_EMPTY (1 << 15) |
165 | #define RX_BD_LEN(x) (((x) & 0xffff) << 16) |
166 | |
167 | #define RX_BD_STATS (RX_BD_LC | RX_BD_CRC | RX_BD_SF | RX_BD_TL | \ |
168 | RX_BD_DN | RX_BD_IS | RX_BD_OR | RX_BD_MISS) |
169 | |
170 | #define ETHOC_BUFSIZ 1536 |
171 | #define ETHOC_ZLEN 64 |
172 | #define ETHOC_BD_BASE 0x400 |
173 | #define ETHOC_TIMEOUT (HZ / 2) |
174 | #define ETHOC_MII_TIMEOUT (1 + (HZ / 5)) |
175 | |
176 | /** |
177 | * struct ethoc - driver-private device structure |
178 | * @iobase: pointer to I/O memory region |
179 | * @membase: pointer to buffer memory region |
180 | * @big_endian: just big or little (endian) |
181 | * @num_bd: number of buffer descriptors |
182 | * @num_tx: number of send buffers |
183 | * @cur_tx: last send buffer written |
184 | * @dty_tx: last buffer actually sent |
185 | * @num_rx: number of receive buffers |
186 | * @cur_rx: current receive buffer |
187 | * @vma: pointer to array of virtual memory addresses for buffers |
188 | * @netdev: pointer to network device structure |
189 | * @napi: NAPI structure |
190 | * @msg_enable: device state flags |
191 | * @lock: device lock |
192 | * @mdio: MDIO bus for PHY access |
193 | * @clk: clock |
194 | * @phy_id: address of attached PHY |
195 | * @old_link: previous link info |
196 | * @old_duplex: previous duplex info |
197 | */ |
198 | struct ethoc { |
199 | void __iomem *iobase; |
200 | void __iomem *membase; |
201 | bool big_endian; |
202 | |
203 | unsigned int num_bd; |
204 | unsigned int num_tx; |
205 | unsigned int cur_tx; |
206 | unsigned int dty_tx; |
207 | |
208 | unsigned int num_rx; |
209 | unsigned int cur_rx; |
210 | |
211 | void **vma; |
212 | |
213 | struct net_device *netdev; |
214 | struct napi_struct napi; |
215 | u32 msg_enable; |
216 | |
217 | spinlock_t lock; |
218 | |
219 | struct mii_bus *mdio; |
220 | struct clk *clk; |
221 | s8 phy_id; |
222 | |
223 | int old_link; |
224 | int old_duplex; |
225 | }; |
226 | |
227 | /** |
228 | * struct ethoc_bd - buffer descriptor |
229 | * @stat: buffer statistics |
230 | * @addr: physical memory address |
231 | */ |
232 | struct ethoc_bd { |
233 | u32 stat; |
234 | u32 addr; |
235 | }; |
236 | |
237 | static inline u32 ethoc_read(struct ethoc *dev, loff_t offset) |
238 | { |
239 | if (dev->big_endian) |
240 | return ioread32be(dev->iobase + offset); |
241 | else |
242 | return ioread32(dev->iobase + offset); |
243 | } |
244 | |
245 | static inline void ethoc_write(struct ethoc *dev, loff_t offset, u32 data) |
246 | { |
247 | if (dev->big_endian) |
248 | iowrite32be(data, dev->iobase + offset); |
249 | else |
250 | iowrite32(data, dev->iobase + offset); |
251 | } |
252 | |
253 | static inline void ethoc_read_bd(struct ethoc *dev, int index, |
254 | struct ethoc_bd *bd) |
255 | { |
256 | loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd)); |
257 | bd->stat = ethoc_read(dev, offset: offset + 0); |
258 | bd->addr = ethoc_read(dev, offset: offset + 4); |
259 | } |
260 | |
261 | static inline void ethoc_write_bd(struct ethoc *dev, int index, |
262 | const struct ethoc_bd *bd) |
263 | { |
264 | loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd)); |
265 | ethoc_write(dev, offset: offset + 0, data: bd->stat); |
266 | ethoc_write(dev, offset: offset + 4, data: bd->addr); |
267 | } |
268 | |
269 | static inline void ethoc_enable_irq(struct ethoc *dev, u32 mask) |
270 | { |
271 | u32 imask = ethoc_read(dev, INT_MASK); |
272 | imask |= mask; |
273 | ethoc_write(dev, INT_MASK, data: imask); |
274 | } |
275 | |
276 | static inline void ethoc_disable_irq(struct ethoc *dev, u32 mask) |
277 | { |
278 | u32 imask = ethoc_read(dev, INT_MASK); |
279 | imask &= ~mask; |
280 | ethoc_write(dev, INT_MASK, data: imask); |
281 | } |
282 | |
283 | static inline void ethoc_ack_irq(struct ethoc *dev, u32 mask) |
284 | { |
285 | ethoc_write(dev, INT_SOURCE, data: mask); |
286 | } |
287 | |
288 | static inline void ethoc_enable_rx_and_tx(struct ethoc *dev) |
289 | { |
290 | u32 mode = ethoc_read(dev, MODER); |
291 | mode |= MODER_RXEN | MODER_TXEN; |
292 | ethoc_write(dev, MODER, data: mode); |
293 | } |
294 | |
295 | static inline void ethoc_disable_rx_and_tx(struct ethoc *dev) |
296 | { |
297 | u32 mode = ethoc_read(dev, MODER); |
298 | mode &= ~(MODER_RXEN | MODER_TXEN); |
299 | ethoc_write(dev, MODER, data: mode); |
300 | } |
301 | |
302 | static int ethoc_init_ring(struct ethoc *dev, unsigned long mem_start) |
303 | { |
304 | struct ethoc_bd bd; |
305 | int i; |
306 | void *vma; |
307 | |
308 | dev->cur_tx = 0; |
309 | dev->dty_tx = 0; |
310 | dev->cur_rx = 0; |
311 | |
312 | ethoc_write(dev, TX_BD_NUM, data: dev->num_tx); |
313 | |
314 | /* setup transmission buffers */ |
315 | bd.addr = mem_start; |
316 | bd.stat = TX_BD_IRQ | TX_BD_CRC; |
317 | vma = dev->membase; |
318 | |
319 | for (i = 0; i < dev->num_tx; i++) { |
320 | if (i == dev->num_tx - 1) |
321 | bd.stat |= TX_BD_WRAP; |
322 | |
323 | ethoc_write_bd(dev, index: i, bd: &bd); |
324 | bd.addr += ETHOC_BUFSIZ; |
325 | |
326 | dev->vma[i] = vma; |
327 | vma += ETHOC_BUFSIZ; |
328 | } |
329 | |
330 | bd.stat = RX_BD_EMPTY | RX_BD_IRQ; |
331 | |
332 | for (i = 0; i < dev->num_rx; i++) { |
333 | if (i == dev->num_rx - 1) |
334 | bd.stat |= RX_BD_WRAP; |
335 | |
336 | ethoc_write_bd(dev, index: dev->num_tx + i, bd: &bd); |
337 | bd.addr += ETHOC_BUFSIZ; |
338 | |
339 | dev->vma[dev->num_tx + i] = vma; |
340 | vma += ETHOC_BUFSIZ; |
341 | } |
342 | |
343 | return 0; |
344 | } |
345 | |
346 | static int ethoc_reset(struct ethoc *dev) |
347 | { |
348 | u32 mode; |
349 | |
350 | /* TODO: reset controller? */ |
351 | |
352 | ethoc_disable_rx_and_tx(dev); |
353 | |
354 | /* TODO: setup registers */ |
355 | |
356 | /* enable FCS generation and automatic padding */ |
357 | mode = ethoc_read(dev, MODER); |
358 | mode |= MODER_CRC | MODER_PAD; |
359 | ethoc_write(dev, MODER, data: mode); |
360 | |
361 | /* set full-duplex mode */ |
362 | mode = ethoc_read(dev, MODER); |
363 | mode |= MODER_FULLD; |
364 | ethoc_write(dev, MODER, data: mode); |
365 | ethoc_write(dev, IPGT, data: 0x15); |
366 | |
367 | ethoc_ack_irq(dev, INT_MASK_ALL); |
368 | ethoc_enable_irq(dev, INT_MASK_ALL); |
369 | ethoc_enable_rx_and_tx(dev); |
370 | return 0; |
371 | } |
372 | |
373 | static unsigned int ethoc_update_rx_stats(struct ethoc *dev, |
374 | struct ethoc_bd *bd) |
375 | { |
376 | struct net_device *netdev = dev->netdev; |
377 | unsigned int ret = 0; |
378 | |
379 | if (bd->stat & RX_BD_TL) { |
380 | dev_err(&netdev->dev, "RX: frame too long\n" ); |
381 | netdev->stats.rx_length_errors++; |
382 | ret++; |
383 | } |
384 | |
385 | if (bd->stat & RX_BD_SF) { |
386 | dev_err(&netdev->dev, "RX: frame too short\n" ); |
387 | netdev->stats.rx_length_errors++; |
388 | ret++; |
389 | } |
390 | |
391 | if (bd->stat & RX_BD_DN) { |
392 | dev_err(&netdev->dev, "RX: dribble nibble\n" ); |
393 | netdev->stats.rx_frame_errors++; |
394 | } |
395 | |
396 | if (bd->stat & RX_BD_CRC) { |
397 | dev_err(&netdev->dev, "RX: wrong CRC\n" ); |
398 | netdev->stats.rx_crc_errors++; |
399 | ret++; |
400 | } |
401 | |
402 | if (bd->stat & RX_BD_OR) { |
403 | dev_err(&netdev->dev, "RX: overrun\n" ); |
404 | netdev->stats.rx_over_errors++; |
405 | ret++; |
406 | } |
407 | |
408 | if (bd->stat & RX_BD_MISS) |
409 | netdev->stats.rx_missed_errors++; |
410 | |
411 | if (bd->stat & RX_BD_LC) { |
412 | dev_err(&netdev->dev, "RX: late collision\n" ); |
413 | netdev->stats.collisions++; |
414 | ret++; |
415 | } |
416 | |
417 | return ret; |
418 | } |
419 | |
420 | static int ethoc_rx(struct net_device *dev, int limit) |
421 | { |
422 | struct ethoc *priv = netdev_priv(dev); |
423 | int count; |
424 | |
425 | for (count = 0; count < limit; ++count) { |
426 | unsigned int entry; |
427 | struct ethoc_bd bd; |
428 | |
429 | entry = priv->num_tx + priv->cur_rx; |
430 | ethoc_read_bd(dev: priv, index: entry, bd: &bd); |
431 | if (bd.stat & RX_BD_EMPTY) { |
432 | ethoc_ack_irq(dev: priv, INT_MASK_RX); |
433 | /* If packet (interrupt) came in between checking |
434 | * BD_EMTPY and clearing the interrupt source, then we |
435 | * risk missing the packet as the RX interrupt won't |
436 | * trigger right away when we reenable it; hence, check |
437 | * BD_EMTPY here again to make sure there isn't such a |
438 | * packet waiting for us... |
439 | */ |
440 | ethoc_read_bd(dev: priv, index: entry, bd: &bd); |
441 | if (bd.stat & RX_BD_EMPTY) |
442 | break; |
443 | } |
444 | |
445 | if (ethoc_update_rx_stats(dev: priv, bd: &bd) == 0) { |
446 | int size = bd.stat >> 16; |
447 | struct sk_buff *skb; |
448 | |
449 | size -= 4; /* strip the CRC */ |
450 | skb = netdev_alloc_skb_ip_align(dev, length: size); |
451 | |
452 | if (likely(skb)) { |
453 | void *src = priv->vma[entry]; |
454 | memcpy_fromio(skb_put(skb, len: size), src, size); |
455 | skb->protocol = eth_type_trans(skb, dev); |
456 | dev->stats.rx_packets++; |
457 | dev->stats.rx_bytes += size; |
458 | netif_receive_skb(skb); |
459 | } else { |
460 | if (net_ratelimit()) |
461 | dev_warn(&dev->dev, |
462 | "low on memory - packet dropped\n" ); |
463 | |
464 | dev->stats.rx_dropped++; |
465 | break; |
466 | } |
467 | } |
468 | |
469 | /* clear the buffer descriptor so it can be reused */ |
470 | bd.stat &= ~RX_BD_STATS; |
471 | bd.stat |= RX_BD_EMPTY; |
472 | ethoc_write_bd(dev: priv, index: entry, bd: &bd); |
473 | if (++priv->cur_rx == priv->num_rx) |
474 | priv->cur_rx = 0; |
475 | } |
476 | |
477 | return count; |
478 | } |
479 | |
480 | static void ethoc_update_tx_stats(struct ethoc *dev, struct ethoc_bd *bd) |
481 | { |
482 | struct net_device *netdev = dev->netdev; |
483 | |
484 | if (bd->stat & TX_BD_LC) { |
485 | dev_err(&netdev->dev, "TX: late collision\n" ); |
486 | netdev->stats.tx_window_errors++; |
487 | } |
488 | |
489 | if (bd->stat & TX_BD_RL) { |
490 | dev_err(&netdev->dev, "TX: retransmit limit\n" ); |
491 | netdev->stats.tx_aborted_errors++; |
492 | } |
493 | |
494 | if (bd->stat & TX_BD_UR) { |
495 | dev_err(&netdev->dev, "TX: underrun\n" ); |
496 | netdev->stats.tx_fifo_errors++; |
497 | } |
498 | |
499 | if (bd->stat & TX_BD_CS) { |
500 | dev_err(&netdev->dev, "TX: carrier sense lost\n" ); |
501 | netdev->stats.tx_carrier_errors++; |
502 | } |
503 | |
504 | if (bd->stat & TX_BD_STATS) |
505 | netdev->stats.tx_errors++; |
506 | |
507 | netdev->stats.collisions += (bd->stat >> 4) & 0xf; |
508 | netdev->stats.tx_bytes += bd->stat >> 16; |
509 | netdev->stats.tx_packets++; |
510 | } |
511 | |
512 | static int ethoc_tx(struct net_device *dev, int limit) |
513 | { |
514 | struct ethoc *priv = netdev_priv(dev); |
515 | int count; |
516 | struct ethoc_bd bd; |
517 | |
518 | for (count = 0; count < limit; ++count) { |
519 | unsigned int entry; |
520 | |
521 | entry = priv->dty_tx & (priv->num_tx-1); |
522 | |
523 | ethoc_read_bd(dev: priv, index: entry, bd: &bd); |
524 | |
525 | if (bd.stat & TX_BD_READY || (priv->dty_tx == priv->cur_tx)) { |
526 | ethoc_ack_irq(dev: priv, INT_MASK_TX); |
527 | /* If interrupt came in between reading in the BD |
528 | * and clearing the interrupt source, then we risk |
529 | * missing the event as the TX interrupt won't trigger |
530 | * right away when we reenable it; hence, check |
531 | * BD_EMPTY here again to make sure there isn't such an |
532 | * event pending... |
533 | */ |
534 | ethoc_read_bd(dev: priv, index: entry, bd: &bd); |
535 | if (bd.stat & TX_BD_READY || |
536 | (priv->dty_tx == priv->cur_tx)) |
537 | break; |
538 | } |
539 | |
540 | ethoc_update_tx_stats(dev: priv, bd: &bd); |
541 | priv->dty_tx++; |
542 | } |
543 | |
544 | if ((priv->cur_tx - priv->dty_tx) <= (priv->num_tx / 2)) |
545 | netif_wake_queue(dev); |
546 | |
547 | return count; |
548 | } |
549 | |
550 | static irqreturn_t ethoc_interrupt(int irq, void *dev_id) |
551 | { |
552 | struct net_device *dev = dev_id; |
553 | struct ethoc *priv = netdev_priv(dev); |
554 | u32 pending; |
555 | u32 mask; |
556 | |
557 | /* Figure out what triggered the interrupt... |
558 | * The tricky bit here is that the interrupt source bits get |
559 | * set in INT_SOURCE for an event regardless of whether that |
560 | * event is masked or not. Thus, in order to figure out what |
561 | * triggered the interrupt, we need to remove the sources |
562 | * for all events that are currently masked. This behaviour |
563 | * is not particularly well documented but reasonable... |
564 | */ |
565 | mask = ethoc_read(dev: priv, INT_MASK); |
566 | pending = ethoc_read(dev: priv, INT_SOURCE); |
567 | pending &= mask; |
568 | |
569 | if (unlikely(pending == 0)) |
570 | return IRQ_NONE; |
571 | |
572 | ethoc_ack_irq(dev: priv, mask: pending); |
573 | |
574 | /* We always handle the dropped packet interrupt */ |
575 | if (pending & INT_MASK_BUSY) { |
576 | dev_dbg(&dev->dev, "packet dropped\n" ); |
577 | dev->stats.rx_dropped++; |
578 | } |
579 | |
580 | /* Handle receive/transmit event by switching to polling */ |
581 | if (pending & (INT_MASK_TX | INT_MASK_RX)) { |
582 | ethoc_disable_irq(dev: priv, INT_MASK_TX | INT_MASK_RX); |
583 | napi_schedule(n: &priv->napi); |
584 | } |
585 | |
586 | return IRQ_HANDLED; |
587 | } |
588 | |
589 | static int ethoc_get_mac_address(struct net_device *dev, void *addr) |
590 | { |
591 | struct ethoc *priv = netdev_priv(dev); |
592 | u8 *mac = (u8 *)addr; |
593 | u32 reg; |
594 | |
595 | reg = ethoc_read(dev: priv, MAC_ADDR0); |
596 | mac[2] = (reg >> 24) & 0xff; |
597 | mac[3] = (reg >> 16) & 0xff; |
598 | mac[4] = (reg >> 8) & 0xff; |
599 | mac[5] = (reg >> 0) & 0xff; |
600 | |
601 | reg = ethoc_read(dev: priv, MAC_ADDR1); |
602 | mac[0] = (reg >> 8) & 0xff; |
603 | mac[1] = (reg >> 0) & 0xff; |
604 | |
605 | return 0; |
606 | } |
607 | |
608 | static int ethoc_poll(struct napi_struct *napi, int budget) |
609 | { |
610 | struct ethoc *priv = container_of(napi, struct ethoc, napi); |
611 | int rx_work_done = 0; |
612 | int tx_work_done = 0; |
613 | |
614 | rx_work_done = ethoc_rx(dev: priv->netdev, limit: budget); |
615 | tx_work_done = ethoc_tx(dev: priv->netdev, limit: budget); |
616 | |
617 | if (rx_work_done < budget && tx_work_done < budget) { |
618 | napi_complete_done(n: napi, work_done: rx_work_done); |
619 | ethoc_enable_irq(dev: priv, INT_MASK_TX | INT_MASK_RX); |
620 | } |
621 | |
622 | return rx_work_done; |
623 | } |
624 | |
625 | static int ethoc_mdio_read(struct mii_bus *bus, int phy, int reg) |
626 | { |
627 | struct ethoc *priv = bus->priv; |
628 | int i; |
629 | |
630 | ethoc_write(dev: priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg)); |
631 | ethoc_write(dev: priv, MIICOMMAND, MIICOMMAND_READ); |
632 | |
633 | for (i = 0; i < 5; i++) { |
634 | u32 status = ethoc_read(dev: priv, MIISTATUS); |
635 | if (!(status & MIISTATUS_BUSY)) { |
636 | u32 data = ethoc_read(dev: priv, MIIRX_DATA); |
637 | /* reset MII command register */ |
638 | ethoc_write(dev: priv, MIICOMMAND, data: 0); |
639 | return data; |
640 | } |
641 | usleep_range(min: 100, max: 200); |
642 | } |
643 | |
644 | return -EBUSY; |
645 | } |
646 | |
647 | static int ethoc_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) |
648 | { |
649 | struct ethoc *priv = bus->priv; |
650 | int i; |
651 | |
652 | ethoc_write(dev: priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg)); |
653 | ethoc_write(dev: priv, MIITX_DATA, data: val); |
654 | ethoc_write(dev: priv, MIICOMMAND, MIICOMMAND_WRITE); |
655 | |
656 | for (i = 0; i < 5; i++) { |
657 | u32 stat = ethoc_read(dev: priv, MIISTATUS); |
658 | if (!(stat & MIISTATUS_BUSY)) { |
659 | /* reset MII command register */ |
660 | ethoc_write(dev: priv, MIICOMMAND, data: 0); |
661 | return 0; |
662 | } |
663 | usleep_range(min: 100, max: 200); |
664 | } |
665 | |
666 | return -EBUSY; |
667 | } |
668 | |
669 | static void ethoc_mdio_poll(struct net_device *dev) |
670 | { |
671 | struct ethoc *priv = netdev_priv(dev); |
672 | struct phy_device *phydev = dev->phydev; |
673 | bool changed = false; |
674 | u32 mode; |
675 | |
676 | if (priv->old_link != phydev->link) { |
677 | changed = true; |
678 | priv->old_link = phydev->link; |
679 | } |
680 | |
681 | if (priv->old_duplex != phydev->duplex) { |
682 | changed = true; |
683 | priv->old_duplex = phydev->duplex; |
684 | } |
685 | |
686 | if (!changed) |
687 | return; |
688 | |
689 | mode = ethoc_read(dev: priv, MODER); |
690 | if (phydev->duplex == DUPLEX_FULL) |
691 | mode |= MODER_FULLD; |
692 | else |
693 | mode &= ~MODER_FULLD; |
694 | ethoc_write(dev: priv, MODER, data: mode); |
695 | |
696 | phy_print_status(phydev); |
697 | } |
698 | |
699 | static int ethoc_mdio_probe(struct net_device *dev) |
700 | { |
701 | struct ethoc *priv = netdev_priv(dev); |
702 | struct phy_device *phy; |
703 | int err; |
704 | |
705 | if (priv->phy_id != -1) |
706 | phy = mdiobus_get_phy(bus: priv->mdio, addr: priv->phy_id); |
707 | else |
708 | phy = phy_find_first(bus: priv->mdio); |
709 | |
710 | if (!phy) |
711 | return dev_err_probe(dev: &dev->dev, err: -ENXIO, fmt: "no PHY found\n" ); |
712 | |
713 | priv->old_duplex = -1; |
714 | priv->old_link = -1; |
715 | |
716 | err = phy_connect_direct(dev, phydev: phy, handler: ethoc_mdio_poll, |
717 | interface: PHY_INTERFACE_MODE_GMII); |
718 | if (err) |
719 | return dev_err_probe(dev: &dev->dev, err, fmt: "could not attach to PHY\n" ); |
720 | |
721 | phy_set_max_speed(phydev: phy, SPEED_100); |
722 | |
723 | return 0; |
724 | } |
725 | |
726 | static int ethoc_open(struct net_device *dev) |
727 | { |
728 | struct ethoc *priv = netdev_priv(dev); |
729 | int ret; |
730 | |
731 | ret = request_irq(irq: dev->irq, handler: ethoc_interrupt, IRQF_SHARED, |
732 | name: dev->name, dev); |
733 | if (ret) |
734 | return ret; |
735 | |
736 | napi_enable(n: &priv->napi); |
737 | |
738 | ethoc_init_ring(dev: priv, mem_start: dev->mem_start); |
739 | ethoc_reset(dev: priv); |
740 | |
741 | if (netif_queue_stopped(dev)) { |
742 | dev_dbg(&dev->dev, " resuming queue\n" ); |
743 | netif_wake_queue(dev); |
744 | } else { |
745 | dev_dbg(&dev->dev, " starting queue\n" ); |
746 | netif_start_queue(dev); |
747 | } |
748 | |
749 | priv->old_link = -1; |
750 | priv->old_duplex = -1; |
751 | |
752 | phy_start(phydev: dev->phydev); |
753 | |
754 | if (netif_msg_ifup(priv)) { |
755 | dev_info(&dev->dev, "I/O: %08lx Memory: %08lx-%08lx\n" , |
756 | dev->base_addr, dev->mem_start, dev->mem_end); |
757 | } |
758 | |
759 | return 0; |
760 | } |
761 | |
762 | static int ethoc_stop(struct net_device *dev) |
763 | { |
764 | struct ethoc *priv = netdev_priv(dev); |
765 | |
766 | napi_disable(n: &priv->napi); |
767 | |
768 | if (dev->phydev) |
769 | phy_stop(phydev: dev->phydev); |
770 | |
771 | ethoc_disable_rx_and_tx(dev: priv); |
772 | free_irq(dev->irq, dev); |
773 | |
774 | if (!netif_queue_stopped(dev)) |
775 | netif_stop_queue(dev); |
776 | |
777 | return 0; |
778 | } |
779 | |
780 | static int ethoc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
781 | { |
782 | struct ethoc *priv = netdev_priv(dev); |
783 | struct mii_ioctl_data *mdio = if_mii(rq: ifr); |
784 | struct phy_device *phy = NULL; |
785 | |
786 | if (!netif_running(dev)) |
787 | return -EINVAL; |
788 | |
789 | if (cmd != SIOCGMIIPHY) { |
790 | if (mdio->phy_id >= PHY_MAX_ADDR) |
791 | return -ERANGE; |
792 | |
793 | phy = mdiobus_get_phy(bus: priv->mdio, addr: mdio->phy_id); |
794 | if (!phy) |
795 | return -ENODEV; |
796 | } else { |
797 | phy = dev->phydev; |
798 | } |
799 | |
800 | return phy_mii_ioctl(phydev: phy, ifr, cmd); |
801 | } |
802 | |
803 | static void ethoc_do_set_mac_address(struct net_device *dev) |
804 | { |
805 | const unsigned char *mac = dev->dev_addr; |
806 | struct ethoc *priv = netdev_priv(dev); |
807 | |
808 | ethoc_write(dev: priv, MAC_ADDR0, data: (mac[2] << 24) | (mac[3] << 16) | |
809 | (mac[4] << 8) | (mac[5] << 0)); |
810 | ethoc_write(dev: priv, MAC_ADDR1, data: (mac[0] << 8) | (mac[1] << 0)); |
811 | } |
812 | |
813 | static int ethoc_set_mac_address(struct net_device *dev, void *p) |
814 | { |
815 | const struct sockaddr *addr = p; |
816 | |
817 | if (!is_valid_ether_addr(addr: addr->sa_data)) |
818 | return -EADDRNOTAVAIL; |
819 | eth_hw_addr_set(dev, addr: addr->sa_data); |
820 | ethoc_do_set_mac_address(dev); |
821 | return 0; |
822 | } |
823 | |
824 | static void ethoc_set_multicast_list(struct net_device *dev) |
825 | { |
826 | struct ethoc *priv = netdev_priv(dev); |
827 | u32 mode = ethoc_read(dev: priv, MODER); |
828 | struct netdev_hw_addr *ha; |
829 | u32 hash[2] = { 0, 0 }; |
830 | |
831 | /* set loopback mode if requested */ |
832 | if (dev->flags & IFF_LOOPBACK) |
833 | mode |= MODER_LOOP; |
834 | else |
835 | mode &= ~MODER_LOOP; |
836 | |
837 | /* receive broadcast frames if requested */ |
838 | if (dev->flags & IFF_BROADCAST) |
839 | mode &= ~MODER_BRO; |
840 | else |
841 | mode |= MODER_BRO; |
842 | |
843 | /* enable promiscuous mode if requested */ |
844 | if (dev->flags & IFF_PROMISC) |
845 | mode |= MODER_PRO; |
846 | else |
847 | mode &= ~MODER_PRO; |
848 | |
849 | ethoc_write(dev: priv, MODER, data: mode); |
850 | |
851 | /* receive multicast frames */ |
852 | if (dev->flags & IFF_ALLMULTI) { |
853 | hash[0] = 0xffffffff; |
854 | hash[1] = 0xffffffff; |
855 | } else { |
856 | netdev_for_each_mc_addr(ha, dev) { |
857 | u32 crc = ether_crc(ETH_ALEN, ha->addr); |
858 | int bit = (crc >> 26) & 0x3f; |
859 | hash[bit >> 5] |= 1 << (bit & 0x1f); |
860 | } |
861 | } |
862 | |
863 | ethoc_write(dev: priv, ETH_HASH0, data: hash[0]); |
864 | ethoc_write(dev: priv, ETH_HASH1, data: hash[1]); |
865 | } |
866 | |
867 | static int ethoc_change_mtu(struct net_device *dev, int new_mtu) |
868 | { |
869 | return -ENOSYS; |
870 | } |
871 | |
872 | static void ethoc_tx_timeout(struct net_device *dev, unsigned int txqueue) |
873 | { |
874 | struct ethoc *priv = netdev_priv(dev); |
875 | u32 pending = ethoc_read(dev: priv, INT_SOURCE); |
876 | if (likely(pending)) |
877 | ethoc_interrupt(irq: dev->irq, dev_id: dev); |
878 | } |
879 | |
880 | static netdev_tx_t ethoc_start_xmit(struct sk_buff *skb, struct net_device *dev) |
881 | { |
882 | struct ethoc *priv = netdev_priv(dev); |
883 | struct ethoc_bd bd; |
884 | unsigned int entry; |
885 | void *dest; |
886 | |
887 | if (skb_put_padto(skb, ETHOC_ZLEN)) { |
888 | dev->stats.tx_errors++; |
889 | goto out_no_free; |
890 | } |
891 | |
892 | if (unlikely(skb->len > ETHOC_BUFSIZ)) { |
893 | dev->stats.tx_errors++; |
894 | goto out; |
895 | } |
896 | |
897 | entry = priv->cur_tx % priv->num_tx; |
898 | spin_lock_irq(lock: &priv->lock); |
899 | priv->cur_tx++; |
900 | |
901 | ethoc_read_bd(dev: priv, index: entry, bd: &bd); |
902 | if (unlikely(skb->len < ETHOC_ZLEN)) |
903 | bd.stat |= TX_BD_PAD; |
904 | else |
905 | bd.stat &= ~TX_BD_PAD; |
906 | |
907 | dest = priv->vma[entry]; |
908 | memcpy_toio(dest, skb->data, skb->len); |
909 | |
910 | bd.stat &= ~(TX_BD_STATS | TX_BD_LEN_MASK); |
911 | bd.stat |= TX_BD_LEN(skb->len); |
912 | ethoc_write_bd(dev: priv, index: entry, bd: &bd); |
913 | |
914 | bd.stat |= TX_BD_READY; |
915 | ethoc_write_bd(dev: priv, index: entry, bd: &bd); |
916 | |
917 | if (priv->cur_tx == (priv->dty_tx + priv->num_tx)) { |
918 | dev_dbg(&dev->dev, "stopping queue\n" ); |
919 | netif_stop_queue(dev); |
920 | } |
921 | |
922 | spin_unlock_irq(lock: &priv->lock); |
923 | skb_tx_timestamp(skb); |
924 | out: |
925 | dev_kfree_skb(skb); |
926 | out_no_free: |
927 | return NETDEV_TX_OK; |
928 | } |
929 | |
930 | static int ethoc_get_regs_len(struct net_device *netdev) |
931 | { |
932 | return ETH_END; |
933 | } |
934 | |
935 | static void ethoc_get_regs(struct net_device *dev, struct ethtool_regs *regs, |
936 | void *p) |
937 | { |
938 | struct ethoc *priv = netdev_priv(dev); |
939 | u32 *regs_buff = p; |
940 | unsigned i; |
941 | |
942 | regs->version = 0; |
943 | for (i = 0; i < ETH_END / sizeof(u32); ++i) |
944 | regs_buff[i] = ethoc_read(dev: priv, offset: i * sizeof(u32)); |
945 | } |
946 | |
947 | static void ethoc_get_ringparam(struct net_device *dev, |
948 | struct ethtool_ringparam *ring, |
949 | struct kernel_ethtool_ringparam *kernel_ring, |
950 | struct netlink_ext_ack *extack) |
951 | { |
952 | struct ethoc *priv = netdev_priv(dev); |
953 | |
954 | ring->rx_max_pending = priv->num_bd - 1; |
955 | ring->rx_mini_max_pending = 0; |
956 | ring->rx_jumbo_max_pending = 0; |
957 | ring->tx_max_pending = priv->num_bd - 1; |
958 | |
959 | ring->rx_pending = priv->num_rx; |
960 | ring->rx_mini_pending = 0; |
961 | ring->rx_jumbo_pending = 0; |
962 | ring->tx_pending = priv->num_tx; |
963 | } |
964 | |
965 | static int ethoc_set_ringparam(struct net_device *dev, |
966 | struct ethtool_ringparam *ring, |
967 | struct kernel_ethtool_ringparam *kernel_ring, |
968 | struct netlink_ext_ack *extack) |
969 | { |
970 | struct ethoc *priv = netdev_priv(dev); |
971 | |
972 | if (ring->tx_pending < 1 || ring->rx_pending < 1 || |
973 | ring->tx_pending + ring->rx_pending > priv->num_bd) |
974 | return -EINVAL; |
975 | if (ring->rx_mini_pending || ring->rx_jumbo_pending) |
976 | return -EINVAL; |
977 | |
978 | if (netif_running(dev)) { |
979 | netif_tx_disable(dev); |
980 | ethoc_disable_rx_and_tx(dev: priv); |
981 | ethoc_disable_irq(dev: priv, INT_MASK_TX | INT_MASK_RX); |
982 | synchronize_irq(irq: dev->irq); |
983 | } |
984 | |
985 | priv->num_tx = rounddown_pow_of_two(ring->tx_pending); |
986 | priv->num_rx = ring->rx_pending; |
987 | ethoc_init_ring(dev: priv, mem_start: dev->mem_start); |
988 | |
989 | if (netif_running(dev)) { |
990 | ethoc_enable_irq(dev: priv, INT_MASK_TX | INT_MASK_RX); |
991 | ethoc_enable_rx_and_tx(dev: priv); |
992 | netif_wake_queue(dev); |
993 | } |
994 | return 0; |
995 | } |
996 | |
997 | static const struct ethtool_ops ethoc_ethtool_ops = { |
998 | .get_regs_len = ethoc_get_regs_len, |
999 | .get_regs = ethoc_get_regs, |
1000 | .nway_reset = phy_ethtool_nway_reset, |
1001 | .get_link = ethtool_op_get_link, |
1002 | .get_ringparam = ethoc_get_ringparam, |
1003 | .set_ringparam = ethoc_set_ringparam, |
1004 | .get_ts_info = ethtool_op_get_ts_info, |
1005 | .get_link_ksettings = phy_ethtool_get_link_ksettings, |
1006 | .set_link_ksettings = phy_ethtool_set_link_ksettings, |
1007 | }; |
1008 | |
1009 | static const struct net_device_ops ethoc_netdev_ops = { |
1010 | .ndo_open = ethoc_open, |
1011 | .ndo_stop = ethoc_stop, |
1012 | .ndo_eth_ioctl = ethoc_ioctl, |
1013 | .ndo_set_mac_address = ethoc_set_mac_address, |
1014 | .ndo_set_rx_mode = ethoc_set_multicast_list, |
1015 | .ndo_change_mtu = ethoc_change_mtu, |
1016 | .ndo_tx_timeout = ethoc_tx_timeout, |
1017 | .ndo_start_xmit = ethoc_start_xmit, |
1018 | }; |
1019 | |
1020 | /** |
1021 | * ethoc_probe - initialize OpenCores ethernet MAC |
1022 | * @pdev: platform device |
1023 | */ |
1024 | static int ethoc_probe(struct platform_device *pdev) |
1025 | { |
1026 | struct net_device *netdev = NULL; |
1027 | struct resource *res = NULL; |
1028 | struct resource *mmio = NULL; |
1029 | struct resource *mem = NULL; |
1030 | struct ethoc *priv = NULL; |
1031 | int num_bd; |
1032 | int ret = 0; |
1033 | struct ethoc_platform_data *pdata = dev_get_platdata(dev: &pdev->dev); |
1034 | u32 eth_clkfreq = pdata ? pdata->eth_clkfreq : 0; |
1035 | |
1036 | /* allocate networking device */ |
1037 | netdev = alloc_etherdev(sizeof(struct ethoc)); |
1038 | if (!netdev) { |
1039 | ret = -ENOMEM; |
1040 | goto out; |
1041 | } |
1042 | |
1043 | SET_NETDEV_DEV(netdev, &pdev->dev); |
1044 | platform_set_drvdata(pdev, data: netdev); |
1045 | |
1046 | /* obtain I/O memory space */ |
1047 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1048 | if (!res) { |
1049 | dev_err(&pdev->dev, "cannot obtain I/O memory space\n" ); |
1050 | ret = -ENXIO; |
1051 | goto free; |
1052 | } |
1053 | |
1054 | mmio = devm_request_mem_region(&pdev->dev, res->start, |
1055 | resource_size(res), res->name); |
1056 | if (!mmio) { |
1057 | dev_err(&pdev->dev, "cannot request I/O memory space\n" ); |
1058 | ret = -ENXIO; |
1059 | goto free; |
1060 | } |
1061 | |
1062 | netdev->base_addr = mmio->start; |
1063 | |
1064 | /* obtain buffer memory space */ |
1065 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
1066 | if (res) { |
1067 | mem = devm_request_mem_region(&pdev->dev, res->start, |
1068 | resource_size(res), res->name); |
1069 | if (!mem) { |
1070 | dev_err(&pdev->dev, "cannot request memory space\n" ); |
1071 | ret = -ENXIO; |
1072 | goto free; |
1073 | } |
1074 | |
1075 | netdev->mem_start = mem->start; |
1076 | netdev->mem_end = mem->end; |
1077 | } |
1078 | |
1079 | |
1080 | /* obtain device IRQ number */ |
1081 | ret = platform_get_irq(pdev, 0); |
1082 | if (ret < 0) |
1083 | goto free; |
1084 | |
1085 | netdev->irq = ret; |
1086 | |
1087 | /* setup driver-private data */ |
1088 | priv = netdev_priv(dev: netdev); |
1089 | priv->netdev = netdev; |
1090 | |
1091 | priv->iobase = devm_ioremap(dev: &pdev->dev, offset: netdev->base_addr, |
1092 | size: resource_size(res: mmio)); |
1093 | if (!priv->iobase) { |
1094 | dev_err(&pdev->dev, "cannot remap I/O memory space\n" ); |
1095 | ret = -ENXIO; |
1096 | goto free; |
1097 | } |
1098 | |
1099 | if (netdev->mem_end) { |
1100 | priv->membase = devm_ioremap(dev: &pdev->dev, |
1101 | offset: netdev->mem_start, size: resource_size(res: mem)); |
1102 | if (!priv->membase) { |
1103 | dev_err(&pdev->dev, "cannot remap memory space\n" ); |
1104 | ret = -ENXIO; |
1105 | goto free; |
1106 | } |
1107 | } else { |
1108 | /* Allocate buffer memory */ |
1109 | priv->membase = dmam_alloc_coherent(dev: &pdev->dev, |
1110 | size: buffer_size, dma_handle: (void *)&netdev->mem_start, |
1111 | GFP_KERNEL); |
1112 | if (!priv->membase) { |
1113 | dev_err(&pdev->dev, "cannot allocate %dB buffer\n" , |
1114 | buffer_size); |
1115 | ret = -ENOMEM; |
1116 | goto free; |
1117 | } |
1118 | netdev->mem_end = netdev->mem_start + buffer_size; |
1119 | } |
1120 | |
1121 | priv->big_endian = pdata ? pdata->big_endian : |
1122 | of_device_is_big_endian(device: pdev->dev.of_node); |
1123 | |
1124 | /* calculate the number of TX/RX buffers, maximum 128 supported */ |
1125 | num_bd = min_t(unsigned int, |
1126 | 128, (netdev->mem_end - netdev->mem_start + 1) / ETHOC_BUFSIZ); |
1127 | if (num_bd < 4) { |
1128 | ret = -ENODEV; |
1129 | goto free; |
1130 | } |
1131 | priv->num_bd = num_bd; |
1132 | /* num_tx must be a power of two */ |
1133 | priv->num_tx = rounddown_pow_of_two(num_bd >> 1); |
1134 | priv->num_rx = num_bd - priv->num_tx; |
1135 | |
1136 | dev_dbg(&pdev->dev, "ethoc: num_tx: %d num_rx: %d\n" , |
1137 | priv->num_tx, priv->num_rx); |
1138 | |
1139 | priv->vma = devm_kcalloc(dev: &pdev->dev, n: num_bd, size: sizeof(void *), |
1140 | GFP_KERNEL); |
1141 | if (!priv->vma) { |
1142 | ret = -ENOMEM; |
1143 | goto free; |
1144 | } |
1145 | |
1146 | /* Allow the platform setup code to pass in a MAC address. */ |
1147 | if (pdata) { |
1148 | eth_hw_addr_set(dev: netdev, addr: pdata->hwaddr); |
1149 | priv->phy_id = pdata->phy_id; |
1150 | } else { |
1151 | of_get_ethdev_address(np: pdev->dev.of_node, dev: netdev); |
1152 | priv->phy_id = -1; |
1153 | } |
1154 | |
1155 | /* Check that the given MAC address is valid. If it isn't, read the |
1156 | * current MAC from the controller. |
1157 | */ |
1158 | if (!is_valid_ether_addr(addr: netdev->dev_addr)) { |
1159 | u8 addr[ETH_ALEN]; |
1160 | |
1161 | ethoc_get_mac_address(dev: netdev, addr); |
1162 | eth_hw_addr_set(dev: netdev, addr); |
1163 | } |
1164 | |
1165 | /* Check the MAC again for validity, if it still isn't choose and |
1166 | * program a random one. |
1167 | */ |
1168 | if (!is_valid_ether_addr(addr: netdev->dev_addr)) |
1169 | eth_hw_addr_random(dev: netdev); |
1170 | |
1171 | ethoc_do_set_mac_address(dev: netdev); |
1172 | |
1173 | /* Allow the platform setup code to adjust MII management bus clock. */ |
1174 | if (!eth_clkfreq) { |
1175 | struct clk *clk = devm_clk_get(dev: &pdev->dev, NULL); |
1176 | |
1177 | if (!IS_ERR(ptr: clk)) { |
1178 | priv->clk = clk; |
1179 | clk_prepare_enable(clk); |
1180 | eth_clkfreq = clk_get_rate(clk); |
1181 | } |
1182 | } |
1183 | if (eth_clkfreq) { |
1184 | u32 clkdiv = MIIMODER_CLKDIV(eth_clkfreq / 2500000 + 1); |
1185 | |
1186 | if (!clkdiv) |
1187 | clkdiv = 2; |
1188 | dev_dbg(&pdev->dev, "setting MII clkdiv to %u\n" , clkdiv); |
1189 | ethoc_write(dev: priv, MIIMODER, |
1190 | data: (ethoc_read(dev: priv, MIIMODER) & MIIMODER_NOPRE) | |
1191 | clkdiv); |
1192 | } |
1193 | |
1194 | /* register MII bus */ |
1195 | priv->mdio = mdiobus_alloc(); |
1196 | if (!priv->mdio) { |
1197 | ret = -ENOMEM; |
1198 | goto free2; |
1199 | } |
1200 | |
1201 | priv->mdio->name = "ethoc-mdio" ; |
1202 | snprintf(buf: priv->mdio->id, MII_BUS_ID_SIZE, fmt: "%s-%d" , |
1203 | priv->mdio->name, pdev->id); |
1204 | priv->mdio->read = ethoc_mdio_read; |
1205 | priv->mdio->write = ethoc_mdio_write; |
1206 | priv->mdio->priv = priv; |
1207 | |
1208 | ret = mdiobus_register(priv->mdio); |
1209 | if (ret) { |
1210 | dev_err(&netdev->dev, "failed to register MDIO bus\n" ); |
1211 | goto free3; |
1212 | } |
1213 | |
1214 | ret = ethoc_mdio_probe(dev: netdev); |
1215 | if (ret) { |
1216 | dev_err(&netdev->dev, "failed to probe MDIO bus\n" ); |
1217 | goto error; |
1218 | } |
1219 | |
1220 | /* setup the net_device structure */ |
1221 | netdev->netdev_ops = ðoc_netdev_ops; |
1222 | netdev->watchdog_timeo = ETHOC_TIMEOUT; |
1223 | netdev->features |= 0; |
1224 | netdev->ethtool_ops = ðoc_ethtool_ops; |
1225 | |
1226 | /* setup NAPI */ |
1227 | netif_napi_add(dev: netdev, napi: &priv->napi, poll: ethoc_poll); |
1228 | |
1229 | spin_lock_init(&priv->lock); |
1230 | |
1231 | ret = register_netdev(dev: netdev); |
1232 | if (ret < 0) { |
1233 | dev_err(&netdev->dev, "failed to register interface\n" ); |
1234 | goto error2; |
1235 | } |
1236 | |
1237 | goto out; |
1238 | |
1239 | error2: |
1240 | netif_napi_del(napi: &priv->napi); |
1241 | error: |
1242 | mdiobus_unregister(bus: priv->mdio); |
1243 | free3: |
1244 | mdiobus_free(bus: priv->mdio); |
1245 | free2: |
1246 | clk_disable_unprepare(clk: priv->clk); |
1247 | free: |
1248 | free_netdev(dev: netdev); |
1249 | out: |
1250 | return ret; |
1251 | } |
1252 | |
1253 | /** |
1254 | * ethoc_remove - shutdown OpenCores ethernet MAC |
1255 | * @pdev: platform device |
1256 | */ |
1257 | static void ethoc_remove(struct platform_device *pdev) |
1258 | { |
1259 | struct net_device *netdev = platform_get_drvdata(pdev); |
1260 | struct ethoc *priv = netdev_priv(dev: netdev); |
1261 | |
1262 | if (netdev) { |
1263 | netif_napi_del(napi: &priv->napi); |
1264 | phy_disconnect(phydev: netdev->phydev); |
1265 | |
1266 | if (priv->mdio) { |
1267 | mdiobus_unregister(bus: priv->mdio); |
1268 | mdiobus_free(bus: priv->mdio); |
1269 | } |
1270 | clk_disable_unprepare(clk: priv->clk); |
1271 | unregister_netdev(dev: netdev); |
1272 | free_netdev(dev: netdev); |
1273 | } |
1274 | } |
1275 | |
1276 | #ifdef CONFIG_PM |
1277 | static int ethoc_suspend(struct platform_device *pdev, pm_message_t state) |
1278 | { |
1279 | return -ENOSYS; |
1280 | } |
1281 | |
1282 | static int ethoc_resume(struct platform_device *pdev) |
1283 | { |
1284 | return -ENOSYS; |
1285 | } |
1286 | #else |
1287 | # define ethoc_suspend NULL |
1288 | # define ethoc_resume NULL |
1289 | #endif |
1290 | |
1291 | static const struct of_device_id ethoc_match[] = { |
1292 | { .compatible = "opencores,ethoc" , }, |
1293 | {}, |
1294 | }; |
1295 | MODULE_DEVICE_TABLE(of, ethoc_match); |
1296 | |
1297 | static struct platform_driver ethoc_driver = { |
1298 | .probe = ethoc_probe, |
1299 | .remove_new = ethoc_remove, |
1300 | .suspend = ethoc_suspend, |
1301 | .resume = ethoc_resume, |
1302 | .driver = { |
1303 | .name = "ethoc" , |
1304 | .of_match_table = ethoc_match, |
1305 | }, |
1306 | }; |
1307 | |
1308 | module_platform_driver(ethoc_driver); |
1309 | |
1310 | MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>" ); |
1311 | MODULE_DESCRIPTION("OpenCores Ethernet MAC driver" ); |
1312 | MODULE_LICENSE("GPL v2" ); |
1313 | |
1314 | |