1/*
2 Written 1998-2000 by Donald Becker.
3
4 This software may be used and distributed according to the terms of
5 the GNU General Public License (GPL), incorporated herein by reference.
6 Drivers based on or derived from this code fall under the GPL and must
7 retain the authorship, copyright and license notice. This file is not
8 a complete program and may only be used when the entire operating
9 system is licensed under the GPL.
10
11 The author may be reached as becker@scyld.com, or C/O
12 Scyld Computing Corporation
13 410 Severn Ave., Suite 210
14 Annapolis MD 21403
15
16 Support information and updates available at
17 http://www.scyld.com/network/pci-skeleton.html
18
19 Linux kernel updates:
20
21 Version 2.51, Nov 17, 2001 (jgarzik):
22 - Add ethtool support
23 - Replace some MII-related magic numbers with constants
24
25*/
26
27#define DRV_NAME "fealnx"
28#define DRV_VERSION "2.52"
29#define DRV_RELDATE "Sep-11-2006"
30
31static int debug; /* 1-> print debug message */
32static int max_interrupt_work = 20;
33
34/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). */
35static int multicast_filter_limit = 32;
36
37/* Set the copy breakpoint for the copy-only-tiny-frames scheme. */
38/* Setting to > 1518 effectively disables this feature. */
39static int rx_copybreak;
40
41/* Used to pass the media type, etc. */
42/* Both 'options[]' and 'full_duplex[]' should exist for driver */
43/* interoperability. */
44/* The media type is usually passed in 'options[]'. */
45#define MAX_UNITS 8 /* More are supported, limit only on options */
46static int options[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
47static int full_duplex[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
48
49/* Operational parameters that are set at compile time. */
50/* Keep the ring sizes a power of two for compile efficiency. */
51/* The compiler will convert <unsigned>'%'<2^N> into a bit mask. */
52/* Making the Tx ring too large decreases the effectiveness of channel */
53/* bonding and packet priority. */
54/* There are no ill effects from too-large receive rings. */
55// 88-12-9 modify,
56// #define TX_RING_SIZE 16
57// #define RX_RING_SIZE 32
58#define TX_RING_SIZE 6
59#define RX_RING_SIZE 12
60#define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct fealnx_desc)
61#define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct fealnx_desc)
62
63/* Operational parameters that usually are not changed. */
64/* Time in jiffies before concluding the transmitter is hung. */
65#define TX_TIMEOUT (2*HZ)
66
67#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer. */
68
69
70/* Include files, designed to support most kernel versions 2.0.0 and later. */
71#include <linux/module.h>
72#include <linux/kernel.h>
73#include <linux/string.h>
74#include <linux/timer.h>
75#include <linux/errno.h>
76#include <linux/ioport.h>
77#include <linux/interrupt.h>
78#include <linux/pci.h>
79#include <linux/netdevice.h>
80#include <linux/etherdevice.h>
81#include <linux/skbuff.h>
82#include <linux/init.h>
83#include <linux/mii.h>
84#include <linux/ethtool.h>
85#include <linux/crc32.h>
86#include <linux/delay.h>
87#include <linux/bitops.h>
88
89#include <asm/processor.h> /* Processor type for cache alignment. */
90#include <asm/io.h>
91#include <linux/uaccess.h>
92#include <asm/byteorder.h>
93
94/* These identify the driver base version and may not be removed. */
95static const char version[] =
96 KERN_INFO DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE "\n";
97
98
99/* This driver was written to use PCI memory space, however some x86 systems
100 work only with I/O space accesses. */
101#ifndef __alpha__
102#define USE_IO_OPS
103#endif
104
105/* Kernel compatibility defines, some common to David Hinds' PCMCIA package. */
106/* This is only in the support-all-kernels source code. */
107
108#define RUN_AT(x) (jiffies + (x))
109
110MODULE_AUTHOR("Myson or whoever");
111MODULE_DESCRIPTION("Myson MTD-8xx 100/10M Ethernet PCI Adapter Driver");
112MODULE_LICENSE("GPL");
113module_param(max_interrupt_work, int, 0);
114module_param(debug, int, 0);
115module_param(rx_copybreak, int, 0);
116module_param(multicast_filter_limit, int, 0);
117module_param_array(options, int, NULL, 0);
118module_param_array(full_duplex, int, NULL, 0);
119MODULE_PARM_DESC(max_interrupt_work, "fealnx maximum events handled per interrupt");
120MODULE_PARM_DESC(debug, "fealnx enable debugging (0-1)");
121MODULE_PARM_DESC(rx_copybreak, "fealnx copy breakpoint for copy-only-tiny-frames");
122MODULE_PARM_DESC(multicast_filter_limit, "fealnx maximum number of filtered multicast addresses");
123MODULE_PARM_DESC(options, "fealnx: Bits 0-3: media type, bit 17: full duplex");
124MODULE_PARM_DESC(full_duplex, "fealnx full duplex setting(s) (1)");
125
126enum {
127 MIN_REGION_SIZE = 136,
128};
129
130/* A chip capabilities table, matching the entries in pci_tbl[] above. */
131enum chip_capability_flags {
132 HAS_MII_XCVR,
133 HAS_CHIP_XCVR,
134};
135
136/* 89/6/13 add, */
137/* for different PHY */
138enum phy_type_flags {
139 MysonPHY = 1,
140 AhdocPHY = 2,
141 SeeqPHY = 3,
142 MarvellPHY = 4,
143 Myson981 = 5,
144 LevelOnePHY = 6,
145 OtherPHY = 10,
146};
147
148struct chip_info {
149 char *chip_name;
150 int flags;
151};
152
153static const struct chip_info skel_netdrv_tbl[] = {
154 { "100/10M Ethernet PCI Adapter", HAS_MII_XCVR },
155 { "100/10M Ethernet PCI Adapter", HAS_CHIP_XCVR },
156 { "1000/100/10M Ethernet PCI Adapter", HAS_MII_XCVR },
157};
158
159/* Offsets to the Command and Status Registers. */
160enum fealnx_offsets {
161 PAR0 = 0x0, /* physical address 0-3 */
162 PAR1 = 0x04, /* physical address 4-5 */
163 MAR0 = 0x08, /* multicast address 0-3 */
164 MAR1 = 0x0C, /* multicast address 4-7 */
165 FAR0 = 0x10, /* flow-control address 0-3 */
166 FAR1 = 0x14, /* flow-control address 4-5 */
167 TCRRCR = 0x18, /* receive & transmit configuration */
168 BCR = 0x1C, /* bus command */
169 TXPDR = 0x20, /* transmit polling demand */
170 RXPDR = 0x24, /* receive polling demand */
171 RXCWP = 0x28, /* receive current word pointer */
172 TXLBA = 0x2C, /* transmit list base address */
173 RXLBA = 0x30, /* receive list base address */
174 ISR = 0x34, /* interrupt status */
175 IMR = 0x38, /* interrupt mask */
176 FTH = 0x3C, /* flow control high/low threshold */
177 MANAGEMENT = 0x40, /* bootrom/eeprom and mii management */
178 TALLY = 0x44, /* tally counters for crc and mpa */
179 TSR = 0x48, /* tally counter for transmit status */
180 BMCRSR = 0x4c, /* basic mode control and status */
181 PHYIDENTIFIER = 0x50, /* phy identifier */
182 ANARANLPAR = 0x54, /* auto-negotiation advertisement and link
183 partner ability */
184 ANEROCR = 0x58, /* auto-negotiation expansion and pci conf. */
185 BPREMRPSR = 0x5c, /* bypass & receive error mask and phy status */
186};
187
188/* Bits in the interrupt status/enable registers. */
189/* The bits in the Intr Status/Enable registers, mostly interrupt sources. */
190enum intr_status_bits {
191 RFCON = 0x00020000, /* receive flow control xon packet */
192 RFCOFF = 0x00010000, /* receive flow control xoff packet */
193 LSCStatus = 0x00008000, /* link status change */
194 ANCStatus = 0x00004000, /* autonegotiation completed */
195 FBE = 0x00002000, /* fatal bus error */
196 FBEMask = 0x00001800, /* mask bit12-11 */
197 ParityErr = 0x00000000, /* parity error */
198 TargetErr = 0x00001000, /* target abort */
199 MasterErr = 0x00000800, /* master error */
200 TUNF = 0x00000400, /* transmit underflow */
201 ROVF = 0x00000200, /* receive overflow */
202 ETI = 0x00000100, /* transmit early int */
203 ERI = 0x00000080, /* receive early int */
204 CNTOVF = 0x00000040, /* counter overflow */
205 RBU = 0x00000020, /* receive buffer unavailable */
206 TBU = 0x00000010, /* transmit buffer unavilable */
207 TI = 0x00000008, /* transmit interrupt */
208 RI = 0x00000004, /* receive interrupt */
209 RxErr = 0x00000002, /* receive error */
210};
211
212/* Bits in the NetworkConfig register, W for writing, R for reading */
213/* FIXME: some names are invented by me. Marked with (name?) */
214/* If you have docs and know bit names, please fix 'em */
215enum rx_mode_bits {
216 CR_W_ENH = 0x02000000, /* enhanced mode (name?) */
217 CR_W_FD = 0x00100000, /* full duplex */
218 CR_W_PS10 = 0x00080000, /* 10 mbit */
219 CR_W_TXEN = 0x00040000, /* tx enable (name?) */
220 CR_W_PS1000 = 0x00010000, /* 1000 mbit */
221 /* CR_W_RXBURSTMASK= 0x00000e00, Im unsure about this */
222 CR_W_RXMODEMASK = 0x000000e0,
223 CR_W_PROM = 0x00000080, /* promiscuous mode */
224 CR_W_AB = 0x00000040, /* accept broadcast */
225 CR_W_AM = 0x00000020, /* accept mutlicast */
226 CR_W_ARP = 0x00000008, /* receive runt pkt */
227 CR_W_ALP = 0x00000004, /* receive long pkt */
228 CR_W_SEP = 0x00000002, /* receive error pkt */
229 CR_W_RXEN = 0x00000001, /* rx enable (unicast?) (name?) */
230
231 CR_R_TXSTOP = 0x04000000, /* tx stopped (name?) */
232 CR_R_FD = 0x00100000, /* full duplex detected */
233 CR_R_PS10 = 0x00080000, /* 10 mbit detected */
234 CR_R_RXSTOP = 0x00008000, /* rx stopped (name?) */
235};
236
237/* The Tulip Rx and Tx buffer descriptors. */
238struct fealnx_desc {
239 s32 status;
240 s32 control;
241 u32 buffer;
242 u32 next_desc;
243 struct fealnx_desc *next_desc_logical;
244 struct sk_buff *skbuff;
245 u32 reserved1;
246 u32 reserved2;
247};
248
249/* Bits in network_desc.status */
250enum rx_desc_status_bits {
251 RXOWN = 0x80000000, /* own bit */
252 FLNGMASK = 0x0fff0000, /* frame length */
253 FLNGShift = 16,
254 MARSTATUS = 0x00004000, /* multicast address received */
255 BARSTATUS = 0x00002000, /* broadcast address received */
256 PHYSTATUS = 0x00001000, /* physical address received */
257 RXFSD = 0x00000800, /* first descriptor */
258 RXLSD = 0x00000400, /* last descriptor */
259 ErrorSummary = 0x80, /* error summary */
260 RUNTPKT = 0x40, /* runt packet received */
261 LONGPKT = 0x20, /* long packet received */
262 FAE = 0x10, /* frame align error */
263 CRC = 0x08, /* crc error */
264 RXER = 0x04, /* receive error */
265};
266
267enum rx_desc_control_bits {
268 RXIC = 0x00800000, /* interrupt control */
269 RBSShift = 0,
270};
271
272enum tx_desc_status_bits {
273 TXOWN = 0x80000000, /* own bit */
274 JABTO = 0x00004000, /* jabber timeout */
275 CSL = 0x00002000, /* carrier sense lost */
276 LC = 0x00001000, /* late collision */
277 EC = 0x00000800, /* excessive collision */
278 UDF = 0x00000400, /* fifo underflow */
279 DFR = 0x00000200, /* deferred */
280 HF = 0x00000100, /* heartbeat fail */
281 NCRMask = 0x000000ff, /* collision retry count */
282 NCRShift = 0,
283};
284
285enum tx_desc_control_bits {
286 TXIC = 0x80000000, /* interrupt control */
287 ETIControl = 0x40000000, /* early transmit interrupt */
288 TXLD = 0x20000000, /* last descriptor */
289 TXFD = 0x10000000, /* first descriptor */
290 CRCEnable = 0x08000000, /* crc control */
291 PADEnable = 0x04000000, /* padding control */
292 RetryTxLC = 0x02000000, /* retry late collision */
293 PKTSMask = 0x3ff800, /* packet size bit21-11 */
294 PKTSShift = 11,
295 TBSMask = 0x000007ff, /* transmit buffer bit 10-0 */
296 TBSShift = 0,
297};
298
299/* BootROM/EEPROM/MII Management Register */
300#define MASK_MIIR_MII_READ 0x00000000
301#define MASK_MIIR_MII_WRITE 0x00000008
302#define MASK_MIIR_MII_MDO 0x00000004
303#define MASK_MIIR_MII_MDI 0x00000002
304#define MASK_MIIR_MII_MDC 0x00000001
305
306/* ST+OP+PHYAD+REGAD+TA */
307#define OP_READ 0x6000 /* ST:01+OP:10+PHYAD+REGAD+TA:Z0 */
308#define OP_WRITE 0x5002 /* ST:01+OP:01+PHYAD+REGAD+TA:10 */
309
310/* ------------------------------------------------------------------------- */
311/* Constants for Myson PHY */
312/* ------------------------------------------------------------------------- */
313#define MysonPHYID 0xd0000302
314/* 89-7-27 add, (begin) */
315#define MysonPHYID0 0x0302
316#define StatusRegister 18
317#define SPEED100 0x0400 // bit10
318#define FULLMODE 0x0800 // bit11
319/* 89-7-27 add, (end) */
320
321/* ------------------------------------------------------------------------- */
322/* Constants for Seeq 80225 PHY */
323/* ------------------------------------------------------------------------- */
324#define SeeqPHYID0 0x0016
325
326#define MIIRegister18 18
327#define SPD_DET_100 0x80
328#define DPLX_DET_FULL 0x40
329
330/* ------------------------------------------------------------------------- */
331/* Constants for Ahdoc 101 PHY */
332/* ------------------------------------------------------------------------- */
333#define AhdocPHYID0 0x0022
334
335#define DiagnosticReg 18
336#define DPLX_FULL 0x0800
337#define Speed_100 0x0400
338
339/* 89/6/13 add, */
340/* -------------------------------------------------------------------------- */
341/* Constants */
342/* -------------------------------------------------------------------------- */
343#define MarvellPHYID0 0x0141
344#define LevelOnePHYID0 0x0013
345
346#define MII1000BaseTControlReg 9
347#define MII1000BaseTStatusReg 10
348#define SpecificReg 17
349
350/* for 1000BaseT Control Register */
351#define PHYAbletoPerform1000FullDuplex 0x0200
352#define PHYAbletoPerform1000HalfDuplex 0x0100
353#define PHY1000AbilityMask 0x300
354
355// for phy specific status register, marvell phy.
356#define SpeedMask 0x0c000
357#define Speed_1000M 0x08000
358#define Speed_100M 0x4000
359#define Speed_10M 0
360#define Full_Duplex 0x2000
361
362// 89/12/29 add, for phy specific status register, levelone phy, (begin)
363#define LXT1000_100M 0x08000
364#define LXT1000_1000M 0x0c000
365#define LXT1000_Full 0x200
366// 89/12/29 add, for phy specific status register, levelone phy, (end)
367
368/* for 3-in-1 case, BMCRSR register */
369#define LinkIsUp2 0x00040000
370
371/* for PHY */
372#define LinkIsUp 0x0004
373
374
375struct netdev_private {
376 /* Descriptor rings first for alignment. */
377 struct fealnx_desc *rx_ring;
378 struct fealnx_desc *tx_ring;
379
380 dma_addr_t rx_ring_dma;
381 dma_addr_t tx_ring_dma;
382
383 spinlock_t lock;
384
385 /* Media monitoring timer. */
386 struct timer_list timer;
387
388 /* Reset timer */
389 struct timer_list reset_timer;
390 int reset_timer_armed;
391 unsigned long crvalue_sv;
392 unsigned long imrvalue_sv;
393
394 /* Frequently used values: keep some adjacent for cache effect. */
395 int flags;
396 struct pci_dev *pci_dev;
397 unsigned long crvalue;
398 unsigned long bcrvalue;
399 unsigned long imrvalue;
400 struct fealnx_desc *cur_rx;
401 struct fealnx_desc *lack_rxbuf;
402 int really_rx_count;
403 struct fealnx_desc *cur_tx;
404 struct fealnx_desc *cur_tx_copy;
405 int really_tx_count;
406 int free_tx_count;
407 unsigned int rx_buf_sz; /* Based on MTU+slack. */
408
409 /* These values are keep track of the transceiver/media in use. */
410 unsigned int linkok;
411 unsigned int line_speed;
412 unsigned int duplexmode;
413 unsigned int default_port:4; /* Last dev->if_port value. */
414 unsigned int PHYType;
415
416 /* MII transceiver section. */
417 int mii_cnt; /* MII device addresses. */
418 unsigned char phys[2]; /* MII device addresses. */
419 struct mii_if_info mii;
420 void __iomem *mem;
421};
422
423
424static int mdio_read(struct net_device *dev, int phy_id, int location);
425static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
426static int netdev_open(struct net_device *dev);
427static void getlinktype(struct net_device *dev);
428static void getlinkstatus(struct net_device *dev);
429static void netdev_timer(struct timer_list *t);
430static void reset_timer(struct timer_list *t);
431static void fealnx_tx_timeout(struct net_device *dev);
432static void init_ring(struct net_device *dev);
433static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev);
434static irqreturn_t intr_handler(int irq, void *dev_instance);
435static int netdev_rx(struct net_device *dev);
436static void set_rx_mode(struct net_device *dev);
437static void __set_rx_mode(struct net_device *dev);
438static struct net_device_stats *get_stats(struct net_device *dev);
439static int mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
440static const struct ethtool_ops netdev_ethtool_ops;
441static int netdev_close(struct net_device *dev);
442static void reset_rx_descriptors(struct net_device *dev);
443static void reset_tx_descriptors(struct net_device *dev);
444
445static void stop_nic_rx(void __iomem *ioaddr, long crvalue)
446{
447 int delay = 0x1000;
448 iowrite32(crvalue & ~(CR_W_RXEN), ioaddr + TCRRCR);
449 while (--delay) {
450 if ( (ioread32(ioaddr + TCRRCR) & CR_R_RXSTOP) == CR_R_RXSTOP)
451 break;
452 }
453}
454
455
456static void stop_nic_rxtx(void __iomem *ioaddr, long crvalue)
457{
458 int delay = 0x1000;
459 iowrite32(crvalue & ~(CR_W_RXEN+CR_W_TXEN), ioaddr + TCRRCR);
460 while (--delay) {
461 if ( (ioread32(ioaddr + TCRRCR) & (CR_R_RXSTOP+CR_R_TXSTOP))
462 == (CR_R_RXSTOP+CR_R_TXSTOP) )
463 break;
464 }
465}
466
467static const struct net_device_ops netdev_ops = {
468 .ndo_open = netdev_open,
469 .ndo_stop = netdev_close,
470 .ndo_start_xmit = start_tx,
471 .ndo_get_stats = get_stats,
472 .ndo_set_rx_mode = set_rx_mode,
473 .ndo_do_ioctl = mii_ioctl,
474 .ndo_tx_timeout = fealnx_tx_timeout,
475 .ndo_set_mac_address = eth_mac_addr,
476 .ndo_validate_addr = eth_validate_addr,
477};
478
479static int fealnx_init_one(struct pci_dev *pdev,
480 const struct pci_device_id *ent)
481{
482 struct netdev_private *np;
483 int i, option, err, irq;
484 static int card_idx = -1;
485 char boardname[12];
486 void __iomem *ioaddr;
487 unsigned long len;
488 unsigned int chip_id = ent->driver_data;
489 struct net_device *dev;
490 void *ring_space;
491 dma_addr_t ring_dma;
492#ifdef USE_IO_OPS
493 int bar = 0;
494#else
495 int bar = 1;
496#endif
497
498/* when built into the kernel, we only print version if device is found */
499#ifndef MODULE
500 static int printed_version;
501 if (!printed_version++)
502 printk(version);
503#endif
504
505 card_idx++;
506 sprintf(boardname, "fealnx%d", card_idx);
507
508 option = card_idx < MAX_UNITS ? options[card_idx] : 0;
509
510 i = pci_enable_device(pdev);
511 if (i) return i;
512 pci_set_master(pdev);
513
514 len = pci_resource_len(pdev, bar);
515 if (len < MIN_REGION_SIZE) {
516 dev_err(&pdev->dev,
517 "region size %ld too small, aborting\n", len);
518 return -ENODEV;
519 }
520
521 i = pci_request_regions(pdev, boardname);
522 if (i)
523 return i;
524
525 irq = pdev->irq;
526
527 ioaddr = pci_iomap(pdev, bar, len);
528 if (!ioaddr) {
529 err = -ENOMEM;
530 goto err_out_res;
531 }
532
533 dev = alloc_etherdev(sizeof(struct netdev_private));
534 if (!dev) {
535 err = -ENOMEM;
536 goto err_out_unmap;
537 }
538 SET_NETDEV_DEV(dev, &pdev->dev);
539
540 /* read ethernet id */
541 for (i = 0; i < 6; ++i)
542 dev->dev_addr[i] = ioread8(ioaddr + PAR0 + i);
543
544 /* Reset the chip to erase previous misconfiguration. */
545 iowrite32(0x00000001, ioaddr + BCR);
546
547 /* Make certain the descriptor lists are aligned. */
548 np = netdev_priv(dev);
549 np->mem = ioaddr;
550 spin_lock_init(&np->lock);
551 np->pci_dev = pdev;
552 np->flags = skel_netdrv_tbl[chip_id].flags;
553 pci_set_drvdata(pdev, dev);
554 np->mii.dev = dev;
555 np->mii.mdio_read = mdio_read;
556 np->mii.mdio_write = mdio_write;
557 np->mii.phy_id_mask = 0x1f;
558 np->mii.reg_num_mask = 0x1f;
559
560 ring_space = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma);
561 if (!ring_space) {
562 err = -ENOMEM;
563 goto err_out_free_dev;
564 }
565 np->rx_ring = ring_space;
566 np->rx_ring_dma = ring_dma;
567
568 ring_space = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma);
569 if (!ring_space) {
570 err = -ENOMEM;
571 goto err_out_free_rx;
572 }
573 np->tx_ring = ring_space;
574 np->tx_ring_dma = ring_dma;
575
576 /* find the connected MII xcvrs */
577 if (np->flags == HAS_MII_XCVR) {
578 int phy, phy_idx = 0;
579
580 for (phy = 1; phy < 32 && phy_idx < ARRAY_SIZE(np->phys);
581 phy++) {
582 int mii_status = mdio_read(dev, phy, 1);
583
584 if (mii_status != 0xffff && mii_status != 0x0000) {
585 np->phys[phy_idx++] = phy;
586 dev_info(&pdev->dev,
587 "MII PHY found at address %d, status "
588 "0x%4.4x.\n", phy, mii_status);
589 /* get phy type */
590 {
591 unsigned int data;
592
593 data = mdio_read(dev, np->phys[0], 2);
594 if (data == SeeqPHYID0)
595 np->PHYType = SeeqPHY;
596 else if (data == AhdocPHYID0)
597 np->PHYType = AhdocPHY;
598 else if (data == MarvellPHYID0)
599 np->PHYType = MarvellPHY;
600 else if (data == MysonPHYID0)
601 np->PHYType = Myson981;
602 else if (data == LevelOnePHYID0)
603 np->PHYType = LevelOnePHY;
604 else
605 np->PHYType = OtherPHY;
606 }
607 }
608 }
609
610 np->mii_cnt = phy_idx;
611 if (phy_idx == 0)
612 dev_warn(&pdev->dev,
613 "MII PHY not found -- this device may "
614 "not operate correctly.\n");
615 } else {
616 np->phys[0] = 32;
617/* 89/6/23 add, (begin) */
618 /* get phy type */
619 if (ioread32(ioaddr + PHYIDENTIFIER) == MysonPHYID)
620 np->PHYType = MysonPHY;
621 else
622 np->PHYType = OtherPHY;
623 }
624 np->mii.phy_id = np->phys[0];
625
626 if (dev->mem_start)
627 option = dev->mem_start;
628
629 /* The lower four bits are the media type. */
630 if (option > 0) {
631 if (option & 0x200)
632 np->mii.full_duplex = 1;
633 np->default_port = option & 15;
634 }
635
636 if (card_idx < MAX_UNITS && full_duplex[card_idx] > 0)
637 np->mii.full_duplex = full_duplex[card_idx];
638
639 if (np->mii.full_duplex) {
640 dev_info(&pdev->dev, "Media type forced to Full Duplex.\n");
641/* 89/6/13 add, (begin) */
642// if (np->PHYType==MarvellPHY)
643 if ((np->PHYType == MarvellPHY) || (np->PHYType == LevelOnePHY)) {
644 unsigned int data;
645
646 data = mdio_read(dev, np->phys[0], 9);
647 data = (data & 0xfcff) | 0x0200;
648 mdio_write(dev, np->phys[0], 9, data);
649 }
650/* 89/6/13 add, (end) */
651 if (np->flags == HAS_MII_XCVR)
652 mdio_write(dev, np->phys[0], MII_ADVERTISE, ADVERTISE_FULL);
653 else
654 iowrite32(ADVERTISE_FULL, ioaddr + ANARANLPAR);
655 np->mii.force_media = 1;
656 }
657
658 dev->netdev_ops = &netdev_ops;
659 dev->ethtool_ops = &netdev_ethtool_ops;
660 dev->watchdog_timeo = TX_TIMEOUT;
661
662 err = register_netdev(dev);
663 if (err)
664 goto err_out_free_tx;
665
666 printk(KERN_INFO "%s: %s at %p, %pM, IRQ %d.\n",
667 dev->name, skel_netdrv_tbl[chip_id].chip_name, ioaddr,
668 dev->dev_addr, irq);
669
670 return 0;
671
672err_out_free_tx:
673 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
674err_out_free_rx:
675 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
676err_out_free_dev:
677 free_netdev(dev);
678err_out_unmap:
679 pci_iounmap(pdev, ioaddr);
680err_out_res:
681 pci_release_regions(pdev);
682 return err;
683}
684
685
686static void fealnx_remove_one(struct pci_dev *pdev)
687{
688 struct net_device *dev = pci_get_drvdata(pdev);
689
690 if (dev) {
691 struct netdev_private *np = netdev_priv(dev);
692
693 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring,
694 np->tx_ring_dma);
695 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring,
696 np->rx_ring_dma);
697 unregister_netdev(dev);
698 pci_iounmap(pdev, np->mem);
699 free_netdev(dev);
700 pci_release_regions(pdev);
701 } else
702 printk(KERN_ERR "fealnx: remove for unknown device\n");
703}
704
705
706static ulong m80x_send_cmd_to_phy(void __iomem *miiport, int opcode, int phyad, int regad)
707{
708 ulong miir;
709 int i;
710 unsigned int mask, data;
711
712 /* enable MII output */
713 miir = (ulong) ioread32(miiport);
714 miir &= 0xfffffff0;
715
716 miir |= MASK_MIIR_MII_WRITE + MASK_MIIR_MII_MDO;
717
718 /* send 32 1's preamble */
719 for (i = 0; i < 32; i++) {
720 /* low MDC; MDO is already high (miir) */
721 miir &= ~MASK_MIIR_MII_MDC;
722 iowrite32(miir, miiport);
723
724 /* high MDC */
725 miir |= MASK_MIIR_MII_MDC;
726 iowrite32(miir, miiport);
727 }
728
729 /* calculate ST+OP+PHYAD+REGAD+TA */
730 data = opcode | (phyad << 7) | (regad << 2);
731
732 /* sent out */
733 mask = 0x8000;
734 while (mask) {
735 /* low MDC, prepare MDO */
736 miir &= ~(MASK_MIIR_MII_MDC + MASK_MIIR_MII_MDO);
737 if (mask & data)
738 miir |= MASK_MIIR_MII_MDO;
739
740 iowrite32(miir, miiport);
741 /* high MDC */
742 miir |= MASK_MIIR_MII_MDC;
743 iowrite32(miir, miiport);
744 udelay(30);
745
746 /* next */
747 mask >>= 1;
748 if (mask == 0x2 && opcode == OP_READ)
749 miir &= ~MASK_MIIR_MII_WRITE;
750 }
751 return miir;
752}
753
754
755static int mdio_read(struct net_device *dev, int phyad, int regad)
756{
757 struct netdev_private *np = netdev_priv(dev);
758 void __iomem *miiport = np->mem + MANAGEMENT;
759 ulong miir;
760 unsigned int mask, data;
761
762 miir = m80x_send_cmd_to_phy(miiport, OP_READ, phyad, regad);
763
764 /* read data */
765 mask = 0x8000;
766 data = 0;
767 while (mask) {
768 /* low MDC */
769 miir &= ~MASK_MIIR_MII_MDC;
770 iowrite32(miir, miiport);
771
772 /* read MDI */
773 miir = ioread32(miiport);
774 if (miir & MASK_MIIR_MII_MDI)
775 data |= mask;
776
777 /* high MDC, and wait */
778 miir |= MASK_MIIR_MII_MDC;
779 iowrite32(miir, miiport);
780 udelay(30);
781
782 /* next */
783 mask >>= 1;
784 }
785
786 /* low MDC */
787 miir &= ~MASK_MIIR_MII_MDC;
788 iowrite32(miir, miiport);
789
790 return data & 0xffff;
791}
792
793
794static void mdio_write(struct net_device *dev, int phyad, int regad, int data)
795{
796 struct netdev_private *np = netdev_priv(dev);
797 void __iomem *miiport = np->mem + MANAGEMENT;
798 ulong miir;
799 unsigned int mask;
800
801 miir = m80x_send_cmd_to_phy(miiport, OP_WRITE, phyad, regad);
802
803 /* write data */
804 mask = 0x8000;
805 while (mask) {
806 /* low MDC, prepare MDO */
807 miir &= ~(MASK_MIIR_MII_MDC + MASK_MIIR_MII_MDO);
808 if (mask & data)
809 miir |= MASK_MIIR_MII_MDO;
810 iowrite32(miir, miiport);
811
812 /* high MDC */
813 miir |= MASK_MIIR_MII_MDC;
814 iowrite32(miir, miiport);
815
816 /* next */
817 mask >>= 1;
818 }
819
820 /* low MDC */
821 miir &= ~MASK_MIIR_MII_MDC;
822 iowrite32(miir, miiport);
823}
824
825
826static int netdev_open(struct net_device *dev)
827{
828 struct netdev_private *np = netdev_priv(dev);
829 void __iomem *ioaddr = np->mem;
830 const int irq = np->pci_dev->irq;
831 int rc, i;
832
833 iowrite32(0x00000001, ioaddr + BCR); /* Reset */
834
835 rc = request_irq(irq, intr_handler, IRQF_SHARED, dev->name, dev);
836 if (rc)
837 return -EAGAIN;
838
839 for (i = 0; i < 3; i++)
840 iowrite16(((unsigned short*)dev->dev_addr)[i],
841 ioaddr + PAR0 + i*2);
842
843 init_ring(dev);
844
845 iowrite32(np->rx_ring_dma, ioaddr + RXLBA);
846 iowrite32(np->tx_ring_dma, ioaddr + TXLBA);
847
848 /* Initialize other registers. */
849 /* Configure the PCI bus bursts and FIFO thresholds.
850 486: Set 8 longword burst.
851 586: no burst limit.
852 Burst length 5:3
853 0 0 0 1
854 0 0 1 4
855 0 1 0 8
856 0 1 1 16
857 1 0 0 32
858 1 0 1 64
859 1 1 0 128
860 1 1 1 256
861 Wait the specified 50 PCI cycles after a reset by initializing
862 Tx and Rx queues and the address filter list.
863 FIXME (Ueimor): optimistic for alpha + posted writes ? */
864
865 np->bcrvalue = 0x10; /* little-endian, 8 burst length */
866#ifdef __BIG_ENDIAN
867 np->bcrvalue |= 0x04; /* big-endian */
868#endif
869
870#if defined(__i386__) && !defined(MODULE)
871 if (boot_cpu_data.x86 <= 4)
872 np->crvalue = 0xa00;
873 else
874#endif
875 np->crvalue = 0xe00; /* rx 128 burst length */
876
877
878// 89/12/29 add,
879// 90/1/16 modify,
880// np->imrvalue=FBE|TUNF|CNTOVF|RBU|TI|RI;
881 np->imrvalue = TUNF | CNTOVF | RBU | TI | RI;
882 if (np->pci_dev->device == 0x891) {
883 np->bcrvalue |= 0x200; /* set PROG bit */
884 np->crvalue |= CR_W_ENH; /* set enhanced bit */
885 np->imrvalue |= ETI;
886 }
887 iowrite32(np->bcrvalue, ioaddr + BCR);
888
889 if (dev->if_port == 0)
890 dev->if_port = np->default_port;
891
892 iowrite32(0, ioaddr + RXPDR);
893// 89/9/1 modify,
894// np->crvalue = 0x00e40001; /* tx store and forward, tx/rx enable */
895 np->crvalue |= 0x00e40001; /* tx store and forward, tx/rx enable */
896 np->mii.full_duplex = np->mii.force_media;
897 getlinkstatus(dev);
898 if (np->linkok)
899 getlinktype(dev);
900 __set_rx_mode(dev);
901
902 netif_start_queue(dev);
903
904 /* Clear and Enable interrupts by setting the interrupt mask. */
905 iowrite32(FBE | TUNF | CNTOVF | RBU | TI | RI, ioaddr + ISR);
906 iowrite32(np->imrvalue, ioaddr + IMR);
907
908 if (debug)
909 printk(KERN_DEBUG "%s: Done netdev_open().\n", dev->name);
910
911 /* Set the timer to check for link beat. */
912 timer_setup(&np->timer, netdev_timer, 0);
913 np->timer.expires = RUN_AT(3 * HZ);
914
915 /* timer handler */
916 add_timer(&np->timer);
917
918 timer_setup(&np->reset_timer, reset_timer, 0);
919 np->reset_timer_armed = 0;
920 return rc;
921}
922
923
924static void getlinkstatus(struct net_device *dev)
925/* function: Routine will read MII Status Register to get link status. */
926/* input : dev... pointer to the adapter block. */
927/* output : none. */
928{
929 struct netdev_private *np = netdev_priv(dev);
930 unsigned int i, DelayTime = 0x1000;
931
932 np->linkok = 0;
933
934 if (np->PHYType == MysonPHY) {
935 for (i = 0; i < DelayTime; ++i) {
936 if (ioread32(np->mem + BMCRSR) & LinkIsUp2) {
937 np->linkok = 1;
938 return;
939 }
940 udelay(100);
941 }
942 } else {
943 for (i = 0; i < DelayTime; ++i) {
944 if (mdio_read(dev, np->phys[0], MII_BMSR) & BMSR_LSTATUS) {
945 np->linkok = 1;
946 return;
947 }
948 udelay(100);
949 }
950 }
951}
952
953
954static void getlinktype(struct net_device *dev)
955{
956 struct netdev_private *np = netdev_priv(dev);
957
958 if (np->PHYType == MysonPHY) { /* 3-in-1 case */
959 if (ioread32(np->mem + TCRRCR) & CR_R_FD)
960 np->duplexmode = 2; /* full duplex */
961 else
962 np->duplexmode = 1; /* half duplex */
963 if (ioread32(np->mem + TCRRCR) & CR_R_PS10)
964 np->line_speed = 1; /* 10M */
965 else
966 np->line_speed = 2; /* 100M */
967 } else {
968 if (np->PHYType == SeeqPHY) { /* this PHY is SEEQ 80225 */
969 unsigned int data;
970
971 data = mdio_read(dev, np->phys[0], MIIRegister18);
972 if (data & SPD_DET_100)
973 np->line_speed = 2; /* 100M */
974 else
975 np->line_speed = 1; /* 10M */
976 if (data & DPLX_DET_FULL)
977 np->duplexmode = 2; /* full duplex mode */
978 else
979 np->duplexmode = 1; /* half duplex mode */
980 } else if (np->PHYType == AhdocPHY) {
981 unsigned int data;
982
983 data = mdio_read(dev, np->phys[0], DiagnosticReg);
984 if (data & Speed_100)
985 np->line_speed = 2; /* 100M */
986 else
987 np->line_speed = 1; /* 10M */
988 if (data & DPLX_FULL)
989 np->duplexmode = 2; /* full duplex mode */
990 else
991 np->duplexmode = 1; /* half duplex mode */
992 }
993/* 89/6/13 add, (begin) */
994 else if (np->PHYType == MarvellPHY) {
995 unsigned int data;
996
997 data = mdio_read(dev, np->phys[0], SpecificReg);
998 if (data & Full_Duplex)
999 np->duplexmode = 2; /* full duplex mode */
1000 else
1001 np->duplexmode = 1; /* half duplex mode */
1002 data &= SpeedMask;
1003 if (data == Speed_1000M)
1004 np->line_speed = 3; /* 1000M */
1005 else if (data == Speed_100M)
1006 np->line_speed = 2; /* 100M */
1007 else
1008 np->line_speed = 1; /* 10M */
1009 }
1010/* 89/6/13 add, (end) */
1011/* 89/7/27 add, (begin) */
1012 else if (np->PHYType == Myson981) {
1013 unsigned int data;
1014
1015 data = mdio_read(dev, np->phys[0], StatusRegister);
1016
1017 if (data & SPEED100)
1018 np->line_speed = 2;
1019 else
1020 np->line_speed = 1;
1021
1022 if (data & FULLMODE)
1023 np->duplexmode = 2;
1024 else
1025 np->duplexmode = 1;
1026 }
1027/* 89/7/27 add, (end) */
1028/* 89/12/29 add */
1029 else if (np->PHYType == LevelOnePHY) {
1030 unsigned int data;
1031
1032 data = mdio_read(dev, np->phys[0], SpecificReg);
1033 if (data & LXT1000_Full)
1034 np->duplexmode = 2; /* full duplex mode */
1035 else
1036 np->duplexmode = 1; /* half duplex mode */
1037 data &= SpeedMask;
1038 if (data == LXT1000_1000M)
1039 np->line_speed = 3; /* 1000M */
1040 else if (data == LXT1000_100M)
1041 np->line_speed = 2; /* 100M */
1042 else
1043 np->line_speed = 1; /* 10M */
1044 }
1045 np->crvalue &= (~CR_W_PS10) & (~CR_W_FD) & (~CR_W_PS1000);
1046 if (np->line_speed == 1)
1047 np->crvalue |= CR_W_PS10;
1048 else if (np->line_speed == 3)
1049 np->crvalue |= CR_W_PS1000;
1050 if (np->duplexmode == 2)
1051 np->crvalue |= CR_W_FD;
1052 }
1053}
1054
1055
1056/* Take lock before calling this */
1057static void allocate_rx_buffers(struct net_device *dev)
1058{
1059 struct netdev_private *np = netdev_priv(dev);
1060
1061 /* allocate skb for rx buffers */
1062 while (np->really_rx_count != RX_RING_SIZE) {
1063 struct sk_buff *skb;
1064
1065 skb = netdev_alloc_skb(dev, np->rx_buf_sz);
1066 if (skb == NULL)
1067 break; /* Better luck next round. */
1068
1069 while (np->lack_rxbuf->skbuff)
1070 np->lack_rxbuf = np->lack_rxbuf->next_desc_logical;
1071
1072 np->lack_rxbuf->skbuff = skb;
1073 np->lack_rxbuf->buffer = pci_map_single(np->pci_dev, skb->data,
1074 np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1075 np->lack_rxbuf->status = RXOWN;
1076 ++np->really_rx_count;
1077 }
1078}
1079
1080
1081static void netdev_timer(struct timer_list *t)
1082{
1083 struct netdev_private *np = from_timer(np, t, timer);
1084 struct net_device *dev = np->mii.dev;
1085 void __iomem *ioaddr = np->mem;
1086 int old_crvalue = np->crvalue;
1087 unsigned int old_linkok = np->linkok;
1088 unsigned long flags;
1089
1090 if (debug)
1091 printk(KERN_DEBUG "%s: Media selection timer tick, status %8.8x "
1092 "config %8.8x.\n", dev->name, ioread32(ioaddr + ISR),
1093 ioread32(ioaddr + TCRRCR));
1094
1095 spin_lock_irqsave(&np->lock, flags);
1096
1097 if (np->flags == HAS_MII_XCVR) {
1098 getlinkstatus(dev);
1099 if ((old_linkok == 0) && (np->linkok == 1)) { /* we need to detect the media type again */
1100 getlinktype(dev);
1101 if (np->crvalue != old_crvalue) {
1102 stop_nic_rxtx(ioaddr, np->crvalue);
1103 iowrite32(np->crvalue, ioaddr + TCRRCR);
1104 }
1105 }
1106 }
1107
1108 allocate_rx_buffers(dev);
1109
1110 spin_unlock_irqrestore(&np->lock, flags);
1111
1112 np->timer.expires = RUN_AT(10 * HZ);
1113 add_timer(&np->timer);
1114}
1115
1116
1117/* Take lock before calling */
1118/* Reset chip and disable rx, tx and interrupts */
1119static void reset_and_disable_rxtx(struct net_device *dev)
1120{
1121 struct netdev_private *np = netdev_priv(dev);
1122 void __iomem *ioaddr = np->mem;
1123 int delay=51;
1124
1125 /* Reset the chip's Tx and Rx processes. */
1126 stop_nic_rxtx(ioaddr, 0);
1127
1128 /* Disable interrupts by clearing the interrupt mask. */
1129 iowrite32(0, ioaddr + IMR);
1130
1131 /* Reset the chip to erase previous misconfiguration. */
1132 iowrite32(0x00000001, ioaddr + BCR);
1133
1134 /* Ueimor: wait for 50 PCI cycles (and flush posted writes btw).
1135 We surely wait too long (address+data phase). Who cares? */
1136 while (--delay) {
1137 ioread32(ioaddr + BCR);
1138 rmb();
1139 }
1140}
1141
1142
1143/* Take lock before calling */
1144/* Restore chip after reset */
1145static void enable_rxtx(struct net_device *dev)
1146{
1147 struct netdev_private *np = netdev_priv(dev);
1148 void __iomem *ioaddr = np->mem;
1149
1150 reset_rx_descriptors(dev);
1151
1152 iowrite32(np->tx_ring_dma + ((char*)np->cur_tx - (char*)np->tx_ring),
1153 ioaddr + TXLBA);
1154 iowrite32(np->rx_ring_dma + ((char*)np->cur_rx - (char*)np->rx_ring),
1155 ioaddr + RXLBA);
1156
1157 iowrite32(np->bcrvalue, ioaddr + BCR);
1158
1159 iowrite32(0, ioaddr + RXPDR);
1160 __set_rx_mode(dev); /* changes np->crvalue, writes it into TCRRCR */
1161
1162 /* Clear and Enable interrupts by setting the interrupt mask. */
1163 iowrite32(FBE | TUNF | CNTOVF | RBU | TI | RI, ioaddr + ISR);
1164 iowrite32(np->imrvalue, ioaddr + IMR);
1165
1166 iowrite32(0, ioaddr + TXPDR);
1167}
1168
1169
1170static void reset_timer(struct timer_list *t)
1171{
1172 struct netdev_private *np = from_timer(np, t, reset_timer);
1173 struct net_device *dev = np->mii.dev;
1174 unsigned long flags;
1175
1176 printk(KERN_WARNING "%s: resetting tx and rx machinery\n", dev->name);
1177
1178 spin_lock_irqsave(&np->lock, flags);
1179 np->crvalue = np->crvalue_sv;
1180 np->imrvalue = np->imrvalue_sv;
1181
1182 reset_and_disable_rxtx(dev);
1183 /* works for me without this:
1184 reset_tx_descriptors(dev); */
1185 enable_rxtx(dev);
1186 netif_start_queue(dev); /* FIXME: or netif_wake_queue(dev); ? */
1187
1188 np->reset_timer_armed = 0;
1189
1190 spin_unlock_irqrestore(&np->lock, flags);
1191}
1192
1193
1194static void fealnx_tx_timeout(struct net_device *dev)
1195{
1196 struct netdev_private *np = netdev_priv(dev);
1197 void __iomem *ioaddr = np->mem;
1198 unsigned long flags;
1199 int i;
1200
1201 printk(KERN_WARNING
1202 "%s: Transmit timed out, status %8.8x, resetting...\n",
1203 dev->name, ioread32(ioaddr + ISR));
1204
1205 {
1206 printk(KERN_DEBUG " Rx ring %p: ", np->rx_ring);
1207 for (i = 0; i < RX_RING_SIZE; i++)
1208 printk(KERN_CONT " %8.8x",
1209 (unsigned int) np->rx_ring[i].status);
1210 printk(KERN_CONT "\n");
1211 printk(KERN_DEBUG " Tx ring %p: ", np->tx_ring);
1212 for (i = 0; i < TX_RING_SIZE; i++)
1213 printk(KERN_CONT " %4.4x", np->tx_ring[i].status);
1214 printk(KERN_CONT "\n");
1215 }
1216
1217 spin_lock_irqsave(&np->lock, flags);
1218
1219 reset_and_disable_rxtx(dev);
1220 reset_tx_descriptors(dev);
1221 enable_rxtx(dev);
1222
1223 spin_unlock_irqrestore(&np->lock, flags);
1224
1225 netif_trans_update(dev); /* prevent tx timeout */
1226 dev->stats.tx_errors++;
1227 netif_wake_queue(dev); /* or .._start_.. ?? */
1228}
1229
1230
1231/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1232static void init_ring(struct net_device *dev)
1233{
1234 struct netdev_private *np = netdev_priv(dev);
1235 int i;
1236
1237 /* initialize rx variables */
1238 np->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
1239 np->cur_rx = &np->rx_ring[0];
1240 np->lack_rxbuf = np->rx_ring;
1241 np->really_rx_count = 0;
1242
1243 /* initial rx descriptors. */
1244 for (i = 0; i < RX_RING_SIZE; i++) {
1245 np->rx_ring[i].status = 0;
1246 np->rx_ring[i].control = np->rx_buf_sz << RBSShift;
1247 np->rx_ring[i].next_desc = np->rx_ring_dma +
1248 (i + 1)*sizeof(struct fealnx_desc);
1249 np->rx_ring[i].next_desc_logical = &np->rx_ring[i + 1];
1250 np->rx_ring[i].skbuff = NULL;
1251 }
1252
1253 /* for the last rx descriptor */
1254 np->rx_ring[i - 1].next_desc = np->rx_ring_dma;
1255 np->rx_ring[i - 1].next_desc_logical = np->rx_ring;
1256
1257 /* allocate skb for rx buffers */
1258 for (i = 0; i < RX_RING_SIZE; i++) {
1259 struct sk_buff *skb = netdev_alloc_skb(dev, np->rx_buf_sz);
1260
1261 if (skb == NULL) {
1262 np->lack_rxbuf = &np->rx_ring[i];
1263 break;
1264 }
1265
1266 ++np->really_rx_count;
1267 np->rx_ring[i].skbuff = skb;
1268 np->rx_ring[i].buffer = pci_map_single(np->pci_dev, skb->data,
1269 np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1270 np->rx_ring[i].status = RXOWN;
1271 np->rx_ring[i].control |= RXIC;
1272 }
1273
1274 /* initialize tx variables */
1275 np->cur_tx = &np->tx_ring[0];
1276 np->cur_tx_copy = &np->tx_ring[0];
1277 np->really_tx_count = 0;
1278 np->free_tx_count = TX_RING_SIZE;
1279
1280 for (i = 0; i < TX_RING_SIZE; i++) {
1281 np->tx_ring[i].status = 0;
1282 /* do we need np->tx_ring[i].control = XXX; ?? */
1283 np->tx_ring[i].next_desc = np->tx_ring_dma +
1284 (i + 1)*sizeof(struct fealnx_desc);
1285 np->tx_ring[i].next_desc_logical = &np->tx_ring[i + 1];
1286 np->tx_ring[i].skbuff = NULL;
1287 }
1288
1289 /* for the last tx descriptor */
1290 np->tx_ring[i - 1].next_desc = np->tx_ring_dma;
1291 np->tx_ring[i - 1].next_desc_logical = &np->tx_ring[0];
1292}
1293
1294
1295static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev)
1296{
1297 struct netdev_private *np = netdev_priv(dev);
1298 unsigned long flags;
1299
1300 spin_lock_irqsave(&np->lock, flags);
1301
1302 np->cur_tx_copy->skbuff = skb;
1303
1304#define one_buffer
1305#define BPT 1022
1306#if defined(one_buffer)
1307 np->cur_tx_copy->buffer = pci_map_single(np->pci_dev, skb->data,
1308 skb->len, PCI_DMA_TODEVICE);
1309 np->cur_tx_copy->control = TXIC | TXLD | TXFD | CRCEnable | PADEnable;
1310 np->cur_tx_copy->control |= (skb->len << PKTSShift); /* pkt size */
1311 np->cur_tx_copy->control |= (skb->len << TBSShift); /* buffer size */
1312// 89/12/29 add,
1313 if (np->pci_dev->device == 0x891)
1314 np->cur_tx_copy->control |= ETIControl | RetryTxLC;
1315 np->cur_tx_copy->status = TXOWN;
1316 np->cur_tx_copy = np->cur_tx_copy->next_desc_logical;
1317 --np->free_tx_count;
1318#elif defined(two_buffer)
1319 if (skb->len > BPT) {
1320 struct fealnx_desc *next;
1321
1322 /* for the first descriptor */
1323 np->cur_tx_copy->buffer = pci_map_single(np->pci_dev, skb->data,
1324 BPT, PCI_DMA_TODEVICE);
1325 np->cur_tx_copy->control = TXIC | TXFD | CRCEnable | PADEnable;
1326 np->cur_tx_copy->control |= (skb->len << PKTSShift); /* pkt size */
1327 np->cur_tx_copy->control |= (BPT << TBSShift); /* buffer size */
1328
1329 /* for the last descriptor */
1330 next = np->cur_tx_copy->next_desc_logical;
1331 next->skbuff = skb;
1332 next->control = TXIC | TXLD | CRCEnable | PADEnable;
1333 next->control |= (skb->len << PKTSShift); /* pkt size */
1334 next->control |= ((skb->len - BPT) << TBSShift); /* buf size */
1335// 89/12/29 add,
1336 if (np->pci_dev->device == 0x891)
1337 np->cur_tx_copy->control |= ETIControl | RetryTxLC;
1338 next->buffer = pci_map_single(ep->pci_dev, skb->data + BPT,
1339 skb->len - BPT, PCI_DMA_TODEVICE);
1340
1341 next->status = TXOWN;
1342 np->cur_tx_copy->status = TXOWN;
1343
1344 np->cur_tx_copy = next->next_desc_logical;
1345 np->free_tx_count -= 2;
1346 } else {
1347 np->cur_tx_copy->buffer = pci_map_single(np->pci_dev, skb->data,
1348 skb->len, PCI_DMA_TODEVICE);
1349 np->cur_tx_copy->control = TXIC | TXLD | TXFD | CRCEnable | PADEnable;
1350 np->cur_tx_copy->control |= (skb->len << PKTSShift); /* pkt size */
1351 np->cur_tx_copy->control |= (skb->len << TBSShift); /* buffer size */
1352// 89/12/29 add,
1353 if (np->pci_dev->device == 0x891)
1354 np->cur_tx_copy->control |= ETIControl | RetryTxLC;
1355 np->cur_tx_copy->status = TXOWN;
1356 np->cur_tx_copy = np->cur_tx_copy->next_desc_logical;
1357 --np->free_tx_count;
1358 }
1359#endif
1360
1361 if (np->free_tx_count < 2)
1362 netif_stop_queue(dev);
1363 ++np->really_tx_count;
1364 iowrite32(0, np->mem + TXPDR);
1365
1366 spin_unlock_irqrestore(&np->lock, flags);
1367 return NETDEV_TX_OK;
1368}
1369
1370
1371/* Take lock before calling */
1372/* Chip probably hosed tx ring. Clean up. */
1373static void reset_tx_descriptors(struct net_device *dev)
1374{
1375 struct netdev_private *np = netdev_priv(dev);
1376 struct fealnx_desc *cur;
1377 int i;
1378
1379 /* initialize tx variables */
1380 np->cur_tx = &np->tx_ring[0];
1381 np->cur_tx_copy = &np->tx_ring[0];
1382 np->really_tx_count = 0;
1383 np->free_tx_count = TX_RING_SIZE;
1384
1385 for (i = 0; i < TX_RING_SIZE; i++) {
1386 cur = &np->tx_ring[i];
1387 if (cur->skbuff) {
1388 pci_unmap_single(np->pci_dev, cur->buffer,
1389 cur->skbuff->len, PCI_DMA_TODEVICE);
1390 dev_kfree_skb_any(cur->skbuff);
1391 cur->skbuff = NULL;
1392 }
1393 cur->status = 0;
1394 cur->control = 0; /* needed? */
1395 /* probably not needed. We do it for purely paranoid reasons */
1396 cur->next_desc = np->tx_ring_dma +
1397 (i + 1)*sizeof(struct fealnx_desc);
1398 cur->next_desc_logical = &np->tx_ring[i + 1];
1399 }
1400 /* for the last tx descriptor */
1401 np->tx_ring[TX_RING_SIZE - 1].next_desc = np->tx_ring_dma;
1402 np->tx_ring[TX_RING_SIZE - 1].next_desc_logical = &np->tx_ring[0];
1403}
1404
1405
1406/* Take lock and stop rx before calling this */
1407static void reset_rx_descriptors(struct net_device *dev)
1408{
1409 struct netdev_private *np = netdev_priv(dev);
1410 struct fealnx_desc *cur = np->cur_rx;
1411 int i;
1412
1413 allocate_rx_buffers(dev);
1414
1415 for (i = 0; i < RX_RING_SIZE; i++) {
1416 if (cur->skbuff)
1417 cur->status = RXOWN;
1418 cur = cur->next_desc_logical;
1419 }
1420
1421 iowrite32(np->rx_ring_dma + ((char*)np->cur_rx - (char*)np->rx_ring),
1422 np->mem + RXLBA);
1423}
1424
1425
1426/* The interrupt handler does all of the Rx thread work and cleans up
1427 after the Tx thread. */
1428static irqreturn_t intr_handler(int irq, void *dev_instance)
1429{
1430 struct net_device *dev = (struct net_device *) dev_instance;
1431 struct netdev_private *np = netdev_priv(dev);
1432 void __iomem *ioaddr = np->mem;
1433 long boguscnt = max_interrupt_work;
1434 unsigned int num_tx = 0;
1435 int handled = 0;
1436
1437 spin_lock(&np->lock);
1438
1439 iowrite32(0, ioaddr + IMR);
1440
1441 do {
1442 u32 intr_status = ioread32(ioaddr + ISR);
1443
1444 /* Acknowledge all of the current interrupt sources ASAP. */
1445 iowrite32(intr_status, ioaddr + ISR);
1446
1447 if (debug)
1448 printk(KERN_DEBUG "%s: Interrupt, status %4.4x.\n", dev->name,
1449 intr_status);
1450
1451 if (!(intr_status & np->imrvalue))
1452 break;
1453
1454 handled = 1;
1455
1456// 90/1/16 delete,
1457//
1458// if (intr_status & FBE)
1459// { /* fatal error */
1460// stop_nic_tx(ioaddr, 0);
1461// stop_nic_rx(ioaddr, 0);
1462// break;
1463// };
1464
1465 if (intr_status & TUNF)
1466 iowrite32(0, ioaddr + TXPDR);
1467
1468 if (intr_status & CNTOVF) {
1469 /* missed pkts */
1470 dev->stats.rx_missed_errors +=
1471 ioread32(ioaddr + TALLY) & 0x7fff;
1472
1473 /* crc error */
1474 dev->stats.rx_crc_errors +=
1475 (ioread32(ioaddr + TALLY) & 0x7fff0000) >> 16;
1476 }
1477
1478 if (intr_status & (RI | RBU)) {
1479 if (intr_status & RI)
1480 netdev_rx(dev);
1481 else {
1482 stop_nic_rx(ioaddr, np->crvalue);
1483 reset_rx_descriptors(dev);
1484 iowrite32(np->crvalue, ioaddr + TCRRCR);
1485 }
1486 }
1487
1488 while (np->really_tx_count) {
1489 long tx_status = np->cur_tx->status;
1490 long tx_control = np->cur_tx->control;
1491
1492 if (!(tx_control & TXLD)) { /* this pkt is combined by two tx descriptors */
1493 struct fealnx_desc *next;
1494
1495 next = np->cur_tx->next_desc_logical;
1496 tx_status = next->status;
1497 tx_control = next->control;
1498 }
1499
1500 if (tx_status & TXOWN)
1501 break;
1502
1503 if (!(np->crvalue & CR_W_ENH)) {
1504 if (tx_status & (CSL | LC | EC | UDF | HF)) {
1505 dev->stats.tx_errors++;
1506 if (tx_status & EC)
1507 dev->stats.tx_aborted_errors++;
1508 if (tx_status & CSL)
1509 dev->stats.tx_carrier_errors++;
1510 if (tx_status & LC)
1511 dev->stats.tx_window_errors++;
1512 if (tx_status & UDF)
1513 dev->stats.tx_fifo_errors++;
1514 if ((tx_status & HF) && np->mii.full_duplex == 0)
1515 dev->stats.tx_heartbeat_errors++;
1516
1517 } else {
1518 dev->stats.tx_bytes +=
1519 ((tx_control & PKTSMask) >> PKTSShift);
1520
1521 dev->stats.collisions +=
1522 ((tx_status & NCRMask) >> NCRShift);
1523 dev->stats.tx_packets++;
1524 }
1525 } else {
1526 dev->stats.tx_bytes +=
1527 ((tx_control & PKTSMask) >> PKTSShift);
1528 dev->stats.tx_packets++;
1529 }
1530
1531 /* Free the original skb. */
1532 pci_unmap_single(np->pci_dev, np->cur_tx->buffer,
1533 np->cur_tx->skbuff->len, PCI_DMA_TODEVICE);
1534 dev_consume_skb_irq(np->cur_tx->skbuff);
1535 np->cur_tx->skbuff = NULL;
1536 --np->really_tx_count;
1537 if (np->cur_tx->control & TXLD) {
1538 np->cur_tx = np->cur_tx->next_desc_logical;
1539 ++np->free_tx_count;
1540 } else {
1541 np->cur_tx = np->cur_tx->next_desc_logical;
1542 np->cur_tx = np->cur_tx->next_desc_logical;
1543 np->free_tx_count += 2;
1544 }
1545 num_tx++;
1546 } /* end of for loop */
1547
1548 if (num_tx && np->free_tx_count >= 2)
1549 netif_wake_queue(dev);
1550
1551 /* read transmit status for enhanced mode only */
1552 if (np->crvalue & CR_W_ENH) {
1553 long data;
1554
1555 data = ioread32(ioaddr + TSR);
1556 dev->stats.tx_errors += (data & 0xff000000) >> 24;
1557 dev->stats.tx_aborted_errors +=
1558 (data & 0xff000000) >> 24;
1559 dev->stats.tx_window_errors +=
1560 (data & 0x00ff0000) >> 16;
1561 dev->stats.collisions += (data & 0x0000ffff);
1562 }
1563
1564 if (--boguscnt < 0) {
1565 printk(KERN_WARNING "%s: Too much work at interrupt, "
1566 "status=0x%4.4x.\n", dev->name, intr_status);
1567 if (!np->reset_timer_armed) {
1568 np->reset_timer_armed = 1;
1569 np->reset_timer.expires = RUN_AT(HZ/2);
1570 add_timer(&np->reset_timer);
1571 stop_nic_rxtx(ioaddr, 0);
1572 netif_stop_queue(dev);
1573 /* or netif_tx_disable(dev); ?? */
1574 /* Prevent other paths from enabling tx,rx,intrs */
1575 np->crvalue_sv = np->crvalue;
1576 np->imrvalue_sv = np->imrvalue;
1577 np->crvalue &= ~(CR_W_TXEN | CR_W_RXEN); /* or simply = 0? */
1578 np->imrvalue = 0;
1579 }
1580
1581 break;
1582 }
1583 } while (1);
1584
1585 /* read the tally counters */
1586 /* missed pkts */
1587 dev->stats.rx_missed_errors += ioread32(ioaddr + TALLY) & 0x7fff;
1588
1589 /* crc error */
1590 dev->stats.rx_crc_errors +=
1591 (ioread32(ioaddr + TALLY) & 0x7fff0000) >> 16;
1592
1593 if (debug)
1594 printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n",
1595 dev->name, ioread32(ioaddr + ISR));
1596
1597 iowrite32(np->imrvalue, ioaddr + IMR);
1598
1599 spin_unlock(&np->lock);
1600
1601 return IRQ_RETVAL(handled);
1602}
1603
1604
1605/* This routine is logically part of the interrupt handler, but separated
1606 for clarity and better register allocation. */
1607static int netdev_rx(struct net_device *dev)
1608{
1609 struct netdev_private *np = netdev_priv(dev);
1610 void __iomem *ioaddr = np->mem;
1611
1612 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1613 while (!(np->cur_rx->status & RXOWN) && np->cur_rx->skbuff) {
1614 s32 rx_status = np->cur_rx->status;
1615
1616 if (np->really_rx_count == 0)
1617 break;
1618
1619 if (debug)
1620 printk(KERN_DEBUG " netdev_rx() status was %8.8x.\n", rx_status);
1621
1622 if ((!((rx_status & RXFSD) && (rx_status & RXLSD))) ||
1623 (rx_status & ErrorSummary)) {
1624 if (rx_status & ErrorSummary) { /* there was a fatal error */
1625 if (debug)
1626 printk(KERN_DEBUG
1627 "%s: Receive error, Rx status %8.8x.\n",
1628 dev->name, rx_status);
1629
1630 dev->stats.rx_errors++; /* end of a packet. */
1631 if (rx_status & (LONGPKT | RUNTPKT))
1632 dev->stats.rx_length_errors++;
1633 if (rx_status & RXER)
1634 dev->stats.rx_frame_errors++;
1635 if (rx_status & CRC)
1636 dev->stats.rx_crc_errors++;
1637 } else {
1638 int need_to_reset = 0;
1639 int desno = 0;
1640
1641 if (rx_status & RXFSD) { /* this pkt is too long, over one rx buffer */
1642 struct fealnx_desc *cur;
1643
1644 /* check this packet is received completely? */
1645 cur = np->cur_rx;
1646 while (desno <= np->really_rx_count) {
1647 ++desno;
1648 if ((!(cur->status & RXOWN)) &&
1649 (cur->status & RXLSD))
1650 break;
1651 /* goto next rx descriptor */
1652 cur = cur->next_desc_logical;
1653 }
1654 if (desno > np->really_rx_count)
1655 need_to_reset = 1;
1656 } else /* RXLSD did not find, something error */
1657 need_to_reset = 1;
1658
1659 if (need_to_reset == 0) {
1660 int i;
1661
1662 dev->stats.rx_length_errors++;
1663
1664 /* free all rx descriptors related this long pkt */
1665 for (i = 0; i < desno; ++i) {
1666 if (!np->cur_rx->skbuff) {
1667 printk(KERN_DEBUG
1668 "%s: I'm scared\n", dev->name);
1669 break;
1670 }
1671 np->cur_rx->status = RXOWN;
1672 np->cur_rx = np->cur_rx->next_desc_logical;
1673 }
1674 continue;
1675 } else { /* rx error, need to reset this chip */
1676 stop_nic_rx(ioaddr, np->crvalue);
1677 reset_rx_descriptors(dev);
1678 iowrite32(np->crvalue, ioaddr + TCRRCR);
1679 }
1680 break; /* exit the while loop */
1681 }
1682 } else { /* this received pkt is ok */
1683
1684 struct sk_buff *skb;
1685 /* Omit the four octet CRC from the length. */
1686 short pkt_len = ((rx_status & FLNGMASK) >> FLNGShift) - 4;
1687
1688#ifndef final_version
1689 if (debug)
1690 printk(KERN_DEBUG " netdev_rx() normal Rx pkt length %d"
1691 " status %x.\n", pkt_len, rx_status);
1692#endif
1693
1694 /* Check if the packet is long enough to accept without copying
1695 to a minimally-sized skbuff. */
1696 if (pkt_len < rx_copybreak &&
1697 (skb = netdev_alloc_skb(dev, pkt_len + 2)) != NULL) {
1698 skb_reserve(skb, 2); /* 16 byte align the IP header */
1699 pci_dma_sync_single_for_cpu(np->pci_dev,
1700 np->cur_rx->buffer,
1701 np->rx_buf_sz,
1702 PCI_DMA_FROMDEVICE);
1703 /* Call copy + cksum if available. */
1704
1705#if ! defined(__alpha__)
1706 skb_copy_to_linear_data(skb,
1707 np->cur_rx->skbuff->data, pkt_len);
1708 skb_put(skb, pkt_len);
1709#else
1710 skb_put_data(skb, np->cur_rx->skbuff->data,
1711 pkt_len);
1712#endif
1713 pci_dma_sync_single_for_device(np->pci_dev,
1714 np->cur_rx->buffer,
1715 np->rx_buf_sz,
1716 PCI_DMA_FROMDEVICE);
1717 } else {
1718 pci_unmap_single(np->pci_dev,
1719 np->cur_rx->buffer,
1720 np->rx_buf_sz,
1721 PCI_DMA_FROMDEVICE);
1722 skb_put(skb = np->cur_rx->skbuff, pkt_len);
1723 np->cur_rx->skbuff = NULL;
1724 --np->really_rx_count;
1725 }
1726 skb->protocol = eth_type_trans(skb, dev);
1727 netif_rx(skb);
1728 dev->stats.rx_packets++;
1729 dev->stats.rx_bytes += pkt_len;
1730 }
1731
1732 np->cur_rx = np->cur_rx->next_desc_logical;
1733 } /* end of while loop */
1734
1735 /* allocate skb for rx buffers */
1736 allocate_rx_buffers(dev);
1737
1738 return 0;
1739}
1740
1741
1742static struct net_device_stats *get_stats(struct net_device *dev)
1743{
1744 struct netdev_private *np = netdev_priv(dev);
1745 void __iomem *ioaddr = np->mem;
1746
1747 /* The chip only need report frame silently dropped. */
1748 if (netif_running(dev)) {
1749 dev->stats.rx_missed_errors +=
1750 ioread32(ioaddr + TALLY) & 0x7fff;
1751 dev->stats.rx_crc_errors +=
1752 (ioread32(ioaddr + TALLY) & 0x7fff0000) >> 16;
1753 }
1754
1755 return &dev->stats;
1756}
1757
1758
1759/* for dev->set_multicast_list */
1760static void set_rx_mode(struct net_device *dev)
1761{
1762 spinlock_t *lp = &((struct netdev_private *)netdev_priv(dev))->lock;
1763 unsigned long flags;
1764 spin_lock_irqsave(lp, flags);
1765 __set_rx_mode(dev);
1766 spin_unlock_irqrestore(lp, flags);
1767}
1768
1769
1770/* Take lock before calling */
1771static void __set_rx_mode(struct net_device *dev)
1772{
1773 struct netdev_private *np = netdev_priv(dev);
1774 void __iomem *ioaddr = np->mem;
1775 u32 mc_filter[2]; /* Multicast hash filter */
1776 u32 rx_mode;
1777
1778 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1779 memset(mc_filter, 0xff, sizeof(mc_filter));
1780 rx_mode = CR_W_PROM | CR_W_AB | CR_W_AM;
1781 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
1782 (dev->flags & IFF_ALLMULTI)) {
1783 /* Too many to match, or accept all multicasts. */
1784 memset(mc_filter, 0xff, sizeof(mc_filter));
1785 rx_mode = CR_W_AB | CR_W_AM;
1786 } else {
1787 struct netdev_hw_addr *ha;
1788
1789 memset(mc_filter, 0, sizeof(mc_filter));
1790 netdev_for_each_mc_addr(ha, dev) {
1791 unsigned int bit;
1792 bit = (ether_crc(ETH_ALEN, ha->addr) >> 26) ^ 0x3F;
1793 mc_filter[bit >> 5] |= (1 << bit);
1794 }
1795 rx_mode = CR_W_AB | CR_W_AM;
1796 }
1797
1798 stop_nic_rxtx(ioaddr, np->crvalue);
1799
1800 iowrite32(mc_filter[0], ioaddr + MAR0);
1801 iowrite32(mc_filter[1], ioaddr + MAR1);
1802 np->crvalue &= ~CR_W_RXMODEMASK;
1803 np->crvalue |= rx_mode;
1804 iowrite32(np->crvalue, ioaddr + TCRRCR);
1805}
1806
1807static void netdev_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1808{
1809 struct netdev_private *np = netdev_priv(dev);
1810
1811 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1812 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1813 strlcpy(info->bus_info, pci_name(np->pci_dev), sizeof(info->bus_info));
1814}
1815
1816static int netdev_get_link_ksettings(struct net_device *dev,
1817 struct ethtool_link_ksettings *cmd)
1818{
1819 struct netdev_private *np = netdev_priv(dev);
1820
1821 spin_lock_irq(&np->lock);
1822 mii_ethtool_get_link_ksettings(&np->mii, cmd);
1823 spin_unlock_irq(&np->lock);
1824
1825 return 0;
1826}
1827
1828static int netdev_set_link_ksettings(struct net_device *dev,
1829 const struct ethtool_link_ksettings *cmd)
1830{
1831 struct netdev_private *np = netdev_priv(dev);
1832 int rc;
1833
1834 spin_lock_irq(&np->lock);
1835 rc = mii_ethtool_set_link_ksettings(&np->mii, cmd);
1836 spin_unlock_irq(&np->lock);
1837
1838 return rc;
1839}
1840
1841static int netdev_nway_reset(struct net_device *dev)
1842{
1843 struct netdev_private *np = netdev_priv(dev);
1844 return mii_nway_restart(&np->mii);
1845}
1846
1847static u32 netdev_get_link(struct net_device *dev)
1848{
1849 struct netdev_private *np = netdev_priv(dev);
1850 return mii_link_ok(&np->mii);
1851}
1852
1853static u32 netdev_get_msglevel(struct net_device *dev)
1854{
1855 return debug;
1856}
1857
1858static void netdev_set_msglevel(struct net_device *dev, u32 value)
1859{
1860 debug = value;
1861}
1862
1863static const struct ethtool_ops netdev_ethtool_ops = {
1864 .get_drvinfo = netdev_get_drvinfo,
1865 .nway_reset = netdev_nway_reset,
1866 .get_link = netdev_get_link,
1867 .get_msglevel = netdev_get_msglevel,
1868 .set_msglevel = netdev_set_msglevel,
1869 .get_link_ksettings = netdev_get_link_ksettings,
1870 .set_link_ksettings = netdev_set_link_ksettings,
1871};
1872
1873static int mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1874{
1875 struct netdev_private *np = netdev_priv(dev);
1876 int rc;
1877
1878 if (!netif_running(dev))
1879 return -EINVAL;
1880
1881 spin_lock_irq(&np->lock);
1882 rc = generic_mii_ioctl(&np->mii, if_mii(rq), cmd, NULL);
1883 spin_unlock_irq(&np->lock);
1884
1885 return rc;
1886}
1887
1888
1889static int netdev_close(struct net_device *dev)
1890{
1891 struct netdev_private *np = netdev_priv(dev);
1892 void __iomem *ioaddr = np->mem;
1893 int i;
1894
1895 netif_stop_queue(dev);
1896
1897 /* Disable interrupts by clearing the interrupt mask. */
1898 iowrite32(0x0000, ioaddr + IMR);
1899
1900 /* Stop the chip's Tx and Rx processes. */
1901 stop_nic_rxtx(ioaddr, 0);
1902
1903 del_timer_sync(&np->timer);
1904 del_timer_sync(&np->reset_timer);
1905
1906 free_irq(np->pci_dev->irq, dev);
1907
1908 /* Free all the skbuffs in the Rx queue. */
1909 for (i = 0; i < RX_RING_SIZE; i++) {
1910 struct sk_buff *skb = np->rx_ring[i].skbuff;
1911
1912 np->rx_ring[i].status = 0;
1913 if (skb) {
1914 pci_unmap_single(np->pci_dev, np->rx_ring[i].buffer,
1915 np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1916 dev_kfree_skb(skb);
1917 np->rx_ring[i].skbuff = NULL;
1918 }
1919 }
1920
1921 for (i = 0; i < TX_RING_SIZE; i++) {
1922 struct sk_buff *skb = np->tx_ring[i].skbuff;
1923
1924 if (skb) {
1925 pci_unmap_single(np->pci_dev, np->tx_ring[i].buffer,
1926 skb->len, PCI_DMA_TODEVICE);
1927 dev_kfree_skb(skb);
1928 np->tx_ring[i].skbuff = NULL;
1929 }
1930 }
1931
1932 return 0;
1933}
1934
1935static const struct pci_device_id fealnx_pci_tbl[] = {
1936 {0x1516, 0x0800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1937 {0x1516, 0x0803, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1938 {0x1516, 0x0891, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1939 {} /* terminate list */
1940};
1941MODULE_DEVICE_TABLE(pci, fealnx_pci_tbl);
1942
1943
1944static struct pci_driver fealnx_driver = {
1945 .name = "fealnx",
1946 .id_table = fealnx_pci_tbl,
1947 .probe = fealnx_init_one,
1948 .remove = fealnx_remove_one,
1949};
1950
1951static int __init fealnx_init(void)
1952{
1953/* when a module, this is printed whether or not devices are found in probe */
1954#ifdef MODULE
1955 printk(version);
1956#endif
1957
1958 return pci_register_driver(&fealnx_driver);
1959}
1960
1961static void __exit fealnx_exit(void)
1962{
1963 pci_unregister_driver(&fealnx_driver);
1964}
1965
1966module_init(fealnx_init);
1967module_exit(fealnx_exit);
1968