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1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, see <http://www.gnu.org/licenses/>.
13 *
14 * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
15 */
16
17#include <linux/kernel.h>
18#include <linux/slab.h>
19#include <linux/errno.h>
20#include <linux/types.h>
21#include <linux/interrupt.h>
22#include <linux/uaccess.h>
23#include <linux/in.h>
24#include <linux/netdevice.h>
25#include <linux/etherdevice.h>
26#include <linux/phy.h>
27#include <linux/ip.h>
28#include <linux/tcp.h>
29#include <linux/skbuff.h>
30#include <linux/mm.h>
31#include <linux/platform_device.h>
32#include <linux/ethtool.h>
33#include <linux/init.h>
34#include <linux/delay.h>
35#include <linux/io.h>
36#include <linux/dma-mapping.h>
37#include <linux/module.h>
38
39#include <asm/checksum.h>
40
41#include <lantiq_soc.h>
42#include <xway_dma.h>
43#include <lantiq_platform.h>
44
45#define LTQ_ETOP_MDIO 0x11804
46#define MDIO_REQUEST 0x80000000
47#define MDIO_READ 0x40000000
48#define MDIO_ADDR_MASK 0x1f
49#define MDIO_ADDR_OFFSET 0x15
50#define MDIO_REG_MASK 0x1f
51#define MDIO_REG_OFFSET 0x10
52#define MDIO_VAL_MASK 0xffff
53
54#define PPE32_CGEN 0x800
55#define LQ_PPE32_ENET_MAC_CFG 0x1840
56
57#define LTQ_ETOP_ENETS0 0x11850
58#define LTQ_ETOP_MAC_DA0 0x1186C
59#define LTQ_ETOP_MAC_DA1 0x11870
60#define LTQ_ETOP_CFG 0x16020
61#define LTQ_ETOP_IGPLEN 0x16080
62
63#define MAX_DMA_CHAN 0x8
64#define MAX_DMA_CRC_LEN 0x4
65#define MAX_DMA_DATA_LEN 0x600
66
67#define ETOP_FTCU BIT(28)
68#define ETOP_MII_MASK 0xf
69#define ETOP_MII_NORMAL 0xd
70#define ETOP_MII_REVERSE 0xe
71#define ETOP_PLEN_UNDER 0x40
72#define ETOP_CGEN 0x800
73
74/* use 2 static channels for TX/RX */
75#define LTQ_ETOP_TX_CHANNEL 1
76#define LTQ_ETOP_RX_CHANNEL 6
77#define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL)
78#define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL)
79
80#define ltq_etop_r32(x) ltq_r32(ltq_etop_membase + (x))
81#define ltq_etop_w32(x, y) ltq_w32(x, ltq_etop_membase + (y))
82#define ltq_etop_w32_mask(x, y, z) \
83 ltq_w32_mask(x, y, ltq_etop_membase + (z))
84
85#define DRV_VERSION "1.0"
86
87static void __iomem *ltq_etop_membase;
88
89struct ltq_etop_chan {
90 int idx;
91 int tx_free;
92 struct net_device *netdev;
93 struct napi_struct napi;
94 struct ltq_dma_channel dma;
95 struct sk_buff *skb[LTQ_DESC_NUM];
96};
97
98struct ltq_etop_priv {
99 struct net_device *netdev;
100 struct platform_device *pdev;
101 struct ltq_eth_data *pldata;
102 struct resource *res;
103
104 struct mii_bus *mii_bus;
105
106 struct ltq_etop_chan ch[MAX_DMA_CHAN];
107 int tx_free[MAX_DMA_CHAN >> 1];
108
109 spinlock_t lock;
110};
111
112static int
113ltq_etop_alloc_skb(struct ltq_etop_chan *ch)
114{
115 struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
116
117 ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN);
118 if (!ch->skb[ch->dma.desc])
119 return -ENOMEM;
120 ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(&priv->pdev->dev,
121 ch->skb[ch->dma.desc]->data, MAX_DMA_DATA_LEN,
122 DMA_FROM_DEVICE);
123 ch->dma.desc_base[ch->dma.desc].addr =
124 CPHYSADDR(ch->skb[ch->dma.desc]->data);
125 ch->dma.desc_base[ch->dma.desc].ctl =
126 LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) |
127 MAX_DMA_DATA_LEN;
128 skb_reserve(ch->skb[ch->dma.desc], NET_IP_ALIGN);
129 return 0;
130}
131
132static void
133ltq_etop_hw_receive(struct ltq_etop_chan *ch)
134{
135 struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
136 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
137 struct sk_buff *skb = ch->skb[ch->dma.desc];
138 int len = (desc->ctl & LTQ_DMA_SIZE_MASK) - MAX_DMA_CRC_LEN;
139 unsigned long flags;
140
141 spin_lock_irqsave(&priv->lock, flags);
142 if (ltq_etop_alloc_skb(ch)) {
143 netdev_err(ch->netdev,
144 "failed to allocate new rx buffer, stopping DMA\n");
145 ltq_dma_close(&ch->dma);
146 }
147 ch->dma.desc++;
148 ch->dma.desc %= LTQ_DESC_NUM;
149 spin_unlock_irqrestore(&priv->lock, flags);
150
151 skb_put(skb, len);
152 skb->protocol = eth_type_trans(skb, ch->netdev);
153 netif_receive_skb(skb);
154}
155
156static int
157ltq_etop_poll_rx(struct napi_struct *napi, int budget)
158{
159 struct ltq_etop_chan *ch = container_of(napi,
160 struct ltq_etop_chan, napi);
161 int work_done = 0;
162
163 while (work_done < budget) {
164 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
165
166 if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) != LTQ_DMA_C)
167 break;
168 ltq_etop_hw_receive(ch);
169 work_done++;
170 }
171 if (work_done < budget) {
172 napi_complete_done(&ch->napi, work_done);
173 ltq_dma_ack_irq(&ch->dma);
174 }
175 return work_done;
176}
177
178static int
179ltq_etop_poll_tx(struct napi_struct *napi, int budget)
180{
181 struct ltq_etop_chan *ch =
182 container_of(napi, struct ltq_etop_chan, napi);
183 struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
184 struct netdev_queue *txq =
185 netdev_get_tx_queue(ch->netdev, ch->idx >> 1);
186 unsigned long flags;
187
188 spin_lock_irqsave(&priv->lock, flags);
189 while ((ch->dma.desc_base[ch->tx_free].ctl &
190 (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
191 dev_kfree_skb_any(ch->skb[ch->tx_free]);
192 ch->skb[ch->tx_free] = NULL;
193 memset(&ch->dma.desc_base[ch->tx_free], 0,
194 sizeof(struct ltq_dma_desc));
195 ch->tx_free++;
196 ch->tx_free %= LTQ_DESC_NUM;
197 }
198 spin_unlock_irqrestore(&priv->lock, flags);
199
200 if (netif_tx_queue_stopped(txq))
201 netif_tx_start_queue(txq);
202 napi_complete(&ch->napi);
203 ltq_dma_ack_irq(&ch->dma);
204 return 1;
205}
206
207static irqreturn_t
208ltq_etop_dma_irq(int irq, void *_priv)
209{
210 struct ltq_etop_priv *priv = _priv;
211 int ch = irq - LTQ_DMA_CH0_INT;
212
213 napi_schedule(&priv->ch[ch].napi);
214 return IRQ_HANDLED;
215}
216
217static void
218ltq_etop_free_channel(struct net_device *dev, struct ltq_etop_chan *ch)
219{
220 struct ltq_etop_priv *priv = netdev_priv(dev);
221
222 ltq_dma_free(&ch->dma);
223 if (ch->dma.irq)
224 free_irq(ch->dma.irq, priv);
225 if (IS_RX(ch->idx)) {
226 int desc;
227 for (desc = 0; desc < LTQ_DESC_NUM; desc++)
228 dev_kfree_skb_any(ch->skb[ch->dma.desc]);
229 }
230}
231
232static void
233ltq_etop_hw_exit(struct net_device *dev)
234{
235 struct ltq_etop_priv *priv = netdev_priv(dev);
236 int i;
237
238 ltq_pmu_disable(PMU_PPE);
239 for (i = 0; i < MAX_DMA_CHAN; i++)
240 if (IS_TX(i) || IS_RX(i))
241 ltq_etop_free_channel(dev, &priv->ch[i]);
242}
243
244static int
245ltq_etop_hw_init(struct net_device *dev)
246{
247 struct ltq_etop_priv *priv = netdev_priv(dev);
248 int i;
249
250 ltq_pmu_enable(PMU_PPE);
251
252 switch (priv->pldata->mii_mode) {
253 case PHY_INTERFACE_MODE_RMII:
254 ltq_etop_w32_mask(ETOP_MII_MASK,
255 ETOP_MII_REVERSE, LTQ_ETOP_CFG);
256 break;
257
258 case PHY_INTERFACE_MODE_MII:
259 ltq_etop_w32_mask(ETOP_MII_MASK,
260 ETOP_MII_NORMAL, LTQ_ETOP_CFG);
261 break;
262
263 default:
264 netdev_err(dev, "unknown mii mode %d\n",
265 priv->pldata->mii_mode);
266 return -ENOTSUPP;
267 }
268
269 /* enable crc generation */
270 ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG);
271
272 ltq_dma_init_port(DMA_PORT_ETOP);
273
274 for (i = 0; i < MAX_DMA_CHAN; i++) {
275 int irq = LTQ_DMA_CH0_INT + i;
276 struct ltq_etop_chan *ch = &priv->ch[i];
277
278 ch->idx = ch->dma.nr = i;
279 ch->dma.dev = &priv->pdev->dev;
280
281 if (IS_TX(i)) {
282 ltq_dma_alloc_tx(&ch->dma);
283 request_irq(irq, ltq_etop_dma_irq, 0, "etop_tx", priv);
284 } else if (IS_RX(i)) {
285 ltq_dma_alloc_rx(&ch->dma);
286 for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;
287 ch->dma.desc++)
288 if (ltq_etop_alloc_skb(ch))
289 return -ENOMEM;
290 ch->dma.desc = 0;
291 request_irq(irq, ltq_etop_dma_irq, 0, "etop_rx", priv);
292 }
293 ch->dma.irq = irq;
294 }
295 return 0;
296}
297
298static void
299ltq_etop_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
300{
301 strlcpy(info->driver, "Lantiq ETOP", sizeof(info->driver));
302 strlcpy(info->bus_info, "internal", sizeof(info->bus_info));
303 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
304}
305
306static const struct ethtool_ops ltq_etop_ethtool_ops = {
307 .get_drvinfo = ltq_etop_get_drvinfo,
308 .nway_reset = phy_ethtool_nway_reset,
309 .get_link_ksettings = phy_ethtool_get_link_ksettings,
310 .set_link_ksettings = phy_ethtool_set_link_ksettings,
311};
312
313static int
314ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data)
315{
316 u32 val = MDIO_REQUEST |
317 ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) |
318 ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) |
319 phy_data;
320
321 while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
322 ;
323 ltq_etop_w32(val, LTQ_ETOP_MDIO);
324 return 0;
325}
326
327static int
328ltq_etop_mdio_rd(struct mii_bus *bus, int phy_addr, int phy_reg)
329{
330 u32 val = MDIO_REQUEST | MDIO_READ |
331 ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) |
332 ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET);
333
334 while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
335 ;
336 ltq_etop_w32(val, LTQ_ETOP_MDIO);
337 while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
338 ;
339 val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK;
340 return val;
341}
342
343static void
344ltq_etop_mdio_link(struct net_device *dev)
345{
346 /* nothing to do */
347}
348
349static int
350ltq_etop_mdio_probe(struct net_device *dev)
351{
352 struct ltq_etop_priv *priv = netdev_priv(dev);
353 struct phy_device *phydev;
354
355 phydev = phy_find_first(priv->mii_bus);
356
357 if (!phydev) {
358 netdev_err(dev, "no PHY found\n");
359 return -ENODEV;
360 }
361
362 phydev = phy_connect(dev, phydev_name(phydev),
363 &ltq_etop_mdio_link, priv->pldata->mii_mode);
364
365 if (IS_ERR(phydev)) {
366 netdev_err(dev, "Could not attach to PHY\n");
367 return PTR_ERR(phydev);
368 }
369
370 phy_set_max_speed(phydev, SPEED_100);
371
372 phy_attached_info(phydev);
373
374 return 0;
375}
376
377static int
378ltq_etop_mdio_init(struct net_device *dev)
379{
380 struct ltq_etop_priv *priv = netdev_priv(dev);
381 int err;
382
383 priv->mii_bus = mdiobus_alloc();
384 if (!priv->mii_bus) {
385 netdev_err(dev, "failed to allocate mii bus\n");
386 err = -ENOMEM;
387 goto err_out;
388 }
389
390 priv->mii_bus->priv = dev;
391 priv->mii_bus->read = ltq_etop_mdio_rd;
392 priv->mii_bus->write = ltq_etop_mdio_wr;
393 priv->mii_bus->name = "ltq_mii";
394 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
395 priv->pdev->name, priv->pdev->id);
396 if (mdiobus_register(priv->mii_bus)) {
397 err = -ENXIO;
398 goto err_out_free_mdiobus;
399 }
400
401 if (ltq_etop_mdio_probe(dev)) {
402 err = -ENXIO;
403 goto err_out_unregister_bus;
404 }
405 return 0;
406
407err_out_unregister_bus:
408 mdiobus_unregister(priv->mii_bus);
409err_out_free_mdiobus:
410 mdiobus_free(priv->mii_bus);
411err_out:
412 return err;
413}
414
415static void
416ltq_etop_mdio_cleanup(struct net_device *dev)
417{
418 struct ltq_etop_priv *priv = netdev_priv(dev);
419
420 phy_disconnect(dev->phydev);
421 mdiobus_unregister(priv->mii_bus);
422 mdiobus_free(priv->mii_bus);
423}
424
425static int
426ltq_etop_open(struct net_device *dev)
427{
428 struct ltq_etop_priv *priv = netdev_priv(dev);
429 int i;
430
431 for (i = 0; i < MAX_DMA_CHAN; i++) {
432 struct ltq_etop_chan *ch = &priv->ch[i];
433
434 if (!IS_TX(i) && (!IS_RX(i)))
435 continue;
436 ltq_dma_open(&ch->dma);
437 ltq_dma_enable_irq(&ch->dma);
438 napi_enable(&ch->napi);
439 }
440 phy_start(dev->phydev);
441 netif_tx_start_all_queues(dev);
442 return 0;
443}
444
445static int
446ltq_etop_stop(struct net_device *dev)
447{
448 struct ltq_etop_priv *priv = netdev_priv(dev);
449 int i;
450
451 netif_tx_stop_all_queues(dev);
452 phy_stop(dev->phydev);
453 for (i = 0; i < MAX_DMA_CHAN; i++) {
454 struct ltq_etop_chan *ch = &priv->ch[i];
455
456 if (!IS_RX(i) && !IS_TX(i))
457 continue;
458 napi_disable(&ch->napi);
459 ltq_dma_close(&ch->dma);
460 }
461 return 0;
462}
463
464static int
465ltq_etop_tx(struct sk_buff *skb, struct net_device *dev)
466{
467 int queue = skb_get_queue_mapping(skb);
468 struct netdev_queue *txq = netdev_get_tx_queue(dev, queue);
469 struct ltq_etop_priv *priv = netdev_priv(dev);
470 struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1];
471 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
472 int len;
473 unsigned long flags;
474 u32 byte_offset;
475
476 len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
477
478 if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) {
479 dev_kfree_skb_any(skb);
480 netdev_err(dev, "tx ring full\n");
481 netif_tx_stop_queue(txq);
482 return NETDEV_TX_BUSY;
483 }
484
485 /* dma needs to start on a 16 byte aligned address */
486 byte_offset = CPHYSADDR(skb->data) % 16;
487 ch->skb[ch->dma.desc] = skb;
488
489 netif_trans_update(dev);
490
491 spin_lock_irqsave(&priv->lock, flags);
492 desc->addr = ((unsigned int) dma_map_single(&priv->pdev->dev, skb->data, len,
493 DMA_TO_DEVICE)) - byte_offset;
494 wmb();
495 desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP |
496 LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK);
497 ch->dma.desc++;
498 ch->dma.desc %= LTQ_DESC_NUM;
499 spin_unlock_irqrestore(&priv->lock, flags);
500
501 if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN)
502 netif_tx_stop_queue(txq);
503
504 return NETDEV_TX_OK;
505}
506
507static int
508ltq_etop_change_mtu(struct net_device *dev, int new_mtu)
509{
510 struct ltq_etop_priv *priv = netdev_priv(dev);
511 unsigned long flags;
512
513 dev->mtu = new_mtu;
514
515 spin_lock_irqsave(&priv->lock, flags);
516 ltq_etop_w32((ETOP_PLEN_UNDER << 16) | new_mtu, LTQ_ETOP_IGPLEN);
517 spin_unlock_irqrestore(&priv->lock, flags);
518
519 return 0;
520}
521
522static int
523ltq_etop_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
524{
525 /* TODO: mii-toll reports "No MII transceiver present!." ?!*/
526 return phy_mii_ioctl(dev->phydev, rq, cmd);
527}
528
529static int
530ltq_etop_set_mac_address(struct net_device *dev, void *p)
531{
532 int ret = eth_mac_addr(dev, p);
533
534 if (!ret) {
535 struct ltq_etop_priv *priv = netdev_priv(dev);
536 unsigned long flags;
537
538 /* store the mac for the unicast filter */
539 spin_lock_irqsave(&priv->lock, flags);
540 ltq_etop_w32(*((u32 *)dev->dev_addr), LTQ_ETOP_MAC_DA0);
541 ltq_etop_w32(*((u16 *)&dev->dev_addr[4]) << 16,
542 LTQ_ETOP_MAC_DA1);
543 spin_unlock_irqrestore(&priv->lock, flags);
544 }
545 return ret;
546}
547
548static void
549ltq_etop_set_multicast_list(struct net_device *dev)
550{
551 struct ltq_etop_priv *priv = netdev_priv(dev);
552 unsigned long flags;
553
554 /* ensure that the unicast filter is not enabled in promiscious mode */
555 spin_lock_irqsave(&priv->lock, flags);
556 if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI))
557 ltq_etop_w32_mask(ETOP_FTCU, 0, LTQ_ETOP_ENETS0);
558 else
559 ltq_etop_w32_mask(0, ETOP_FTCU, LTQ_ETOP_ENETS0);
560 spin_unlock_irqrestore(&priv->lock, flags);
561}
562
563static int
564ltq_etop_init(struct net_device *dev)
565{
566 struct ltq_etop_priv *priv = netdev_priv(dev);
567 struct sockaddr mac;
568 int err;
569 bool random_mac = false;
570
571 dev->watchdog_timeo = 10 * HZ;
572 err = ltq_etop_hw_init(dev);
573 if (err)
574 goto err_hw;
575 ltq_etop_change_mtu(dev, 1500);
576
577 memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr));
578 if (!is_valid_ether_addr(mac.sa_data)) {
579 pr_warn("etop: invalid MAC, using random\n");
580 eth_random_addr(mac.sa_data);
581 random_mac = true;
582 }
583
584 err = ltq_etop_set_mac_address(dev, &mac);
585 if (err)
586 goto err_netdev;
587
588 /* Set addr_assign_type here, ltq_etop_set_mac_address would reset it. */
589 if (random_mac)
590 dev->addr_assign_type = NET_ADDR_RANDOM;
591
592 ltq_etop_set_multicast_list(dev);
593 err = ltq_etop_mdio_init(dev);
594 if (err)
595 goto err_netdev;
596 return 0;
597
598err_netdev:
599 unregister_netdev(dev);
600 free_netdev(dev);
601err_hw:
602 ltq_etop_hw_exit(dev);
603 return err;
604}
605
606static void
607ltq_etop_tx_timeout(struct net_device *dev)
608{
609 int err;
610
611 ltq_etop_hw_exit(dev);
612 err = ltq_etop_hw_init(dev);
613 if (err)
614 goto err_hw;
615 netif_trans_update(dev);
616 netif_wake_queue(dev);
617 return;
618
619err_hw:
620 ltq_etop_hw_exit(dev);
621 netdev_err(dev, "failed to restart etop after TX timeout\n");
622}
623
624static const struct net_device_ops ltq_eth_netdev_ops = {
625 .ndo_open = ltq_etop_open,
626 .ndo_stop = ltq_etop_stop,
627 .ndo_start_xmit = ltq_etop_tx,
628 .ndo_change_mtu = ltq_etop_change_mtu,
629 .ndo_do_ioctl = ltq_etop_ioctl,
630 .ndo_set_mac_address = ltq_etop_set_mac_address,
631 .ndo_validate_addr = eth_validate_addr,
632 .ndo_set_rx_mode = ltq_etop_set_multicast_list,
633 .ndo_select_queue = dev_pick_tx_zero,
634 .ndo_init = ltq_etop_init,
635 .ndo_tx_timeout = ltq_etop_tx_timeout,
636};
637
638static int __init
639ltq_etop_probe(struct platform_device *pdev)
640{
641 struct net_device *dev;
642 struct ltq_etop_priv *priv;
643 struct resource *res;
644 int err;
645 int i;
646
647 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
648 if (!res) {
649 dev_err(&pdev->dev, "failed to get etop resource\n");
650 err = -ENOENT;
651 goto err_out;
652 }
653
654 res = devm_request_mem_region(&pdev->dev, res->start,
655 resource_size(res), dev_name(&pdev->dev));
656 if (!res) {
657 dev_err(&pdev->dev, "failed to request etop resource\n");
658 err = -EBUSY;
659 goto err_out;
660 }
661
662 ltq_etop_membase = devm_ioremap_nocache(&pdev->dev,
663 res->start, resource_size(res));
664 if (!ltq_etop_membase) {
665 dev_err(&pdev->dev, "failed to remap etop engine %d\n",
666 pdev->id);
667 err = -ENOMEM;
668 goto err_out;
669 }
670
671 dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
672 if (!dev) {
673 err = -ENOMEM;
674 goto err_out;
675 }
676 strcpy(dev->name, "eth%d");
677 dev->netdev_ops = &ltq_eth_netdev_ops;
678 dev->ethtool_ops = &ltq_etop_ethtool_ops;
679 priv = netdev_priv(dev);
680 priv->res = res;
681 priv->pdev = pdev;
682 priv->pldata = dev_get_platdata(&pdev->dev);
683 priv->netdev = dev;
684 spin_lock_init(&priv->lock);
685 SET_NETDEV_DEV(dev, &pdev->dev);
686
687 for (i = 0; i < MAX_DMA_CHAN; i++) {
688 if (IS_TX(i))
689 netif_napi_add(dev, &priv->ch[i].napi,
690 ltq_etop_poll_tx, 8);
691 else if (IS_RX(i))
692 netif_napi_add(dev, &priv->ch[i].napi,
693 ltq_etop_poll_rx, 32);
694 priv->ch[i].netdev = dev;
695 }
696
697 err = register_netdev(dev);
698 if (err)
699 goto err_free;
700
701 platform_set_drvdata(pdev, dev);
702 return 0;
703
704err_free:
705 free_netdev(dev);
706err_out:
707 return err;
708}
709
710static int
711ltq_etop_remove(struct platform_device *pdev)
712{
713 struct net_device *dev = platform_get_drvdata(pdev);
714
715 if (dev) {
716 netif_tx_stop_all_queues(dev);
717 ltq_etop_hw_exit(dev);
718 ltq_etop_mdio_cleanup(dev);
719 unregister_netdev(dev);
720 }
721 return 0;
722}
723
724static struct platform_driver ltq_mii_driver = {
725 .remove = ltq_etop_remove,
726 .driver = {
727 .name = "ltq_etop",
728 },
729};
730
731int __init
732init_ltq_etop(void)
733{
734 int ret = platform_driver_probe(&ltq_mii_driver, ltq_etop_probe);
735
736 if (ret)
737 pr_err("ltq_etop: Error registering platform driver!");
738 return ret;
739}
740
741static void __exit
742exit_ltq_etop(void)
743{
744 platform_driver_unregister(&ltq_mii_driver);
745}
746
747module_init(init_ltq_etop);
748module_exit(exit_ltq_etop);
749
750MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
751MODULE_DESCRIPTION("Lantiq SoC ETOP");
752MODULE_LICENSE("GPL");
753

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