1/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
2/* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
3
4#ifndef _MLXSW_REG_H
5#define _MLXSW_REG_H
6
7#include <linux/kernel.h>
8#include <linux/string.h>
9#include <linux/bitops.h>
10#include <linux/if_vlan.h>
11
12#include "item.h"
13#include "port.h"
14
15struct mlxsw_reg_info {
16 u16 id;
17 u16 len; /* In u8 */
18 const char *name;
19};
20
21#define MLXSW_REG_DEFINE(_name, _id, _len) \
22static const struct mlxsw_reg_info mlxsw_reg_##_name = { \
23 .id = _id, \
24 .len = _len, \
25 .name = #_name, \
26}
27
28#define MLXSW_REG(type) (&mlxsw_reg_##type)
29#define MLXSW_REG_LEN(type) MLXSW_REG(type)->len
30#define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len)
31
32/* SGCR - Switch General Configuration Register
33 * --------------------------------------------
34 * This register is used for configuration of the switch capabilities.
35 */
36#define MLXSW_REG_SGCR_ID 0x2000
37#define MLXSW_REG_SGCR_LEN 0x10
38
39MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN);
40
41/* reg_sgcr_llb
42 * Link Local Broadcast (Default=0)
43 * When set, all Link Local packets (224.0.0.X) will be treated as broadcast
44 * packets and ignore the IGMP snooping entries.
45 * Access: RW
46 */
47MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1);
48
49static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb)
50{
51 MLXSW_REG_ZERO(sgcr, payload);
52 mlxsw_reg_sgcr_llb_set(payload, !!llb);
53}
54
55/* SPAD - Switch Physical Address Register
56 * ---------------------------------------
57 * The SPAD register configures the switch physical MAC address.
58 */
59#define MLXSW_REG_SPAD_ID 0x2002
60#define MLXSW_REG_SPAD_LEN 0x10
61
62MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN);
63
64/* reg_spad_base_mac
65 * Base MAC address for the switch partitions.
66 * Per switch partition MAC address is equal to:
67 * base_mac + swid
68 * Access: RW
69 */
70MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6);
71
72/* SMID - Switch Multicast ID
73 * --------------------------
74 * The MID record maps from a MID (Multicast ID), which is a unique identifier
75 * of the multicast group within the stacking domain, into a list of local
76 * ports into which the packet is replicated.
77 */
78#define MLXSW_REG_SMID_ID 0x2007
79#define MLXSW_REG_SMID_LEN 0x240
80
81MLXSW_REG_DEFINE(smid, MLXSW_REG_SMID_ID, MLXSW_REG_SMID_LEN);
82
83/* reg_smid_swid
84 * Switch partition ID.
85 * Access: Index
86 */
87MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8);
88
89/* reg_smid_mid
90 * Multicast identifier - global identifier that represents the multicast group
91 * across all devices.
92 * Access: Index
93 */
94MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16);
95
96/* reg_smid_port
97 * Local port memebership (1 bit per port).
98 * Access: RW
99 */
100MLXSW_ITEM_BIT_ARRAY(reg, smid, port, 0x20, 0x20, 1);
101
102/* reg_smid_port_mask
103 * Local port mask (1 bit per port).
104 * Access: W
105 */
106MLXSW_ITEM_BIT_ARRAY(reg, smid, port_mask, 0x220, 0x20, 1);
107
108static inline void mlxsw_reg_smid_pack(char *payload, u16 mid,
109 u8 port, bool set)
110{
111 MLXSW_REG_ZERO(smid, payload);
112 mlxsw_reg_smid_swid_set(payload, 0);
113 mlxsw_reg_smid_mid_set(payload, mid);
114 mlxsw_reg_smid_port_set(payload, port, set);
115 mlxsw_reg_smid_port_mask_set(payload, port, 1);
116}
117
118/* SSPR - Switch System Port Record Register
119 * -----------------------------------------
120 * Configures the system port to local port mapping.
121 */
122#define MLXSW_REG_SSPR_ID 0x2008
123#define MLXSW_REG_SSPR_LEN 0x8
124
125MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN);
126
127/* reg_sspr_m
128 * Master - if set, then the record describes the master system port.
129 * This is needed in case a local port is mapped into several system ports
130 * (for multipathing). That number will be reported as the source system
131 * port when packets are forwarded to the CPU. Only one master port is allowed
132 * per local port.
133 *
134 * Note: Must be set for Spectrum.
135 * Access: RW
136 */
137MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1);
138
139/* reg_sspr_local_port
140 * Local port number.
141 *
142 * Access: RW
143 */
144MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8);
145
146/* reg_sspr_sub_port
147 * Virtual port within the physical port.
148 * Should be set to 0 when virtual ports are not enabled on the port.
149 *
150 * Access: RW
151 */
152MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8);
153
154/* reg_sspr_system_port
155 * Unique identifier within the stacking domain that represents all the ports
156 * that are available in the system (external ports).
157 *
158 * Currently, only single-ASIC configurations are supported, so we default to
159 * 1:1 mapping between system ports and local ports.
160 * Access: Index
161 */
162MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16);
163
164static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port)
165{
166 MLXSW_REG_ZERO(sspr, payload);
167 mlxsw_reg_sspr_m_set(payload, 1);
168 mlxsw_reg_sspr_local_port_set(payload, local_port);
169 mlxsw_reg_sspr_sub_port_set(payload, 0);
170 mlxsw_reg_sspr_system_port_set(payload, local_port);
171}
172
173/* SFDAT - Switch Filtering Database Aging Time
174 * --------------------------------------------
175 * Controls the Switch aging time. Aging time is able to be set per Switch
176 * Partition.
177 */
178#define MLXSW_REG_SFDAT_ID 0x2009
179#define MLXSW_REG_SFDAT_LEN 0x8
180
181MLXSW_REG_DEFINE(sfdat, MLXSW_REG_SFDAT_ID, MLXSW_REG_SFDAT_LEN);
182
183/* reg_sfdat_swid
184 * Switch partition ID.
185 * Access: Index
186 */
187MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8);
188
189/* reg_sfdat_age_time
190 * Aging time in seconds
191 * Min - 10 seconds
192 * Max - 1,000,000 seconds
193 * Default is 300 seconds.
194 * Access: RW
195 */
196MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20);
197
198static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time)
199{
200 MLXSW_REG_ZERO(sfdat, payload);
201 mlxsw_reg_sfdat_swid_set(payload, 0);
202 mlxsw_reg_sfdat_age_time_set(payload, age_time);
203}
204
205/* SFD - Switch Filtering Database
206 * -------------------------------
207 * The following register defines the access to the filtering database.
208 * The register supports querying, adding, removing and modifying the database.
209 * The access is optimized for bulk updates in which case more than one
210 * FDB record is present in the same command.
211 */
212#define MLXSW_REG_SFD_ID 0x200A
213#define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */
214#define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */
215#define MLXSW_REG_SFD_REC_MAX_COUNT 64
216#define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \
217 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT)
218
219MLXSW_REG_DEFINE(sfd, MLXSW_REG_SFD_ID, MLXSW_REG_SFD_LEN);
220
221/* reg_sfd_swid
222 * Switch partition ID for queries. Reserved on Write.
223 * Access: Index
224 */
225MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8);
226
227enum mlxsw_reg_sfd_op {
228 /* Dump entire FDB a (process according to record_locator) */
229 MLXSW_REG_SFD_OP_QUERY_DUMP = 0,
230 /* Query records by {MAC, VID/FID} value */
231 MLXSW_REG_SFD_OP_QUERY_QUERY = 1,
232 /* Query and clear activity. Query records by {MAC, VID/FID} value */
233 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2,
234 /* Test. Response indicates if each of the records could be
235 * added to the FDB.
236 */
237 MLXSW_REG_SFD_OP_WRITE_TEST = 0,
238 /* Add/modify. Aged-out records cannot be added. This command removes
239 * the learning notification of the {MAC, VID/FID}. Response includes
240 * the entries that were added to the FDB.
241 */
242 MLXSW_REG_SFD_OP_WRITE_EDIT = 1,
243 /* Remove record by {MAC, VID/FID}. This command also removes
244 * the learning notification and aged-out notifications
245 * of the {MAC, VID/FID}. The response provides current (pre-removal)
246 * entries as non-aged-out.
247 */
248 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2,
249 /* Remove learned notification by {MAC, VID/FID}. The response provides
250 * the removed learning notification.
251 */
252 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2,
253};
254
255/* reg_sfd_op
256 * Operation.
257 * Access: OP
258 */
259MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2);
260
261/* reg_sfd_record_locator
262 * Used for querying the FDB. Use record_locator=0 to initiate the
263 * query. When a record is returned, a new record_locator is
264 * returned to be used in the subsequent query.
265 * Reserved for database update.
266 * Access: Index
267 */
268MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30);
269
270/* reg_sfd_num_rec
271 * Request: Number of records to read/add/modify/remove
272 * Response: Number of records read/added/replaced/removed
273 * See above description for more details.
274 * Ranges 0..64
275 * Access: RW
276 */
277MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8);
278
279static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op,
280 u32 record_locator)
281{
282 MLXSW_REG_ZERO(sfd, payload);
283 mlxsw_reg_sfd_op_set(payload, op);
284 mlxsw_reg_sfd_record_locator_set(payload, record_locator);
285}
286
287/* reg_sfd_rec_swid
288 * Switch partition ID.
289 * Access: Index
290 */
291MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8,
292 MLXSW_REG_SFD_REC_LEN, 0x00, false);
293
294enum mlxsw_reg_sfd_rec_type {
295 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0,
296 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1,
297 MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2,
298 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL = 0xC,
299};
300
301/* reg_sfd_rec_type
302 * FDB record type.
303 * Access: RW
304 */
305MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4,
306 MLXSW_REG_SFD_REC_LEN, 0x00, false);
307
308enum mlxsw_reg_sfd_rec_policy {
309 /* Replacement disabled, aging disabled. */
310 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0,
311 /* (mlag remote): Replacement enabled, aging disabled,
312 * learning notification enabled on this port.
313 */
314 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1,
315 /* (ingress device): Replacement enabled, aging enabled. */
316 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3,
317};
318
319/* reg_sfd_rec_policy
320 * Policy.
321 * Access: RW
322 */
323MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2,
324 MLXSW_REG_SFD_REC_LEN, 0x00, false);
325
326/* reg_sfd_rec_a
327 * Activity. Set for new static entries. Set for static entries if a frame SMAC
328 * lookup hits on the entry.
329 * To clear the a bit, use "query and clear activity" op.
330 * Access: RO
331 */
332MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1,
333 MLXSW_REG_SFD_REC_LEN, 0x00, false);
334
335/* reg_sfd_rec_mac
336 * MAC address.
337 * Access: Index
338 */
339MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6,
340 MLXSW_REG_SFD_REC_LEN, 0x02);
341
342enum mlxsw_reg_sfd_rec_action {
343 /* forward */
344 MLXSW_REG_SFD_REC_ACTION_NOP = 0,
345 /* forward and trap, trap_id is FDB_TRAP */
346 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1,
347 /* trap and do not forward, trap_id is FDB_TRAP */
348 MLXSW_REG_SFD_REC_ACTION_TRAP = 2,
349 /* forward to IP router */
350 MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3,
351 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15,
352};
353
354/* reg_sfd_rec_action
355 * Action to apply on the packet.
356 * Note: Dynamic entries can only be configured with NOP action.
357 * Access: RW
358 */
359MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4,
360 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
361
362/* reg_sfd_uc_sub_port
363 * VEPA channel on local port.
364 * Valid only if local port is a non-stacking port. Must be 0 if multichannel
365 * VEPA is not enabled.
366 * Access: RW
367 */
368MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
369 MLXSW_REG_SFD_REC_LEN, 0x08, false);
370
371/* reg_sfd_uc_fid_vid
372 * Filtering ID or VLAN ID
373 * For SwitchX and SwitchX-2:
374 * - Dynamic entries (policy 2,3) use FID
375 * - Static entries (policy 0) use VID
376 * - When independent learning is configured, VID=FID
377 * For Spectrum: use FID for both Dynamic and Static entries.
378 * VID should not be used.
379 * Access: Index
380 */
381MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
382 MLXSW_REG_SFD_REC_LEN, 0x08, false);
383
384/* reg_sfd_uc_system_port
385 * Unique port identifier for the final destination of the packet.
386 * Access: RW
387 */
388MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16,
389 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
390
391static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index,
392 enum mlxsw_reg_sfd_rec_type rec_type,
393 const char *mac,
394 enum mlxsw_reg_sfd_rec_action action)
395{
396 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload);
397
398 if (rec_index >= num_rec)
399 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1);
400 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0);
401 mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type);
402 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac);
403 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action);
404}
405
406static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index,
407 enum mlxsw_reg_sfd_rec_policy policy,
408 const char *mac, u16 fid_vid,
409 enum mlxsw_reg_sfd_rec_action action,
410 u8 local_port)
411{
412 mlxsw_reg_sfd_rec_pack(payload, rec_index,
413 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action);
414 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
415 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0);
416 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid);
417 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port);
418}
419
420static inline void mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index,
421 char *mac, u16 *p_fid_vid,
422 u8 *p_local_port)
423{
424 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac);
425 *p_fid_vid = mlxsw_reg_sfd_uc_fid_vid_get(payload, rec_index);
426 *p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index);
427}
428
429/* reg_sfd_uc_lag_sub_port
430 * LAG sub port.
431 * Must be 0 if multichannel VEPA is not enabled.
432 * Access: RW
433 */
434MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
435 MLXSW_REG_SFD_REC_LEN, 0x08, false);
436
437/* reg_sfd_uc_lag_fid_vid
438 * Filtering ID or VLAN ID
439 * For SwitchX and SwitchX-2:
440 * - Dynamic entries (policy 2,3) use FID
441 * - Static entries (policy 0) use VID
442 * - When independent learning is configured, VID=FID
443 * For Spectrum: use FID for both Dynamic and Static entries.
444 * VID should not be used.
445 * Access: Index
446 */
447MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
448 MLXSW_REG_SFD_REC_LEN, 0x08, false);
449
450/* reg_sfd_uc_lag_lag_vid
451 * Indicates VID in case of vFIDs. Reserved for FIDs.
452 * Access: RW
453 */
454MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12,
455 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
456
457/* reg_sfd_uc_lag_lag_id
458 * LAG Identifier - pointer into the LAG descriptor table.
459 * Access: RW
460 */
461MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10,
462 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
463
464static inline void
465mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index,
466 enum mlxsw_reg_sfd_rec_policy policy,
467 const char *mac, u16 fid_vid,
468 enum mlxsw_reg_sfd_rec_action action, u16 lag_vid,
469 u16 lag_id)
470{
471 mlxsw_reg_sfd_rec_pack(payload, rec_index,
472 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG,
473 mac, action);
474 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
475 mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0);
476 mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid);
477 mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid);
478 mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id);
479}
480
481static inline void mlxsw_reg_sfd_uc_lag_unpack(char *payload, int rec_index,
482 char *mac, u16 *p_vid,
483 u16 *p_lag_id)
484{
485 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac);
486 *p_vid = mlxsw_reg_sfd_uc_lag_fid_vid_get(payload, rec_index);
487 *p_lag_id = mlxsw_reg_sfd_uc_lag_lag_id_get(payload, rec_index);
488}
489
490/* reg_sfd_mc_pgi
491 *
492 * Multicast port group index - index into the port group table.
493 * Value 0x1FFF indicates the pgi should point to the MID entry.
494 * For Spectrum this value must be set to 0x1FFF
495 * Access: RW
496 */
497MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13,
498 MLXSW_REG_SFD_REC_LEN, 0x08, false);
499
500/* reg_sfd_mc_fid_vid
501 *
502 * Filtering ID or VLAN ID
503 * Access: Index
504 */
505MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
506 MLXSW_REG_SFD_REC_LEN, 0x08, false);
507
508/* reg_sfd_mc_mid
509 *
510 * Multicast identifier - global identifier that represents the multicast
511 * group across all devices.
512 * Access: RW
513 */
514MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
515 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
516
517static inline void
518mlxsw_reg_sfd_mc_pack(char *payload, int rec_index,
519 const char *mac, u16 fid_vid,
520 enum mlxsw_reg_sfd_rec_action action, u16 mid)
521{
522 mlxsw_reg_sfd_rec_pack(payload, rec_index,
523 MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action);
524 mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF);
525 mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid);
526 mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid);
527}
528
529/* reg_sfd_uc_tunnel_uip_msb
530 * When protocol is IPv4, the most significant byte of the underlay IPv4
531 * destination IP.
532 * When protocol is IPv6, reserved.
533 * Access: RW
534 */
535MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_msb, MLXSW_REG_SFD_BASE_LEN, 24,
536 8, MLXSW_REG_SFD_REC_LEN, 0x08, false);
537
538/* reg_sfd_uc_tunnel_fid
539 * Filtering ID.
540 * Access: Index
541 */
542MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_fid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
543 MLXSW_REG_SFD_REC_LEN, 0x08, false);
544
545enum mlxsw_reg_sfd_uc_tunnel_protocol {
546 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4,
547 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6,
548};
549
550/* reg_sfd_uc_tunnel_protocol
551 * IP protocol.
552 * Access: RW
553 */
554MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_protocol, MLXSW_REG_SFD_BASE_LEN, 27,
555 1, MLXSW_REG_SFD_REC_LEN, 0x0C, false);
556
557/* reg_sfd_uc_tunnel_uip_lsb
558 * When protocol is IPv4, the least significant bytes of the underlay
559 * IPv4 destination IP.
560 * When protocol is IPv6, pointer to the underlay IPv6 destination IP
561 * which is configured by RIPS.
562 * Access: RW
563 */
564MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_lsb, MLXSW_REG_SFD_BASE_LEN, 0,
565 24, MLXSW_REG_SFD_REC_LEN, 0x0C, false);
566
567static inline void
568mlxsw_reg_sfd_uc_tunnel_pack(char *payload, int rec_index,
569 enum mlxsw_reg_sfd_rec_policy policy,
570 const char *mac, u16 fid,
571 enum mlxsw_reg_sfd_rec_action action, u32 uip,
572 enum mlxsw_reg_sfd_uc_tunnel_protocol proto)
573{
574 mlxsw_reg_sfd_rec_pack(payload, rec_index,
575 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL, mac,
576 action);
577 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
578 mlxsw_reg_sfd_uc_tunnel_uip_msb_set(payload, rec_index, uip >> 24);
579 mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip);
580 mlxsw_reg_sfd_uc_tunnel_fid_set(payload, rec_index, fid);
581 mlxsw_reg_sfd_uc_tunnel_protocol_set(payload, rec_index, proto);
582}
583
584/* SFN - Switch FDB Notification Register
585 * -------------------------------------------
586 * The switch provides notifications on newly learned FDB entries and
587 * aged out entries. The notifications can be polled by software.
588 */
589#define MLXSW_REG_SFN_ID 0x200B
590#define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */
591#define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */
592#define MLXSW_REG_SFN_REC_MAX_COUNT 64
593#define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \
594 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT)
595
596MLXSW_REG_DEFINE(sfn, MLXSW_REG_SFN_ID, MLXSW_REG_SFN_LEN);
597
598/* reg_sfn_swid
599 * Switch partition ID.
600 * Access: Index
601 */
602MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8);
603
604/* reg_sfn_end
605 * Forces the current session to end.
606 * Access: OP
607 */
608MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1);
609
610/* reg_sfn_num_rec
611 * Request: Number of learned notifications and aged-out notification
612 * records requested.
613 * Response: Number of notification records returned (must be smaller
614 * than or equal to the value requested)
615 * Ranges 0..64
616 * Access: OP
617 */
618MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8);
619
620static inline void mlxsw_reg_sfn_pack(char *payload)
621{
622 MLXSW_REG_ZERO(sfn, payload);
623 mlxsw_reg_sfn_swid_set(payload, 0);
624 mlxsw_reg_sfn_end_set(payload, 1);
625 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT);
626}
627
628/* reg_sfn_rec_swid
629 * Switch partition ID.
630 * Access: RO
631 */
632MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8,
633 MLXSW_REG_SFN_REC_LEN, 0x00, false);
634
635enum mlxsw_reg_sfn_rec_type {
636 /* MAC addresses learned on a regular port. */
637 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5,
638 /* MAC addresses learned on a LAG port. */
639 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6,
640 /* Aged-out MAC address on a regular port. */
641 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7,
642 /* Aged-out MAC address on a LAG port. */
643 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8,
644 /* Learned unicast tunnel record. */
645 MLXSW_REG_SFN_REC_TYPE_LEARNED_UNICAST_TUNNEL = 0xD,
646 /* Aged-out unicast tunnel record. */
647 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_UNICAST_TUNNEL = 0xE,
648};
649
650/* reg_sfn_rec_type
651 * Notification record type.
652 * Access: RO
653 */
654MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4,
655 MLXSW_REG_SFN_REC_LEN, 0x00, false);
656
657/* reg_sfn_rec_mac
658 * MAC address.
659 * Access: RO
660 */
661MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6,
662 MLXSW_REG_SFN_REC_LEN, 0x02);
663
664/* reg_sfn_mac_sub_port
665 * VEPA channel on the local port.
666 * 0 if multichannel VEPA is not enabled.
667 * Access: RO
668 */
669MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8,
670 MLXSW_REG_SFN_REC_LEN, 0x08, false);
671
672/* reg_sfn_mac_fid
673 * Filtering identifier.
674 * Access: RO
675 */
676MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16,
677 MLXSW_REG_SFN_REC_LEN, 0x08, false);
678
679/* reg_sfn_mac_system_port
680 * Unique port identifier for the final destination of the packet.
681 * Access: RO
682 */
683MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16,
684 MLXSW_REG_SFN_REC_LEN, 0x0C, false);
685
686static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index,
687 char *mac, u16 *p_vid,
688 u8 *p_local_port)
689{
690 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
691 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
692 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index);
693}
694
695/* reg_sfn_mac_lag_lag_id
696 * LAG ID (pointer into the LAG descriptor table).
697 * Access: RO
698 */
699MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10,
700 MLXSW_REG_SFN_REC_LEN, 0x0C, false);
701
702static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index,
703 char *mac, u16 *p_vid,
704 u16 *p_lag_id)
705{
706 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
707 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
708 *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index);
709}
710
711/* reg_sfn_uc_tunnel_uip_msb
712 * When protocol is IPv4, the most significant byte of the underlay IPv4
713 * address of the remote VTEP.
714 * When protocol is IPv6, reserved.
715 * Access: RO
716 */
717MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_msb, MLXSW_REG_SFN_BASE_LEN, 24,
718 8, MLXSW_REG_SFN_REC_LEN, 0x08, false);
719
720enum mlxsw_reg_sfn_uc_tunnel_protocol {
721 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV4,
722 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV6,
723};
724
725/* reg_sfn_uc_tunnel_protocol
726 * IP protocol.
727 * Access: RO
728 */
729MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_protocol, MLXSW_REG_SFN_BASE_LEN, 27,
730 1, MLXSW_REG_SFN_REC_LEN, 0x0C, false);
731
732/* reg_sfn_uc_tunnel_uip_lsb
733 * When protocol is IPv4, the least significant bytes of the underlay
734 * IPv4 address of the remote VTEP.
735 * When protocol is IPv6, ipv6_id to be queried from TNIPSD.
736 * Access: RO
737 */
738MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_lsb, MLXSW_REG_SFN_BASE_LEN, 0,
739 24, MLXSW_REG_SFN_REC_LEN, 0x0C, false);
740
741enum mlxsw_reg_sfn_tunnel_port {
742 MLXSW_REG_SFN_TUNNEL_PORT_NVE,
743 MLXSW_REG_SFN_TUNNEL_PORT_VPLS,
744 MLXSW_REG_SFN_TUNNEL_FLEX_TUNNEL0,
745 MLXSW_REG_SFN_TUNNEL_FLEX_TUNNEL1,
746};
747
748/* reg_sfn_uc_tunnel_port
749 * Tunnel port.
750 * Reserved on Spectrum.
751 * Access: RO
752 */
753MLXSW_ITEM32_INDEXED(reg, sfn, tunnel_port, MLXSW_REG_SFN_BASE_LEN, 0, 4,
754 MLXSW_REG_SFN_REC_LEN, 0x10, false);
755
756static inline void
757mlxsw_reg_sfn_uc_tunnel_unpack(char *payload, int rec_index, char *mac,
758 u16 *p_fid, u32 *p_uip,
759 enum mlxsw_reg_sfn_uc_tunnel_protocol *p_proto)
760{
761 u32 uip_msb, uip_lsb;
762
763 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
764 *p_fid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
765 uip_msb = mlxsw_reg_sfn_uc_tunnel_uip_msb_get(payload, rec_index);
766 uip_lsb = mlxsw_reg_sfn_uc_tunnel_uip_lsb_get(payload, rec_index);
767 *p_uip = uip_msb << 24 | uip_lsb;
768 *p_proto = mlxsw_reg_sfn_uc_tunnel_protocol_get(payload, rec_index);
769}
770
771/* SPMS - Switch Port MSTP/RSTP State Register
772 * -------------------------------------------
773 * Configures the spanning tree state of a physical port.
774 */
775#define MLXSW_REG_SPMS_ID 0x200D
776#define MLXSW_REG_SPMS_LEN 0x404
777
778MLXSW_REG_DEFINE(spms, MLXSW_REG_SPMS_ID, MLXSW_REG_SPMS_LEN);
779
780/* reg_spms_local_port
781 * Local port number.
782 * Access: Index
783 */
784MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8);
785
786enum mlxsw_reg_spms_state {
787 MLXSW_REG_SPMS_STATE_NO_CHANGE,
788 MLXSW_REG_SPMS_STATE_DISCARDING,
789 MLXSW_REG_SPMS_STATE_LEARNING,
790 MLXSW_REG_SPMS_STATE_FORWARDING,
791};
792
793/* reg_spms_state
794 * Spanning tree state of each VLAN ID (VID) of the local port.
795 * 0 - Do not change spanning tree state (used only when writing).
796 * 1 - Discarding. No learning or forwarding to/from this port (default).
797 * 2 - Learning. Port is learning, but not forwarding.
798 * 3 - Forwarding. Port is learning and forwarding.
799 * Access: RW
800 */
801MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2);
802
803static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port)
804{
805 MLXSW_REG_ZERO(spms, payload);
806 mlxsw_reg_spms_local_port_set(payload, local_port);
807}
808
809static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid,
810 enum mlxsw_reg_spms_state state)
811{
812 mlxsw_reg_spms_state_set(payload, vid, state);
813}
814
815/* SPVID - Switch Port VID
816 * -----------------------
817 * The switch port VID configures the default VID for a port.
818 */
819#define MLXSW_REG_SPVID_ID 0x200E
820#define MLXSW_REG_SPVID_LEN 0x08
821
822MLXSW_REG_DEFINE(spvid, MLXSW_REG_SPVID_ID, MLXSW_REG_SPVID_LEN);
823
824/* reg_spvid_local_port
825 * Local port number.
826 * Access: Index
827 */
828MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8);
829
830/* reg_spvid_sub_port
831 * Virtual port within the physical port.
832 * Should be set to 0 when virtual ports are not enabled on the port.
833 * Access: Index
834 */
835MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8);
836
837/* reg_spvid_pvid
838 * Port default VID
839 * Access: RW
840 */
841MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12);
842
843static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid)
844{
845 MLXSW_REG_ZERO(spvid, payload);
846 mlxsw_reg_spvid_local_port_set(payload, local_port);
847 mlxsw_reg_spvid_pvid_set(payload, pvid);
848}
849
850/* SPVM - Switch Port VLAN Membership
851 * ----------------------------------
852 * The Switch Port VLAN Membership register configures the VLAN membership
853 * of a port in a VLAN denoted by VID. VLAN membership is managed per
854 * virtual port. The register can be used to add and remove VID(s) from a port.
855 */
856#define MLXSW_REG_SPVM_ID 0x200F
857#define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */
858#define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */
859#define MLXSW_REG_SPVM_REC_MAX_COUNT 255
860#define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \
861 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT)
862
863MLXSW_REG_DEFINE(spvm, MLXSW_REG_SPVM_ID, MLXSW_REG_SPVM_LEN);
864
865/* reg_spvm_pt
866 * Priority tagged. If this bit is set, packets forwarded to the port with
867 * untagged VLAN membership (u bit is set) will be tagged with priority tag
868 * (VID=0)
869 * Access: RW
870 */
871MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1);
872
873/* reg_spvm_pte
874 * Priority Tagged Update Enable. On Write operations, if this bit is cleared,
875 * the pt bit will NOT be updated. To update the pt bit, pte must be set.
876 * Access: WO
877 */
878MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1);
879
880/* reg_spvm_local_port
881 * Local port number.
882 * Access: Index
883 */
884MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8);
885
886/* reg_spvm_sub_port
887 * Virtual port within the physical port.
888 * Should be set to 0 when virtual ports are not enabled on the port.
889 * Access: Index
890 */
891MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8);
892
893/* reg_spvm_num_rec
894 * Number of records to update. Each record contains: i, e, u, vid.
895 * Access: OP
896 */
897MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8);
898
899/* reg_spvm_rec_i
900 * Ingress membership in VLAN ID.
901 * Access: Index
902 */
903MLXSW_ITEM32_INDEXED(reg, spvm, rec_i,
904 MLXSW_REG_SPVM_BASE_LEN, 14, 1,
905 MLXSW_REG_SPVM_REC_LEN, 0, false);
906
907/* reg_spvm_rec_e
908 * Egress membership in VLAN ID.
909 * Access: Index
910 */
911MLXSW_ITEM32_INDEXED(reg, spvm, rec_e,
912 MLXSW_REG_SPVM_BASE_LEN, 13, 1,
913 MLXSW_REG_SPVM_REC_LEN, 0, false);
914
915/* reg_spvm_rec_u
916 * Untagged - port is an untagged member - egress transmission uses untagged
917 * frames on VID<n>
918 * Access: Index
919 */
920MLXSW_ITEM32_INDEXED(reg, spvm, rec_u,
921 MLXSW_REG_SPVM_BASE_LEN, 12, 1,
922 MLXSW_REG_SPVM_REC_LEN, 0, false);
923
924/* reg_spvm_rec_vid
925 * Egress membership in VLAN ID.
926 * Access: Index
927 */
928MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid,
929 MLXSW_REG_SPVM_BASE_LEN, 0, 12,
930 MLXSW_REG_SPVM_REC_LEN, 0, false);
931
932static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port,
933 u16 vid_begin, u16 vid_end,
934 bool is_member, bool untagged)
935{
936 int size = vid_end - vid_begin + 1;
937 int i;
938
939 MLXSW_REG_ZERO(spvm, payload);
940 mlxsw_reg_spvm_local_port_set(payload, local_port);
941 mlxsw_reg_spvm_num_rec_set(payload, size);
942
943 for (i = 0; i < size; i++) {
944 mlxsw_reg_spvm_rec_i_set(payload, i, is_member);
945 mlxsw_reg_spvm_rec_e_set(payload, i, is_member);
946 mlxsw_reg_spvm_rec_u_set(payload, i, untagged);
947 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i);
948 }
949}
950
951/* SPAFT - Switch Port Acceptable Frame Types
952 * ------------------------------------------
953 * The Switch Port Acceptable Frame Types register configures the frame
954 * admittance of the port.
955 */
956#define MLXSW_REG_SPAFT_ID 0x2010
957#define MLXSW_REG_SPAFT_LEN 0x08
958
959MLXSW_REG_DEFINE(spaft, MLXSW_REG_SPAFT_ID, MLXSW_REG_SPAFT_LEN);
960
961/* reg_spaft_local_port
962 * Local port number.
963 * Access: Index
964 *
965 * Note: CPU port is not supported (all tag types are allowed).
966 */
967MLXSW_ITEM32(reg, spaft, local_port, 0x00, 16, 8);
968
969/* reg_spaft_sub_port
970 * Virtual port within the physical port.
971 * Should be set to 0 when virtual ports are not enabled on the port.
972 * Access: RW
973 */
974MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8);
975
976/* reg_spaft_allow_untagged
977 * When set, untagged frames on the ingress are allowed (default).
978 * Access: RW
979 */
980MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1);
981
982/* reg_spaft_allow_prio_tagged
983 * When set, priority tagged frames on the ingress are allowed (default).
984 * Access: RW
985 */
986MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1);
987
988/* reg_spaft_allow_tagged
989 * When set, tagged frames on the ingress are allowed (default).
990 * Access: RW
991 */
992MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1);
993
994static inline void mlxsw_reg_spaft_pack(char *payload, u8 local_port,
995 bool allow_untagged)
996{
997 MLXSW_REG_ZERO(spaft, payload);
998 mlxsw_reg_spaft_local_port_set(payload, local_port);
999 mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged);
1000 mlxsw_reg_spaft_allow_prio_tagged_set(payload, true);
1001 mlxsw_reg_spaft_allow_tagged_set(payload, true);
1002}
1003
1004/* SFGC - Switch Flooding Group Configuration
1005 * ------------------------------------------
1006 * The following register controls the association of flooding tables and MIDs
1007 * to packet types used for flooding.
1008 */
1009#define MLXSW_REG_SFGC_ID 0x2011
1010#define MLXSW_REG_SFGC_LEN 0x10
1011
1012MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN);
1013
1014enum mlxsw_reg_sfgc_type {
1015 MLXSW_REG_SFGC_TYPE_BROADCAST,
1016 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST,
1017 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4,
1018 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6,
1019 MLXSW_REG_SFGC_TYPE_RESERVED,
1020 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP,
1021 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL,
1022 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST,
1023 MLXSW_REG_SFGC_TYPE_MAX,
1024};
1025
1026/* reg_sfgc_type
1027 * The traffic type to reach the flooding table.
1028 * Access: Index
1029 */
1030MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4);
1031
1032enum mlxsw_reg_sfgc_bridge_type {
1033 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0,
1034 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1,
1035};
1036
1037/* reg_sfgc_bridge_type
1038 * Access: Index
1039 *
1040 * Note: SwitchX-2 only supports 802.1Q mode.
1041 */
1042MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3);
1043
1044enum mlxsw_flood_table_type {
1045 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1,
1046 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2,
1047 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0,
1048 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFSET = 3,
1049 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4,
1050};
1051
1052/* reg_sfgc_table_type
1053 * See mlxsw_flood_table_type
1054 * Access: RW
1055 *
1056 * Note: FID offset and FID types are not supported in SwitchX-2.
1057 */
1058MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3);
1059
1060/* reg_sfgc_flood_table
1061 * Flooding table index to associate with the specific type on the specific
1062 * switch partition.
1063 * Access: RW
1064 */
1065MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6);
1066
1067/* reg_sfgc_mid
1068 * The multicast ID for the swid. Not supported for Spectrum
1069 * Access: RW
1070 */
1071MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16);
1072
1073/* reg_sfgc_counter_set_type
1074 * Counter Set Type for flow counters.
1075 * Access: RW
1076 */
1077MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8);
1078
1079/* reg_sfgc_counter_index
1080 * Counter Index for flow counters.
1081 * Access: RW
1082 */
1083MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24);
1084
1085static inline void
1086mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type,
1087 enum mlxsw_reg_sfgc_bridge_type bridge_type,
1088 enum mlxsw_flood_table_type table_type,
1089 unsigned int flood_table)
1090{
1091 MLXSW_REG_ZERO(sfgc, payload);
1092 mlxsw_reg_sfgc_type_set(payload, type);
1093 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type);
1094 mlxsw_reg_sfgc_table_type_set(payload, table_type);
1095 mlxsw_reg_sfgc_flood_table_set(payload, flood_table);
1096 mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID);
1097}
1098
1099/* SFTR - Switch Flooding Table Register
1100 * -------------------------------------
1101 * The switch flooding table is used for flooding packet replication. The table
1102 * defines a bit mask of ports for packet replication.
1103 */
1104#define MLXSW_REG_SFTR_ID 0x2012
1105#define MLXSW_REG_SFTR_LEN 0x420
1106
1107MLXSW_REG_DEFINE(sftr, MLXSW_REG_SFTR_ID, MLXSW_REG_SFTR_LEN);
1108
1109/* reg_sftr_swid
1110 * Switch partition ID with which to associate the port.
1111 * Access: Index
1112 */
1113MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8);
1114
1115/* reg_sftr_flood_table
1116 * Flooding table index to associate with the specific type on the specific
1117 * switch partition.
1118 * Access: Index
1119 */
1120MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6);
1121
1122/* reg_sftr_index
1123 * Index. Used as an index into the Flooding Table in case the table is
1124 * configured to use VID / FID or FID Offset.
1125 * Access: Index
1126 */
1127MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16);
1128
1129/* reg_sftr_table_type
1130 * See mlxsw_flood_table_type
1131 * Access: RW
1132 */
1133MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3);
1134
1135/* reg_sftr_range
1136 * Range of entries to update
1137 * Access: Index
1138 */
1139MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16);
1140
1141/* reg_sftr_port
1142 * Local port membership (1 bit per port).
1143 * Access: RW
1144 */
1145MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1);
1146
1147/* reg_sftr_cpu_port_mask
1148 * CPU port mask (1 bit per port).
1149 * Access: W
1150 */
1151MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1);
1152
1153static inline void mlxsw_reg_sftr_pack(char *payload,
1154 unsigned int flood_table,
1155 unsigned int index,
1156 enum mlxsw_flood_table_type table_type,
1157 unsigned int range, u8 port, bool set)
1158{
1159 MLXSW_REG_ZERO(sftr, payload);
1160 mlxsw_reg_sftr_swid_set(payload, 0);
1161 mlxsw_reg_sftr_flood_table_set(payload, flood_table);
1162 mlxsw_reg_sftr_index_set(payload, index);
1163 mlxsw_reg_sftr_table_type_set(payload, table_type);
1164 mlxsw_reg_sftr_range_set(payload, range);
1165 mlxsw_reg_sftr_port_set(payload, port, set);
1166 mlxsw_reg_sftr_port_mask_set(payload, port, 1);
1167}
1168
1169/* SFDF - Switch Filtering DB Flush
1170 * --------------------------------
1171 * The switch filtering DB flush register is used to flush the FDB.
1172 * Note that FDB notifications are flushed as well.
1173 */
1174#define MLXSW_REG_SFDF_ID 0x2013
1175#define MLXSW_REG_SFDF_LEN 0x14
1176
1177MLXSW_REG_DEFINE(sfdf, MLXSW_REG_SFDF_ID, MLXSW_REG_SFDF_LEN);
1178
1179/* reg_sfdf_swid
1180 * Switch partition ID.
1181 * Access: Index
1182 */
1183MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8);
1184
1185enum mlxsw_reg_sfdf_flush_type {
1186 MLXSW_REG_SFDF_FLUSH_PER_SWID,
1187 MLXSW_REG_SFDF_FLUSH_PER_FID,
1188 MLXSW_REG_SFDF_FLUSH_PER_PORT,
1189 MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID,
1190 MLXSW_REG_SFDF_FLUSH_PER_LAG,
1191 MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID,
1192 MLXSW_REG_SFDF_FLUSH_PER_NVE,
1193 MLXSW_REG_SFDF_FLUSH_PER_NVE_AND_FID,
1194};
1195
1196/* reg_sfdf_flush_type
1197 * Flush type.
1198 * 0 - All SWID dynamic entries are flushed.
1199 * 1 - All FID dynamic entries are flushed.
1200 * 2 - All dynamic entries pointing to port are flushed.
1201 * 3 - All FID dynamic entries pointing to port are flushed.
1202 * 4 - All dynamic entries pointing to LAG are flushed.
1203 * 5 - All FID dynamic entries pointing to LAG are flushed.
1204 * 6 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are
1205 * flushed.
1206 * 7 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are
1207 * flushed, per FID.
1208 * Access: RW
1209 */
1210MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4);
1211
1212/* reg_sfdf_flush_static
1213 * Static.
1214 * 0 - Flush only dynamic entries.
1215 * 1 - Flush both dynamic and static entries.
1216 * Access: RW
1217 */
1218MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1);
1219
1220static inline void mlxsw_reg_sfdf_pack(char *payload,
1221 enum mlxsw_reg_sfdf_flush_type type)
1222{
1223 MLXSW_REG_ZERO(sfdf, payload);
1224 mlxsw_reg_sfdf_flush_type_set(payload, type);
1225 mlxsw_reg_sfdf_flush_static_set(payload, true);
1226}
1227
1228/* reg_sfdf_fid
1229 * FID to flush.
1230 * Access: RW
1231 */
1232MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16);
1233
1234/* reg_sfdf_system_port
1235 * Port to flush.
1236 * Access: RW
1237 */
1238MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16);
1239
1240/* reg_sfdf_port_fid_system_port
1241 * Port to flush, pointed to by FID.
1242 * Access: RW
1243 */
1244MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16);
1245
1246/* reg_sfdf_lag_id
1247 * LAG ID to flush.
1248 * Access: RW
1249 */
1250MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10);
1251
1252/* reg_sfdf_lag_fid_lag_id
1253 * LAG ID to flush, pointed to by FID.
1254 * Access: RW
1255 */
1256MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10);
1257
1258/* SLDR - Switch LAG Descriptor Register
1259 * -----------------------------------------
1260 * The switch LAG descriptor register is populated by LAG descriptors.
1261 * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to
1262 * max_lag-1.
1263 */
1264#define MLXSW_REG_SLDR_ID 0x2014
1265#define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */
1266
1267MLXSW_REG_DEFINE(sldr, MLXSW_REG_SLDR_ID, MLXSW_REG_SLDR_LEN);
1268
1269enum mlxsw_reg_sldr_op {
1270 /* Indicates a creation of a new LAG-ID, lag_id must be valid */
1271 MLXSW_REG_SLDR_OP_LAG_CREATE,
1272 MLXSW_REG_SLDR_OP_LAG_DESTROY,
1273 /* Ports that appear in the list have the Distributor enabled */
1274 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST,
1275 /* Removes ports from the disributor list */
1276 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST,
1277};
1278
1279/* reg_sldr_op
1280 * Operation.
1281 * Access: RW
1282 */
1283MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3);
1284
1285/* reg_sldr_lag_id
1286 * LAG identifier. The lag_id is the index into the LAG descriptor table.
1287 * Access: Index
1288 */
1289MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10);
1290
1291static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id)
1292{
1293 MLXSW_REG_ZERO(sldr, payload);
1294 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE);
1295 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1296}
1297
1298static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id)
1299{
1300 MLXSW_REG_ZERO(sldr, payload);
1301 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY);
1302 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1303}
1304
1305/* reg_sldr_num_ports
1306 * The number of member ports of the LAG.
1307 * Reserved for Create / Destroy operations
1308 * For Add / Remove operations - indicates the number of ports in the list.
1309 * Access: RW
1310 */
1311MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8);
1312
1313/* reg_sldr_system_port
1314 * System port.
1315 * Access: RW
1316 */
1317MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false);
1318
1319static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id,
1320 u8 local_port)
1321{
1322 MLXSW_REG_ZERO(sldr, payload);
1323 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST);
1324 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1325 mlxsw_reg_sldr_num_ports_set(payload, 1);
1326 mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1327}
1328
1329static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id,
1330 u8 local_port)
1331{
1332 MLXSW_REG_ZERO(sldr, payload);
1333 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST);
1334 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1335 mlxsw_reg_sldr_num_ports_set(payload, 1);
1336 mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1337}
1338
1339/* SLCR - Switch LAG Configuration 2 Register
1340 * -------------------------------------------
1341 * The Switch LAG Configuration register is used for configuring the
1342 * LAG properties of the switch.
1343 */
1344#define MLXSW_REG_SLCR_ID 0x2015
1345#define MLXSW_REG_SLCR_LEN 0x10
1346
1347MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN);
1348
1349enum mlxsw_reg_slcr_pp {
1350 /* Global Configuration (for all ports) */
1351 MLXSW_REG_SLCR_PP_GLOBAL,
1352 /* Per port configuration, based on local_port field */
1353 MLXSW_REG_SLCR_PP_PER_PORT,
1354};
1355
1356/* reg_slcr_pp
1357 * Per Port Configuration
1358 * Note: Reading at Global mode results in reading port 1 configuration.
1359 * Access: Index
1360 */
1361MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1);
1362
1363/* reg_slcr_local_port
1364 * Local port number
1365 * Supported from CPU port
1366 * Not supported from router port
1367 * Reserved when pp = Global Configuration
1368 * Access: Index
1369 */
1370MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8);
1371
1372enum mlxsw_reg_slcr_type {
1373 MLXSW_REG_SLCR_TYPE_CRC, /* default */
1374 MLXSW_REG_SLCR_TYPE_XOR,
1375 MLXSW_REG_SLCR_TYPE_RANDOM,
1376};
1377
1378/* reg_slcr_type
1379 * Hash type
1380 * Access: RW
1381 */
1382MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4);
1383
1384/* Ingress port */
1385#define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0)
1386/* SMAC - for IPv4 and IPv6 packets */
1387#define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1)
1388/* SMAC - for non-IP packets */
1389#define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2)
1390#define MLXSW_REG_SLCR_LAG_HASH_SMAC \
1391 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \
1392 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP)
1393/* DMAC - for IPv4 and IPv6 packets */
1394#define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3)
1395/* DMAC - for non-IP packets */
1396#define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4)
1397#define MLXSW_REG_SLCR_LAG_HASH_DMAC \
1398 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \
1399 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP)
1400/* Ethertype - for IPv4 and IPv6 packets */
1401#define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5)
1402/* Ethertype - for non-IP packets */
1403#define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6)
1404#define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \
1405 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \
1406 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP)
1407/* VLAN ID - for IPv4 and IPv6 packets */
1408#define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7)
1409/* VLAN ID - for non-IP packets */
1410#define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8)
1411#define MLXSW_REG_SLCR_LAG_HASH_VLANID \
1412 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \
1413 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP)
1414/* Source IP address (can be IPv4 or IPv6) */
1415#define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9)
1416/* Destination IP address (can be IPv4 or IPv6) */
1417#define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10)
1418/* TCP/UDP source port */
1419#define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11)
1420/* TCP/UDP destination port*/
1421#define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12)
1422/* IPv4 Protocol/IPv6 Next Header */
1423#define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13)
1424/* IPv6 Flow label */
1425#define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14)
1426/* SID - FCoE source ID */
1427#define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15)
1428/* DID - FCoE destination ID */
1429#define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16)
1430/* OXID - FCoE originator exchange ID */
1431#define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17)
1432/* Destination QP number - for RoCE packets */
1433#define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19)
1434
1435/* reg_slcr_lag_hash
1436 * LAG hashing configuration. This is a bitmask, in which each set
1437 * bit includes the corresponding item in the LAG hash calculation.
1438 * The default lag_hash contains SMAC, DMAC, VLANID and
1439 * Ethertype (for all packet types).
1440 * Access: RW
1441 */
1442MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20);
1443
1444/* reg_slcr_seed
1445 * LAG seed value. The seed is the same for all ports.
1446 * Access: RW
1447 */
1448MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32);
1449
1450static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash, u32 seed)
1451{
1452 MLXSW_REG_ZERO(slcr, payload);
1453 mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL);
1454 mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC);
1455 mlxsw_reg_slcr_lag_hash_set(payload, lag_hash);
1456 mlxsw_reg_slcr_seed_set(payload, seed);
1457}
1458
1459/* SLCOR - Switch LAG Collector Register
1460 * -------------------------------------
1461 * The Switch LAG Collector register controls the Local Port membership
1462 * in a LAG and enablement of the collector.
1463 */
1464#define MLXSW_REG_SLCOR_ID 0x2016
1465#define MLXSW_REG_SLCOR_LEN 0x10
1466
1467MLXSW_REG_DEFINE(slcor, MLXSW_REG_SLCOR_ID, MLXSW_REG_SLCOR_LEN);
1468
1469enum mlxsw_reg_slcor_col {
1470 /* Port is added with collector disabled */
1471 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT,
1472 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED,
1473 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED,
1474 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT,
1475};
1476
1477/* reg_slcor_col
1478 * Collector configuration
1479 * Access: RW
1480 */
1481MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2);
1482
1483/* reg_slcor_local_port
1484 * Local port number
1485 * Not supported for CPU port
1486 * Access: Index
1487 */
1488MLXSW_ITEM32(reg, slcor, local_port, 0x00, 16, 8);
1489
1490/* reg_slcor_lag_id
1491 * LAG Identifier. Index into the LAG descriptor table.
1492 * Access: Index
1493 */
1494MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10);
1495
1496/* reg_slcor_port_index
1497 * Port index in the LAG list. Only valid on Add Port to LAG col.
1498 * Valid range is from 0 to cap_max_lag_members-1
1499 * Access: RW
1500 */
1501MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10);
1502
1503static inline void mlxsw_reg_slcor_pack(char *payload,
1504 u8 local_port, u16 lag_id,
1505 enum mlxsw_reg_slcor_col col)
1506{
1507 MLXSW_REG_ZERO(slcor, payload);
1508 mlxsw_reg_slcor_col_set(payload, col);
1509 mlxsw_reg_slcor_local_port_set(payload, local_port);
1510 mlxsw_reg_slcor_lag_id_set(payload, lag_id);
1511}
1512
1513static inline void mlxsw_reg_slcor_port_add_pack(char *payload,
1514 u8 local_port, u16 lag_id,
1515 u8 port_index)
1516{
1517 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1518 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT);
1519 mlxsw_reg_slcor_port_index_set(payload, port_index);
1520}
1521
1522static inline void mlxsw_reg_slcor_port_remove_pack(char *payload,
1523 u8 local_port, u16 lag_id)
1524{
1525 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1526 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT);
1527}
1528
1529static inline void mlxsw_reg_slcor_col_enable_pack(char *payload,
1530 u8 local_port, u16 lag_id)
1531{
1532 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1533 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1534}
1535
1536static inline void mlxsw_reg_slcor_col_disable_pack(char *payload,
1537 u8 local_port, u16 lag_id)
1538{
1539 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1540 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1541}
1542
1543/* SPMLR - Switch Port MAC Learning Register
1544 * -----------------------------------------
1545 * Controls the Switch MAC learning policy per port.
1546 */
1547#define MLXSW_REG_SPMLR_ID 0x2018
1548#define MLXSW_REG_SPMLR_LEN 0x8
1549
1550MLXSW_REG_DEFINE(spmlr, MLXSW_REG_SPMLR_ID, MLXSW_REG_SPMLR_LEN);
1551
1552/* reg_spmlr_local_port
1553 * Local port number.
1554 * Access: Index
1555 */
1556MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8);
1557
1558/* reg_spmlr_sub_port
1559 * Virtual port within the physical port.
1560 * Should be set to 0 when virtual ports are not enabled on the port.
1561 * Access: Index
1562 */
1563MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8);
1564
1565enum mlxsw_reg_spmlr_learn_mode {
1566 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0,
1567 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2,
1568 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3,
1569};
1570
1571/* reg_spmlr_learn_mode
1572 * Learning mode on the port.
1573 * 0 - Learning disabled.
1574 * 2 - Learning enabled.
1575 * 3 - Security mode.
1576 *
1577 * In security mode the switch does not learn MACs on the port, but uses the
1578 * SMAC to see if it exists on another ingress port. If so, the packet is
1579 * classified as a bad packet and is discarded unless the software registers
1580 * to receive port security error packets usign HPKT.
1581 */
1582MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2);
1583
1584static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port,
1585 enum mlxsw_reg_spmlr_learn_mode mode)
1586{
1587 MLXSW_REG_ZERO(spmlr, payload);
1588 mlxsw_reg_spmlr_local_port_set(payload, local_port);
1589 mlxsw_reg_spmlr_sub_port_set(payload, 0);
1590 mlxsw_reg_spmlr_learn_mode_set(payload, mode);
1591}
1592
1593/* SVFA - Switch VID to FID Allocation Register
1594 * --------------------------------------------
1595 * Controls the VID to FID mapping and {Port, VID} to FID mapping for
1596 * virtualized ports.
1597 */
1598#define MLXSW_REG_SVFA_ID 0x201C
1599#define MLXSW_REG_SVFA_LEN 0x10
1600
1601MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN);
1602
1603/* reg_svfa_swid
1604 * Switch partition ID.
1605 * Access: Index
1606 */
1607MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8);
1608
1609/* reg_svfa_local_port
1610 * Local port number.
1611 * Access: Index
1612 *
1613 * Note: Reserved for 802.1Q FIDs.
1614 */
1615MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8);
1616
1617enum mlxsw_reg_svfa_mt {
1618 MLXSW_REG_SVFA_MT_VID_TO_FID,
1619 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
1620};
1621
1622/* reg_svfa_mapping_table
1623 * Mapping table:
1624 * 0 - VID to FID
1625 * 1 - {Port, VID} to FID
1626 * Access: Index
1627 *
1628 * Note: Reserved for SwitchX-2.
1629 */
1630MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3);
1631
1632/* reg_svfa_v
1633 * Valid.
1634 * Valid if set.
1635 * Access: RW
1636 *
1637 * Note: Reserved for SwitchX-2.
1638 */
1639MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1);
1640
1641/* reg_svfa_fid
1642 * Filtering ID.
1643 * Access: RW
1644 */
1645MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16);
1646
1647/* reg_svfa_vid
1648 * VLAN ID.
1649 * Access: Index
1650 */
1651MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12);
1652
1653/* reg_svfa_counter_set_type
1654 * Counter set type for flow counters.
1655 * Access: RW
1656 *
1657 * Note: Reserved for SwitchX-2.
1658 */
1659MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8);
1660
1661/* reg_svfa_counter_index
1662 * Counter index for flow counters.
1663 * Access: RW
1664 *
1665 * Note: Reserved for SwitchX-2.
1666 */
1667MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24);
1668
1669static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port,
1670 enum mlxsw_reg_svfa_mt mt, bool valid,
1671 u16 fid, u16 vid)
1672{
1673 MLXSW_REG_ZERO(svfa, payload);
1674 local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port;
1675 mlxsw_reg_svfa_swid_set(payload, 0);
1676 mlxsw_reg_svfa_local_port_set(payload, local_port);
1677 mlxsw_reg_svfa_mapping_table_set(payload, mt);
1678 mlxsw_reg_svfa_v_set(payload, valid);
1679 mlxsw_reg_svfa_fid_set(payload, fid);
1680 mlxsw_reg_svfa_vid_set(payload, vid);
1681}
1682
1683/* SVPE - Switch Virtual-Port Enabling Register
1684 * --------------------------------------------
1685 * Enables port virtualization.
1686 */
1687#define MLXSW_REG_SVPE_ID 0x201E
1688#define MLXSW_REG_SVPE_LEN 0x4
1689
1690MLXSW_REG_DEFINE(svpe, MLXSW_REG_SVPE_ID, MLXSW_REG_SVPE_LEN);
1691
1692/* reg_svpe_local_port
1693 * Local port number
1694 * Access: Index
1695 *
1696 * Note: CPU port is not supported (uses VLAN mode only).
1697 */
1698MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8);
1699
1700/* reg_svpe_vp_en
1701 * Virtual port enable.
1702 * 0 - Disable, VLAN mode (VID to FID).
1703 * 1 - Enable, Virtual port mode ({Port, VID} to FID).
1704 * Access: RW
1705 */
1706MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1);
1707
1708static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port,
1709 bool enable)
1710{
1711 MLXSW_REG_ZERO(svpe, payload);
1712 mlxsw_reg_svpe_local_port_set(payload, local_port);
1713 mlxsw_reg_svpe_vp_en_set(payload, enable);
1714}
1715
1716/* SFMR - Switch FID Management Register
1717 * -------------------------------------
1718 * Creates and configures FIDs.
1719 */
1720#define MLXSW_REG_SFMR_ID 0x201F
1721#define MLXSW_REG_SFMR_LEN 0x18
1722
1723MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN);
1724
1725enum mlxsw_reg_sfmr_op {
1726 MLXSW_REG_SFMR_OP_CREATE_FID,
1727 MLXSW_REG_SFMR_OP_DESTROY_FID,
1728};
1729
1730/* reg_sfmr_op
1731 * Operation.
1732 * 0 - Create or edit FID.
1733 * 1 - Destroy FID.
1734 * Access: WO
1735 */
1736MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4);
1737
1738/* reg_sfmr_fid
1739 * Filtering ID.
1740 * Access: Index
1741 */
1742MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16);
1743
1744/* reg_sfmr_fid_offset
1745 * FID offset.
1746 * Used to point into the flooding table selected by SFGC register if
1747 * the table is of type FID-Offset. Otherwise, this field is reserved.
1748 * Access: RW
1749 */
1750MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16);
1751
1752/* reg_sfmr_vtfp
1753 * Valid Tunnel Flood Pointer.
1754 * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL.
1755 * Access: RW
1756 *
1757 * Note: Reserved for 802.1Q FIDs.
1758 */
1759MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1);
1760
1761/* reg_sfmr_nve_tunnel_flood_ptr
1762 * Underlay Flooding and BC Pointer.
1763 * Used as a pointer to the first entry of the group based link lists of
1764 * flooding or BC entries (for NVE tunnels).
1765 * Access: RW
1766 */
1767MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24);
1768
1769/* reg_sfmr_vv
1770 * VNI Valid.
1771 * If not set, then vni is reserved.
1772 * Access: RW
1773 *
1774 * Note: Reserved for 802.1Q FIDs.
1775 */
1776MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1);
1777
1778/* reg_sfmr_vni
1779 * Virtual Network Identifier.
1780 * Access: RW
1781 *
1782 * Note: A given VNI can only be assigned to one FID.
1783 */
1784MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24);
1785
1786static inline void mlxsw_reg_sfmr_pack(char *payload,
1787 enum mlxsw_reg_sfmr_op op, u16 fid,
1788 u16 fid_offset)
1789{
1790 MLXSW_REG_ZERO(sfmr, payload);
1791 mlxsw_reg_sfmr_op_set(payload, op);
1792 mlxsw_reg_sfmr_fid_set(payload, fid);
1793 mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset);
1794 mlxsw_reg_sfmr_vtfp_set(payload, false);
1795 mlxsw_reg_sfmr_vv_set(payload, false);
1796}
1797
1798/* SPVMLR - Switch Port VLAN MAC Learning Register
1799 * -----------------------------------------------
1800 * Controls the switch MAC learning policy per {Port, VID}.
1801 */
1802#define MLXSW_REG_SPVMLR_ID 0x2020
1803#define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */
1804#define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */
1805#define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255
1806#define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \
1807 MLXSW_REG_SPVMLR_REC_LEN * \
1808 MLXSW_REG_SPVMLR_REC_MAX_COUNT)
1809
1810MLXSW_REG_DEFINE(spvmlr, MLXSW_REG_SPVMLR_ID, MLXSW_REG_SPVMLR_LEN);
1811
1812/* reg_spvmlr_local_port
1813 * Local ingress port.
1814 * Access: Index
1815 *
1816 * Note: CPU port is not supported.
1817 */
1818MLXSW_ITEM32(reg, spvmlr, local_port, 0x00, 16, 8);
1819
1820/* reg_spvmlr_num_rec
1821 * Number of records to update.
1822 * Access: OP
1823 */
1824MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8);
1825
1826/* reg_spvmlr_rec_learn_enable
1827 * 0 - Disable learning for {Port, VID}.
1828 * 1 - Enable learning for {Port, VID}.
1829 * Access: RW
1830 */
1831MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN,
1832 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1833
1834/* reg_spvmlr_rec_vid
1835 * VLAN ID to be added/removed from port or for querying.
1836 * Access: Index
1837 */
1838MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12,
1839 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1840
1841static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port,
1842 u16 vid_begin, u16 vid_end,
1843 bool learn_enable)
1844{
1845 int num_rec = vid_end - vid_begin + 1;
1846 int i;
1847
1848 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT);
1849
1850 MLXSW_REG_ZERO(spvmlr, payload);
1851 mlxsw_reg_spvmlr_local_port_set(payload, local_port);
1852 mlxsw_reg_spvmlr_num_rec_set(payload, num_rec);
1853
1854 for (i = 0; i < num_rec; i++) {
1855 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable);
1856 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i);
1857 }
1858}
1859
1860/* CWTP - Congetion WRED ECN TClass Profile
1861 * ----------------------------------------
1862 * Configures the profiles for queues of egress port and traffic class
1863 */
1864#define MLXSW_REG_CWTP_ID 0x2802
1865#define MLXSW_REG_CWTP_BASE_LEN 0x28
1866#define MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN 0x08
1867#define MLXSW_REG_CWTP_LEN 0x40
1868
1869MLXSW_REG_DEFINE(cwtp, MLXSW_REG_CWTP_ID, MLXSW_REG_CWTP_LEN);
1870
1871/* reg_cwtp_local_port
1872 * Local port number
1873 * Not supported for CPU port
1874 * Access: Index
1875 */
1876MLXSW_ITEM32(reg, cwtp, local_port, 0, 16, 8);
1877
1878/* reg_cwtp_traffic_class
1879 * Traffic Class to configure
1880 * Access: Index
1881 */
1882MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8);
1883
1884/* reg_cwtp_profile_min
1885 * Minimum Average Queue Size of the profile in cells.
1886 * Access: RW
1887 */
1888MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN,
1889 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 0, false);
1890
1891/* reg_cwtp_profile_percent
1892 * Percentage of WRED and ECN marking for maximum Average Queue size
1893 * Range is 0 to 100, units of integer percentage
1894 * Access: RW
1895 */
1896MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN,
1897 24, 7, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false);
1898
1899/* reg_cwtp_profile_max
1900 * Maximum Average Queue size of the profile in cells
1901 * Access: RW
1902 */
1903MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN,
1904 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false);
1905
1906#define MLXSW_REG_CWTP_MIN_VALUE 64
1907#define MLXSW_REG_CWTP_MAX_PROFILE 2
1908#define MLXSW_REG_CWTP_DEFAULT_PROFILE 1
1909
1910static inline void mlxsw_reg_cwtp_pack(char *payload, u8 local_port,
1911 u8 traffic_class)
1912{
1913 int i;
1914
1915 MLXSW_REG_ZERO(cwtp, payload);
1916 mlxsw_reg_cwtp_local_port_set(payload, local_port);
1917 mlxsw_reg_cwtp_traffic_class_set(payload, traffic_class);
1918
1919 for (i = 0; i <= MLXSW_REG_CWTP_MAX_PROFILE; i++) {
1920 mlxsw_reg_cwtp_profile_min_set(payload, i,
1921 MLXSW_REG_CWTP_MIN_VALUE);
1922 mlxsw_reg_cwtp_profile_max_set(payload, i,
1923 MLXSW_REG_CWTP_MIN_VALUE);
1924 }
1925}
1926
1927#define MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile) (profile - 1)
1928
1929static inline void
1930mlxsw_reg_cwtp_profile_pack(char *payload, u8 profile, u32 min, u32 max,
1931 u32 probability)
1932{
1933 u8 index = MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile);
1934
1935 mlxsw_reg_cwtp_profile_min_set(payload, index, min);
1936 mlxsw_reg_cwtp_profile_max_set(payload, index, max);
1937 mlxsw_reg_cwtp_profile_percent_set(payload, index, probability);
1938}
1939
1940/* CWTPM - Congestion WRED ECN TClass and Pool Mapping
1941 * ---------------------------------------------------
1942 * The CWTPM register maps each egress port and traffic class to profile num.
1943 */
1944#define MLXSW_REG_CWTPM_ID 0x2803
1945#define MLXSW_REG_CWTPM_LEN 0x44
1946
1947MLXSW_REG_DEFINE(cwtpm, MLXSW_REG_CWTPM_ID, MLXSW_REG_CWTPM_LEN);
1948
1949/* reg_cwtpm_local_port
1950 * Local port number
1951 * Not supported for CPU port
1952 * Access: Index
1953 */
1954MLXSW_ITEM32(reg, cwtpm, local_port, 0, 16, 8);
1955
1956/* reg_cwtpm_traffic_class
1957 * Traffic Class to configure
1958 * Access: Index
1959 */
1960MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8);
1961
1962/* reg_cwtpm_ew
1963 * Control enablement of WRED for traffic class:
1964 * 0 - Disable
1965 * 1 - Enable
1966 * Access: RW
1967 */
1968MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1);
1969
1970/* reg_cwtpm_ee
1971 * Control enablement of ECN for traffic class:
1972 * 0 - Disable
1973 * 1 - Enable
1974 * Access: RW
1975 */
1976MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1);
1977
1978/* reg_cwtpm_tcp_g
1979 * TCP Green Profile.
1980 * Index of the profile within {port, traffic class} to use.
1981 * 0 for disabling both WRED and ECN for this type of traffic.
1982 * Access: RW
1983 */
1984MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2);
1985
1986/* reg_cwtpm_tcp_y
1987 * TCP Yellow Profile.
1988 * Index of the profile within {port, traffic class} to use.
1989 * 0 for disabling both WRED and ECN for this type of traffic.
1990 * Access: RW
1991 */
1992MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2);
1993
1994/* reg_cwtpm_tcp_r
1995 * TCP Red Profile.
1996 * Index of the profile within {port, traffic class} to use.
1997 * 0 for disabling both WRED and ECN for this type of traffic.
1998 * Access: RW
1999 */
2000MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2);
2001
2002/* reg_cwtpm_ntcp_g
2003 * Non-TCP Green Profile.
2004 * Index of the profile within {port, traffic class} to use.
2005 * 0 for disabling both WRED and ECN for this type of traffic.
2006 * Access: RW
2007 */
2008MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2);
2009
2010/* reg_cwtpm_ntcp_y
2011 * Non-TCP Yellow Profile.
2012 * Index of the profile within {port, traffic class} to use.
2013 * 0 for disabling both WRED and ECN for this type of traffic.
2014 * Access: RW
2015 */
2016MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2);
2017
2018/* reg_cwtpm_ntcp_r
2019 * Non-TCP Red Profile.
2020 * Index of the profile within {port, traffic class} to use.
2021 * 0 for disabling both WRED and ECN for this type of traffic.
2022 * Access: RW
2023 */
2024MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2);
2025
2026#define MLXSW_REG_CWTPM_RESET_PROFILE 0
2027
2028static inline void mlxsw_reg_cwtpm_pack(char *payload, u8 local_port,
2029 u8 traffic_class, u8 profile,
2030 bool wred, bool ecn)
2031{
2032 MLXSW_REG_ZERO(cwtpm, payload);
2033 mlxsw_reg_cwtpm_local_port_set(payload, local_port);
2034 mlxsw_reg_cwtpm_traffic_class_set(payload, traffic_class);
2035 mlxsw_reg_cwtpm_ew_set(payload, wred);
2036 mlxsw_reg_cwtpm_ee_set(payload, ecn);
2037 mlxsw_reg_cwtpm_tcp_g_set(payload, profile);
2038 mlxsw_reg_cwtpm_tcp_y_set(payload, profile);
2039 mlxsw_reg_cwtpm_tcp_r_set(payload, profile);
2040 mlxsw_reg_cwtpm_ntcp_g_set(payload, profile);
2041 mlxsw_reg_cwtpm_ntcp_y_set(payload, profile);
2042 mlxsw_reg_cwtpm_ntcp_r_set(payload, profile);
2043}
2044
2045/* PGCR - Policy-Engine General Configuration Register
2046 * ---------------------------------------------------
2047 * This register configures general Policy-Engine settings.
2048 */
2049#define MLXSW_REG_PGCR_ID 0x3001
2050#define MLXSW_REG_PGCR_LEN 0x20
2051
2052MLXSW_REG_DEFINE(pgcr, MLXSW_REG_PGCR_ID, MLXSW_REG_PGCR_LEN);
2053
2054/* reg_pgcr_default_action_pointer_base
2055 * Default action pointer base. Each region has a default action pointer
2056 * which is equal to default_action_pointer_base + region_id.
2057 * Access: RW
2058 */
2059MLXSW_ITEM32(reg, pgcr, default_action_pointer_base, 0x1C, 0, 24);
2060
2061static inline void mlxsw_reg_pgcr_pack(char *payload, u32 pointer_base)
2062{
2063 MLXSW_REG_ZERO(pgcr, payload);
2064 mlxsw_reg_pgcr_default_action_pointer_base_set(payload, pointer_base);
2065}
2066
2067/* PPBT - Policy-Engine Port Binding Table
2068 * ---------------------------------------
2069 * This register is used for configuration of the Port Binding Table.
2070 */
2071#define MLXSW_REG_PPBT_ID 0x3002
2072#define MLXSW_REG_PPBT_LEN 0x14
2073
2074MLXSW_REG_DEFINE(ppbt, MLXSW_REG_PPBT_ID, MLXSW_REG_PPBT_LEN);
2075
2076enum mlxsw_reg_pxbt_e {
2077 MLXSW_REG_PXBT_E_IACL,
2078 MLXSW_REG_PXBT_E_EACL,
2079};
2080
2081/* reg_ppbt_e
2082 * Access: Index
2083 */
2084MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1);
2085
2086enum mlxsw_reg_pxbt_op {
2087 MLXSW_REG_PXBT_OP_BIND,
2088 MLXSW_REG_PXBT_OP_UNBIND,
2089};
2090
2091/* reg_ppbt_op
2092 * Access: RW
2093 */
2094MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3);
2095
2096/* reg_ppbt_local_port
2097 * Local port. Not including CPU port.
2098 * Access: Index
2099 */
2100MLXSW_ITEM32(reg, ppbt, local_port, 0x00, 16, 8);
2101
2102/* reg_ppbt_g
2103 * group - When set, the binding is of an ACL group. When cleared,
2104 * the binding is of an ACL.
2105 * Must be set to 1 for Spectrum.
2106 * Access: RW
2107 */
2108MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1);
2109
2110/* reg_ppbt_acl_info
2111 * ACL/ACL group identifier. If the g bit is set, this field should hold
2112 * the acl_group_id, else it should hold the acl_id.
2113 * Access: RW
2114 */
2115MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16);
2116
2117static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e,
2118 enum mlxsw_reg_pxbt_op op,
2119 u8 local_port, u16 acl_info)
2120{
2121 MLXSW_REG_ZERO(ppbt, payload);
2122 mlxsw_reg_ppbt_e_set(payload, e);
2123 mlxsw_reg_ppbt_op_set(payload, op);
2124 mlxsw_reg_ppbt_local_port_set(payload, local_port);
2125 mlxsw_reg_ppbt_g_set(payload, true);
2126 mlxsw_reg_ppbt_acl_info_set(payload, acl_info);
2127}
2128
2129/* PACL - Policy-Engine ACL Register
2130 * ---------------------------------
2131 * This register is used for configuration of the ACL.
2132 */
2133#define MLXSW_REG_PACL_ID 0x3004
2134#define MLXSW_REG_PACL_LEN 0x70
2135
2136MLXSW_REG_DEFINE(pacl, MLXSW_REG_PACL_ID, MLXSW_REG_PACL_LEN);
2137
2138/* reg_pacl_v
2139 * Valid. Setting the v bit makes the ACL valid. It should not be cleared
2140 * while the ACL is bounded to either a port, VLAN or ACL rule.
2141 * Access: RW
2142 */
2143MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1);
2144
2145/* reg_pacl_acl_id
2146 * An identifier representing the ACL (managed by software)
2147 * Range 0 .. cap_max_acl_regions - 1
2148 * Access: Index
2149 */
2150MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16);
2151
2152#define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 16
2153
2154/* reg_pacl_tcam_region_info
2155 * Opaque object that represents a TCAM region.
2156 * Obtained through PTAR register.
2157 * Access: RW
2158 */
2159MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30,
2160 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2161
2162static inline void mlxsw_reg_pacl_pack(char *payload, u16 acl_id,
2163 bool valid, const char *tcam_region_info)
2164{
2165 MLXSW_REG_ZERO(pacl, payload);
2166 mlxsw_reg_pacl_acl_id_set(payload, acl_id);
2167 mlxsw_reg_pacl_v_set(payload, valid);
2168 mlxsw_reg_pacl_tcam_region_info_memcpy_to(payload, tcam_region_info);
2169}
2170
2171/* PAGT - Policy-Engine ACL Group Table
2172 * ------------------------------------
2173 * This register is used for configuration of the ACL Group Table.
2174 */
2175#define MLXSW_REG_PAGT_ID 0x3005
2176#define MLXSW_REG_PAGT_BASE_LEN 0x30
2177#define MLXSW_REG_PAGT_ACL_LEN 4
2178#define MLXSW_REG_PAGT_ACL_MAX_NUM 16
2179#define MLXSW_REG_PAGT_LEN (MLXSW_REG_PAGT_BASE_LEN + \
2180 MLXSW_REG_PAGT_ACL_MAX_NUM * MLXSW_REG_PAGT_ACL_LEN)
2181
2182MLXSW_REG_DEFINE(pagt, MLXSW_REG_PAGT_ID, MLXSW_REG_PAGT_LEN);
2183
2184/* reg_pagt_size
2185 * Number of ACLs in the group.
2186 * Size 0 invalidates a group.
2187 * Range 0 .. cap_max_acl_group_size (hard coded to 16 for now)
2188 * Total number of ACLs in all groups must be lower or equal
2189 * to cap_max_acl_tot_groups
2190 * Note: a group which is binded must not be invalidated
2191 * Access: Index
2192 */
2193MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8);
2194
2195/* reg_pagt_acl_group_id
2196 * An identifier (numbered from 0..cap_max_acl_groups-1) representing
2197 * the ACL Group identifier (managed by software).
2198 * Access: Index
2199 */
2200MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16);
2201
2202/* reg_pagt_multi
2203 * Multi-ACL
2204 * 0 - This ACL is the last ACL in the multi-ACL
2205 * 1 - This ACL is part of a multi-ACL
2206 * Access: RW
2207 */
2208MLXSW_ITEM32_INDEXED(reg, pagt, multi, 0x30, 31, 1, 0x04, 0x00, false);
2209
2210/* reg_pagt_acl_id
2211 * ACL identifier
2212 * Access: RW
2213 */
2214MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false);
2215
2216static inline void mlxsw_reg_pagt_pack(char *payload, u16 acl_group_id)
2217{
2218 MLXSW_REG_ZERO(pagt, payload);
2219 mlxsw_reg_pagt_acl_group_id_set(payload, acl_group_id);
2220}
2221
2222static inline void mlxsw_reg_pagt_acl_id_pack(char *payload, int index,
2223 u16 acl_id, bool multi)
2224{
2225 u8 size = mlxsw_reg_pagt_size_get(payload);
2226
2227 if (index >= size)
2228 mlxsw_reg_pagt_size_set(payload, index + 1);
2229 mlxsw_reg_pagt_multi_set(payload, index, multi);
2230 mlxsw_reg_pagt_acl_id_set(payload, index, acl_id);
2231}
2232
2233/* PTAR - Policy-Engine TCAM Allocation Register
2234 * ---------------------------------------------
2235 * This register is used for allocation of regions in the TCAM.
2236 * Note: Query method is not supported on this register.
2237 */
2238#define MLXSW_REG_PTAR_ID 0x3006
2239#define MLXSW_REG_PTAR_BASE_LEN 0x20
2240#define MLXSW_REG_PTAR_KEY_ID_LEN 1
2241#define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 16
2242#define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \
2243 MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN)
2244
2245MLXSW_REG_DEFINE(ptar, MLXSW_REG_PTAR_ID, MLXSW_REG_PTAR_LEN);
2246
2247enum mlxsw_reg_ptar_op {
2248 /* allocate a TCAM region */
2249 MLXSW_REG_PTAR_OP_ALLOC,
2250 /* resize a TCAM region */
2251 MLXSW_REG_PTAR_OP_RESIZE,
2252 /* deallocate TCAM region */
2253 MLXSW_REG_PTAR_OP_FREE,
2254 /* test allocation */
2255 MLXSW_REG_PTAR_OP_TEST,
2256};
2257
2258/* reg_ptar_op
2259 * Access: OP
2260 */
2261MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4);
2262
2263/* reg_ptar_action_set_type
2264 * Type of action set to be used on this region.
2265 * For Spectrum and Spectrum-2, this is always type 2 - "flexible"
2266 * Access: WO
2267 */
2268MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8);
2269
2270enum mlxsw_reg_ptar_key_type {
2271 MLXSW_REG_PTAR_KEY_TYPE_FLEX = 0x50, /* Spetrum */
2272 MLXSW_REG_PTAR_KEY_TYPE_FLEX2 = 0x51, /* Spectrum-2 */
2273};
2274
2275/* reg_ptar_key_type
2276 * TCAM key type for the region.
2277 * Access: WO
2278 */
2279MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8);
2280
2281/* reg_ptar_region_size
2282 * TCAM region size. When allocating/resizing this is the requested size,
2283 * the response is the actual size. Note that actual size may be
2284 * larger than requested.
2285 * Allowed range 1 .. cap_max_rules-1
2286 * Reserved during op deallocate.
2287 * Access: WO
2288 */
2289MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16);
2290
2291/* reg_ptar_region_id
2292 * Region identifier
2293 * Range 0 .. cap_max_regions-1
2294 * Access: Index
2295 */
2296MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16);
2297
2298/* reg_ptar_tcam_region_info
2299 * Opaque object that represents the TCAM region.
2300 * Returned when allocating a region.
2301 * Provided by software for ACL generation and region deallocation and resize.
2302 * Access: RW
2303 */
2304MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10,
2305 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2306
2307/* reg_ptar_flexible_key_id
2308 * Identifier of the Flexible Key.
2309 * Only valid if key_type == "FLEX_KEY"
2310 * The key size will be rounded up to one of the following values:
2311 * 9B, 18B, 36B, 54B.
2312 * This field is reserved for in resize operation.
2313 * Access: WO
2314 */
2315MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8,
2316 MLXSW_REG_PTAR_KEY_ID_LEN, 0x00, false);
2317
2318static inline void mlxsw_reg_ptar_pack(char *payload, enum mlxsw_reg_ptar_op op,
2319 enum mlxsw_reg_ptar_key_type key_type,
2320 u16 region_size, u16 region_id,
2321 const char *tcam_region_info)
2322{
2323 MLXSW_REG_ZERO(ptar, payload);
2324 mlxsw_reg_ptar_op_set(payload, op);
2325 mlxsw_reg_ptar_action_set_type_set(payload, 2); /* "flexible" */
2326 mlxsw_reg_ptar_key_type_set(payload, key_type);
2327 mlxsw_reg_ptar_region_size_set(payload, region_size);
2328 mlxsw_reg_ptar_region_id_set(payload, region_id);
2329 mlxsw_reg_ptar_tcam_region_info_memcpy_to(payload, tcam_region_info);
2330}
2331
2332static inline void mlxsw_reg_ptar_key_id_pack(char *payload, int index,
2333 u16 key_id)
2334{
2335 mlxsw_reg_ptar_flexible_key_id_set(payload, index, key_id);
2336}
2337
2338static inline void mlxsw_reg_ptar_unpack(char *payload, char *tcam_region_info)
2339{
2340 mlxsw_reg_ptar_tcam_region_info_memcpy_from(payload, tcam_region_info);
2341}
2342
2343/* PPBS - Policy-Engine Policy Based Switching Register
2344 * ----------------------------------------------------
2345 * This register retrieves and sets Policy Based Switching Table entries.
2346 */
2347#define MLXSW_REG_PPBS_ID 0x300C
2348#define MLXSW_REG_PPBS_LEN 0x14
2349
2350MLXSW_REG_DEFINE(ppbs, MLXSW_REG_PPBS_ID, MLXSW_REG_PPBS_LEN);
2351
2352/* reg_ppbs_pbs_ptr
2353 * Index into the PBS table.
2354 * For Spectrum, the index points to the KVD Linear.
2355 * Access: Index
2356 */
2357MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24);
2358
2359/* reg_ppbs_system_port
2360 * Unique port identifier for the final destination of the packet.
2361 * Access: RW
2362 */
2363MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16);
2364
2365static inline void mlxsw_reg_ppbs_pack(char *payload, u32 pbs_ptr,
2366 u16 system_port)
2367{
2368 MLXSW_REG_ZERO(ppbs, payload);
2369 mlxsw_reg_ppbs_pbs_ptr_set(payload, pbs_ptr);
2370 mlxsw_reg_ppbs_system_port_set(payload, system_port);
2371}
2372
2373/* PRCR - Policy-Engine Rules Copy Register
2374 * ----------------------------------------
2375 * This register is used for accessing rules within a TCAM region.
2376 */
2377#define MLXSW_REG_PRCR_ID 0x300D
2378#define MLXSW_REG_PRCR_LEN 0x40
2379
2380MLXSW_REG_DEFINE(prcr, MLXSW_REG_PRCR_ID, MLXSW_REG_PRCR_LEN);
2381
2382enum mlxsw_reg_prcr_op {
2383 /* Move rules. Moves the rules from "tcam_region_info" starting
2384 * at offset "offset" to "dest_tcam_region_info"
2385 * at offset "dest_offset."
2386 */
2387 MLXSW_REG_PRCR_OP_MOVE,
2388 /* Copy rules. Copies the rules from "tcam_region_info" starting
2389 * at offset "offset" to "dest_tcam_region_info"
2390 * at offset "dest_offset."
2391 */
2392 MLXSW_REG_PRCR_OP_COPY,
2393};
2394
2395/* reg_prcr_op
2396 * Access: OP
2397 */
2398MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4);
2399
2400/* reg_prcr_offset
2401 * Offset within the source region to copy/move from.
2402 * Access: Index
2403 */
2404MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16);
2405
2406/* reg_prcr_size
2407 * The number of rules to copy/move.
2408 * Access: WO
2409 */
2410MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16);
2411
2412/* reg_prcr_tcam_region_info
2413 * Opaque object that represents the source TCAM region.
2414 * Access: Index
2415 */
2416MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10,
2417 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2418
2419/* reg_prcr_dest_offset
2420 * Offset within the source region to copy/move to.
2421 * Access: Index
2422 */
2423MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16);
2424
2425/* reg_prcr_dest_tcam_region_info
2426 * Opaque object that represents the destination TCAM region.
2427 * Access: Index
2428 */
2429MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30,
2430 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2431
2432static inline void mlxsw_reg_prcr_pack(char *payload, enum mlxsw_reg_prcr_op op,
2433 const char *src_tcam_region_info,
2434 u16 src_offset,
2435 const char *dest_tcam_region_info,
2436 u16 dest_offset, u16 size)
2437{
2438 MLXSW_REG_ZERO(prcr, payload);
2439 mlxsw_reg_prcr_op_set(payload, op);
2440 mlxsw_reg_prcr_offset_set(payload, src_offset);
2441 mlxsw_reg_prcr_size_set(payload, size);
2442 mlxsw_reg_prcr_tcam_region_info_memcpy_to(payload,
2443 src_tcam_region_info);
2444 mlxsw_reg_prcr_dest_offset_set(payload, dest_offset);
2445 mlxsw_reg_prcr_dest_tcam_region_info_memcpy_to(payload,
2446 dest_tcam_region_info);
2447}
2448
2449/* PEFA - Policy-Engine Extended Flexible Action Register
2450 * ------------------------------------------------------
2451 * This register is used for accessing an extended flexible action entry
2452 * in the central KVD Linear Database.
2453 */
2454#define MLXSW_REG_PEFA_ID 0x300F
2455#define MLXSW_REG_PEFA_LEN 0xB0
2456
2457MLXSW_REG_DEFINE(pefa, MLXSW_REG_PEFA_ID, MLXSW_REG_PEFA_LEN);
2458
2459/* reg_pefa_index
2460 * Index in the KVD Linear Centralized Database.
2461 * Access: Index
2462 */
2463MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24);
2464
2465/* reg_pefa_a
2466 * Index in the KVD Linear Centralized Database.
2467 * Activity
2468 * For a new entry: set if ca=0, clear if ca=1
2469 * Set if a packet lookup has hit on the specific entry
2470 * Access: RO
2471 */
2472MLXSW_ITEM32(reg, pefa, a, 0x04, 29, 1);
2473
2474/* reg_pefa_ca
2475 * Clear activity
2476 * When write: activity is according to this field
2477 * When read: after reading the activity is cleared according to ca
2478 * Access: OP
2479 */
2480MLXSW_ITEM32(reg, pefa, ca, 0x04, 24, 1);
2481
2482#define MLXSW_REG_FLEX_ACTION_SET_LEN 0xA8
2483
2484/* reg_pefa_flex_action_set
2485 * Action-set to perform when rule is matched.
2486 * Must be zero padded if action set is shorter.
2487 * Access: RW
2488 */
2489MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN);
2490
2491static inline void mlxsw_reg_pefa_pack(char *payload, u32 index, bool ca,
2492 const char *flex_action_set)
2493{
2494 MLXSW_REG_ZERO(pefa, payload);
2495 mlxsw_reg_pefa_index_set(payload, index);
2496 mlxsw_reg_pefa_ca_set(payload, ca);
2497 if (flex_action_set)
2498 mlxsw_reg_pefa_flex_action_set_memcpy_to(payload,
2499 flex_action_set);
2500}
2501
2502static inline void mlxsw_reg_pefa_unpack(char *payload, bool *p_a)
2503{
2504 *p_a = mlxsw_reg_pefa_a_get(payload);
2505}
2506
2507/* PEMRBT - Policy-Engine Multicast Router Binding Table Register
2508 * --------------------------------------------------------------
2509 * This register is used for binding Multicast router to an ACL group
2510 * that serves the MC router.
2511 * This register is not supported by SwitchX/-2 and Spectrum.
2512 */
2513#define MLXSW_REG_PEMRBT_ID 0x3014
2514#define MLXSW_REG_PEMRBT_LEN 0x14
2515
2516MLXSW_REG_DEFINE(pemrbt, MLXSW_REG_PEMRBT_ID, MLXSW_REG_PEMRBT_LEN);
2517
2518enum mlxsw_reg_pemrbt_protocol {
2519 MLXSW_REG_PEMRBT_PROTO_IPV4,
2520 MLXSW_REG_PEMRBT_PROTO_IPV6,
2521};
2522
2523/* reg_pemrbt_protocol
2524 * Access: Index
2525 */
2526MLXSW_ITEM32(reg, pemrbt, protocol, 0x00, 0, 1);
2527
2528/* reg_pemrbt_group_id
2529 * ACL group identifier.
2530 * Range 0..cap_max_acl_groups-1
2531 * Access: RW
2532 */
2533MLXSW_ITEM32(reg, pemrbt, group_id, 0x10, 0, 16);
2534
2535static inline void
2536mlxsw_reg_pemrbt_pack(char *payload, enum mlxsw_reg_pemrbt_protocol protocol,
2537 u16 group_id)
2538{
2539 MLXSW_REG_ZERO(pemrbt, payload);
2540 mlxsw_reg_pemrbt_protocol_set(payload, protocol);
2541 mlxsw_reg_pemrbt_group_id_set(payload, group_id);
2542}
2543
2544/* PTCE-V2 - Policy-Engine TCAM Entry Register Version 2
2545 * -----------------------------------------------------
2546 * This register is used for accessing rules within a TCAM region.
2547 * It is a new version of PTCE in order to support wider key,
2548 * mask and action within a TCAM region. This register is not supported
2549 * by SwitchX and SwitchX-2.
2550 */
2551#define MLXSW_REG_PTCE2_ID 0x3017
2552#define MLXSW_REG_PTCE2_LEN 0x1D8
2553
2554MLXSW_REG_DEFINE(ptce2, MLXSW_REG_PTCE2_ID, MLXSW_REG_PTCE2_LEN);
2555
2556/* reg_ptce2_v
2557 * Valid.
2558 * Access: RW
2559 */
2560MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1);
2561
2562/* reg_ptce2_a
2563 * Activity. Set if a packet lookup has hit on the specific entry.
2564 * To clear the "a" bit, use "clear activity" op or "clear on read" op.
2565 * Access: RO
2566 */
2567MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1);
2568
2569enum mlxsw_reg_ptce2_op {
2570 /* Read operation. */
2571 MLXSW_REG_PTCE2_OP_QUERY_READ = 0,
2572 /* clear on read operation. Used to read entry
2573 * and clear Activity bit.
2574 */
2575 MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ = 1,
2576 /* Write operation. Used to write a new entry to the table.
2577 * All R/W fields are relevant for new entry. Activity bit is set
2578 * for new entries - Note write with v = 0 will delete the entry.
2579 */
2580 MLXSW_REG_PTCE2_OP_WRITE_WRITE = 0,
2581 /* Update action. Only action set will be updated. */
2582 MLXSW_REG_PTCE2_OP_WRITE_UPDATE = 1,
2583 /* Clear activity. A bit is cleared for the entry. */
2584 MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY = 2,
2585};
2586
2587/* reg_ptce2_op
2588 * Access: OP
2589 */
2590MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3);
2591
2592/* reg_ptce2_offset
2593 * Access: Index
2594 */
2595MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16);
2596
2597/* reg_ptce2_priority
2598 * Priority of the rule, higher values win. The range is 1..cap_kvd_size-1.
2599 * Note: priority does not have to be unique per rule.
2600 * Within a region, higher priority should have lower offset (no limitation
2601 * between regions in a multi-region).
2602 * Access: RW
2603 */
2604MLXSW_ITEM32(reg, ptce2, priority, 0x04, 0, 24);
2605
2606/* reg_ptce2_tcam_region_info
2607 * Opaque object that represents the TCAM region.
2608 * Access: Index
2609 */
2610MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10,
2611 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2612
2613#define MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN 96
2614
2615/* reg_ptce2_flex_key_blocks
2616 * ACL Key.
2617 * Access: RW
2618 */
2619MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20,
2620 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
2621
2622/* reg_ptce2_mask
2623 * mask- in the same size as key. A bit that is set directs the TCAM
2624 * to compare the corresponding bit in key. A bit that is clear directs
2625 * the TCAM to ignore the corresponding bit in key.
2626 * Access: RW
2627 */
2628MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80,
2629 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
2630
2631/* reg_ptce2_flex_action_set
2632 * ACL action set.
2633 * Access: RW
2634 */
2635MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0,
2636 MLXSW_REG_FLEX_ACTION_SET_LEN);
2637
2638static inline void mlxsw_reg_ptce2_pack(char *payload, bool valid,
2639 enum mlxsw_reg_ptce2_op op,
2640 const char *tcam_region_info,
2641 u16 offset, u32 priority)
2642{
2643 MLXSW_REG_ZERO(ptce2, payload);
2644 mlxsw_reg_ptce2_v_set(payload, valid);
2645 mlxsw_reg_ptce2_op_set(payload, op);
2646 mlxsw_reg_ptce2_offset_set(payload, offset);
2647 mlxsw_reg_ptce2_priority_set(payload, priority);
2648 mlxsw_reg_ptce2_tcam_region_info_memcpy_to(payload, tcam_region_info);
2649}
2650
2651/* PERPT - Policy-Engine ERP Table Register
2652 * ----------------------------------------
2653 * This register adds and removes eRPs from the eRP table.
2654 */
2655#define MLXSW_REG_PERPT_ID 0x3021
2656#define MLXSW_REG_PERPT_LEN 0x80
2657
2658MLXSW_REG_DEFINE(perpt, MLXSW_REG_PERPT_ID, MLXSW_REG_PERPT_LEN);
2659
2660/* reg_perpt_erpt_bank
2661 * eRP table bank.
2662 * Range 0 .. cap_max_erp_table_banks - 1
2663 * Access: Index
2664 */
2665MLXSW_ITEM32(reg, perpt, erpt_bank, 0x00, 16, 4);
2666
2667/* reg_perpt_erpt_index
2668 * Index to eRP table within the eRP bank.
2669 * Range is 0 .. cap_max_erp_table_bank_size - 1
2670 * Access: Index
2671 */
2672MLXSW_ITEM32(reg, perpt, erpt_index, 0x00, 0, 8);
2673
2674enum mlxsw_reg_perpt_key_size {
2675 MLXSW_REG_PERPT_KEY_SIZE_2KB,
2676 MLXSW_REG_PERPT_KEY_SIZE_4KB,
2677 MLXSW_REG_PERPT_KEY_SIZE_8KB,
2678 MLXSW_REG_PERPT_KEY_SIZE_12KB,
2679};
2680
2681/* reg_perpt_key_size
2682 * Access: OP
2683 */
2684MLXSW_ITEM32(reg, perpt, key_size, 0x04, 0, 4);
2685
2686/* reg_perpt_bf_bypass
2687 * 0 - The eRP is used only if bloom filter state is set for the given
2688 * rule.
2689 * 1 - The eRP is used regardless of bloom filter state.
2690 * The bypass is an OR condition of region_id or eRP. See PERCR.bf_bypass
2691 * Access: RW
2692 */
2693MLXSW_ITEM32(reg, perpt, bf_bypass, 0x08, 8, 1);
2694
2695/* reg_perpt_erp_id
2696 * eRP ID for use by the rules.
2697 * Access: RW
2698 */
2699MLXSW_ITEM32(reg, perpt, erp_id, 0x08, 0, 4);
2700
2701/* reg_perpt_erpt_base_bank
2702 * Base eRP table bank, points to head of erp_vector
2703 * Range is 0 .. cap_max_erp_table_banks - 1
2704 * Access: OP
2705 */
2706MLXSW_ITEM32(reg, perpt, erpt_base_bank, 0x0C, 16, 4);
2707
2708/* reg_perpt_erpt_base_index
2709 * Base index to eRP table within the eRP bank
2710 * Range is 0 .. cap_max_erp_table_bank_size - 1
2711 * Access: OP
2712 */
2713MLXSW_ITEM32(reg, perpt, erpt_base_index, 0x0C, 0, 8);
2714
2715/* reg_perpt_erp_index_in_vector
2716 * eRP index in the vector.
2717 * Access: OP
2718 */
2719MLXSW_ITEM32(reg, perpt, erp_index_in_vector, 0x10, 0, 4);
2720
2721/* reg_perpt_erp_vector
2722 * eRP vector.
2723 * Access: OP
2724 */
2725MLXSW_ITEM_BIT_ARRAY(reg, perpt, erp_vector, 0x14, 4, 1);
2726
2727/* reg_perpt_mask
2728 * Mask
2729 * 0 - A-TCAM will ignore the bit in key
2730 * 1 - A-TCAM will compare the bit in key
2731 * Access: RW
2732 */
2733MLXSW_ITEM_BUF(reg, perpt, mask, 0x20, MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
2734
2735static inline void mlxsw_reg_perpt_erp_vector_pack(char *payload,
2736 unsigned long *erp_vector,
2737 unsigned long size)
2738{
2739 unsigned long bit;
2740
2741 for_each_set_bit(bit, erp_vector, size)
2742 mlxsw_reg_perpt_erp_vector_set(payload, bit, true);
2743}
2744
2745static inline void
2746mlxsw_reg_perpt_pack(char *payload, u8 erpt_bank, u8 erpt_index,
2747 enum mlxsw_reg_perpt_key_size key_size, u8 erp_id,
2748 u8 erpt_base_bank, u8 erpt_base_index, u8 erp_index,
2749 char *mask)
2750{
2751 MLXSW_REG_ZERO(perpt, payload);
2752 mlxsw_reg_perpt_erpt_bank_set(payload, erpt_bank);
2753 mlxsw_reg_perpt_erpt_index_set(payload, erpt_index);
2754 mlxsw_reg_perpt_key_size_set(payload, key_size);
2755 mlxsw_reg_perpt_bf_bypass_set(payload, false);
2756 mlxsw_reg_perpt_erp_id_set(payload, erp_id);
2757 mlxsw_reg_perpt_erpt_base_bank_set(payload, erpt_base_bank);
2758 mlxsw_reg_perpt_erpt_base_index_set(payload, erpt_base_index);
2759 mlxsw_reg_perpt_erp_index_in_vector_set(payload, erp_index);
2760 mlxsw_reg_perpt_mask_memcpy_to(payload, mask);
2761}
2762
2763/* PERAR - Policy-Engine Region Association Register
2764 * -------------------------------------------------
2765 * This register associates a hw region for region_id's. Changing on the fly
2766 * is supported by the device.
2767 */
2768#define MLXSW_REG_PERAR_ID 0x3026
2769#define MLXSW_REG_PERAR_LEN 0x08
2770
2771MLXSW_REG_DEFINE(perar, MLXSW_REG_PERAR_ID, MLXSW_REG_PERAR_LEN);
2772
2773/* reg_perar_region_id
2774 * Region identifier
2775 * Range 0 .. cap_max_regions-1
2776 * Access: Index
2777 */
2778MLXSW_ITEM32(reg, perar, region_id, 0x00, 0, 16);
2779
2780static inline unsigned int
2781mlxsw_reg_perar_hw_regions_needed(unsigned int block_num)
2782{
2783 return DIV_ROUND_UP(block_num, 4);
2784}
2785
2786/* reg_perar_hw_region
2787 * HW Region
2788 * Range 0 .. cap_max_regions-1
2789 * Default: hw_region = region_id
2790 * For a 8 key block region, 2 consecutive regions are used
2791 * For a 12 key block region, 3 consecutive regions are used
2792 * Access: RW
2793 */
2794MLXSW_ITEM32(reg, perar, hw_region, 0x04, 0, 16);
2795
2796static inline void mlxsw_reg_perar_pack(char *payload, u16 region_id,
2797 u16 hw_region)
2798{
2799 MLXSW_REG_ZERO(perar, payload);
2800 mlxsw_reg_perar_region_id_set(payload, region_id);
2801 mlxsw_reg_perar_hw_region_set(payload, hw_region);
2802}
2803
2804/* PTCE-V3 - Policy-Engine TCAM Entry Register Version 3
2805 * -----------------------------------------------------
2806 * This register is a new version of PTCE-V2 in order to support the
2807 * A-TCAM. This register is not supported by SwitchX/-2 and Spectrum.
2808 */
2809#define MLXSW_REG_PTCE3_ID 0x3027
2810#define MLXSW_REG_PTCE3_LEN 0xF0
2811
2812MLXSW_REG_DEFINE(ptce3, MLXSW_REG_PTCE3_ID, MLXSW_REG_PTCE3_LEN);
2813
2814/* reg_ptce3_v
2815 * Valid.
2816 * Access: RW
2817 */
2818MLXSW_ITEM32(reg, ptce3, v, 0x00, 31, 1);
2819
2820enum mlxsw_reg_ptce3_op {
2821 /* Write operation. Used to write a new entry to the table.
2822 * All R/W fields are relevant for new entry. Activity bit is set
2823 * for new entries. Write with v = 0 will delete the entry. Must
2824 * not be used if an entry exists.
2825 */
2826 MLXSW_REG_PTCE3_OP_WRITE_WRITE = 0,
2827 /* Update operation */
2828 MLXSW_REG_PTCE3_OP_WRITE_UPDATE = 1,
2829 /* Read operation */
2830 MLXSW_REG_PTCE3_OP_QUERY_READ = 0,
2831};
2832
2833/* reg_ptce3_op
2834 * Access: OP
2835 */
2836MLXSW_ITEM32(reg, ptce3, op, 0x00, 20, 3);
2837
2838/* reg_ptce3_priority
2839 * Priority of the rule. Higher values win.
2840 * For Spectrum-2 range is 1..cap_kvd_size - 1
2841 * Note: Priority does not have to be unique per rule.
2842 * Access: RW
2843 */
2844MLXSW_ITEM32(reg, ptce3, priority, 0x04, 0, 24);
2845
2846/* reg_ptce3_tcam_region_info
2847 * Opaque object that represents the TCAM region.
2848 * Access: Index
2849 */
2850MLXSW_ITEM_BUF(reg, ptce3, tcam_region_info, 0x10,
2851 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2852
2853/* reg_ptce3_flex2_key_blocks
2854 * ACL key. The key must be masked according to eRP (if exists) or
2855 * according to master mask.
2856 * Access: Index
2857 */
2858MLXSW_ITEM_BUF(reg, ptce3, flex2_key_blocks, 0x20,
2859 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
2860
2861/* reg_ptce3_erp_id
2862 * eRP ID.
2863 * Access: Index
2864 */
2865MLXSW_ITEM32(reg, ptce3, erp_id, 0x80, 0, 4);
2866
2867/* reg_ptce3_delta_start
2868 * Start point of delta_value and delta_mask, in bits. Must not exceed
2869 * num_key_blocks * 36 - 8. Reserved when delta_mask = 0.
2870 * Access: Index
2871 */
2872MLXSW_ITEM32(reg, ptce3, delta_start, 0x84, 0, 10);
2873
2874/* reg_ptce3_delta_mask
2875 * Delta mask.
2876 * 0 - Ignore relevant bit in delta_value
2877 * 1 - Compare relevant bit in delta_value
2878 * Delta mask must not be set for reserved fields in the key blocks.
2879 * Note: No delta when no eRPs. Thus, for regions with
2880 * PERERP.erpt_pointer_valid = 0 the delta mask must be 0.
2881 * Access: Index
2882 */
2883MLXSW_ITEM32(reg, ptce3, delta_mask, 0x88, 16, 8);
2884
2885/* reg_ptce3_delta_value
2886 * Delta value.
2887 * Bits which are masked by delta_mask must be 0.
2888 * Access: Index
2889 */
2890MLXSW_ITEM32(reg, ptce3, delta_value, 0x88, 0, 8);
2891
2892/* reg_ptce3_prune_vector
2893 * Pruning vector relative to the PERPT.erp_id.
2894 * Used for reducing lookups.
2895 * 0 - NEED: Do a lookup using the eRP.
2896 * 1 - PRUNE: Do not perform a lookup using the eRP.
2897 * Maybe be modified by PEAPBL and PEAPBM.
2898 * Note: In Spectrum-2, a region of 8 key blocks must be set to either
2899 * all 1's or all 0's.
2900 * Access: RW
2901 */
2902MLXSW_ITEM_BIT_ARRAY(reg, ptce3, prune_vector, 0x90, 4, 1);
2903
2904/* reg_ptce3_prune_ctcam
2905 * Pruning on C-TCAM. Used for reducing lookups.
2906 * 0 - NEED: Do a lookup in the C-TCAM.
2907 * 1 - PRUNE: Do not perform a lookup in the C-TCAM.
2908 * Access: RW
2909 */
2910MLXSW_ITEM32(reg, ptce3, prune_ctcam, 0x94, 31, 1);
2911
2912/* reg_ptce3_large_exists
2913 * Large entry key ID exists.
2914 * Within the region:
2915 * 0 - SINGLE: The large_entry_key_id is not currently in use.
2916 * For rule insert: The MSB of the key (blocks 6..11) will be added.
2917 * For rule delete: The MSB of the key will be removed.
2918 * 1 - NON_SINGLE: The large_entry_key_id is currently in use.
2919 * For rule insert: The MSB of the key (blocks 6..11) will not be added.
2920 * For rule delete: The MSB of the key will not be removed.
2921 * Access: WO
2922 */
2923MLXSW_ITEM32(reg, ptce3, large_exists, 0x98, 31, 1);
2924
2925/* reg_ptce3_large_entry_key_id
2926 * Large entry key ID.
2927 * A key for 12 key blocks rules. Reserved when region has less than 12 key
2928 * blocks. Must be different for different keys which have the same common
2929 * 6 key blocks (MSB, blocks 6..11) key within a region.
2930 * Range is 0..cap_max_pe_large_key_id - 1
2931 * Access: RW
2932 */
2933MLXSW_ITEM32(reg, ptce3, large_entry_key_id, 0x98, 0, 24);
2934
2935/* reg_ptce3_action_pointer
2936 * Pointer to action.
2937 * Range is 0..cap_max_kvd_action_sets - 1
2938 * Access: RW
2939 */
2940MLXSW_ITEM32(reg, ptce3, action_pointer, 0xA0, 0, 24);
2941
2942static inline void mlxsw_reg_ptce3_pack(char *payload, bool valid,
2943 enum mlxsw_reg_ptce3_op op,
2944 u32 priority,
2945 const char *tcam_region_info,
2946 const char *key, u8 erp_id,
2947 u16 delta_start, u8 delta_mask,
2948 u8 delta_value, bool large_exists,
2949 u32 lkey_id, u32 action_pointer)
2950{
2951 MLXSW_REG_ZERO(ptce3, payload);
2952 mlxsw_reg_ptce3_v_set(payload, valid);
2953 mlxsw_reg_ptce3_op_set(payload, op);
2954 mlxsw_reg_ptce3_priority_set(payload, priority);
2955 mlxsw_reg_ptce3_tcam_region_info_memcpy_to(payload, tcam_region_info);
2956 mlxsw_reg_ptce3_flex2_key_blocks_memcpy_to(payload, key);
2957 mlxsw_reg_ptce3_erp_id_set(payload, erp_id);
2958 mlxsw_reg_ptce3_delta_start_set(payload, delta_start);
2959 mlxsw_reg_ptce3_delta_mask_set(payload, delta_mask);
2960 mlxsw_reg_ptce3_delta_value_set(payload, delta_value);
2961 mlxsw_reg_ptce3_large_exists_set(payload, large_exists);
2962 mlxsw_reg_ptce3_large_entry_key_id_set(payload, lkey_id);
2963 mlxsw_reg_ptce3_action_pointer_set(payload, action_pointer);
2964}
2965
2966/* PERCR - Policy-Engine Region Configuration Register
2967 * ---------------------------------------------------
2968 * This register configures the region parameters. The region_id must be
2969 * allocated.
2970 */
2971#define MLXSW_REG_PERCR_ID 0x302A
2972#define MLXSW_REG_PERCR_LEN 0x80
2973
2974MLXSW_REG_DEFINE(percr, MLXSW_REG_PERCR_ID, MLXSW_REG_PERCR_LEN);
2975
2976/* reg_percr_region_id
2977 * Region identifier.
2978 * Range 0..cap_max_regions-1
2979 * Access: Index
2980 */
2981MLXSW_ITEM32(reg, percr, region_id, 0x00, 0, 16);
2982
2983/* reg_percr_atcam_ignore_prune
2984 * Ignore prune_vector by other A-TCAM rules. Used e.g., for a new rule.
2985 * Access: RW
2986 */
2987MLXSW_ITEM32(reg, percr, atcam_ignore_prune, 0x04, 25, 1);
2988
2989/* reg_percr_ctcam_ignore_prune
2990 * Ignore prune_ctcam by other A-TCAM rules. Used e.g., for a new rule.
2991 * Access: RW
2992 */
2993MLXSW_ITEM32(reg, percr, ctcam_ignore_prune, 0x04, 24, 1);
2994
2995/* reg_percr_bf_bypass
2996 * Bloom filter bypass.
2997 * 0 - Bloom filter is used (default)
2998 * 1 - Bloom filter is bypassed. The bypass is an OR condition of
2999 * region_id or eRP. See PERPT.bf_bypass
3000 * Access: RW
3001 */
3002MLXSW_ITEM32(reg, percr, bf_bypass, 0x04, 16, 1);
3003
3004/* reg_percr_master_mask
3005 * Master mask. Logical OR mask of all masks of all rules of a region
3006 * (both A-TCAM and C-TCAM). When there are no eRPs
3007 * (erpt_pointer_valid = 0), then this provides the mask.
3008 * Access: RW
3009 */
3010MLXSW_ITEM_BUF(reg, percr, master_mask, 0x20, 96);
3011
3012static inline void mlxsw_reg_percr_pack(char *payload, u16 region_id)
3013{
3014 MLXSW_REG_ZERO(percr, payload);
3015 mlxsw_reg_percr_region_id_set(payload, region_id);
3016 mlxsw_reg_percr_atcam_ignore_prune_set(payload, false);
3017 mlxsw_reg_percr_ctcam_ignore_prune_set(payload, false);
3018 mlxsw_reg_percr_bf_bypass_set(payload, false);
3019}
3020
3021/* PERERP - Policy-Engine Region eRP Register
3022 * ------------------------------------------
3023 * This register configures the region eRP. The region_id must be
3024 * allocated.
3025 */
3026#define MLXSW_REG_PERERP_ID 0x302B
3027#define MLXSW_REG_PERERP_LEN 0x1C
3028
3029MLXSW_REG_DEFINE(pererp, MLXSW_REG_PERERP_ID, MLXSW_REG_PERERP_LEN);
3030
3031/* reg_pererp_region_id
3032 * Region identifier.
3033 * Range 0..cap_max_regions-1
3034 * Access: Index
3035 */
3036MLXSW_ITEM32(reg, pererp, region_id, 0x00, 0, 16);
3037
3038/* reg_pererp_ctcam_le
3039 * C-TCAM lookup enable. Reserved when erpt_pointer_valid = 0.
3040 * Access: RW
3041 */
3042MLXSW_ITEM32(reg, pererp, ctcam_le, 0x04, 28, 1);
3043
3044/* reg_pererp_erpt_pointer_valid
3045 * erpt_pointer is valid.
3046 * Access: RW
3047 */
3048MLXSW_ITEM32(reg, pererp, erpt_pointer_valid, 0x10, 31, 1);
3049
3050/* reg_pererp_erpt_bank_pointer
3051 * Pointer to eRP table bank. May be modified at any time.
3052 * Range 0..cap_max_erp_table_banks-1
3053 * Reserved when erpt_pointer_valid = 0
3054 */
3055MLXSW_ITEM32(reg, pererp, erpt_bank_pointer, 0x10, 16, 4);
3056
3057/* reg_pererp_erpt_pointer
3058 * Pointer to eRP table within the eRP bank. Can be changed for an
3059 * existing region.
3060 * Range 0..cap_max_erp_table_size-1
3061 * Reserved when erpt_pointer_valid = 0
3062 * Access: RW
3063 */
3064MLXSW_ITEM32(reg, pererp, erpt_pointer, 0x10, 0, 8);
3065
3066/* reg_pererp_erpt_vector
3067 * Vector of allowed eRP indexes starting from erpt_pointer within the
3068 * erpt_bank_pointer. Next entries will be in next bank.
3069 * Note that eRP index is used and not eRP ID.
3070 * Reserved when erpt_pointer_valid = 0
3071 * Access: RW
3072 */
3073MLXSW_ITEM_BIT_ARRAY(reg, pererp, erpt_vector, 0x14, 4, 1);
3074
3075/* reg_pererp_master_rp_id
3076 * Master RP ID. When there are no eRPs, then this provides the eRP ID
3077 * for the lookup. Can be changed for an existing region.
3078 * Reserved when erpt_pointer_valid = 1
3079 * Access: RW
3080 */
3081MLXSW_ITEM32(reg, pererp, master_rp_id, 0x18, 0, 4);
3082
3083static inline void mlxsw_reg_pererp_erp_vector_pack(char *payload,
3084 unsigned long *erp_vector,
3085 unsigned long size)
3086{
3087 unsigned long bit;
3088
3089 for_each_set_bit(bit, erp_vector, size)
3090 mlxsw_reg_pererp_erpt_vector_set(payload, bit, true);
3091}
3092
3093static inline void mlxsw_reg_pererp_pack(char *payload, u16 region_id,
3094 bool ctcam_le, bool erpt_pointer_valid,
3095 u8 erpt_bank_pointer, u8 erpt_pointer,
3096 u8 master_rp_id)
3097{
3098 MLXSW_REG_ZERO(pererp, payload);
3099 mlxsw_reg_pererp_region_id_set(payload, region_id);
3100 mlxsw_reg_pererp_ctcam_le_set(payload, ctcam_le);
3101 mlxsw_reg_pererp_erpt_pointer_valid_set(payload, erpt_pointer_valid);
3102 mlxsw_reg_pererp_erpt_bank_pointer_set(payload, erpt_bank_pointer);
3103 mlxsw_reg_pererp_erpt_pointer_set(payload, erpt_pointer);
3104 mlxsw_reg_pererp_master_rp_id_set(payload, master_rp_id);
3105}
3106
3107/* PEABFE - Policy-Engine Algorithmic Bloom Filter Entries Register
3108 * ----------------------------------------------------------------
3109 * This register configures the Bloom filter entries.
3110 */
3111#define MLXSW_REG_PEABFE_ID 0x3022
3112#define MLXSW_REG_PEABFE_BASE_LEN 0x10
3113#define MLXSW_REG_PEABFE_BF_REC_LEN 0x4
3114#define MLXSW_REG_PEABFE_BF_REC_MAX_COUNT 256
3115#define MLXSW_REG_PEABFE_LEN (MLXSW_REG_PEABFE_BASE_LEN + \
3116 MLXSW_REG_PEABFE_BF_REC_LEN * \
3117 MLXSW_REG_PEABFE_BF_REC_MAX_COUNT)
3118
3119MLXSW_REG_DEFINE(peabfe, MLXSW_REG_PEABFE_ID, MLXSW_REG_PEABFE_LEN);
3120
3121/* reg_peabfe_size
3122 * Number of BF entries to be updated.
3123 * Range 1..256
3124 * Access: Op
3125 */
3126MLXSW_ITEM32(reg, peabfe, size, 0x00, 0, 9);
3127
3128/* reg_peabfe_bf_entry_state
3129 * Bloom filter state
3130 * 0 - Clear
3131 * 1 - Set
3132 * Access: RW
3133 */
3134MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_state,
3135 MLXSW_REG_PEABFE_BASE_LEN, 31, 1,
3136 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false);
3137
3138/* reg_peabfe_bf_entry_bank
3139 * Bloom filter bank ID
3140 * Range 0..cap_max_erp_table_banks-1
3141 * Access: Index
3142 */
3143MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_bank,
3144 MLXSW_REG_PEABFE_BASE_LEN, 24, 4,
3145 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false);
3146
3147/* reg_peabfe_bf_entry_index
3148 * Bloom filter entry index
3149 * Range 0..2^cap_max_bf_log-1
3150 * Access: Index
3151 */
3152MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_index,
3153 MLXSW_REG_PEABFE_BASE_LEN, 0, 24,
3154 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false);
3155
3156static inline void mlxsw_reg_peabfe_pack(char *payload)
3157{
3158 MLXSW_REG_ZERO(peabfe, payload);
3159}
3160
3161static inline void mlxsw_reg_peabfe_rec_pack(char *payload, int rec_index,
3162 u8 state, u8 bank, u32 bf_index)
3163{
3164 u8 num_rec = mlxsw_reg_peabfe_size_get(payload);
3165
3166 if (rec_index >= num_rec)
3167 mlxsw_reg_peabfe_size_set(payload, rec_index + 1);
3168 mlxsw_reg_peabfe_bf_entry_state_set(payload, rec_index, state);
3169 mlxsw_reg_peabfe_bf_entry_bank_set(payload, rec_index, bank);
3170 mlxsw_reg_peabfe_bf_entry_index_set(payload, rec_index, bf_index);
3171}
3172
3173/* IEDR - Infrastructure Entry Delete Register
3174 * ----------------------------------------------------
3175 * This register is used for deleting entries from the entry tables.
3176 * It is legitimate to attempt to delete a nonexisting entry (the device will
3177 * respond as a good flow).
3178 */
3179#define MLXSW_REG_IEDR_ID 0x3804
3180#define MLXSW_REG_IEDR_BASE_LEN 0x10 /* base length, without records */
3181#define MLXSW_REG_IEDR_REC_LEN 0x8 /* record length */
3182#define MLXSW_REG_IEDR_REC_MAX_COUNT 64
3183#define MLXSW_REG_IEDR_LEN (MLXSW_REG_IEDR_BASE_LEN + \
3184 MLXSW_REG_IEDR_REC_LEN * \
3185 MLXSW_REG_IEDR_REC_MAX_COUNT)
3186
3187MLXSW_REG_DEFINE(iedr, MLXSW_REG_IEDR_ID, MLXSW_REG_IEDR_LEN);
3188
3189/* reg_iedr_num_rec
3190 * Number of records.
3191 * Access: OP
3192 */
3193MLXSW_ITEM32(reg, iedr, num_rec, 0x00, 0, 8);
3194
3195/* reg_iedr_rec_type
3196 * Resource type.
3197 * Access: OP
3198 */
3199MLXSW_ITEM32_INDEXED(reg, iedr, rec_type, MLXSW_REG_IEDR_BASE_LEN, 24, 8,
3200 MLXSW_REG_IEDR_REC_LEN, 0x00, false);
3201
3202/* reg_iedr_rec_size
3203 * Size of entries do be deleted. The unit is 1 entry, regardless of entry type.
3204 * Access: OP
3205 */
3206MLXSW_ITEM32_INDEXED(reg, iedr, rec_size, MLXSW_REG_IEDR_BASE_LEN, 0, 11,
3207 MLXSW_REG_IEDR_REC_LEN, 0x00, false);
3208
3209/* reg_iedr_rec_index_start
3210 * Resource index start.
3211 * Access: OP
3212 */
3213MLXSW_ITEM32_INDEXED(reg, iedr, rec_index_start, MLXSW_REG_IEDR_BASE_LEN, 0, 24,
3214 MLXSW_REG_IEDR_REC_LEN, 0x04, false);
3215
3216static inline void mlxsw_reg_iedr_pack(char *payload)
3217{
3218 MLXSW_REG_ZERO(iedr, payload);
3219}
3220
3221static inline void mlxsw_reg_iedr_rec_pack(char *payload, int rec_index,
3222 u8 rec_type, u16 rec_size,
3223 u32 rec_index_start)
3224{
3225 u8 num_rec = mlxsw_reg_iedr_num_rec_get(payload);
3226
3227 if (rec_index >= num_rec)
3228 mlxsw_reg_iedr_num_rec_set(payload, rec_index + 1);
3229 mlxsw_reg_iedr_rec_type_set(payload, rec_index, rec_type);
3230 mlxsw_reg_iedr_rec_size_set(payload, rec_index, rec_size);
3231 mlxsw_reg_iedr_rec_index_start_set(payload, rec_index, rec_index_start);
3232}
3233
3234/* QPTS - QoS Priority Trust State Register
3235 * ----------------------------------------
3236 * This register controls the port policy to calculate the switch priority and
3237 * packet color based on incoming packet fields.
3238 */
3239#define MLXSW_REG_QPTS_ID 0x4002
3240#define MLXSW_REG_QPTS_LEN 0x8
3241
3242MLXSW_REG_DEFINE(qpts, MLXSW_REG_QPTS_ID, MLXSW_REG_QPTS_LEN);
3243
3244/* reg_qpts_local_port
3245 * Local port number.
3246 * Access: Index
3247 *
3248 * Note: CPU port is supported.
3249 */
3250MLXSW_ITEM32(reg, qpts, local_port, 0x00, 16, 8);
3251
3252enum mlxsw_reg_qpts_trust_state {
3253 MLXSW_REG_QPTS_TRUST_STATE_PCP = 1,
3254 MLXSW_REG_QPTS_TRUST_STATE_DSCP = 2, /* For MPLS, trust EXP. */
3255};
3256
3257/* reg_qpts_trust_state
3258 * Trust state for a given port.
3259 * Access: RW
3260 */
3261MLXSW_ITEM32(reg, qpts, trust_state, 0x04, 0, 3);
3262
3263static inline void mlxsw_reg_qpts_pack(char *payload, u8 local_port,
3264 enum mlxsw_reg_qpts_trust_state ts)
3265{
3266 MLXSW_REG_ZERO(qpts, payload);
3267
3268 mlxsw_reg_qpts_local_port_set(payload, local_port);
3269 mlxsw_reg_qpts_trust_state_set(payload, ts);
3270}
3271
3272/* QPCR - QoS Policer Configuration Register
3273 * -----------------------------------------
3274 * The QPCR register is used to create policers - that limit
3275 * the rate of bytes or packets via some trap group.
3276 */
3277#define MLXSW_REG_QPCR_ID 0x4004
3278#define MLXSW_REG_QPCR_LEN 0x28
3279
3280MLXSW_REG_DEFINE(qpcr, MLXSW_REG_QPCR_ID, MLXSW_REG_QPCR_LEN);
3281
3282enum mlxsw_reg_qpcr_g {
3283 MLXSW_REG_QPCR_G_GLOBAL = 2,
3284 MLXSW_REG_QPCR_G_STORM_CONTROL = 3,
3285};
3286
3287/* reg_qpcr_g
3288 * The policer type.
3289 * Access: Index
3290 */
3291MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2);
3292
3293/* reg_qpcr_pid
3294 * Policer ID.
3295 * Access: Index
3296 */
3297MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14);
3298
3299/* reg_qpcr_color_aware
3300 * Is the policer aware of colors.
3301 * Must be 0 (unaware) for cpu port.
3302 * Access: RW for unbounded policer. RO for bounded policer.
3303 */
3304MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1);
3305
3306/* reg_qpcr_bytes
3307 * Is policer limit is for bytes per sec or packets per sec.
3308 * 0 - packets
3309 * 1 - bytes
3310 * Access: RW for unbounded policer. RO for bounded policer.
3311 */
3312MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1);
3313
3314enum mlxsw_reg_qpcr_ir_units {
3315 MLXSW_REG_QPCR_IR_UNITS_M,
3316 MLXSW_REG_QPCR_IR_UNITS_K,
3317};
3318
3319/* reg_qpcr_ir_units
3320 * Policer's units for cir and eir fields (for bytes limits only)
3321 * 1 - 10^3
3322 * 0 - 10^6
3323 * Access: OP
3324 */
3325MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1);
3326
3327enum mlxsw_reg_qpcr_rate_type {
3328 MLXSW_REG_QPCR_RATE_TYPE_SINGLE = 1,
3329 MLXSW_REG_QPCR_RATE_TYPE_DOUBLE = 2,
3330};
3331
3332/* reg_qpcr_rate_type
3333 * Policer can have one limit (single rate) or 2 limits with specific operation
3334 * for packets that exceed the lower rate but not the upper one.
3335 * (For cpu port must be single rate)
3336 * Access: RW for unbounded policer. RO for bounded policer.
3337 */
3338MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2);
3339
3340/* reg_qpc_cbs
3341 * Policer's committed burst size.
3342 * The policer is working with time slices of 50 nano sec. By default every
3343 * slice is granted the proportionate share of the committed rate. If we want to
3344 * allow a slice to exceed that share (while still keeping the rate per sec) we
3345 * can allow burst. The burst size is between the default proportionate share
3346 * (and no lower than 8) to 32Gb. (Even though giving a number higher than the
3347 * committed rate will result in exceeding the rate). The burst size must be a
3348 * log of 2 and will be determined by 2^cbs.
3349 * Access: RW
3350 */
3351MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6);
3352
3353/* reg_qpcr_cir
3354 * Policer's committed rate.
3355 * The rate used for sungle rate, the lower rate for double rate.
3356 * For bytes limits, the rate will be this value * the unit from ir_units.
3357 * (Resolution error is up to 1%).
3358 * Access: RW
3359 */
3360MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32);
3361
3362/* reg_qpcr_eir
3363 * Policer's exceed rate.
3364 * The higher rate for double rate, reserved for single rate.
3365 * Lower rate for double rate policer.
3366 * For bytes limits, the rate will be this value * the unit from ir_units.
3367 * (Resolution error is up to 1%).
3368 * Access: RW
3369 */
3370MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32);
3371
3372#define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2
3373
3374/* reg_qpcr_exceed_action.
3375 * What to do with packets between the 2 limits for double rate.
3376 * Access: RW for unbounded policer. RO for bounded policer.
3377 */
3378MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4);
3379
3380enum mlxsw_reg_qpcr_action {
3381 /* Discard */
3382 MLXSW_REG_QPCR_ACTION_DISCARD = 1,
3383 /* Forward and set color to red.
3384 * If the packet is intended to cpu port, it will be dropped.
3385 */
3386 MLXSW_REG_QPCR_ACTION_FORWARD = 2,
3387};
3388
3389/* reg_qpcr_violate_action
3390 * What to do with packets that cross the cir limit (for single rate) or the eir
3391 * limit (for double rate).
3392 * Access: RW for unbounded policer. RO for bounded policer.
3393 */
3394MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4);
3395
3396static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid,
3397 enum mlxsw_reg_qpcr_ir_units ir_units,
3398 bool bytes, u32 cir, u16 cbs)
3399{
3400 MLXSW_REG_ZERO(qpcr, payload);
3401 mlxsw_reg_qpcr_pid_set(payload, pid);
3402 mlxsw_reg_qpcr_g_set(payload, MLXSW_REG_QPCR_G_GLOBAL);
3403 mlxsw_reg_qpcr_rate_type_set(payload, MLXSW_REG_QPCR_RATE_TYPE_SINGLE);
3404 mlxsw_reg_qpcr_violate_action_set(payload,
3405 MLXSW_REG_QPCR_ACTION_DISCARD);
3406 mlxsw_reg_qpcr_cir_set(payload, cir);
3407 mlxsw_reg_qpcr_ir_units_set(payload, ir_units);
3408 mlxsw_reg_qpcr_bytes_set(payload, bytes);
3409 mlxsw_reg_qpcr_cbs_set(payload, cbs);
3410}
3411
3412/* QTCT - QoS Switch Traffic Class Table
3413 * -------------------------------------
3414 * Configures the mapping between the packet switch priority and the
3415 * traffic class on the transmit port.
3416 */
3417#define MLXSW_REG_QTCT_ID 0x400A
3418#define MLXSW_REG_QTCT_LEN 0x08
3419
3420MLXSW_REG_DEFINE(qtct, MLXSW_REG_QTCT_ID, MLXSW_REG_QTCT_LEN);
3421
3422/* reg_qtct_local_port
3423 * Local port number.
3424 * Access: Index
3425 *
3426 * Note: CPU port is not supported.
3427 */
3428MLXSW_ITEM32(reg, qtct, local_port, 0x00, 16, 8);
3429
3430/* reg_qtct_sub_port
3431 * Virtual port within the physical port.
3432 * Should be set to 0 when virtual ports are not enabled on the port.
3433 * Access: Index
3434 */
3435MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8);
3436
3437/* reg_qtct_switch_prio
3438 * Switch priority.
3439 * Access: Index
3440 */
3441MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4);
3442
3443/* reg_qtct_tclass
3444 * Traffic class.
3445 * Default values:
3446 * switch_prio 0 : tclass 1
3447 * switch_prio 1 : tclass 0
3448 * switch_prio i : tclass i, for i > 1
3449 * Access: RW
3450 */
3451MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4);
3452
3453static inline void mlxsw_reg_qtct_pack(char *payload, u8 local_port,
3454 u8 switch_prio, u8 tclass)
3455{
3456 MLXSW_REG_ZERO(qtct, payload);
3457 mlxsw_reg_qtct_local_port_set(payload, local_port);
3458 mlxsw_reg_qtct_switch_prio_set(payload, switch_prio);
3459 mlxsw_reg_qtct_tclass_set(payload, tclass);
3460}
3461
3462/* QEEC - QoS ETS Element Configuration Register
3463 * ---------------------------------------------
3464 * Configures the ETS elements.
3465 */
3466#define MLXSW_REG_QEEC_ID 0x400D
3467#define MLXSW_REG_QEEC_LEN 0x20
3468
3469MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN);
3470
3471/* reg_qeec_local_port
3472 * Local port number.
3473 * Access: Index
3474 *
3475 * Note: CPU port is supported.
3476 */
3477MLXSW_ITEM32(reg, qeec, local_port, 0x00, 16, 8);
3478
3479enum mlxsw_reg_qeec_hr {
3480 MLXSW_REG_QEEC_HIERARCY_PORT,
3481 MLXSW_REG_QEEC_HIERARCY_GROUP,
3482 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
3483 MLXSW_REG_QEEC_HIERARCY_TC,
3484};
3485
3486/* reg_qeec_element_hierarchy
3487 * 0 - Port
3488 * 1 - Group
3489 * 2 - Subgroup
3490 * 3 - Traffic Class
3491 * Access: Index
3492 */
3493MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4);
3494
3495/* reg_qeec_element_index
3496 * The index of the element in the hierarchy.
3497 * Access: Index
3498 */
3499MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8);
3500
3501/* reg_qeec_next_element_index
3502 * The index of the next (lower) element in the hierarchy.
3503 * Access: RW
3504 *
3505 * Note: Reserved for element_hierarchy 0.
3506 */
3507MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8);
3508
3509/* reg_qeec_mise
3510 * Min shaper configuration enable. Enables configuration of the min
3511 * shaper on this ETS element
3512 * 0 - Disable
3513 * 1 - Enable
3514 * Access: RW
3515 */
3516MLXSW_ITEM32(reg, qeec, mise, 0x0C, 31, 1);
3517
3518enum {
3519 MLXSW_REG_QEEC_BYTES_MODE,
3520 MLXSW_REG_QEEC_PACKETS_MODE,
3521};
3522
3523/* reg_qeec_pb
3524 * Packets or bytes mode.
3525 * 0 - Bytes mode
3526 * 1 - Packets mode
3527 * Access: RW
3528 *
3529 * Note: Used for max shaper configuration. For Spectrum, packets mode
3530 * is supported only for traffic classes of CPU port.
3531 */
3532MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1);
3533
3534/* The smallest permitted min shaper rate. */
3535#define MLXSW_REG_QEEC_MIS_MIN 200000 /* Kbps */
3536
3537/* reg_qeec_min_shaper_rate
3538 * Min shaper information rate.
3539 * For CPU port, can only be configured for port hierarchy.
3540 * When in bytes mode, value is specified in units of 1000bps.
3541 * Access: RW
3542 */
3543MLXSW_ITEM32(reg, qeec, min_shaper_rate, 0x0C, 0, 28);
3544
3545/* reg_qeec_mase
3546 * Max shaper configuration enable. Enables configuration of the max
3547 * shaper on this ETS element.
3548 * 0 - Disable
3549 * 1 - Enable
3550 * Access: RW
3551 */
3552MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1);
3553
3554/* A large max rate will disable the max shaper. */
3555#define MLXSW_REG_QEEC_MAS_DIS 200000000 /* Kbps */
3556
3557/* reg_qeec_max_shaper_rate
3558 * Max shaper information rate.
3559 * For CPU port, can only be configured for port hierarchy.
3560 * When in bytes mode, value is specified in units of 1000bps.
3561 * Access: RW
3562 */
3563MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 28);
3564
3565/* reg_qeec_de
3566 * DWRR configuration enable. Enables configuration of the dwrr and
3567 * dwrr_weight.
3568 * 0 - Disable
3569 * 1 - Enable
3570 * Access: RW
3571 */
3572MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1);
3573
3574/* reg_qeec_dwrr
3575 * Transmission selection algorithm to use on the link going down from
3576 * the ETS element.
3577 * 0 - Strict priority
3578 * 1 - DWRR
3579 * Access: RW
3580 */
3581MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1);
3582
3583/* reg_qeec_dwrr_weight
3584 * DWRR weight on the link going down from the ETS element. The
3585 * percentage of bandwidth guaranteed to an ETS element within
3586 * its hierarchy. The sum of all weights across all ETS elements
3587 * within one hierarchy should be equal to 100. Reserved when
3588 * transmission selection algorithm is strict priority.
3589 * Access: RW
3590 */
3591MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8);
3592
3593static inline void mlxsw_reg_qeec_pack(char *payload, u8 local_port,
3594 enum mlxsw_reg_qeec_hr hr, u8 index,
3595 u8 next_index)
3596{
3597 MLXSW_REG_ZERO(qeec, payload);
3598 mlxsw_reg_qeec_local_port_set(payload, local_port);
3599 mlxsw_reg_qeec_element_hierarchy_set(payload, hr);
3600 mlxsw_reg_qeec_element_index_set(payload, index);
3601 mlxsw_reg_qeec_next_element_index_set(payload, next_index);
3602}
3603
3604/* QRWE - QoS ReWrite Enable
3605 * -------------------------
3606 * This register configures the rewrite enable per receive port.
3607 */
3608#define MLXSW_REG_QRWE_ID 0x400F
3609#define MLXSW_REG_QRWE_LEN 0x08
3610
3611MLXSW_REG_DEFINE(qrwe, MLXSW_REG_QRWE_ID, MLXSW_REG_QRWE_LEN);
3612
3613/* reg_qrwe_local_port
3614 * Local port number.
3615 * Access: Index
3616 *
3617 * Note: CPU port is supported. No support for router port.
3618 */
3619MLXSW_ITEM32(reg, qrwe, local_port, 0x00, 16, 8);
3620
3621/* reg_qrwe_dscp
3622 * Whether to enable DSCP rewrite (default is 0, don't rewrite).
3623 * Access: RW
3624 */
3625MLXSW_ITEM32(reg, qrwe, dscp, 0x04, 1, 1);
3626
3627/* reg_qrwe_pcp
3628 * Whether to enable PCP and DEI rewrite (default is 0, don't rewrite).
3629 * Access: RW
3630 */
3631MLXSW_ITEM32(reg, qrwe, pcp, 0x04, 0, 1);
3632
3633static inline void mlxsw_reg_qrwe_pack(char *payload, u8 local_port,
3634 bool rewrite_pcp, bool rewrite_dscp)
3635{
3636 MLXSW_REG_ZERO(qrwe, payload);
3637 mlxsw_reg_qrwe_local_port_set(payload, local_port);
3638 mlxsw_reg_qrwe_pcp_set(payload, rewrite_pcp);
3639 mlxsw_reg_qrwe_dscp_set(payload, rewrite_dscp);
3640}
3641
3642/* QPDSM - QoS Priority to DSCP Mapping
3643 * ------------------------------------
3644 * QoS Priority to DSCP Mapping Register
3645 */
3646#define MLXSW_REG_QPDSM_ID 0x4011
3647#define MLXSW_REG_QPDSM_BASE_LEN 0x04 /* base length, without records */
3648#define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN 0x4 /* record length */
3649#define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT 16
3650#define MLXSW_REG_QPDSM_LEN (MLXSW_REG_QPDSM_BASE_LEN + \
3651 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN * \
3652 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT)
3653
3654MLXSW_REG_DEFINE(qpdsm, MLXSW_REG_QPDSM_ID, MLXSW_REG_QPDSM_LEN);
3655
3656/* reg_qpdsm_local_port
3657 * Local Port. Supported for data packets from CPU port.
3658 * Access: Index
3659 */
3660MLXSW_ITEM32(reg, qpdsm, local_port, 0x00, 16, 8);
3661
3662/* reg_qpdsm_prio_entry_color0_e
3663 * Enable update of the entry for color 0 and a given port.
3664 * Access: WO
3665 */
3666MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_e,
3667 MLXSW_REG_QPDSM_BASE_LEN, 31, 1,
3668 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3669
3670/* reg_qpdsm_prio_entry_color0_dscp
3671 * DSCP field in the outer label of the packet for color 0 and a given port.
3672 * Reserved when e=0.
3673 * Access: RW
3674 */
3675MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_dscp,
3676 MLXSW_REG_QPDSM_BASE_LEN, 24, 6,
3677 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3678
3679/* reg_qpdsm_prio_entry_color1_e
3680 * Enable update of the entry for color 1 and a given port.
3681 * Access: WO
3682 */
3683MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_e,
3684 MLXSW_REG_QPDSM_BASE_LEN, 23, 1,
3685 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3686
3687/* reg_qpdsm_prio_entry_color1_dscp
3688 * DSCP field in the outer label of the packet for color 1 and a given port.
3689 * Reserved when e=0.
3690 * Access: RW
3691 */
3692MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_dscp,
3693 MLXSW_REG_QPDSM_BASE_LEN, 16, 6,
3694 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3695
3696/* reg_qpdsm_prio_entry_color2_e
3697 * Enable update of the entry for color 2 and a given port.
3698 * Access: WO
3699 */
3700MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_e,
3701 MLXSW_REG_QPDSM_BASE_LEN, 15, 1,
3702 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3703
3704/* reg_qpdsm_prio_entry_color2_dscp
3705 * DSCP field in the outer label of the packet for color 2 and a given port.
3706 * Reserved when e=0.
3707 * Access: RW
3708 */
3709MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_dscp,
3710 MLXSW_REG_QPDSM_BASE_LEN, 8, 6,
3711 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3712
3713static inline void mlxsw_reg_qpdsm_pack(char *payload, u8 local_port)
3714{
3715 MLXSW_REG_ZERO(qpdsm, payload);
3716 mlxsw_reg_qpdsm_local_port_set(payload, local_port);
3717}
3718
3719static inline void
3720mlxsw_reg_qpdsm_prio_pack(char *payload, unsigned short prio, u8 dscp)
3721{
3722 mlxsw_reg_qpdsm_prio_entry_color0_e_set(payload, prio, 1);
3723 mlxsw_reg_qpdsm_prio_entry_color0_dscp_set(payload, prio, dscp);
3724 mlxsw_reg_qpdsm_prio_entry_color1_e_set(payload, prio, 1);
3725 mlxsw_reg_qpdsm_prio_entry_color1_dscp_set(payload, prio, dscp);
3726 mlxsw_reg_qpdsm_prio_entry_color2_e_set(payload, prio, 1);
3727 mlxsw_reg_qpdsm_prio_entry_color2_dscp_set(payload, prio, dscp);
3728}
3729
3730/* QPDPM - QoS Port DSCP to Priority Mapping Register
3731 * --------------------------------------------------
3732 * This register controls the mapping from DSCP field to
3733 * Switch Priority for IP packets.
3734 */
3735#define MLXSW_REG_QPDPM_ID 0x4013
3736#define MLXSW_REG_QPDPM_BASE_LEN 0x4 /* base length, without records */
3737#define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN 0x2 /* record length */
3738#define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT 64
3739#define MLXSW_REG_QPDPM_LEN (MLXSW_REG_QPDPM_BASE_LEN + \
3740 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN * \
3741 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT)
3742
3743MLXSW_REG_DEFINE(qpdpm, MLXSW_REG_QPDPM_ID, MLXSW_REG_QPDPM_LEN);
3744
3745/* reg_qpdpm_local_port
3746 * Local Port. Supported for data packets from CPU port.
3747 * Access: Index
3748 */
3749MLXSW_ITEM32(reg, qpdpm, local_port, 0x00, 16, 8);
3750
3751/* reg_qpdpm_dscp_e
3752 * Enable update of the specific entry. When cleared, the switch_prio and color
3753 * fields are ignored and the previous switch_prio and color values are
3754 * preserved.
3755 * Access: WO
3756 */
3757MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_e, MLXSW_REG_QPDPM_BASE_LEN, 15, 1,
3758 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
3759
3760/* reg_qpdpm_dscp_prio
3761 * The new Switch Priority value for the relevant DSCP value.
3762 * Access: RW
3763 */
3764MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_prio,
3765 MLXSW_REG_QPDPM_BASE_LEN, 0, 4,
3766 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
3767
3768static inline void mlxsw_reg_qpdpm_pack(char *payload, u8 local_port)
3769{
3770 MLXSW_REG_ZERO(qpdpm, payload);
3771 mlxsw_reg_qpdpm_local_port_set(payload, local_port);
3772}
3773
3774static inline void
3775mlxsw_reg_qpdpm_dscp_pack(char *payload, unsigned short dscp, u8 prio)
3776{
3777 mlxsw_reg_qpdpm_dscp_entry_e_set(payload, dscp, 1);
3778 mlxsw_reg_qpdpm_dscp_entry_prio_set(payload, dscp, prio);
3779}
3780
3781/* QTCTM - QoS Switch Traffic Class Table is Multicast-Aware Register
3782 * ------------------------------------------------------------------
3783 * This register configures if the Switch Priority to Traffic Class mapping is
3784 * based on Multicast packet indication. If so, then multicast packets will get
3785 * a Traffic Class that is plus (cap_max_tclass_data/2) the value configured by
3786 * QTCT.
3787 * By default, Switch Priority to Traffic Class mapping is not based on
3788 * Multicast packet indication.
3789 */
3790#define MLXSW_REG_QTCTM_ID 0x401A
3791#define MLXSW_REG_QTCTM_LEN 0x08
3792
3793MLXSW_REG_DEFINE(qtctm, MLXSW_REG_QTCTM_ID, MLXSW_REG_QTCTM_LEN);
3794
3795/* reg_qtctm_local_port
3796 * Local port number.
3797 * No support for CPU port.
3798 * Access: Index
3799 */
3800MLXSW_ITEM32(reg, qtctm, local_port, 0x00, 16, 8);
3801
3802/* reg_qtctm_mc
3803 * Multicast Mode
3804 * Whether Switch Priority to Traffic Class mapping is based on Multicast packet
3805 * indication (default is 0, not based on Multicast packet indication).
3806 */
3807MLXSW_ITEM32(reg, qtctm, mc, 0x04, 0, 1);
3808
3809static inline void
3810mlxsw_reg_qtctm_pack(char *payload, u8 local_port, bool mc)
3811{
3812 MLXSW_REG_ZERO(qtctm, payload);
3813 mlxsw_reg_qtctm_local_port_set(payload, local_port);
3814 mlxsw_reg_qtctm_mc_set(payload, mc);
3815}
3816
3817/* PMLP - Ports Module to Local Port Register
3818 * ------------------------------------------
3819 * Configures the assignment of modules to local ports.
3820 */
3821#define MLXSW_REG_PMLP_ID 0x5002
3822#define MLXSW_REG_PMLP_LEN 0x40
3823
3824MLXSW_REG_DEFINE(pmlp, MLXSW_REG_PMLP_ID, MLXSW_REG_PMLP_LEN);
3825
3826/* reg_pmlp_rxtx
3827 * 0 - Tx value is used for both Tx and Rx.
3828 * 1 - Rx value is taken from a separte field.
3829 * Access: RW
3830 */
3831MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1);
3832
3833/* reg_pmlp_local_port
3834 * Local port number.
3835 * Access: Index
3836 */
3837MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8);
3838
3839/* reg_pmlp_width
3840 * 0 - Unmap local port.
3841 * 1 - Lane 0 is used.
3842 * 2 - Lanes 0 and 1 are used.
3843 * 4 - Lanes 0, 1, 2 and 3 are used.
3844 * Access: RW
3845 */
3846MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8);
3847
3848/* reg_pmlp_module
3849 * Module number.
3850 * Access: RW
3851 */
3852MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false);
3853
3854/* reg_pmlp_tx_lane
3855 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well.
3856 * Access: RW
3857 */
3858MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 2, 0x04, 0x00, false);
3859
3860/* reg_pmlp_rx_lane
3861 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is
3862 * equal to Tx lane.
3863 * Access: RW
3864 */
3865MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 2, 0x04, 0x00, false);
3866
3867static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port)
3868{
3869 MLXSW_REG_ZERO(pmlp, payload);
3870 mlxsw_reg_pmlp_local_port_set(payload, local_port);
3871}
3872
3873/* PMTU - Port MTU Register
3874 * ------------------------
3875 * Configures and reports the port MTU.
3876 */
3877#define MLXSW_REG_PMTU_ID 0x5003
3878#define MLXSW_REG_PMTU_LEN 0x10
3879
3880MLXSW_REG_DEFINE(pmtu, MLXSW_REG_PMTU_ID, MLXSW_REG_PMTU_LEN);
3881
3882/* reg_pmtu_local_port
3883 * Local port number.
3884 * Access: Index
3885 */
3886MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8);
3887
3888/* reg_pmtu_max_mtu
3889 * Maximum MTU.
3890 * When port type (e.g. Ethernet) is configured, the relevant MTU is
3891 * reported, otherwise the minimum between the max_mtu of the different
3892 * types is reported.
3893 * Access: RO
3894 */
3895MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16);
3896
3897/* reg_pmtu_admin_mtu
3898 * MTU value to set port to. Must be smaller or equal to max_mtu.
3899 * Note: If port type is Infiniband, then port must be disabled, when its
3900 * MTU is set.
3901 * Access: RW
3902 */
3903MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16);
3904
3905/* reg_pmtu_oper_mtu
3906 * The actual MTU configured on the port. Packets exceeding this size
3907 * will be dropped.
3908 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband
3909 * oper_mtu might be smaller than admin_mtu.
3910 * Access: RO
3911 */
3912MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16);
3913
3914static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port,
3915 u16 new_mtu)
3916{
3917 MLXSW_REG_ZERO(pmtu, payload);
3918 mlxsw_reg_pmtu_local_port_set(payload, local_port);
3919 mlxsw_reg_pmtu_max_mtu_set(payload, 0);
3920 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu);
3921 mlxsw_reg_pmtu_oper_mtu_set(payload, 0);
3922}
3923
3924/* PTYS - Port Type and Speed Register
3925 * -----------------------------------
3926 * Configures and reports the port speed type.
3927 *
3928 * Note: When set while the link is up, the changes will not take effect
3929 * until the port transitions from down to up state.
3930 */
3931#define MLXSW_REG_PTYS_ID 0x5004
3932#define MLXSW_REG_PTYS_LEN 0x40
3933
3934MLXSW_REG_DEFINE(ptys, MLXSW_REG_PTYS_ID, MLXSW_REG_PTYS_LEN);
3935
3936/* an_disable_admin
3937 * Auto negotiation disable administrative configuration
3938 * 0 - Device doesn't support AN disable.
3939 * 1 - Device supports AN disable.
3940 * Access: RW
3941 */
3942MLXSW_ITEM32(reg, ptys, an_disable_admin, 0x00, 30, 1);
3943
3944/* reg_ptys_local_port
3945 * Local port number.
3946 * Access: Index
3947 */
3948MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8);
3949
3950#define MLXSW_REG_PTYS_PROTO_MASK_IB BIT(0)
3951#define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2)
3952
3953/* reg_ptys_proto_mask
3954 * Protocol mask. Indicates which protocol is used.
3955 * 0 - Infiniband.
3956 * 1 - Fibre Channel.
3957 * 2 - Ethernet.
3958 * Access: Index
3959 */
3960MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3);
3961
3962enum {
3963 MLXSW_REG_PTYS_AN_STATUS_NA,
3964 MLXSW_REG_PTYS_AN_STATUS_OK,
3965 MLXSW_REG_PTYS_AN_STATUS_FAIL,
3966};
3967
3968/* reg_ptys_an_status
3969 * Autonegotiation status.
3970 * Access: RO
3971 */
3972MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4);
3973
3974#define MLXSW_REG_PTYS_EXT_ETH_SPEED_SGMII_100M BIT(0)
3975#define MLXSW_REG_PTYS_EXT_ETH_SPEED_1000BASE_X_SGMII BIT(1)
3976#define MLXSW_REG_PTYS_EXT_ETH_SPEED_2_5GBASE_X_2_5GMII BIT(2)
3977#define MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R BIT(3)
3978#define MLXSW_REG_PTYS_EXT_ETH_SPEED_XFI_XAUI_1_10G BIT(4)
3979#define MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G BIT(5)
3980#define MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR BIT(6)
3981#define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_2_LAUI_2_50GBASE_CR2_KR2 BIT(7)
3982#define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR BIT(8)
3983#define MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4 BIT(9)
3984#define MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2 BIT(10)
3985#define MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4 BIT(12)
3986
3987/* reg_ptys_ext_eth_proto_cap
3988 * Extended Ethernet port supported speeds and protocols.
3989 * Access: RO
3990 */
3991MLXSW_ITEM32(reg, ptys, ext_eth_proto_cap, 0x08, 0, 32);
3992
3993#define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0)
3994#define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1)
3995#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2)
3996#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3)
3997#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4)
3998#define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2 BIT(5)
3999#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6)
4000#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7)
4001#define MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4 BIT(8)
4002#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12)
4003#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13)
4004#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14)
4005#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15)
4006#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16)
4007#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2 BIT(18)
4008#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19)
4009#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20)
4010#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21)
4011#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22)
4012#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23)
4013#define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX BIT(24)
4014#define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(25)
4015#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T BIT(26)
4016#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27)
4017#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28)
4018#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29)
4019#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30)
4020#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31)
4021
4022/* reg_ptys_eth_proto_cap
4023 * Ethernet port supported speeds and protocols.
4024 * Access: RO
4025 */
4026MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32);
4027
4028/* reg_ptys_ib_link_width_cap
4029 * IB port supported widths.
4030 * Access: RO
4031 */
4032MLXSW_ITEM32(reg, ptys, ib_link_width_cap, 0x10, 16, 16);
4033
4034#define MLXSW_REG_PTYS_IB_SPEED_SDR BIT(0)
4035#define MLXSW_REG_PTYS_IB_SPEED_DDR BIT(1)
4036#define MLXSW_REG_PTYS_IB_SPEED_QDR BIT(2)
4037#define MLXSW_REG_PTYS_IB_SPEED_FDR10 BIT(3)
4038#define MLXSW_REG_PTYS_IB_SPEED_FDR BIT(4)
4039#define MLXSW_REG_PTYS_IB_SPEED_EDR BIT(5)
4040
4041/* reg_ptys_ib_proto_cap
4042 * IB port supported speeds and protocols.
4043 * Access: RO
4044 */
4045MLXSW_ITEM32(reg, ptys, ib_proto_cap, 0x10, 0, 16);
4046
4047/* reg_ptys_ext_eth_proto_admin
4048 * Extended speed and protocol to set port to.
4049 * Access: RW
4050 */
4051MLXSW_ITEM32(reg, ptys, ext_eth_proto_admin, 0x14, 0, 32);
4052
4053/* reg_ptys_eth_proto_admin
4054 * Speed and protocol to set port to.
4055 * Access: RW
4056 */
4057MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32);
4058
4059/* reg_ptys_ib_link_width_admin
4060 * IB width to set port to.
4061 * Access: RW
4062 */
4063MLXSW_ITEM32(reg, ptys, ib_link_width_admin, 0x1C, 16, 16);
4064
4065/* reg_ptys_ib_proto_admin
4066 * IB speeds and protocols to set port to.
4067 * Access: RW
4068 */
4069MLXSW_ITEM32(reg, ptys, ib_proto_admin, 0x1C, 0, 16);
4070
4071/* reg_ptys_ext_eth_proto_oper
4072 * The extended current speed and protocol configured for the port.
4073 * Access: RO
4074 */
4075MLXSW_ITEM32(reg, ptys, ext_eth_proto_oper, 0x20, 0, 32);
4076
4077/* reg_ptys_eth_proto_oper
4078 * The current speed and protocol configured for the port.
4079 * Access: RO
4080 */
4081MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32);
4082
4083/* reg_ptys_ib_link_width_oper
4084 * The current IB width to set port to.
4085 * Access: RO
4086 */
4087MLXSW_ITEM32(reg, ptys, ib_link_width_oper, 0x28, 16, 16);
4088
4089/* reg_ptys_ib_proto_oper
4090 * The current IB speed and protocol.
4091 * Access: RO
4092 */
4093MLXSW_ITEM32(reg, ptys, ib_proto_oper, 0x28, 0, 16);
4094
4095enum mlxsw_reg_ptys_connector_type {
4096 MLXSW_REG_PTYS_CONNECTOR_TYPE_UNKNOWN_OR_NO_CONNECTOR,
4097 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_NONE,
4098 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_TP,
4099 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_AUI,
4100 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_BNC,
4101 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_MII,
4102 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_FIBRE,
4103 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_DA,
4104 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_OTHER,
4105};
4106
4107/* reg_ptys_connector_type
4108 * Connector type indication.
4109 * Access: RO
4110 */
4111MLXSW_ITEM32(reg, ptys, connector_type, 0x2C, 0, 4);
4112
4113static inline void mlxsw_reg_ptys_eth_pack(char *payload, u8 local_port,
4114 u32 proto_admin, bool autoneg)
4115{
4116 MLXSW_REG_ZERO(ptys, payload);
4117 mlxsw_reg_ptys_local_port_set(payload, local_port);
4118 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH);
4119 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin);
4120 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg);
4121}
4122
4123static inline void mlxsw_reg_ptys_ext_eth_pack(char *payload, u8 local_port,
4124 u32 proto_admin, bool autoneg)
4125{
4126 MLXSW_REG_ZERO(ptys, payload);
4127 mlxsw_reg_ptys_local_port_set(payload, local_port);
4128 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH);
4129 mlxsw_reg_ptys_ext_eth_proto_admin_set(payload, proto_admin);
4130 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg);
4131}
4132
4133static inline void mlxsw_reg_ptys_eth_unpack(char *payload,
4134 u32 *p_eth_proto_cap,
4135 u32 *p_eth_proto_admin,
4136 u32 *p_eth_proto_oper)
4137{
4138 if (p_eth_proto_cap)
4139 *p_eth_proto_cap =
4140 mlxsw_reg_ptys_eth_proto_cap_get(payload);
4141 if (p_eth_proto_admin)
4142 *p_eth_proto_admin =
4143 mlxsw_reg_ptys_eth_proto_admin_get(payload);
4144 if (p_eth_proto_oper)
4145 *p_eth_proto_oper =
4146 mlxsw_reg_ptys_eth_proto_oper_get(payload);
4147}
4148
4149static inline void mlxsw_reg_ptys_ext_eth_unpack(char *payload,
4150 u32 *p_eth_proto_cap,
4151 u32 *p_eth_proto_admin,
4152 u32 *p_eth_proto_oper)
4153{
4154 if (p_eth_proto_cap)
4155 *p_eth_proto_cap =
4156 mlxsw_reg_ptys_ext_eth_proto_cap_get(payload);
4157 if (p_eth_proto_admin)
4158 *p_eth_proto_admin =
4159 mlxsw_reg_ptys_ext_eth_proto_admin_get(payload);
4160 if (p_eth_proto_oper)
4161 *p_eth_proto_oper =
4162 mlxsw_reg_ptys_ext_eth_proto_oper_get(payload);
4163}
4164
4165static inline void mlxsw_reg_ptys_ib_pack(char *payload, u8 local_port,
4166 u16 proto_admin, u16 link_width)
4167{
4168 MLXSW_REG_ZERO(ptys, payload);
4169 mlxsw_reg_ptys_local_port_set(payload, local_port);
4170 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_IB);
4171 mlxsw_reg_ptys_ib_proto_admin_set(payload, proto_admin);
4172 mlxsw_reg_ptys_ib_link_width_admin_set(payload, link_width);
4173}
4174
4175static inline void mlxsw_reg_ptys_ib_unpack(char *payload, u16 *p_ib_proto_cap,
4176 u16 *p_ib_link_width_cap,
4177 u16 *p_ib_proto_oper,
4178 u16 *p_ib_link_width_oper)
4179{
4180 if (p_ib_proto_cap)
4181 *p_ib_proto_cap = mlxsw_reg_ptys_ib_proto_cap_get(payload);
4182 if (p_ib_link_width_cap)
4183 *p_ib_link_width_cap =
4184 mlxsw_reg_ptys_ib_link_width_cap_get(payload);
4185 if (p_ib_proto_oper)
4186 *p_ib_proto_oper = mlxsw_reg_ptys_ib_proto_oper_get(payload);
4187 if (p_ib_link_width_oper)
4188 *p_ib_link_width_oper =
4189 mlxsw_reg_ptys_ib_link_width_oper_get(payload);
4190}
4191
4192/* PPAD - Port Physical Address Register
4193 * -------------------------------------
4194 * The PPAD register configures the per port physical MAC address.
4195 */
4196#define MLXSW_REG_PPAD_ID 0x5005
4197#define MLXSW_REG_PPAD_LEN 0x10
4198
4199MLXSW_REG_DEFINE(ppad, MLXSW_REG_PPAD_ID, MLXSW_REG_PPAD_LEN);
4200
4201/* reg_ppad_single_base_mac
4202 * 0: base_mac, local port should be 0 and mac[7:0] is
4203 * reserved. HW will set incremental
4204 * 1: single_mac - mac of the local_port
4205 * Access: RW
4206 */
4207MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1);
4208
4209/* reg_ppad_local_port
4210 * port number, if single_base_mac = 0 then local_port is reserved
4211 * Access: RW
4212 */
4213MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8);
4214
4215/* reg_ppad_mac
4216 * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved.
4217 * If single_base_mac = 1 - the per port MAC address
4218 * Access: RW
4219 */
4220MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6);
4221
4222static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac,
4223 u8 local_port)
4224{
4225 MLXSW_REG_ZERO(ppad, payload);
4226 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac);
4227 mlxsw_reg_ppad_local_port_set(payload, local_port);
4228}
4229
4230/* PAOS - Ports Administrative and Operational Status Register
4231 * -----------------------------------------------------------
4232 * Configures and retrieves per port administrative and operational status.
4233 */
4234#define MLXSW_REG_PAOS_ID 0x5006
4235#define MLXSW_REG_PAOS_LEN 0x10
4236
4237MLXSW_REG_DEFINE(paos, MLXSW_REG_PAOS_ID, MLXSW_REG_PAOS_LEN);
4238
4239/* reg_paos_swid
4240 * Switch partition ID with which to associate the port.
4241 * Note: while external ports uses unique local port numbers (and thus swid is
4242 * redundant), router ports use the same local port number where swid is the
4243 * only indication for the relevant port.
4244 * Access: Index
4245 */
4246MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8);
4247
4248/* reg_paos_local_port
4249 * Local port number.
4250 * Access: Index
4251 */
4252MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8);
4253
4254/* reg_paos_admin_status
4255 * Port administrative state (the desired state of the port):
4256 * 1 - Up.
4257 * 2 - Down.
4258 * 3 - Up once. This means that in case of link failure, the port won't go
4259 * into polling mode, but will wait to be re-enabled by software.
4260 * 4 - Disabled by system. Can only be set by hardware.
4261 * Access: RW
4262 */
4263MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4);
4264
4265/* reg_paos_oper_status
4266 * Port operational state (the current state):
4267 * 1 - Up.
4268 * 2 - Down.
4269 * 3 - Down by port failure. This means that the device will not let the
4270 * port up again until explicitly specified by software.
4271 * Access: RO
4272 */
4273MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4);
4274
4275/* reg_paos_ase
4276 * Admin state update enabled.
4277 * Access: WO
4278 */
4279MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1);
4280
4281/* reg_paos_ee
4282 * Event update enable. If this bit is set, event generation will be
4283 * updated based on the e field.
4284 * Access: WO
4285 */
4286MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1);
4287
4288/* reg_paos_e
4289 * Event generation on operational state change:
4290 * 0 - Do not generate event.
4291 * 1 - Generate Event.
4292 * 2 - Generate Single Event.
4293 * Access: RW
4294 */
4295MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2);
4296
4297static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port,
4298 enum mlxsw_port_admin_status status)
4299{
4300 MLXSW_REG_ZERO(paos, payload);
4301 mlxsw_reg_paos_swid_set(payload, 0);
4302 mlxsw_reg_paos_local_port_set(payload, local_port);
4303 mlxsw_reg_paos_admin_status_set(payload, status);
4304 mlxsw_reg_paos_oper_status_set(payload, 0);
4305 mlxsw_reg_paos_ase_set(payload, 1);
4306 mlxsw_reg_paos_ee_set(payload, 1);
4307 mlxsw_reg_paos_e_set(payload, 1);
4308}
4309
4310/* PFCC - Ports Flow Control Configuration Register
4311 * ------------------------------------------------
4312 * Configures and retrieves the per port flow control configuration.
4313 */
4314#define MLXSW_REG_PFCC_ID 0x5007
4315#define MLXSW_REG_PFCC_LEN 0x20
4316
4317MLXSW_REG_DEFINE(pfcc, MLXSW_REG_PFCC_ID, MLXSW_REG_PFCC_LEN);
4318
4319/* reg_pfcc_local_port
4320 * Local port number.
4321 * Access: Index
4322 */
4323MLXSW_ITEM32(reg, pfcc, local_port, 0x00, 16, 8);
4324
4325/* reg_pfcc_pnat
4326 * Port number access type. Determines the way local_port is interpreted:
4327 * 0 - Local port number.
4328 * 1 - IB / label port number.
4329 * Access: Index
4330 */
4331MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2);
4332
4333/* reg_pfcc_shl_cap
4334 * Send to higher layers capabilities:
4335 * 0 - No capability of sending Pause and PFC frames to higher layers.
4336 * 1 - Device has capability of sending Pause and PFC frames to higher
4337 * layers.
4338 * Access: RO
4339 */
4340MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1);
4341
4342/* reg_pfcc_shl_opr
4343 * Send to higher layers operation:
4344 * 0 - Pause and PFC frames are handled by the port (default).
4345 * 1 - Pause and PFC frames are handled by the port and also sent to
4346 * higher layers. Only valid if shl_cap = 1.
4347 * Access: RW
4348 */
4349MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1);
4350
4351/* reg_pfcc_ppan
4352 * Pause policy auto negotiation.
4353 * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx.
4354 * 1 - Enabled. When auto-negotiation is performed, set the Pause policy
4355 * based on the auto-negotiation resolution.
4356 * Access: RW
4357 *
4358 * Note: The auto-negotiation advertisement is set according to pptx and
4359 * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0.
4360 */
4361MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4);
4362
4363/* reg_pfcc_prio_mask_tx
4364 * Bit per priority indicating if Tx flow control policy should be
4365 * updated based on bit pfctx.
4366 * Access: WO
4367 */
4368MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8);
4369
4370/* reg_pfcc_prio_mask_rx
4371 * Bit per priority indicating if Rx flow control policy should be
4372 * updated based on bit pfcrx.
4373 * Access: WO
4374 */
4375MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8);
4376
4377/* reg_pfcc_pptx
4378 * Admin Pause policy on Tx.
4379 * 0 - Never generate Pause frames (default).
4380 * 1 - Generate Pause frames according to Rx buffer threshold.
4381 * Access: RW
4382 */
4383MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1);
4384
4385/* reg_pfcc_aptx
4386 * Active (operational) Pause policy on Tx.
4387 * 0 - Never generate Pause frames.
4388 * 1 - Generate Pause frames according to Rx buffer threshold.
4389 * Access: RO
4390 */
4391MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1);
4392
4393/* reg_pfcc_pfctx
4394 * Priority based flow control policy on Tx[7:0]. Per-priority bit mask:
4395 * 0 - Never generate priority Pause frames on the specified priority
4396 * (default).
4397 * 1 - Generate priority Pause frames according to Rx buffer threshold on
4398 * the specified priority.
4399 * Access: RW
4400 *
4401 * Note: pfctx and pptx must be mutually exclusive.
4402 */
4403MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8);
4404
4405/* reg_pfcc_pprx
4406 * Admin Pause policy on Rx.
4407 * 0 - Ignore received Pause frames (default).
4408 * 1 - Respect received Pause frames.
4409 * Access: RW
4410 */
4411MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1);
4412
4413/* reg_pfcc_aprx
4414 * Active (operational) Pause policy on Rx.
4415 * 0 - Ignore received Pause frames.
4416 * 1 - Respect received Pause frames.
4417 * Access: RO
4418 */
4419MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1);
4420
4421/* reg_pfcc_pfcrx
4422 * Priority based flow control policy on Rx[7:0]. Per-priority bit mask:
4423 * 0 - Ignore incoming priority Pause frames on the specified priority
4424 * (default).
4425 * 1 - Respect incoming priority Pause frames on the specified priority.
4426 * Access: RW
4427 */
4428MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8);
4429
4430#define MLXSW_REG_PFCC_ALL_PRIO 0xFF
4431
4432static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en)
4433{
4434 mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);
4435 mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);
4436 mlxsw_reg_pfcc_pfctx_set(payload, pfc_en);
4437 mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en);
4438}
4439
4440static inline void mlxsw_reg_pfcc_pack(char *payload, u8 local_port)
4441{
4442 MLXSW_REG_ZERO(pfcc, payload);
4443 mlxsw_reg_pfcc_local_port_set(payload, local_port);
4444}
4445
4446/* PPCNT - Ports Performance Counters Register
4447 * -------------------------------------------
4448 * The PPCNT register retrieves per port performance counters.
4449 */
4450#define MLXSW_REG_PPCNT_ID 0x5008
4451#define MLXSW_REG_PPCNT_LEN 0x100
4452#define MLXSW_REG_PPCNT_COUNTERS_OFFSET 0x08
4453
4454MLXSW_REG_DEFINE(ppcnt, MLXSW_REG_PPCNT_ID, MLXSW_REG_PPCNT_LEN);
4455
4456/* reg_ppcnt_swid
4457 * For HCA: must be always 0.
4458 * Switch partition ID to associate port with.
4459 * Switch partitions are numbered from 0 to 7 inclusively.
4460 * Switch partition 254 indicates stacking ports.
4461 * Switch partition 255 indicates all switch partitions.
4462 * Only valid on Set() operation with local_port=255.
4463 * Access: Index
4464 */
4465MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8);
4466
4467/* reg_ppcnt_local_port
4468 * Local port number.
4469 * 255 indicates all ports on the device, and is only allowed
4470 * for Set() operation.
4471 * Access: Index
4472 */
4473MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8);
4474
4475/* reg_ppcnt_pnat
4476 * Port number access type:
4477 * 0 - Local port number
4478 * 1 - IB port number
4479 * Access: Index
4480 */
4481MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2);
4482
4483enum mlxsw_reg_ppcnt_grp {
4484 MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0,
4485 MLXSW_REG_PPCNT_RFC_2863_CNT = 0x1,
4486 MLXSW_REG_PPCNT_RFC_2819_CNT = 0x2,
4487 MLXSW_REG_PPCNT_RFC_3635_CNT = 0x3,
4488 MLXSW_REG_PPCNT_EXT_CNT = 0x5,
4489 MLXSW_REG_PPCNT_DISCARD_CNT = 0x6,
4490 MLXSW_REG_PPCNT_PRIO_CNT = 0x10,
4491 MLXSW_REG_PPCNT_TC_CNT = 0x11,
4492 MLXSW_REG_PPCNT_TC_CONG_TC = 0x13,
4493};
4494
4495/* reg_ppcnt_grp
4496 * Performance counter group.
4497 * Group 63 indicates all groups. Only valid on Set() operation with
4498 * clr bit set.
4499 * 0x0: IEEE 802.3 Counters
4500 * 0x1: RFC 2863 Counters
4501 * 0x2: RFC 2819 Counters
4502 * 0x3: RFC 3635 Counters
4503 * 0x5: Ethernet Extended Counters
4504 * 0x6: Ethernet Discard Counters
4505 * 0x8: Link Level Retransmission Counters
4506 * 0x10: Per Priority Counters
4507 * 0x11: Per Traffic Class Counters
4508 * 0x12: Physical Layer Counters
4509 * 0x13: Per Traffic Class Congestion Counters
4510 * Access: Index
4511 */
4512MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6);
4513
4514/* reg_ppcnt_clr
4515 * Clear counters. Setting the clr bit will reset the counter value
4516 * for all counters in the counter group. This bit can be set
4517 * for both Set() and Get() operation.
4518 * Access: OP
4519 */
4520MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1);
4521
4522/* reg_ppcnt_prio_tc
4523 * Priority for counter set that support per priority, valid values: 0-7.
4524 * Traffic class for counter set that support per traffic class,
4525 * valid values: 0- cap_max_tclass-1 .
4526 * For HCA: cap_max_tclass is always 8.
4527 * Otherwise must be 0.
4528 * Access: Index
4529 */
4530MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5);
4531
4532/* Ethernet IEEE 802.3 Counter Group */
4533
4534/* reg_ppcnt_a_frames_transmitted_ok
4535 * Access: RO
4536 */
4537MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok,
4538 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
4539
4540/* reg_ppcnt_a_frames_received_ok
4541 * Access: RO
4542 */
4543MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok,
4544 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
4545
4546/* reg_ppcnt_a_frame_check_sequence_errors
4547 * Access: RO
4548 */
4549MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors,
4550 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64);
4551
4552/* reg_ppcnt_a_alignment_errors
4553 * Access: RO
4554 */
4555MLXSW_ITEM64(reg, ppcnt, a_alignment_errors,
4556 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64);
4557
4558/* reg_ppcnt_a_octets_transmitted_ok
4559 * Access: RO
4560 */
4561MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok,
4562 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64);
4563
4564/* reg_ppcnt_a_octets_received_ok
4565 * Access: RO
4566 */
4567MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok,
4568 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64);
4569
4570/* reg_ppcnt_a_multicast_frames_xmitted_ok
4571 * Access: RO
4572 */
4573MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok,
4574 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64);
4575
4576/* reg_ppcnt_a_broadcast_frames_xmitted_ok
4577 * Access: RO
4578 */
4579MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok,
4580 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64);
4581
4582/* reg_ppcnt_a_multicast_frames_received_ok
4583 * Access: RO
4584 */
4585MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok,
4586 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
4587
4588/* reg_ppcnt_a_broadcast_frames_received_ok
4589 * Access: RO
4590 */
4591MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok,
4592 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64);
4593
4594/* reg_ppcnt_a_in_range_length_errors
4595 * Access: RO
4596 */
4597MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors,
4598 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64);
4599
4600/* reg_ppcnt_a_out_of_range_length_field
4601 * Access: RO
4602 */
4603MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field,
4604 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
4605
4606/* reg_ppcnt_a_frame_too_long_errors
4607 * Access: RO
4608 */
4609MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors,
4610 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
4611
4612/* reg_ppcnt_a_symbol_error_during_carrier
4613 * Access: RO
4614 */
4615MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier,
4616 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
4617
4618/* reg_ppcnt_a_mac_control_frames_transmitted
4619 * Access: RO
4620 */
4621MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted,
4622 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
4623
4624/* reg_ppcnt_a_mac_control_frames_received
4625 * Access: RO
4626 */
4627MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received,
4628 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64);
4629
4630/* reg_ppcnt_a_unsupported_opcodes_received
4631 * Access: RO
4632 */
4633MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received,
4634 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64);
4635
4636/* reg_ppcnt_a_pause_mac_ctrl_frames_received
4637 * Access: RO
4638 */
4639MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received,
4640 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64);
4641
4642/* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted
4643 * Access: RO
4644 */
4645MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted,
4646 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64);
4647
4648/* Ethernet RFC 2863 Counter Group */
4649
4650/* reg_ppcnt_if_in_discards
4651 * Access: RO
4652 */
4653MLXSW_ITEM64(reg, ppcnt, if_in_discards,
4654 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64);
4655
4656/* reg_ppcnt_if_out_discards
4657 * Access: RO
4658 */
4659MLXSW_ITEM64(reg, ppcnt, if_out_discards,
4660 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64);
4661
4662/* reg_ppcnt_if_out_errors
4663 * Access: RO
4664 */
4665MLXSW_ITEM64(reg, ppcnt, if_out_errors,
4666 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
4667
4668/* Ethernet RFC 2819 Counter Group */
4669
4670/* reg_ppcnt_ether_stats_undersize_pkts
4671 * Access: RO
4672 */
4673MLXSW_ITEM64(reg, ppcnt, ether_stats_undersize_pkts,
4674 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64);
4675
4676/* reg_ppcnt_ether_stats_oversize_pkts
4677 * Access: RO
4678 */
4679MLXSW_ITEM64(reg, ppcnt, ether_stats_oversize_pkts,
4680 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64);
4681
4682/* reg_ppcnt_ether_stats_fragments
4683 * Access: RO
4684 */
4685MLXSW_ITEM64(reg, ppcnt, ether_stats_fragments,
4686 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
4687
4688/* reg_ppcnt_ether_stats_pkts64octets
4689 * Access: RO
4690 */
4691MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts64octets,
4692 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
4693
4694/* reg_ppcnt_ether_stats_pkts65to127octets
4695 * Access: RO
4696 */
4697MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts65to127octets,
4698 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
4699
4700/* reg_ppcnt_ether_stats_pkts128to255octets
4701 * Access: RO
4702 */
4703MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts128to255octets,
4704 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
4705
4706/* reg_ppcnt_ether_stats_pkts256to511octets
4707 * Access: RO
4708 */
4709MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts256to511octets,
4710 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
4711
4712/* reg_ppcnt_ether_stats_pkts512to1023octets
4713 * Access: RO
4714 */
4715MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts512to1023octets,
4716 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64);
4717
4718/* reg_ppcnt_ether_stats_pkts1024to1518octets
4719 * Access: RO
4720 */
4721MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1024to1518octets,
4722 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64);
4723
4724/* reg_ppcnt_ether_stats_pkts1519to2047octets
4725 * Access: RO
4726 */
4727MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1519to2047octets,
4728 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64);
4729
4730/* reg_ppcnt_ether_stats_pkts2048to4095octets
4731 * Access: RO
4732 */
4733MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts2048to4095octets,
4734 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64);
4735
4736/* reg_ppcnt_ether_stats_pkts4096to8191octets
4737 * Access: RO
4738 */
4739MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts4096to8191octets,
4740 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x98, 0, 64);
4741
4742/* reg_ppcnt_ether_stats_pkts8192to10239octets
4743 * Access: RO
4744 */
4745MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts8192to10239octets,
4746 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0xA0, 0, 64);
4747
4748/* Ethernet RFC 3635 Counter Group */
4749
4750/* reg_ppcnt_dot3stats_fcs_errors
4751 * Access: RO
4752 */
4753MLXSW_ITEM64(reg, ppcnt, dot3stats_fcs_errors,
4754 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
4755
4756/* reg_ppcnt_dot3stats_symbol_errors
4757