| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * encx24j600_hw.h: Register definitions |
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| 4 | * |
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| 5 | */ |
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| 6 | |
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| 7 | #ifndef _ENCX24J600_HW_H |
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| 8 | #define _ENCX24J600_HW_H |
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| 9 | |
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| 10 | struct encx24j600_context { |
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| 11 | struct spi_device *spi; |
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| 12 | struct regmap *regmap; |
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| 13 | struct regmap *phymap; |
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| 14 | struct mutex mutex; /* mutex to protect access to regmap */ |
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| 15 | int bank; |
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| 16 | }; |
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| 17 | |
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| 18 | int devm_regmap_init_encx24j600(struct device *dev, |
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| 19 | struct encx24j600_context *ctx); |
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| 20 | |
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| 21 | /* Single-byte instructions */ |
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| 22 | #define BANK_SELECT(bank) (0xC0 | ((bank & (BANK_MASK >> BANK_SHIFT)) << 1)) |
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| 23 | #define B0SEL 0xC0 /* Bank 0 Select */ |
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| 24 | #define B1SEL 0xC2 /* Bank 1 Select */ |
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| 25 | #define B2SEL 0xC4 /* Bank 2 Select */ |
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| 26 | #define B3SEL 0xC6 /* Bank 3 Select */ |
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| 27 | #define SETETHRST 0xCA /* System Reset */ |
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| 28 | #define FCDISABLE 0xE0 /* Flow Control Disable */ |
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| 29 | #define FCSINGLE 0xE2 /* Flow Control Single */ |
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| 30 | #define FCMULTIPLE 0xE4 /* Flow Control Multiple */ |
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| 31 | #define FCCLEAR 0xE6 /* Flow Control Clear */ |
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| 32 | #define SETPKTDEC 0xCC /* Decrement Packet Counter */ |
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| 33 | #define DMASTOP 0xD2 /* DMA Stop */ |
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| 34 | #define DMACKSUM 0xD8 /* DMA Start Checksum */ |
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| 35 | #define DMACKSUMS 0xDA /* DMA Start Checksum with Seed */ |
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| 36 | #define DMACOPY 0xDC /* DMA Start Copy */ |
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| 37 | #define DMACOPYS 0xDE /* DMA Start Copy and Checksum with Seed */ |
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| 38 | #define SETTXRTS 0xD4 /* Request Packet Transmission */ |
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| 39 | #define ENABLERX 0xE8 /* Enable RX */ |
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| 40 | #define DISABLERX 0xEA /* Disable RX */ |
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| 41 | #define SETEIE 0xEC /* Enable Interrupts */ |
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| 42 | #define CLREIE 0xEE /* Disable Interrupts */ |
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| 43 | |
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| 44 | /* Two byte instructions */ |
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| 45 | #define RBSEL 0xC8 /* Read Bank Select */ |
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| 46 | |
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| 47 | /* Three byte instructions */ |
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| 48 | #define WGPRDPT 0x60 /* Write EGPRDPT */ |
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| 49 | #define RGPRDPT 0x62 /* Read EGPRDPT */ |
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| 50 | #define WRXRDPT 0x64 /* Write ERXRDPT */ |
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| 51 | #define RRXRDPT 0x66 /* Read ERXRDPT */ |
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| 52 | #define WUDARDPT 0x68 /* Write EUDARDPT */ |
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| 53 | #define RUDARDPT 0x6A /* Read EUDARDPT */ |
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| 54 | #define WGPWRPT 0x6C /* Write EGPWRPT */ |
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| 55 | #define RGPWRPT 0x6E /* Read EGPWRPT */ |
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| 56 | #define WRXWRPT 0x70 /* Write ERXWRPT */ |
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| 57 | #define RRXWRPT 0x72 /* Read ERXWRPT */ |
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| 58 | #define WUDAWRPT 0x74 /* Write EUDAWRPT */ |
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| 59 | #define RUDAWRPT 0x76 /* Read EUDAWRPT */ |
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| 60 | |
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| 61 | /* n byte instructions */ |
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| 62 | #define RCRCODE 0x00 |
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| 63 | #define WCRCODE 0x40 |
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| 64 | #define BFSCODE 0x80 |
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| 65 | #define BFCCODE 0xA0 |
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| 66 | #define RCR(addr) (RCRCODE | (addr & ADDR_MASK)) /* Read Control Register */ |
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| 67 | #define WCR(addr) (WCRCODE | (addr & ADDR_MASK)) /* Write Control Register */ |
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| 68 | #define RCRU 0x20 /* Read Control Register Unbanked */ |
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| 69 | #define WCRU 0x22 /* Write Control Register Unbanked */ |
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| 70 | #define BFS(addr) (BFSCODE | (addr & ADDR_MASK)) /* Bit Field Set */ |
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| 71 | #define BFC(addr) (BFCCODE | (addr & ADDR_MASK)) /* Bit Field Clear */ |
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| 72 | #define BFSU 0x24 /* Bit Field Set Unbanked */ |
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| 73 | #define BFCU 0x26 /* Bit Field Clear Unbanked */ |
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| 74 | #define RGPDATA 0x28 /* Read EGPDATA */ |
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| 75 | #define WGPDATA 0x2A /* Write EGPDATA */ |
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| 76 | #define RRXDATA 0x2C /* Read ERXDATA */ |
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| 77 | #define WRXDATA 0x2E /* Write ERXDATA */ |
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| 78 | #define RUDADATA 0x30 /* Read EUDADATA */ |
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| 79 | #define WUDADATA 0x32 /* Write EUDADATA */ |
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| 80 | |
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| 81 | #define SFR_REG_COUNT 0xA0 |
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| 82 | |
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| 83 | /* ENC424J600 Control Registers |
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| 84 | * Control register definitions are a combination of address |
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| 85 | * and bank number |
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| 86 | * - Register address (bits 0-4) |
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| 87 | * - Bank number (bits 5-6) |
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| 88 | */ |
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| 89 | #define ADDR_MASK 0x1F |
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| 90 | #define BANK_MASK 0x60 |
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| 91 | #define BANK_SHIFT 5 |
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| 92 | |
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| 93 | /* All-bank registers */ |
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| 94 | #define EUDAST 0x16 |
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| 95 | #define EUDAND 0x18 |
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| 96 | #define ESTAT 0x1A |
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| 97 | #define EIR 0x1C |
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| 98 | #define ECON1 0x1E |
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| 99 | |
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| 100 | /* Bank 0 registers */ |
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| 101 | #define ETXST (0x00 | 0x00) |
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| 102 | #define ETXLEN (0x02 | 0x00) |
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| 103 | #define ERXST (0x04 | 0x00) |
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| 104 | #define ERXTAIL (0x06 | 0x00) |
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| 105 | #define ERXHEAD (0x08 | 0x00) |
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| 106 | #define EDMAST (0x0A | 0x00) |
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| 107 | #define EDMALEN (0x0C | 0x00) |
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| 108 | #define EDMADST (0x0E | 0x00) |
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| 109 | #define EDMACS (0x10 | 0x00) |
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| 110 | #define ETXSTAT (0x12 | 0x00) |
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| 111 | #define ETXWIRE (0x14 | 0x00) |
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| 112 | |
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| 113 | /* Bank 1 registers */ |
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| 114 | #define EHT1 (0x00 | 0x20) |
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| 115 | #define EHT2 (0x02 | 0x20) |
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| 116 | #define EHT3 (0x04 | 0x20) |
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| 117 | #define EHT4 (0x06 | 0x20) |
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| 118 | #define EPMM1 (0x08 | 0x20) |
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| 119 | #define EPMM2 (0x0A | 0x20) |
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| 120 | #define EPMM3 (0x0C | 0x20) |
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| 121 | #define EPMM4 (0x0E | 0x20) |
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| 122 | #define EPMCS (0x10 | 0x20) |
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| 123 | #define EPMO (0x12 | 0x20) |
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| 124 | #define ERXFCON (0x14 | 0x20) |
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| 125 | |
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| 126 | /* Bank 2 registers */ |
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| 127 | #define MACON1 (0x00 | 0x40) |
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| 128 | #define MACON2 (0x02 | 0x40) |
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| 129 | #define MABBIPG (0x04 | 0x40) |
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| 130 | #define MAIPG (0x06 | 0x40) |
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| 131 | #define MACLCON (0x08 | 0x40) |
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| 132 | #define MAMXFL (0x0A | 0x40) |
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| 133 | #define MICMD (0x12 | 0x40) |
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| 134 | #define MIREGADR (0x14 | 0x40) |
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| 135 | |
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| 136 | /* Bank 3 registers */ |
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| 137 | #define MAADR3 (0x00 | 0x60) |
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| 138 | #define MAADR2 (0x02 | 0x60) |
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| 139 | #define MAADR1 (0x04 | 0x60) |
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| 140 | #define MIWR (0x06 | 0x60) |
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| 141 | #define MIRD (0x08 | 0x60) |
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| 142 | #define MISTAT (0x0A | 0x60) |
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| 143 | #define EPAUS (0x0C | 0x60) |
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| 144 | #define ECON2 (0x0E | 0x60) |
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| 145 | #define ERXWM (0x10 | 0x60) |
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| 146 | #define EIE (0x12 | 0x60) |
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| 147 | #define EIDLED (0x14 | 0x60) |
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| 148 | |
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| 149 | /* Unbanked registers */ |
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| 150 | #define EGPDATA (0x00 | 0x80) |
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| 151 | #define ERXDATA (0x02 | 0x80) |
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| 152 | #define EUDADATA (0x04 | 0x80) |
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| 153 | #define EGPRDPT (0x06 | 0x80) |
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| 154 | #define EGPWRPT (0x08 | 0x80) |
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| 155 | #define ERXRDPT (0x0A | 0x80) |
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| 156 | #define ERXWRPT (0x0C | 0x80) |
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| 157 | #define EUDARDPT (0x0E | 0x80) |
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| 158 | #define EUDAWRPT (0x10 | 0x80) |
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| 159 | |
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| 160 | |
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| 161 | /* Register bit definitions */ |
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| 162 | /* ESTAT */ |
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| 163 | #define INT (1 << 15) |
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| 164 | #define FCIDLE (1 << 14) |
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| 165 | #define RXBUSY (1 << 13) |
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| 166 | #define CLKRDY (1 << 12) |
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| 167 | #define PHYDPX (1 << 10) |
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| 168 | #define PHYLNK (1 << 8) |
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| 169 | |
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| 170 | /* EIR */ |
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| 171 | #define CRYPTEN (1 << 15) |
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| 172 | #define MODEXIF (1 << 14) |
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| 173 | #define HASHIF (1 << 13) |
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| 174 | #define AESIF (1 << 12) |
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| 175 | #define LINKIF (1 << 11) |
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| 176 | #define PKTIF (1 << 6) |
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| 177 | #define DMAIF (1 << 5) |
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| 178 | #define TXIF (1 << 3) |
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| 179 | #define TXABTIF (1 << 2) |
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| 180 | #define RXABTIF (1 << 1) |
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| 181 | #define PCFULIF (1 << 0) |
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| 182 | |
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| 183 | /* ECON1 */ |
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| 184 | #define MODEXST (1 << 15) |
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| 185 | #define HASHEN (1 << 14) |
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| 186 | #define HASHOP (1 << 13) |
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| 187 | #define HASHLST (1 << 12) |
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| 188 | #define AESST (1 << 11) |
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| 189 | #define AESOP1 (1 << 10) |
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| 190 | #define AESOP0 (1 << 9) |
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| 191 | #define PKTDEC (1 << 8) |
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| 192 | #define FCOP1 (1 << 7) |
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| 193 | #define FCOP0 (1 << 6) |
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| 194 | #define DMAST (1 << 5) |
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| 195 | #define DMACPY (1 << 4) |
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| 196 | #define DMACSSD (1 << 3) |
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| 197 | #define DMANOCS (1 << 2) |
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| 198 | #define TXRTS (1 << 1) |
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| 199 | #define RXEN (1 << 0) |
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| 200 | |
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| 201 | /* ETXSTAT */ |
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| 202 | #define LATECOL (1 << 10) |
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| 203 | #define MAXCOL (1 << 9) |
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| 204 | #define EXDEFER (1 << 8) |
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| 205 | #define ETXSTATL_DEFER (1 << 7) |
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| 206 | #define CRCBAD (1 << 4) |
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| 207 | #define COLCNT_MASK 0xF |
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| 208 | |
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| 209 | /* ERXFCON */ |
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| 210 | #define HTEN (1 << 15) |
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| 211 | #define MPEN (1 << 14) |
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| 212 | #define NOTPM (1 << 12) |
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| 213 | #define PMEN3 (1 << 11) |
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| 214 | #define PMEN2 (1 << 10) |
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| 215 | #define PMEN1 (1 << 9) |
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| 216 | #define PMEN0 (1 << 8) |
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| 217 | #define CRCEEN (1 << 7) |
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| 218 | #define CRCEN (1 << 6) |
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| 219 | #define RUNTEEN (1 << 5) |
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| 220 | #define RUNTEN (1 << 4) |
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| 221 | #define UCEN (1 << 3) |
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| 222 | #define NOTMEEN (1 << 2) |
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| 223 | #define MCEN (1 << 1) |
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| 224 | #define BCEN (1 << 0) |
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| 225 | |
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| 226 | /* MACON1 */ |
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| 227 | #define LOOPBK (1 << 4) |
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| 228 | #define RXPAUS (1 << 2) |
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| 229 | #define PASSALL (1 << 1) |
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| 230 | |
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| 231 | /* MACON2 */ |
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| 232 | #define MACON2_DEFER (1 << 14) |
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| 233 | #define BPEN (1 << 13) |
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| 234 | #define NOBKOFF (1 << 12) |
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| 235 | #define PADCFG2 (1 << 7) |
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| 236 | #define PADCFG1 (1 << 6) |
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| 237 | #define PADCFG0 (1 << 5) |
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| 238 | #define TXCRCEN (1 << 4) |
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| 239 | #define PHDREN (1 << 3) |
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| 240 | #define HFRMEN (1 << 2) |
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| 241 | #define MACON2_RSV1 (1 << 1) |
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| 242 | #define FULDPX (1 << 0) |
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| 243 | |
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| 244 | /* MAIPG */ |
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| 245 | /* value of the high byte is given by the reserved bits, |
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| 246 | * value of the low byte is recomended setting of the |
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| 247 | * IPG parameter. |
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| 248 | */ |
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| 249 | #define MAIPGH_VAL 0x0C |
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| 250 | #define MAIPGL_VAL 0x12 |
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| 251 | |
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| 252 | /* MIREGADRH */ |
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| 253 | #define MIREGADR_VAL (1 << 8) |
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| 254 | |
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| 255 | /* MIREGADRL */ |
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| 256 | #define PHREG_MASK 0x1F |
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| 257 | |
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| 258 | /* MICMD */ |
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| 259 | #define MIISCAN (1 << 1) |
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| 260 | #define MIIRD (1 << 0) |
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| 261 | |
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| 262 | /* MISTAT */ |
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| 263 | #define NVALID (1 << 2) |
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| 264 | #define SCAN (1 << 1) |
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| 265 | #define BUSY (1 << 0) |
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| 266 | |
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| 267 | /* ECON2 */ |
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| 268 | #define ETHEN (1 << 15) |
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| 269 | #define STRCH (1 << 14) |
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| 270 | #define TXMAC (1 << 13) |
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| 271 | #define SHA1MD5 (1 << 12) |
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| 272 | #define COCON3 (1 << 11) |
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| 273 | #define COCON2 (1 << 10) |
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| 274 | #define COCON1 (1 << 9) |
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| 275 | #define COCON0 (1 << 8) |
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| 276 | #define AUTOFC (1 << 7) |
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| 277 | #define TXRST (1 << 6) |
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| 278 | #define RXRST (1 << 5) |
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| 279 | #define ETHRST (1 << 4) |
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| 280 | #define MODLEN1 (1 << 3) |
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| 281 | #define MODLEN0 (1 << 2) |
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| 282 | #define AESLEN1 (1 << 1) |
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| 283 | #define AESLEN0 (1 << 0) |
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| 284 | |
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| 285 | /* EIE */ |
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| 286 | #define INTIE (1 << 15) |
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| 287 | #define MODEXIE (1 << 14) |
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| 288 | #define HASHIE (1 << 13) |
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| 289 | #define AESIE (1 << 12) |
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| 290 | #define LINKIE (1 << 11) |
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| 291 | #define PKTIE (1 << 6) |
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| 292 | #define DMAIE (1 << 5) |
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| 293 | #define TXIE (1 << 3) |
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| 294 | #define TXABTIE (1 << 2) |
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| 295 | #define RXABTIE (1 << 1) |
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| 296 | #define PCFULIE (1 << 0) |
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| 297 | |
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| 298 | /* EIDLED */ |
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| 299 | #define LACFG3 (1 << 15) |
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| 300 | #define LACFG2 (1 << 14) |
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| 301 | #define LACFG1 (1 << 13) |
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| 302 | #define LACFG0 (1 << 12) |
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| 303 | #define LBCFG3 (1 << 11) |
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| 304 | #define LBCFG2 (1 << 10) |
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| 305 | #define LBCFG1 (1 << 9) |
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| 306 | #define LBCFG0 (1 << 8) |
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| 307 | #define DEVID_SHIFT 5 |
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| 308 | #define DEVID_MASK (0x7 << DEVID_SHIFT) |
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| 309 | #define REVID_SHIFT 0 |
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| 310 | #define REVID_MASK (0x1F << REVID_SHIFT) |
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| 311 | |
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| 312 | /* PHY registers */ |
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| 313 | #define PHCON1 0x00 |
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| 314 | #define PHSTAT1 0x01 |
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| 315 | #define PHANA 0x04 |
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| 316 | #define PHANLPA 0x05 |
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| 317 | #define PHANE 0x06 |
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| 318 | #define PHCON2 0x11 |
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| 319 | #define PHSTAT2 0x1B |
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| 320 | #define PHSTAT3 0x1F |
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| 321 | |
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| 322 | /* PHCON1 */ |
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| 323 | #define PRST (1 << 15) |
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| 324 | #define PLOOPBK (1 << 14) |
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| 325 | #define SPD100 (1 << 13) |
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| 326 | #define ANEN (1 << 12) |
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| 327 | #define PSLEEP (1 << 11) |
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| 328 | #define RENEG (1 << 9) |
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| 329 | #define PFULDPX (1 << 8) |
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| 330 | |
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| 331 | /* PHSTAT1 */ |
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| 332 | #define FULL100 (1 << 14) |
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| 333 | #define HALF100 (1 << 13) |
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| 334 | #define FULL10 (1 << 12) |
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| 335 | #define HALF10 (1 << 11) |
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| 336 | #define ANDONE (1 << 5) |
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| 337 | #define LRFAULT (1 << 4) |
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| 338 | #define ANABLE (1 << 3) |
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| 339 | #define LLSTAT (1 << 2) |
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| 340 | #define EXTREGS (1 << 0) |
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| 341 | |
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| 342 | /* PHSTAT2 */ |
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| 343 | #define PLRITY (1 << 4) |
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| 344 | |
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| 345 | /* PHSTAT3 */ |
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| 346 | #define PHY3SPD100 (1 << 3) |
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| 347 | #define PHY3DPX (1 << 4) |
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| 348 | #define SPDDPX_SHIFT 2 |
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| 349 | #define SPDDPX_MASK (0x7 << SPDDPX_SHIFT) |
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| 350 | |
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| 351 | /* PHANA */ |
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| 352 | /* Default value for PHY initialization*/ |
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| 353 | #define PHANA_DEFAULT 0x05E1 |
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| 354 | |
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| 355 | /* PHANE */ |
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| 356 | #define PDFLT (1 << 4) |
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| 357 | #define LPARCD (1 << 1) |
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| 358 | #define LPANABL (1 << 0) |
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| 359 | |
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| 360 | #define EUDAST_TEST_VAL 0x1234 |
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| 361 | |
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| 362 | #define TSV_SIZE 7 |
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| 363 | |
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| 364 | #define ENCX24J600_DEV_ID 0x1 |
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| 365 | |
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| 366 | /* Configuration */ |
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| 367 | |
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| 368 | /* Led is on when the link is present and driven low |
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| 369 | * temporarily when packet is TX'd or RX'd |
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| 370 | */ |
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| 371 | #define LED_A_SETTINGS 0xC |
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| 372 | |
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| 373 | /* Led is on if the link is in 100 Mbps mode */ |
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| 374 | #define LED_B_SETTINGS 0x8 |
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| 375 | |
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| 376 | /* maximum ethernet frame length |
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| 377 | * Currently not used as a limit anywhere |
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| 378 | * (we're using the "huge frame enable" feature of |
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| 379 | * enc424j600). |
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| 380 | */ |
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| 381 | #define MAX_FRAMELEN 1518 |
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| 382 | |
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| 383 | /* Size in bytes of the receive buffer in enc424j600. |
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| 384 | * Must be word aligned (even). |
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| 385 | */ |
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| 386 | #define RX_BUFFER_SIZE (15 * MAX_FRAMELEN) |
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| 387 | |
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| 388 | /* Start of the general purpose area in sram */ |
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| 389 | #define SRAM_GP_START 0x0 |
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| 390 | |
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| 391 | /* SRAM size */ |
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| 392 | #define SRAM_SIZE 0x6000 |
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| 393 | |
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| 394 | /* Start of the receive buffer */ |
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| 395 | #define ERXST_VAL (SRAM_SIZE - RX_BUFFER_SIZE) |
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| 396 | |
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| 397 | #define RSV_RXLONGEVDROPEV 16 |
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| 398 | #define RSV_CARRIEREV 18 |
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| 399 | #define RSV_CRCERROR 20 |
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| 400 | #define RSV_LENCHECKERR 21 |
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| 401 | #define RSV_LENOUTOFRANGE 22 |
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| 402 | #define RSV_RXOK 23 |
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| 403 | #define RSV_RXMULTICAST 24 |
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| 404 | #define RSV_RXBROADCAST 25 |
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| 405 | #define RSV_DRIBBLENIBBLE 26 |
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| 406 | #define RSV_RXCONTROLFRAME 27 |
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| 407 | #define RSV_RXPAUSEFRAME 28 |
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| 408 | #define RSV_RXUNKNOWNOPCODE 29 |
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| 409 | #define RSV_RXTYPEVLAN 30 |
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| 410 | |
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| 411 | #define RSV_RUNTFILTERMATCH 31 |
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| 412 | #define RSV_NOTMEFILTERMATCH 32 |
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| 413 | #define RSV_HASHFILTERMATCH 33 |
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| 414 | #define RSV_MAGICPKTFILTERMATCH 34 |
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| 415 | #define RSV_PTRNMTCHFILTERMATCH 35 |
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| 416 | #define RSV_UNICASTFILTERMATCH 36 |
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| 417 | |
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| 418 | #define RSV_SIZE 8 |
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| 419 | #define RSV_BITMASK(x) (1 << ((x) - 16)) |
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| 420 | #define RSV_GETBIT(x, y) (((x) & RSV_BITMASK(y)) ? 1 : 0) |
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| 421 | |
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| 422 | struct rsv { |
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| 423 | u16 next_packet; |
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| 424 | u16 len; |
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| 425 | u32 rxstat; |
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| 426 | }; |
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| 427 | |
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| 428 | /* Put RX buffer at 0 as suggested by the Errata datasheet */ |
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| 429 | |
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| 430 | #define RXSTART_INIT ERXST_VAL |
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| 431 | #define RXEND_INIT 0x5FFF |
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| 432 | |
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| 433 | int regmap_encx24j600_spi_write(void *context, u8 reg, const u8 *data, |
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| 434 | size_t count); |
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| 435 | int regmap_encx24j600_spi_read(void *context, u8 reg, u8 *data, size_t count); |
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| 436 | |
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| 437 | |
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| 438 | #endif |
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| 439 | |
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