| 1 | /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ |
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| 2 | /* |
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| 3 | * Microsemi Ocelot Switch driver |
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| 4 | * |
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| 5 | * Copyright (c) 2017 Microsemi Corporation |
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| 6 | */ |
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| 7 | |
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| 8 | #ifndef _MSCC_OCELOT_QS_H_ |
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| 9 | #define _MSCC_OCELOT_QS_H_ |
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| 10 | |
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| 11 | /* TODO handle BE */ |
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| 12 | #define XTR_EOF_0 0x00000080U |
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| 13 | #define XTR_EOF_1 0x01000080U |
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| 14 | #define XTR_EOF_2 0x02000080U |
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| 15 | #define XTR_EOF_3 0x03000080U |
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| 16 | #define XTR_PRUNED 0x04000080U |
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| 17 | #define XTR_ABORT 0x05000080U |
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| 18 | #define XTR_ESCAPE 0x06000080U |
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| 19 | #define XTR_NOT_READY 0x07000080U |
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| 20 | #define XTR_VALID_BYTES(x) (4 - (((x) >> 24) & 3)) |
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| 21 | |
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| 22 | #define QS_XTR_GRP_CFG_RSZ 0x4 |
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| 23 | |
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| 24 | #define QS_XTR_GRP_CFG_MODE(x) (((x) << 2) & GENMASK(3, 2)) |
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| 25 | #define QS_XTR_GRP_CFG_MODE_M GENMASK(3, 2) |
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| 26 | #define QS_XTR_GRP_CFG_MODE_X(x) (((x) & GENMASK(3, 2)) >> 2) |
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| 27 | #define QS_XTR_GRP_CFG_STATUS_WORD_POS BIT(1) |
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| 28 | #define QS_XTR_GRP_CFG_BYTE_SWAP BIT(0) |
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| 29 | |
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| 30 | #define QS_XTR_RD_RSZ 0x4 |
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| 31 | |
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| 32 | #define QS_XTR_FRM_PRUNING_RSZ 0x4 |
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| 33 | |
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| 34 | #define QS_XTR_CFG_DP_WM(x) (((x) << 5) & GENMASK(7, 5)) |
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| 35 | #define QS_XTR_CFG_DP_WM_M GENMASK(7, 5) |
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| 36 | #define QS_XTR_CFG_DP_WM_X(x) (((x) & GENMASK(7, 5)) >> 5) |
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| 37 | #define QS_XTR_CFG_SCH_WM(x) (((x) << 2) & GENMASK(4, 2)) |
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| 38 | #define QS_XTR_CFG_SCH_WM_M GENMASK(4, 2) |
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| 39 | #define QS_XTR_CFG_SCH_WM_X(x) (((x) & GENMASK(4, 2)) >> 2) |
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| 40 | #define QS_XTR_CFG_OFLW_ERR_STICKY(x) ((x) & GENMASK(1, 0)) |
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| 41 | #define QS_XTR_CFG_OFLW_ERR_STICKY_M GENMASK(1, 0) |
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| 42 | |
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| 43 | #define QS_INJ_GRP_CFG_RSZ 0x4 |
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| 44 | |
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| 45 | #define QS_INJ_GRP_CFG_MODE(x) (((x) << 2) & GENMASK(3, 2)) |
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| 46 | #define QS_INJ_GRP_CFG_MODE_M GENMASK(3, 2) |
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| 47 | #define QS_INJ_GRP_CFG_MODE_X(x) (((x) & GENMASK(3, 2)) >> 2) |
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| 48 | #define QS_INJ_GRP_CFG_BYTE_SWAP BIT(0) |
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| 49 | |
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| 50 | #define QS_INJ_WR_RSZ 0x4 |
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| 51 | |
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| 52 | #define QS_INJ_CTRL_RSZ 0x4 |
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| 53 | |
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| 54 | #define QS_INJ_CTRL_GAP_SIZE(x) (((x) << 21) & GENMASK(24, 21)) |
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| 55 | #define QS_INJ_CTRL_GAP_SIZE_M GENMASK(24, 21) |
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| 56 | #define QS_INJ_CTRL_GAP_SIZE_X(x) (((x) & GENMASK(24, 21)) >> 21) |
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| 57 | #define QS_INJ_CTRL_ABORT BIT(20) |
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| 58 | #define QS_INJ_CTRL_EOF BIT(19) |
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| 59 | #define QS_INJ_CTRL_SOF BIT(18) |
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| 60 | #define QS_INJ_CTRL_VLD_BYTES(x) (((x) << 16) & GENMASK(17, 16)) |
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| 61 | #define QS_INJ_CTRL_VLD_BYTES_M GENMASK(17, 16) |
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| 62 | #define QS_INJ_CTRL_VLD_BYTES_X(x) (((x) & GENMASK(17, 16)) >> 16) |
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| 63 | |
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| 64 | #define QS_INJ_STATUS_WMARK_REACHED(x) (((x) << 4) & GENMASK(5, 4)) |
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| 65 | #define QS_INJ_STATUS_WMARK_REACHED_M GENMASK(5, 4) |
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| 66 | #define QS_INJ_STATUS_WMARK_REACHED_X(x) (((x) & GENMASK(5, 4)) >> 4) |
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| 67 | #define QS_INJ_STATUS_FIFO_RDY(x) (((x) << 2) & GENMASK(3, 2)) |
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| 68 | #define QS_INJ_STATUS_FIFO_RDY_M GENMASK(3, 2) |
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| 69 | #define QS_INJ_STATUS_FIFO_RDY_X(x) (((x) & GENMASK(3, 2)) >> 2) |
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| 70 | #define QS_INJ_STATUS_INJ_IN_PROGRESS(x) ((x) & GENMASK(1, 0)) |
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| 71 | #define QS_INJ_STATUS_INJ_IN_PROGRESS_M GENMASK(1, 0) |
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| 72 | |
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| 73 | #define QS_INJ_ERR_RSZ 0x4 |
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| 74 | |
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| 75 | #define QS_INJ_ERR_ABORT_ERR_STICKY BIT(1) |
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| 76 | #define QS_INJ_ERR_WR_ERR_STICKY BIT(0) |
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| 77 | |
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| 78 | #endif |
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| 79 | |
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