1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * Copyright (C) 2006 PA Semi, Inc |
4 | * |
5 | * Driver for the PA6T-1682M onchip 1G/10G Ethernet MACs, soft state and |
6 | * hardware register layouts. |
7 | */ |
8 | |
9 | #ifndef PASEMI_MAC_H |
10 | #define PASEMI_MAC_H |
11 | |
12 | #include <linux/ethtool.h> |
13 | #include <linux/netdevice.h> |
14 | #include <linux/spinlock.h> |
15 | #include <linux/phy.h> |
16 | |
17 | /* Must be a power of two */ |
18 | #define RX_RING_SIZE 2048 |
19 | #define TX_RING_SIZE 4096 |
20 | #define CS_RING_SIZE (TX_RING_SIZE*2) |
21 | |
22 | |
23 | #define MAX_CS 2 |
24 | |
25 | struct pasemi_mac_txring { |
26 | struct pasemi_dmachan chan; /* Must be first */ |
27 | spinlock_t lock; |
28 | unsigned int size; |
29 | unsigned int next_to_fill; |
30 | unsigned int next_to_clean; |
31 | struct pasemi_mac_buffer *ring_info; |
32 | struct pasemi_mac *mac; /* Needed in intr handler */ |
33 | struct timer_list clean_timer; |
34 | }; |
35 | |
36 | struct pasemi_mac_rxring { |
37 | struct pasemi_dmachan chan; /* Must be first */ |
38 | spinlock_t lock; |
39 | u64 *buffers; /* RX interface buffer ring */ |
40 | dma_addr_t buf_dma; |
41 | unsigned int size; |
42 | unsigned int next_to_fill; |
43 | unsigned int next_to_clean; |
44 | struct pasemi_mac_buffer *ring_info; |
45 | struct pasemi_mac *mac; /* Needed in intr handler */ |
46 | }; |
47 | |
48 | struct pasemi_mac_csring { |
49 | struct pasemi_dmachan chan; |
50 | unsigned int size; |
51 | unsigned int next_to_fill; |
52 | int events[2]; |
53 | int last_event; |
54 | int fun; |
55 | }; |
56 | |
57 | struct pasemi_mac { |
58 | struct net_device *netdev; |
59 | struct pci_dev *pdev; |
60 | struct pci_dev *dma_pdev; |
61 | struct pci_dev *iob_pdev; |
62 | struct napi_struct napi; |
63 | |
64 | int bufsz; /* RX ring buffer size */ |
65 | int last_cs; |
66 | int num_cs; |
67 | u32 dma_if; |
68 | u8 type; |
69 | #define MAC_TYPE_GMAC 1 |
70 | #define MAC_TYPE_XAUI 2 |
71 | |
72 | u8 mac_addr[ETH_ALEN]; |
73 | |
74 | struct timer_list rxtimer; |
75 | |
76 | struct pasemi_mac_txring *tx; |
77 | struct pasemi_mac_rxring *rx; |
78 | struct pasemi_mac_csring *cs[MAX_CS]; |
79 | char tx_irq_name[10]; /* "eth%d tx" */ |
80 | char rx_irq_name[10]; /* "eth%d rx" */ |
81 | int link; |
82 | int speed; |
83 | int duplex; |
84 | |
85 | unsigned int msg_enable; |
86 | }; |
87 | |
88 | /* Software status descriptor (ring_info) */ |
89 | struct pasemi_mac_buffer { |
90 | struct sk_buff *skb; |
91 | dma_addr_t dma; |
92 | }; |
93 | |
94 | #define TX_DESC(tx, num) ((tx)->chan.ring_virt[(num) & (TX_RING_SIZE-1)]) |
95 | #define TX_DESC_INFO(tx, num) ((tx)->ring_info[(num) & (TX_RING_SIZE-1)]) |
96 | #define RX_DESC(rx, num) ((rx)->chan.ring_virt[(num) & (RX_RING_SIZE-1)]) |
97 | #define RX_DESC_INFO(rx, num) ((rx)->ring_info[(num) & (RX_RING_SIZE-1)]) |
98 | #define RX_BUFF(rx, num) ((rx)->buffers[(num) & (RX_RING_SIZE-1)]) |
99 | #define CS_DESC(cs, num) ((cs)->chan.ring_virt[(num) & (CS_RING_SIZE-1)]) |
100 | |
101 | #define RING_USED(ring) (((ring)->next_to_fill - (ring)->next_to_clean) \ |
102 | & ((ring)->size - 1)) |
103 | #define RING_AVAIL(ring) ((ring->size) - RING_USED(ring)) |
104 | |
105 | /* PCI register offsets and formats */ |
106 | |
107 | |
108 | /* MAC CFG register offsets */ |
109 | enum { |
110 | PAS_MAC_CFG_PCFG = 0x80, |
111 | PAS_MAC_CFG_MACCFG = 0x84, |
112 | PAS_MAC_CFG_ADR0 = 0x8c, |
113 | PAS_MAC_CFG_ADR1 = 0x90, |
114 | PAS_MAC_CFG_TXP = 0x98, |
115 | PAS_MAC_CFG_RMON = 0x100, |
116 | PAS_MAC_IPC_CHNL = 0x208, |
117 | }; |
118 | |
119 | /* MAC CFG register fields */ |
120 | #define PAS_MAC_CFG_PCFG_PE 0x80000000 |
121 | #define PAS_MAC_CFG_PCFG_CE 0x40000000 |
122 | #define PAS_MAC_CFG_PCFG_BU 0x20000000 |
123 | #define PAS_MAC_CFG_PCFG_TT 0x10000000 |
124 | #define PAS_MAC_CFG_PCFG_TSR_M 0x0c000000 |
125 | #define PAS_MAC_CFG_PCFG_TSR_10M 0x00000000 |
126 | #define PAS_MAC_CFG_PCFG_TSR_100M 0x04000000 |
127 | #define PAS_MAC_CFG_PCFG_TSR_1G 0x08000000 |
128 | #define PAS_MAC_CFG_PCFG_TSR_10G 0x0c000000 |
129 | #define PAS_MAC_CFG_PCFG_T24 0x02000000 |
130 | #define PAS_MAC_CFG_PCFG_PR 0x01000000 |
131 | #define PAS_MAC_CFG_PCFG_CRO_M 0x00ff0000 |
132 | #define PAS_MAC_CFG_PCFG_CRO_S 16 |
133 | #define PAS_MAC_CFG_PCFG_IPO_M 0x0000ff00 |
134 | #define PAS_MAC_CFG_PCFG_IPO_S 8 |
135 | #define PAS_MAC_CFG_PCFG_S1 0x00000080 |
136 | #define PAS_MAC_CFG_PCFG_IO_M 0x00000060 |
137 | #define PAS_MAC_CFG_PCFG_IO_MAC 0x00000000 |
138 | #define PAS_MAC_CFG_PCFG_IO_OFF 0x00000020 |
139 | #define PAS_MAC_CFG_PCFG_IO_IND_ETH 0x00000040 |
140 | #define PAS_MAC_CFG_PCFG_IO_IND_IP 0x00000060 |
141 | #define PAS_MAC_CFG_PCFG_LP 0x00000010 |
142 | #define PAS_MAC_CFG_PCFG_TS 0x00000008 |
143 | #define PAS_MAC_CFG_PCFG_HD 0x00000004 |
144 | #define PAS_MAC_CFG_PCFG_SPD_M 0x00000003 |
145 | #define PAS_MAC_CFG_PCFG_SPD_10M 0x00000000 |
146 | #define PAS_MAC_CFG_PCFG_SPD_100M 0x00000001 |
147 | #define PAS_MAC_CFG_PCFG_SPD_1G 0x00000002 |
148 | #define PAS_MAC_CFG_PCFG_SPD_10G 0x00000003 |
149 | |
150 | #define PAS_MAC_CFG_MACCFG_TXT_M 0x70000000 |
151 | #define PAS_MAC_CFG_MACCFG_TXT_S 28 |
152 | #define PAS_MAC_CFG_MACCFG_PRES_M 0x0f000000 |
153 | #define PAS_MAC_CFG_MACCFG_PRES_S 24 |
154 | #define PAS_MAC_CFG_MACCFG_MAXF_M 0x00ffff00 |
155 | #define PAS_MAC_CFG_MACCFG_MAXF_S 8 |
156 | #define PAS_MAC_CFG_MACCFG_MAXF(x) (((x) << PAS_MAC_CFG_MACCFG_MAXF_S) & \ |
157 | PAS_MAC_CFG_MACCFG_MAXF_M) |
158 | #define PAS_MAC_CFG_MACCFG_MINF_M 0x000000ff |
159 | #define PAS_MAC_CFG_MACCFG_MINF_S 0 |
160 | |
161 | #define PAS_MAC_CFG_TXP_FCF 0x01000000 |
162 | #define PAS_MAC_CFG_TXP_FCE 0x00800000 |
163 | #define PAS_MAC_CFG_TXP_FC 0x00400000 |
164 | #define PAS_MAC_CFG_TXP_FPC_M 0x00300000 |
165 | #define PAS_MAC_CFG_TXP_FPC_S 20 |
166 | #define PAS_MAC_CFG_TXP_FPC(x) (((x) << PAS_MAC_CFG_TXP_FPC_S) & \ |
167 | PAS_MAC_CFG_TXP_FPC_M) |
168 | #define PAS_MAC_CFG_TXP_RT 0x00080000 |
169 | #define PAS_MAC_CFG_TXP_BL 0x00040000 |
170 | #define PAS_MAC_CFG_TXP_SL_M 0x00030000 |
171 | #define PAS_MAC_CFG_TXP_SL_S 16 |
172 | #define PAS_MAC_CFG_TXP_SL(x) (((x) << PAS_MAC_CFG_TXP_SL_S) & \ |
173 | PAS_MAC_CFG_TXP_SL_M) |
174 | #define PAS_MAC_CFG_TXP_COB_M 0x0000f000 |
175 | #define PAS_MAC_CFG_TXP_COB_S 12 |
176 | #define PAS_MAC_CFG_TXP_COB(x) (((x) << PAS_MAC_CFG_TXP_COB_S) & \ |
177 | PAS_MAC_CFG_TXP_COB_M) |
178 | #define PAS_MAC_CFG_TXP_TIFT_M 0x00000f00 |
179 | #define PAS_MAC_CFG_TXP_TIFT_S 8 |
180 | #define PAS_MAC_CFG_TXP_TIFT(x) (((x) << PAS_MAC_CFG_TXP_TIFT_S) & \ |
181 | PAS_MAC_CFG_TXP_TIFT_M) |
182 | #define PAS_MAC_CFG_TXP_TIFG_M 0x000000ff |
183 | #define PAS_MAC_CFG_TXP_TIFG_S 0 |
184 | #define PAS_MAC_CFG_TXP_TIFG(x) (((x) << PAS_MAC_CFG_TXP_TIFG_S) & \ |
185 | PAS_MAC_CFG_TXP_TIFG_M) |
186 | |
187 | #define PAS_MAC_RMON(r) (0x100+(r)*4) |
188 | |
189 | #define PAS_MAC_IPC_CHNL_DCHNO_M 0x003f0000 |
190 | #define PAS_MAC_IPC_CHNL_DCHNO_S 16 |
191 | #define PAS_MAC_IPC_CHNL_DCHNO(x) (((x) << PAS_MAC_IPC_CHNL_DCHNO_S) & \ |
192 | PAS_MAC_IPC_CHNL_DCHNO_M) |
193 | #define PAS_MAC_IPC_CHNL_BCH_M 0x0000003f |
194 | #define PAS_MAC_IPC_CHNL_BCH_S 0 |
195 | #define PAS_MAC_IPC_CHNL_BCH(x) (((x) << PAS_MAC_IPC_CHNL_BCH_S) & \ |
196 | PAS_MAC_IPC_CHNL_BCH_M) |
197 | |
198 | |
199 | #endif /* PASEMI_MAC_H */ |
200 | |