1 | /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ |
2 | /* QLogic qed NIC Driver |
3 | * Copyright (c) 2015-2017 QLogic Corporation |
4 | * Copyright (c) 2019-2020 Marvell International Ltd. |
5 | */ |
6 | |
7 | #ifndef _QED_H |
8 | #define _QED_H |
9 | |
10 | #include <linux/types.h> |
11 | #include <linux/io.h> |
12 | #include <linux/delay.h> |
13 | #include <linux/firmware.h> |
14 | #include <linux/interrupt.h> |
15 | #include <linux/list.h> |
16 | #include <linux/mutex.h> |
17 | #include <linux/pci.h> |
18 | #include <linux/slab.h> |
19 | #include <linux/string.h> |
20 | #include <linux/workqueue.h> |
21 | #include <linux/zlib.h> |
22 | #include <linux/hashtable.h> |
23 | #include <linux/qed/qed_if.h> |
24 | #include "qed_debug.h" |
25 | #include "qed_hsi.h" |
26 | #include "qed_dbg_hsi.h" |
27 | #include "qed_mfw_hsi.h" |
28 | |
29 | extern const struct qed_common_ops qed_common_ops_pass; |
30 | |
31 | #define STORM_FW_VERSION \ |
32 | ((FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) | \ |
33 | (FW_REVISION_VERSION << 8) | FW_ENGINEERING_VERSION) |
34 | |
35 | #define MAX_HWFNS_PER_DEVICE (4) |
36 | #define NAME_SIZE 16 |
37 | #define VER_SIZE 16 |
38 | |
39 | #define QED_WFQ_UNIT 100 |
40 | |
41 | #define QED_WID_SIZE (1024) |
42 | #define QED_MIN_WIDS (4) |
43 | #define QED_PF_DEMS_SIZE (4) |
44 | |
45 | #define QED_LLH_DONT_CARE 0 |
46 | |
47 | /* cau states */ |
48 | enum qed_coalescing_mode { |
49 | QED_COAL_MODE_DISABLE, |
50 | QED_COAL_MODE_ENABLE |
51 | }; |
52 | |
53 | enum qed_nvm_cmd { |
54 | QED_PUT_FILE_BEGIN = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN, |
55 | QED_PUT_FILE_DATA = DRV_MSG_CODE_NVM_PUT_FILE_DATA, |
56 | QED_NVM_WRITE_NVRAM = DRV_MSG_CODE_NVM_WRITE_NVRAM, |
57 | QED_GET_MCP_NVM_RESP = 0xFFFFFF00 |
58 | }; |
59 | |
60 | struct qed_eth_cb_ops; |
61 | struct qed_dev_info; |
62 | union qed_mcp_protocol_stats; |
63 | enum qed_mcp_protocol_type; |
64 | enum qed_mfw_tlv_type; |
65 | union qed_mfw_tlv_data; |
66 | |
67 | /* helpers */ |
68 | #define QED_MFW_GET_FIELD(name, field) \ |
69 | (((name) & (field ## _MASK)) >> (field ## _SHIFT)) |
70 | |
71 | #define QED_MFW_SET_FIELD(name, field, value) \ |
72 | do { \ |
73 | (name) &= ~(field ## _MASK); \ |
74 | (name) |= (((value) << (field ## _SHIFT)) & (field ## _MASK));\ |
75 | } while (0) |
76 | |
77 | static inline u32 qed_db_addr(u32 cid, u32 DEMS) |
78 | { |
79 | u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) | |
80 | (cid * QED_PF_DEMS_SIZE); |
81 | |
82 | return db_addr; |
83 | } |
84 | |
85 | static inline u32 qed_db_addr_vf(u32 cid, u32 DEMS) |
86 | { |
87 | u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) | |
88 | FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid); |
89 | |
90 | return db_addr; |
91 | } |
92 | |
93 | #define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \ |
94 | ((sizeof(type_name) + (u32)(1 << ((p_hwfn)->cdev->cache_shift)) - 1) & \ |
95 | ~((1 << (p_hwfn->cdev->cache_shift)) - 1)) |
96 | |
97 | #define for_each_hwfn(cdev, i) for (i = 0; i < (cdev)->num_hwfns; i++) |
98 | |
99 | #define D_TRINE(val, cond1, cond2, true1, true2, def) \ |
100 | ((val) == (cond1) ? true1 : \ |
101 | ((val) == (cond2) ? true2 : def)) |
102 | |
103 | /* forward */ |
104 | struct qed_ptt_pool; |
105 | struct qed_spq; |
106 | struct qed_sb_info; |
107 | struct qed_sb_attn_info; |
108 | struct qed_cxt_mngr; |
109 | struct qed_sb_sp_info; |
110 | struct qed_ll2_info; |
111 | struct qed_mcp_info; |
112 | struct qed_llh_info; |
113 | |
114 | struct qed_rt_data { |
115 | u32 *init_val; |
116 | bool *b_valid; |
117 | }; |
118 | |
119 | enum qed_tunn_mode { |
120 | QED_MODE_L2GENEVE_TUNN, |
121 | QED_MODE_IPGENEVE_TUNN, |
122 | QED_MODE_L2GRE_TUNN, |
123 | QED_MODE_IPGRE_TUNN, |
124 | QED_MODE_VXLAN_TUNN, |
125 | }; |
126 | |
127 | enum qed_tunn_clss { |
128 | QED_TUNN_CLSS_MAC_VLAN, |
129 | QED_TUNN_CLSS_MAC_VNI, |
130 | QED_TUNN_CLSS_INNER_MAC_VLAN, |
131 | QED_TUNN_CLSS_INNER_MAC_VNI, |
132 | QED_TUNN_CLSS_MAC_VLAN_DUAL_STAGE, |
133 | MAX_QED_TUNN_CLSS, |
134 | }; |
135 | |
136 | struct qed_tunn_update_type { |
137 | bool b_update_mode; |
138 | bool b_mode_enabled; |
139 | enum qed_tunn_clss tun_cls; |
140 | }; |
141 | |
142 | struct qed_tunn_update_udp_port { |
143 | bool b_update_port; |
144 | u16 port; |
145 | }; |
146 | |
147 | struct qed_tunnel_info { |
148 | struct qed_tunn_update_type vxlan; |
149 | struct qed_tunn_update_type l2_geneve; |
150 | struct qed_tunn_update_type ip_geneve; |
151 | struct qed_tunn_update_type l2_gre; |
152 | struct qed_tunn_update_type ip_gre; |
153 | |
154 | struct qed_tunn_update_udp_port vxlan_port; |
155 | struct qed_tunn_update_udp_port geneve_port; |
156 | |
157 | bool b_update_rx_cls; |
158 | bool b_update_tx_cls; |
159 | }; |
160 | |
161 | struct qed_tunn_start_params { |
162 | unsigned long tunn_mode; |
163 | u16 vxlan_udp_port; |
164 | u16 geneve_udp_port; |
165 | u8 update_vxlan_udp_port; |
166 | u8 update_geneve_udp_port; |
167 | u8 tunn_clss_vxlan; |
168 | u8 tunn_clss_l2geneve; |
169 | u8 tunn_clss_ipgeneve; |
170 | u8 tunn_clss_l2gre; |
171 | u8 tunn_clss_ipgre; |
172 | }; |
173 | |
174 | struct qed_tunn_update_params { |
175 | unsigned long tunn_mode_update_mask; |
176 | unsigned long tunn_mode; |
177 | u16 vxlan_udp_port; |
178 | u16 geneve_udp_port; |
179 | u8 update_rx_pf_clss; |
180 | u8 update_tx_pf_clss; |
181 | u8 update_vxlan_udp_port; |
182 | u8 update_geneve_udp_port; |
183 | u8 tunn_clss_vxlan; |
184 | u8 tunn_clss_l2geneve; |
185 | u8 tunn_clss_ipgeneve; |
186 | u8 tunn_clss_l2gre; |
187 | u8 tunn_clss_ipgre; |
188 | }; |
189 | |
190 | /* The PCI personality is not quite synonymous to protocol ID: |
191 | * 1. All personalities need CORE connections |
192 | * 2. The Ethernet personality may support also the RoCE/iWARP protocol |
193 | */ |
194 | enum qed_pci_personality { |
195 | QED_PCI_ETH, |
196 | QED_PCI_FCOE, |
197 | QED_PCI_ISCSI, |
198 | QED_PCI_NVMETCP, |
199 | QED_PCI_ETH_ROCE, |
200 | QED_PCI_ETH_IWARP, |
201 | QED_PCI_ETH_RDMA, |
202 | QED_PCI_DEFAULT, /* default in shmem */ |
203 | }; |
204 | |
205 | /* All VFs are symmetric, all counters are PF + all VFs */ |
206 | struct qed_qm_iids { |
207 | u32 cids; |
208 | u32 vf_cids; |
209 | u32 tids; |
210 | }; |
211 | |
212 | /* HW / FW resources, output of features supported below, most information |
213 | * is received from MFW. |
214 | */ |
215 | enum qed_resources { |
216 | QED_SB, |
217 | QED_L2_QUEUE, |
218 | QED_VPORT, |
219 | , |
220 | QED_PQ, |
221 | QED_RL, |
222 | QED_MAC, |
223 | QED_VLAN, |
224 | QED_RDMA_CNQ_RAM, |
225 | QED_ILT, |
226 | QED_LL2_RAM_QUEUE, |
227 | QED_LL2_CTX_QUEUE, |
228 | QED_CMDQS_CQS, |
229 | QED_RDMA_STATS_QUEUE, |
230 | QED_BDQ, |
231 | QED_MAX_RESC, |
232 | }; |
233 | |
234 | enum QED_FEATURE { |
235 | QED_PF_L2_QUE, |
236 | QED_VF, |
237 | QED_RDMA_CNQ, |
238 | QED_NVMETCP_CQ, |
239 | QED_ISCSI_CQ, |
240 | QED_FCOE_CQ, |
241 | QED_VF_L2_QUE, |
242 | QED_MAX_FEATURES, |
243 | }; |
244 | |
245 | enum qed_dev_cap { |
246 | QED_DEV_CAP_ETH, |
247 | QED_DEV_CAP_FCOE, |
248 | QED_DEV_CAP_ISCSI, |
249 | QED_DEV_CAP_ROCE, |
250 | QED_DEV_CAP_IWARP, |
251 | }; |
252 | |
253 | enum qed_wol_support { |
254 | QED_WOL_SUPPORT_NONE, |
255 | QED_WOL_SUPPORT_PME, |
256 | }; |
257 | |
258 | enum qed_db_rec_exec { |
259 | DB_REC_DRY_RUN, |
260 | DB_REC_REAL_DEAL, |
261 | DB_REC_ONCE, |
262 | }; |
263 | |
264 | struct qed_hw_info { |
265 | /* PCI personality */ |
266 | enum qed_pci_personality personality; |
267 | #define QED_IS_RDMA_PERSONALITY(dev) \ |
268 | ((dev)->hw_info.personality == QED_PCI_ETH_ROCE || \ |
269 | (dev)->hw_info.personality == QED_PCI_ETH_IWARP || \ |
270 | (dev)->hw_info.personality == QED_PCI_ETH_RDMA) |
271 | #define QED_IS_ROCE_PERSONALITY(dev) \ |
272 | ((dev)->hw_info.personality == QED_PCI_ETH_ROCE || \ |
273 | (dev)->hw_info.personality == QED_PCI_ETH_RDMA) |
274 | #define QED_IS_IWARP_PERSONALITY(dev) \ |
275 | ((dev)->hw_info.personality == QED_PCI_ETH_IWARP || \ |
276 | (dev)->hw_info.personality == QED_PCI_ETH_RDMA) |
277 | #define QED_IS_L2_PERSONALITY(dev) \ |
278 | ((dev)->hw_info.personality == QED_PCI_ETH || \ |
279 | QED_IS_RDMA_PERSONALITY(dev)) |
280 | #define QED_IS_FCOE_PERSONALITY(dev) \ |
281 | ((dev)->hw_info.personality == QED_PCI_FCOE) |
282 | #define QED_IS_ISCSI_PERSONALITY(dev) \ |
283 | ((dev)->hw_info.personality == QED_PCI_ISCSI) |
284 | #define QED_IS_NVMETCP_PERSONALITY(dev) \ |
285 | ((dev)->hw_info.personality == QED_PCI_NVMETCP) |
286 | |
287 | /* Resource Allocation scheme results */ |
288 | u32 resc_start[QED_MAX_RESC]; |
289 | u32 resc_num[QED_MAX_RESC]; |
290 | #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc]) |
291 | #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc]) |
292 | #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \ |
293 | RESC_NUM(_p_hwfn, resc)) |
294 | |
295 | u32 feat_num[QED_MAX_FEATURES]; |
296 | #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc]) |
297 | |
298 | /* Amount of traffic classes HW supports */ |
299 | u8 num_hw_tc; |
300 | |
301 | /* Amount of TCs which should be active according to DCBx or upper |
302 | * layer driver configuration. |
303 | */ |
304 | u8 num_active_tc; |
305 | |
306 | u8 offload_tc; |
307 | bool offload_tc_set; |
308 | |
309 | bool multi_tc_roce_en; |
310 | #define IS_QED_MULTI_TC_ROCE(p_hwfn) ((p_hwfn)->hw_info.multi_tc_roce_en) |
311 | |
312 | u32 concrete_fid; |
313 | u16 opaque_fid; |
314 | u16 ovlan; |
315 | u32 part_num[4]; |
316 | |
317 | unsigned char hw_mac_addr[ETH_ALEN]; |
318 | u64 node_wwn; |
319 | u64 port_wwn; |
320 | |
321 | u16 num_fcoe_conns; |
322 | |
323 | struct qed_igu_info *p_igu_info; |
324 | |
325 | u32 hw_mode; |
326 | unsigned long device_capabilities; |
327 | u16 mtu; |
328 | |
329 | enum qed_wol_support b_wol_support; |
330 | }; |
331 | |
332 | /* maximun size of read/write commands (HW limit) */ |
333 | #define DMAE_MAX_RW_SIZE 0x2000 |
334 | |
335 | struct qed_dmae_info { |
336 | /* Mutex for synchronizing access to functions */ |
337 | struct mutex mutex; |
338 | |
339 | u8 channel; |
340 | |
341 | dma_addr_t completion_word_phys_addr; |
342 | |
343 | /* The memory location where the DMAE writes the completion |
344 | * value when an operation is finished on this context. |
345 | */ |
346 | u32 *p_completion_word; |
347 | |
348 | dma_addr_t intermediate_buffer_phys_addr; |
349 | |
350 | /* An intermediate buffer for DMAE operations that use virtual |
351 | * addresses - data is DMA'd to/from this buffer and then |
352 | * memcpy'd to/from the virtual address |
353 | */ |
354 | u32 *p_intermediate_buffer; |
355 | |
356 | dma_addr_t dmae_cmd_phys_addr; |
357 | struct dmae_cmd *p_dmae_cmd; |
358 | }; |
359 | |
360 | struct qed_wfq_data { |
361 | /* when feature is configured for at least 1 vport */ |
362 | u32 min_speed; |
363 | bool configured; |
364 | }; |
365 | |
366 | struct qed_qm_info { |
367 | struct init_qm_pq_params *qm_pq_params; |
368 | struct init_qm_vport_params *qm_vport_params; |
369 | struct init_qm_port_params *qm_port_params; |
370 | u16 start_pq; |
371 | u8 start_vport; |
372 | u16 pure_lb_pq; |
373 | u16 first_ofld_pq; |
374 | u16 first_llt_pq; |
375 | u16 pure_ack_pq; |
376 | u16 ooo_pq; |
377 | u16 first_vf_pq; |
378 | u16 first_mcos_pq; |
379 | u16 first_rl_pq; |
380 | u16 num_pqs; |
381 | u16 num_vf_pqs; |
382 | u8 num_vports; |
383 | u8 max_phys_tcs_per_port; |
384 | u8 ooo_tc; |
385 | bool pf_rl_en; |
386 | bool pf_wfq_en; |
387 | bool vport_rl_en; |
388 | bool vport_wfq_en; |
389 | u8 pf_wfq; |
390 | u32 pf_rl; |
391 | struct qed_wfq_data *wfq_data; |
392 | u8 num_pf_rls; |
393 | }; |
394 | |
395 | #define QED_OVERFLOW_BIT 1 |
396 | |
397 | struct qed_db_recovery_info { |
398 | struct list_head list; |
399 | |
400 | /* Lock to protect the doorbell recovery mechanism list */ |
401 | spinlock_t lock; |
402 | bool dorq_attn; |
403 | u32 db_recovery_counter; |
404 | unsigned long overflow; |
405 | }; |
406 | |
407 | struct storm_stats { |
408 | u32 address; |
409 | u32 len; |
410 | }; |
411 | |
412 | struct qed_storm_stats { |
413 | struct storm_stats mstats; |
414 | struct storm_stats pstats; |
415 | struct storm_stats tstats; |
416 | struct storm_stats ustats; |
417 | }; |
418 | |
419 | struct qed_fw_data { |
420 | struct fw_ver_info *fw_ver_info; |
421 | const u8 *modes_tree_buf; |
422 | union init_op *init_ops; |
423 | const u32 *arr_data; |
424 | const u32 *fw_overlays; |
425 | u32 fw_overlays_len; |
426 | u32 init_ops_size; |
427 | }; |
428 | |
429 | enum qed_mf_mode_bit { |
430 | /* Supports PF-classification based on tag */ |
431 | QED_MF_OVLAN_CLSS, |
432 | |
433 | /* Supports PF-classification based on MAC */ |
434 | QED_MF_LLH_MAC_CLSS, |
435 | |
436 | /* Supports PF-classification based on protocol type */ |
437 | QED_MF_LLH_PROTO_CLSS, |
438 | |
439 | /* Requires a default PF to be set */ |
440 | QED_MF_NEED_DEF_PF, |
441 | |
442 | /* Allow LL2 to multicast/broadcast */ |
443 | QED_MF_LL2_NON_UNICAST, |
444 | |
445 | /* Allow Cross-PF [& child VFs] Tx-switching */ |
446 | QED_MF_INTER_PF_SWITCH, |
447 | |
448 | /* Unified Fabtic Port support enabled */ |
449 | QED_MF_UFP_SPECIFIC, |
450 | |
451 | /* Disable Accelerated Receive Flow Steering (aRFS) */ |
452 | QED_MF_DISABLE_ARFS, |
453 | |
454 | /* Use vlan for steering */ |
455 | QED_MF_8021Q_TAGGING, |
456 | |
457 | /* Use stag for steering */ |
458 | QED_MF_8021AD_TAGGING, |
459 | |
460 | /* Allow DSCP to TC mapping */ |
461 | QED_MF_DSCP_TO_TC_MAP, |
462 | |
463 | /* Do not insert a vlan tag with id 0 */ |
464 | QED_MF_DONT_ADD_VLAN0_TAG, |
465 | }; |
466 | |
467 | enum qed_ufp_mode { |
468 | QED_UFP_MODE_ETS, |
469 | QED_UFP_MODE_VNIC_BW, |
470 | QED_UFP_MODE_UNKNOWN |
471 | }; |
472 | |
473 | enum qed_ufp_pri_type { |
474 | QED_UFP_PRI_OS, |
475 | QED_UFP_PRI_VNIC, |
476 | QED_UFP_PRI_UNKNOWN |
477 | }; |
478 | |
479 | struct qed_ufp_info { |
480 | enum qed_ufp_pri_type pri_type; |
481 | enum qed_ufp_mode mode; |
482 | u8 tc; |
483 | }; |
484 | |
485 | enum BAR_ID { |
486 | BAR_ID_0, /* used for GRC */ |
487 | BAR_ID_1 /* Used for doorbells */ |
488 | }; |
489 | |
490 | struct qed_nvm_image_info { |
491 | u32 num_images; |
492 | struct bist_nvm_image_att *image_att; |
493 | bool valid; |
494 | }; |
495 | |
496 | enum qed_hsi_def_type { |
497 | QED_HSI_DEF_MAX_NUM_VFS, |
498 | QED_HSI_DEF_MAX_NUM_L2_QUEUES, |
499 | QED_HSI_DEF_MAX_NUM_PORTS, |
500 | QED_HSI_DEF_MAX_SB_PER_PATH, |
501 | QED_HSI_DEF_MAX_NUM_PFS, |
502 | QED_HSI_DEF_MAX_NUM_VPORTS, |
503 | , |
504 | QED_HSI_DEF_MAX_QM_TX_QUEUES, |
505 | QED_HSI_DEF_NUM_PXP_ILT_RECORDS, |
506 | QED_HSI_DEF_NUM_RDMA_STATISTIC_COUNTERS, |
507 | QED_HSI_DEF_MAX_QM_GLOBAL_RLS, |
508 | QED_HSI_DEF_MAX_PBF_CMD_LINES, |
509 | QED_HSI_DEF_MAX_BTB_BLOCKS, |
510 | QED_NUM_HSI_DEFS |
511 | }; |
512 | |
513 | struct qed_simd_fp_handler { |
514 | void *token; |
515 | void (*func)(void *cookie); |
516 | }; |
517 | |
518 | enum qed_slowpath_wq_flag { |
519 | QED_SLOWPATH_MFW_TLV_REQ, |
520 | QED_SLOWPATH_PERIODIC_DB_REC, |
521 | }; |
522 | |
523 | struct qed_hwfn { |
524 | struct qed_dev *cdev; |
525 | u8 my_id; /* ID inside the PF */ |
526 | #define IS_LEAD_HWFN(edev) (!((edev)->my_id)) |
527 | u8 rel_pf_id; /* Relative to engine*/ |
528 | u8 abs_pf_id; |
529 | #define QED_PATH_ID(_p_hwfn) \ |
530 | (QED_IS_K2((_p_hwfn)->cdev) ? 0 : ((_p_hwfn)->abs_pf_id & 1)) |
531 | u8 port_id; |
532 | bool b_active; |
533 | |
534 | u32 dp_module; |
535 | u8 dp_level; |
536 | char name[NAME_SIZE]; |
537 | |
538 | bool hw_init_done; |
539 | |
540 | u8 num_funcs_on_engine; |
541 | u8 enabled_func_idx; |
542 | |
543 | /* BAR access */ |
544 | void __iomem *regview; |
545 | void __iomem *doorbells; |
546 | u64 db_phys_addr; |
547 | unsigned long db_size; |
548 | |
549 | /* PTT pool */ |
550 | struct qed_ptt_pool *p_ptt_pool; |
551 | |
552 | /* HW info */ |
553 | struct qed_hw_info hw_info; |
554 | |
555 | /* rt_array (for init-tool) */ |
556 | struct qed_rt_data rt_data; |
557 | |
558 | /* SPQ */ |
559 | struct qed_spq *p_spq; |
560 | |
561 | /* EQ */ |
562 | struct qed_eq *p_eq; |
563 | |
564 | /* Consolidate Q*/ |
565 | struct qed_consq *p_consq; |
566 | |
567 | /* Slow-Path definitions */ |
568 | struct tasklet_struct sp_dpc; |
569 | bool b_sp_dpc_enabled; |
570 | |
571 | struct qed_ptt *p_main_ptt; |
572 | struct qed_ptt *p_dpc_ptt; |
573 | |
574 | /* PTP will be used only by the leading function. |
575 | * Usage of all PTP-apis should be synchronized as result. |
576 | */ |
577 | struct qed_ptt *p_ptp_ptt; |
578 | |
579 | struct qed_sb_sp_info *p_sp_sb; |
580 | struct qed_sb_attn_info *p_sb_attn; |
581 | |
582 | /* Protocol related */ |
583 | bool using_ll2; |
584 | struct qed_ll2_info *p_ll2_info; |
585 | struct qed_ooo_info *p_ooo_info; |
586 | struct qed_rdma_info *p_rdma_info; |
587 | struct qed_iscsi_info *p_iscsi_info; |
588 | struct qed_nvmetcp_info *p_nvmetcp_info; |
589 | struct qed_fcoe_info *p_fcoe_info; |
590 | struct qed_pf_params pf_params; |
591 | |
592 | bool b_rdma_enabled_in_prs; |
593 | u32 rdma_prs_search_reg; |
594 | |
595 | struct qed_cxt_mngr *p_cxt_mngr; |
596 | |
597 | /* Flag indicating whether interrupts are enabled or not*/ |
598 | bool b_int_enabled; |
599 | bool b_int_requested; |
600 | |
601 | /* True if the driver requests for the link */ |
602 | bool b_drv_link_init; |
603 | |
604 | struct qed_vf_iov *vf_iov_info; |
605 | struct qed_pf_iov *pf_iov_info; |
606 | struct qed_mcp_info *mcp_info; |
607 | |
608 | struct qed_dcbx_info *p_dcbx_info; |
609 | |
610 | struct qed_ufp_info ufp_info; |
611 | |
612 | struct qed_dmae_info dmae_info; |
613 | |
614 | /* QM init */ |
615 | struct qed_qm_info qm_info; |
616 | struct qed_storm_stats storm_stats; |
617 | |
618 | /* Buffer for unzipping firmware data */ |
619 | void *unzip_buf; |
620 | |
621 | struct dbg_tools_data dbg_info; |
622 | void *dbg_user_info; |
623 | struct virt_mem_desc dbg_arrays[MAX_BIN_DBG_BUFFER_TYPE]; |
624 | |
625 | /* PWM region specific data */ |
626 | u16 wid_count; |
627 | u32 dpi_size; |
628 | u32 dpi_count; |
629 | |
630 | /* This is used to calculate the doorbell address */ |
631 | u32 dpi_start_offset; |
632 | |
633 | /* If one of the following is set then EDPM shouldn't be used */ |
634 | u8 dcbx_no_edpm; |
635 | u8 db_bar_no_edpm; |
636 | |
637 | /* L2-related */ |
638 | struct qed_l2_info *p_l2_info; |
639 | |
640 | /* Mechanism for recovering from doorbell drop */ |
641 | struct qed_db_recovery_info db_recovery_info; |
642 | |
643 | /* Nvm images number and attributes */ |
644 | struct qed_nvm_image_info nvm_info; |
645 | |
646 | struct phys_mem_desc *fw_overlay_mem; |
647 | struct qed_ptt *p_arfs_ptt; |
648 | |
649 | struct qed_simd_fp_handler simd_proto_handler[64]; |
650 | |
651 | #ifdef CONFIG_QED_SRIOV |
652 | struct workqueue_struct *iov_wq; |
653 | struct delayed_work iov_task; |
654 | unsigned long iov_task_flags; |
655 | #endif |
656 | struct z_stream_s *stream; |
657 | bool slowpath_wq_active; |
658 | struct workqueue_struct *slowpath_wq; |
659 | struct delayed_work slowpath_task; |
660 | unsigned long slowpath_task_flags; |
661 | u32 periodic_db_rec_count; |
662 | }; |
663 | |
664 | struct pci_params { |
665 | int pm_cap; |
666 | |
667 | unsigned long mem_start; |
668 | unsigned long mem_end; |
669 | unsigned int irq; |
670 | u8 pf_num; |
671 | }; |
672 | |
673 | struct qed_int_param { |
674 | u32 int_mode; |
675 | u8 num_vectors; |
676 | u8 min_msix_cnt; /* for minimal functionality */ |
677 | }; |
678 | |
679 | struct qed_int_params { |
680 | struct qed_int_param in; |
681 | struct qed_int_param out; |
682 | struct msix_entry *msix_table; |
683 | bool fp_initialized; |
684 | u8 fp_msix_base; |
685 | u8 fp_msix_cnt; |
686 | u8 rdma_msix_base; |
687 | u8 rdma_msix_cnt; |
688 | }; |
689 | |
690 | struct qed_dbg_feature { |
691 | struct dentry *dentry; |
692 | u8 *dump_buf; |
693 | u32 buf_size; |
694 | u32 dumped_dwords; |
695 | }; |
696 | |
697 | struct qed_dev { |
698 | u32 dp_module; |
699 | u8 dp_level; |
700 | char name[NAME_SIZE]; |
701 | |
702 | enum qed_dev_type type; |
703 | /* Translate type/revision combo into the proper conditions */ |
704 | #define QED_IS_BB(dev) ((dev)->type == QED_DEV_TYPE_BB) |
705 | #define QED_IS_BB_B0(dev) (QED_IS_BB(dev) && CHIP_REV_IS_B0(dev)) |
706 | #define QED_IS_AH(dev) ((dev)->type == QED_DEV_TYPE_AH) |
707 | #define QED_IS_K2(dev) QED_IS_AH(dev) |
708 | |
709 | u16 vendor_id; |
710 | |
711 | u16 device_id; |
712 | #define QED_DEV_ID_MASK 0xff00 |
713 | #define QED_DEV_ID_MASK_BB 0x1600 |
714 | #define QED_DEV_ID_MASK_AH 0x8000 |
715 | |
716 | u16 chip_num; |
717 | #define CHIP_NUM_MASK 0xffff |
718 | #define CHIP_NUM_SHIFT 16 |
719 | |
720 | u16 chip_rev; |
721 | #define CHIP_REV_MASK 0xf |
722 | #define CHIP_REV_SHIFT 12 |
723 | #define CHIP_REV_IS_B0(_cdev) ((_cdev)->chip_rev == 1) |
724 | |
725 | u16 chip_metal; |
726 | #define CHIP_METAL_MASK 0xff |
727 | #define CHIP_METAL_SHIFT 4 |
728 | |
729 | u16 chip_bond_id; |
730 | #define CHIP_BOND_ID_MASK 0xf |
731 | #define CHIP_BOND_ID_SHIFT 0 |
732 | |
733 | u8 num_engines; |
734 | u8 num_ports; |
735 | u8 num_ports_in_engine; |
736 | u8 num_funcs_in_port; |
737 | |
738 | u8 path_id; |
739 | |
740 | unsigned long mf_bits; |
741 | |
742 | int pcie_width; |
743 | int pcie_speed; |
744 | |
745 | /* Add MF related configuration */ |
746 | u8 mcp_rev; |
747 | u8 boot_mode; |
748 | |
749 | /* WoL related configurations */ |
750 | u8 wol_config; |
751 | u8 wol_mac[ETH_ALEN]; |
752 | |
753 | u32 int_mode; |
754 | enum qed_coalescing_mode int_coalescing_mode; |
755 | u16 rx_coalesce_usecs; |
756 | u16 tx_coalesce_usecs; |
757 | |
758 | /* Start Bar offset of first hwfn */ |
759 | void __iomem *regview; |
760 | void __iomem *doorbells; |
761 | u64 db_phys_addr; |
762 | unsigned long db_size; |
763 | |
764 | /* PCI */ |
765 | u8 cache_shift; |
766 | |
767 | /* Init */ |
768 | const u32 *iro_arr; |
769 | #define IRO ((const struct iro *)p_hwfn->cdev->iro_arr) |
770 | |
771 | /* HW functions */ |
772 | u8 num_hwfns; |
773 | struct qed_hwfn hwfns[MAX_HWFNS_PER_DEVICE]; |
774 | |
775 | /* Engine affinity */ |
776 | u8 l2_affin_hint; |
777 | u8 fir_affin; |
778 | u8 iwarp_affin; |
779 | |
780 | /* SRIOV */ |
781 | struct qed_hw_sriov_info *p_iov_info; |
782 | #define IS_QED_SRIOV(cdev) (!!(cdev)->p_iov_info) |
783 | struct qed_tunnel_info tunnel; |
784 | bool b_is_vf; |
785 | u32 drv_type; |
786 | struct qed_eth_stats *reset_stats; |
787 | struct qed_fw_data *fw_data; |
788 | |
789 | u32 mcp_nvm_resp; |
790 | |
791 | /* Recovery */ |
792 | bool recov_in_prog; |
793 | |
794 | /* Indicates whether should prevent attentions from being reasserted */ |
795 | bool attn_clr_en; |
796 | |
797 | /* LLH info */ |
798 | u8 ppfid_bitmap; |
799 | struct qed_llh_info *p_llh_info; |
800 | |
801 | /* Linux specific here */ |
802 | struct qed_dev_info common_dev_info; |
803 | struct qede_dev *edev; |
804 | struct pci_dev *pdev; |
805 | u32 flags; |
806 | #define QED_FLAG_STORAGE_STARTED (BIT(0)) |
807 | int msg_enable; |
808 | |
809 | struct pci_params pci_params; |
810 | |
811 | struct qed_int_params int_params; |
812 | |
813 | u8 protocol; |
814 | #define IS_QED_ETH_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_ETH) |
815 | #define IS_QED_FCOE_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_FCOE) |
816 | |
817 | /* Callbacks to protocol driver */ |
818 | union { |
819 | struct qed_common_cb_ops *common; |
820 | struct qed_eth_cb_ops *eth; |
821 | struct qed_fcoe_cb_ops *fcoe; |
822 | struct qed_iscsi_cb_ops *iscsi; |
823 | struct qed_nvmetcp_cb_ops *nvmetcp; |
824 | } protocol_ops; |
825 | void *ops_cookie; |
826 | |
827 | #ifdef CONFIG_QED_LL2 |
828 | struct qed_cb_ll2_info *ll2; |
829 | u8 ll2_mac_address[ETH_ALEN]; |
830 | #endif |
831 | struct qed_dbg_feature dbg_features[DBG_FEATURE_NUM]; |
832 | u8 engine_for_debug; |
833 | bool disable_ilt_dump; |
834 | bool dbg_bin_dump; |
835 | |
836 | DECLARE_HASHTABLE(connections, 10); |
837 | const struct firmware *firmware; |
838 | |
839 | bool print_dbg_data; |
840 | |
841 | u32 rdma_max_sge; |
842 | u32 rdma_max_inline; |
843 | u32 rdma_max_srq_sge; |
844 | u16 tunn_feature_mask; |
845 | |
846 | bool iwarp_cmt; |
847 | }; |
848 | |
849 | u32 qed_get_hsi_def_val(struct qed_dev *cdev, enum qed_hsi_def_type type); |
850 | |
851 | #define NUM_OF_VFS(dev) \ |
852 | qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_NUM_VFS) |
853 | #define NUM_OF_L2_QUEUES(dev) \ |
854 | qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_NUM_L2_QUEUES) |
855 | #define NUM_OF_PORTS(dev) \ |
856 | qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_NUM_PORTS) |
857 | #define NUM_OF_SBS(dev) \ |
858 | qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_SB_PER_PATH) |
859 | #define NUM_OF_ENG_PFS(dev) \ |
860 | qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_NUM_PFS) |
861 | #define NUM_OF_VPORTS(dev) \ |
862 | qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_NUM_VPORTS) |
863 | #define (dev) \ |
864 | qed_get_hsi_def_val(dev, QED_HSI_DEF_NUM_ETH_RSS_ENGINE) |
865 | #define NUM_OF_QM_TX_QUEUES(dev) \ |
866 | qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_QM_TX_QUEUES) |
867 | #define NUM_OF_PXP_ILT_RECORDS(dev) \ |
868 | qed_get_hsi_def_val(dev, QED_HSI_DEF_NUM_PXP_ILT_RECORDS) |
869 | #define NUM_OF_RDMA_STATISTIC_COUNTERS(dev) \ |
870 | qed_get_hsi_def_val(dev, QED_HSI_DEF_NUM_RDMA_STATISTIC_COUNTERS) |
871 | #define NUM_OF_QM_GLOBAL_RLS(dev) \ |
872 | qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_QM_GLOBAL_RLS) |
873 | #define NUM_OF_PBF_CMD_LINES(dev) \ |
874 | qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_PBF_CMD_LINES) |
875 | #define NUM_OF_BTB_BLOCKS(dev) \ |
876 | qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_BTB_BLOCKS) |
877 | |
878 | /** |
879 | * qed_concrete_to_sw_fid(): Get the sw function id from |
880 | * the concrete value. |
881 | * |
882 | * @cdev: Qed dev pointer. |
883 | * @concrete_fid: Concrete fid. |
884 | * |
885 | * Return: inline u8. |
886 | */ |
887 | static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev, |
888 | u32 concrete_fid) |
889 | { |
890 | u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID); |
891 | u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID); |
892 | u8 vf_valid = GET_FIELD(concrete_fid, |
893 | PXP_CONCRETE_FID_VFVALID); |
894 | u8 sw_fid; |
895 | |
896 | if (vf_valid) |
897 | sw_fid = vfid + MAX_NUM_PFS; |
898 | else |
899 | sw_fid = pfid; |
900 | |
901 | return sw_fid; |
902 | } |
903 | |
904 | #define PKT_LB_TC 9 |
905 | |
906 | int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate); |
907 | void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, |
908 | struct qed_ptt *p_ptt, |
909 | u32 min_pf_rate); |
910 | |
911 | void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); |
912 | void qed_set_fw_mac_addr(__le16 *fw_msb, |
913 | __le16 *fw_mid, __le16 *fw_lsb, u8 *mac); |
914 | |
915 | #define QED_LEADING_HWFN(dev) (&(dev)->hwfns[0]) |
916 | #define QED_IS_CMT(dev) ((dev)->num_hwfns > 1) |
917 | /* Macros for getting the engine-affinitized hwfn (FIR: fcoe,iscsi,roce) */ |
918 | #define QED_FIR_AFFIN_HWFN(dev) (&(dev)->hwfns[dev->fir_affin]) |
919 | #define QED_IWARP_AFFIN_HWFN(dev) (&(dev)->hwfns[dev->iwarp_affin]) |
920 | #define QED_AFFIN_HWFN(dev) \ |
921 | (QED_IS_IWARP_PERSONALITY(QED_LEADING_HWFN(dev)) ? \ |
922 | QED_IWARP_AFFIN_HWFN(dev) : QED_FIR_AFFIN_HWFN(dev)) |
923 | #define QED_AFFIN_HWFN_IDX(dev) (IS_LEAD_HWFN(QED_AFFIN_HWFN(dev)) ? 0 : 1) |
924 | |
925 | /* Flags for indication of required queues */ |
926 | #define PQ_FLAGS_RLS (BIT(0)) |
927 | #define PQ_FLAGS_MCOS (BIT(1)) |
928 | #define PQ_FLAGS_LB (BIT(2)) |
929 | #define PQ_FLAGS_OOO (BIT(3)) |
930 | #define PQ_FLAGS_ACK (BIT(4)) |
931 | #define PQ_FLAGS_OFLD (BIT(5)) |
932 | #define PQ_FLAGS_VFS (BIT(6)) |
933 | #define PQ_FLAGS_LLT (BIT(7)) |
934 | #define PQ_FLAGS_MTC (BIT(8)) |
935 | |
936 | /* physical queue index for cm context initialization */ |
937 | u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags); |
938 | u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc); |
939 | u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf); |
940 | u16 qed_get_cm_pq_idx_ofld_mtc(struct qed_hwfn *p_hwfn, u8 tc); |
941 | u16 qed_get_cm_pq_idx_llt_mtc(struct qed_hwfn *p_hwfn, u8 tc); |
942 | |
943 | /* doorbell recovery mechanism */ |
944 | void qed_db_recovery_dp(struct qed_hwfn *p_hwfn); |
945 | void qed_db_recovery_execute(struct qed_hwfn *p_hwfn); |
946 | bool qed_edpm_enabled(struct qed_hwfn *p_hwfn); |
947 | |
948 | #define GET_GTT_REG_ADDR(__base, __offset, __idx) \ |
949 | ((__base) + __offset ## _GTT_OFFSET((__idx))) |
950 | |
951 | #define GET_GTT_BDQ_REG_ADDR(__base, __offset, __idx, __bdq_idx) \ |
952 | ((__base) + __offset ## _GTT_OFFSET((__idx), (__bdq_idx))) |
953 | |
954 | /* Other Linux specific common definitions */ |
955 | #define DP_NAME(cdev) ((cdev)->name) |
956 | |
957 | #define REG_ADDR(cdev, offset) ((void __iomem *)((u8 __iomem *)\ |
958 | ((cdev)->regview) + \ |
959 | (offset))) |
960 | |
961 | #define REG_RD(cdev, offset) readl(REG_ADDR(cdev, offset)) |
962 | #define REG_WR(cdev, offset, val) writel((u32)val, REG_ADDR(cdev, offset)) |
963 | #define REG_WR16(cdev, offset, val) writew((u16)val, REG_ADDR(cdev, offset)) |
964 | |
965 | #define DOORBELL(cdev, db_addr, val) \ |
966 | writel((u32)val, (void __iomem *)((u8 __iomem *)\ |
967 | ((cdev)->doorbells) + (db_addr))) |
968 | |
969 | #define MFW_PORT(_p_hwfn) ((_p_hwfn)->abs_pf_id % \ |
970 | qed_device_num_ports((_p_hwfn)->cdev)) |
971 | int qed_device_num_ports(struct qed_dev *cdev); |
972 | |
973 | /* Prototypes */ |
974 | int qed_fill_dev_info(struct qed_dev *cdev, |
975 | struct qed_dev_info *dev_info); |
976 | void qed_link_update(struct qed_hwfn *hwfn, struct qed_ptt *ptt); |
977 | void qed_bw_update(struct qed_hwfn *hwfn, struct qed_ptt *ptt); |
978 | u32 qed_unzip_data(struct qed_hwfn *p_hwfn, |
979 | u32 input_len, u8 *input_buf, |
980 | u32 max_size, u8 *unzip_buf); |
981 | int qed_recovery_process(struct qed_dev *cdev); |
982 | void qed_schedule_recovery_handler(struct qed_hwfn *p_hwfn); |
983 | void qed_hw_error_occurred(struct qed_hwfn *p_hwfn, |
984 | enum qed_hw_err_type err_type); |
985 | void qed_get_protocol_stats(struct qed_dev *cdev, |
986 | enum qed_mcp_protocol_type type, |
987 | union qed_mcp_protocol_stats *stats); |
988 | int qed_slowpath_irq_req(struct qed_hwfn *hwfn); |
989 | void qed_slowpath_irq_sync(struct qed_hwfn *p_hwfn); |
990 | int qed_mfw_tlv_req(struct qed_hwfn *hwfn); |
991 | |
992 | int qed_mfw_fill_tlv_data(struct qed_hwfn *hwfn, |
993 | enum qed_mfw_tlv_type type, |
994 | union qed_mfw_tlv_data *tlv_data); |
995 | |
996 | void qed_hw_info_set_offload_tc(struct qed_hw_info *p_info, u8 tc); |
997 | |
998 | void qed_periodic_db_rec_start(struct qed_hwfn *p_hwfn); |
999 | |
1000 | int qed_llh_add_src_tcp_port_filter(struct qed_dev *cdev, u16 src_port); |
1001 | int qed_llh_add_dst_tcp_port_filter(struct qed_dev *cdev, u16 dest_port); |
1002 | void qed_llh_remove_src_tcp_port_filter(struct qed_dev *cdev, u16 src_port); |
1003 | void qed_llh_remove_dst_tcp_port_filter(struct qed_dev *cdev, u16 src_port); |
1004 | void qed_llh_clear_all_filters(struct qed_dev *cdev); |
1005 | unsigned long qed_get_epoch_time(void); |
1006 | #endif /* _QED_H */ |
1007 | |