1	// SPDX-License-Identifier: GPL-2.0-or-later
2	/*
3	* QLogic QLA3xxx NIC HBA Driver
4	* Copyright (c) 2003-2006 QLogic Corporation
5	*/
6
7	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
8
9	#include <linux/kernel.h>
10	#include <linux/types.h>
11	#include <linux/module.h>
12	#include <linux/list.h>
13	#include <linux/pci.h>
14	#include <linux/dma-mapping.h>
15	#include <linux/sched.h>
16	#include <linux/slab.h>
17	#include <linux/dmapool.h>
18	#include <linux/mempool.h>
19	#include <linux/spinlock.h>
20	#include <linux/kthread.h>
21	#include <linux/interrupt.h>
22	#include <linux/errno.h>
23	#include <linux/ioport.h>
24	#include <linux/ip.h>
25	#include <linux/in.h>
26	#include <linux/if_arp.h>
27	#include <linux/if_ether.h>
28	#include <linux/netdevice.h>
29	#include <linux/etherdevice.h>
30	#include <linux/ethtool.h>
31	#include <linux/skbuff.h>
32	#include <linux/rtnetlink.h>
33	#include <linux/if_vlan.h>
34	#include <linux/delay.h>
35	#include <linux/mm.h>
36	#include <linux/prefetch.h>
37
38	#include "qla3xxx.h"
39
40	#define DRV_NAME "qla3xxx"
41	#define DRV_STRING "QLogic ISP3XXX Network Driver"
42	#define DRV_VERSION "v2.03.00-k5"
43
44	static const char ql3xxx_driver_name[] = DRV_NAME;
45	static const char ql3xxx_driver_version[] = DRV_VERSION;
46
47	#define TIMED_OUT_MSG \
48	"Timed out waiting for management port to get free before issuing command\n"
49
50	MODULE_AUTHOR("QLogic Corporation");
51	MODULE_DESCRIPTION("QLogic ISP3XXX Network Driver " DRV_VERSION " ");
52	MODULE_LICENSE("GPL");
53	MODULE_VERSION(DRV_VERSION);
54
55	static const u32 default_msg
56	= NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
57	| NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
58
59	static int debug = -1; /* defaults above */
60	module_param(debug, int, 0);
61	MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
62
63	static int msi;
64	module_param(msi, int, 0);
65	MODULE_PARM_DESC(msi, "Turn on Message Signaled Interrupts.");
66
67	static const struct pci_device_id ql3xxx_pci_tbl[] = {
68	{PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3022_DEVICE_ID)},
69	{PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3032_DEVICE_ID)},
70	/* required last entry */
71	{0,}
72	};
73
74	MODULE_DEVICE_TABLE(pci, ql3xxx_pci_tbl);
75
76	/*
77	* These are the known PHY's which are used
78	*/
79	enum PHY_DEVICE_TYPE {
80	PHY_TYPE_UNKNOWN = 0,
81	PHY_VITESSE_VSC8211,
82	PHY_AGERE_ET1011C,
83	MAX_PHY_DEV_TYPES
84	};
85
86	struct PHY_DEVICE_INFO {
87	const enum PHY_DEVICE_TYPE phyDevice;
88	const u32 phyIdOUI;
89	const u16 phyIdModel;
90	const char *name;
91	};
92
93	static const struct PHY_DEVICE_INFO PHY_DEVICES[] = {
94	{PHY_TYPE_UNKNOWN, 0x000000, 0x0, "PHY_TYPE_UNKNOWN"},
95	{PHY_VITESSE_VSC8211, 0x0003f1, 0xb, "PHY_VITESSE_VSC8211"},
96	{PHY_AGERE_ET1011C, 0x00a0bc, 0x1, "PHY_AGERE_ET1011C"},
97	};
98
99
100	/*
101	* Caller must take hw_lock.
102	*/
103	static int ql_sem_spinlock(struct ql3_adapter *qdev,
104	u32 sem_mask, u32 sem_bits)
105	{
106	struct ql3xxx_port_registers __iomem *port_regs =
107	qdev->mem_map_registers;
108	u32 value;
109	unsigned int seconds = 3;
110
111	do {
112	writel(val: (sem_mask | sem_bits),
113	addr: &port_regs->CommonRegs.semaphoreReg);
114	value = readl(addr: &port_regs->CommonRegs.semaphoreReg);
115	if ((value & (sem_mask >> 16)) == sem_bits)
116	return 0;
117	mdelay(1000);
118	} while (--seconds);
119	return -1;
120	}
121
122	static void ql_sem_unlock(struct ql3_adapter *qdev, u32 sem_mask)
123	{
124	struct ql3xxx_port_registers __iomem *port_regs =
125	qdev->mem_map_registers;
126	writel(val: sem_mask, addr: &port_regs->CommonRegs.semaphoreReg);
127	readl(addr: &port_regs->CommonRegs.semaphoreReg);
128	}
129
130	static int ql_sem_lock(struct ql3_adapter *qdev, u32 sem_mask, u32 sem_bits)
131	{
132	struct ql3xxx_port_registers __iomem *port_regs =
133	qdev->mem_map_registers;
134	u32 value;
135
136	writel(val: (sem_mask | sem_bits), addr: &port_regs->CommonRegs.semaphoreReg);
137	value = readl(addr: &port_regs->CommonRegs.semaphoreReg);
138	return ((value & (sem_mask >> 16)) == sem_bits);
139	}
140
141	/*
142	* Caller holds hw_lock.
143	*/
144	static int ql_wait_for_drvr_lock(struct ql3_adapter *qdev)
145	{
146	int i = 0;
147
148	do {
149	if (ql_sem_lock(qdev,
150	sem_mask: QL_DRVR_SEM_MASK,
151	sem_bits: (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
152	* 2) << 1)) {
153	netdev_printk(KERN_DEBUG, dev: qdev->ndev,
154	format: "driver lock acquired\n");
155	return 1;
156	}
157	mdelay(1000);
158	} while (++i < 10);
159
160	netdev_err(dev: qdev->ndev, format: "Timed out waiting for driver lock...\n");
161	return 0;
162	}
163
164	static void ql_set_register_page(struct ql3_adapter *qdev, u32 page)
165	{
166	struct ql3xxx_port_registers __iomem *port_regs =
167	qdev->mem_map_registers;
168
169	writel(val: ((ISP_CONTROL_NP_MASK << 16) | page),
170	addr: &port_regs->CommonRegs.ispControlStatus);
171	readl(addr: &port_regs->CommonRegs.ispControlStatus);
172	qdev->current_page = page;
173	}
174
175	static u32 ql_read_common_reg_l(struct ql3_adapter *qdev, u32 __iomem *reg)
176	{
177	u32 value;
178	unsigned long hw_flags;
179
180	spin_lock_irqsave(&qdev->hw_lock, hw_flags);
181	value = readl(addr: reg);
182	spin_unlock_irqrestore(lock: &qdev->hw_lock, flags: hw_flags);
183
184	return value;
185	}
186
187	static u32 ql_read_common_reg(struct ql3_adapter *qdev, u32 __iomem *reg)
188	{
189	return readl(addr: reg);
190	}
191
192	static u32 ql_read_page0_reg_l(struct ql3_adapter *qdev, u32 __iomem *reg)
193	{
194	u32 value;
195	unsigned long hw_flags;
196
197	spin_lock_irqsave(&qdev->hw_lock, hw_flags);
198
199	if (qdev->current_page != 0)
200	ql_set_register_page(qdev, page: 0);
201	value = readl(addr: reg);
202
203	spin_unlock_irqrestore(lock: &qdev->hw_lock, flags: hw_flags);
204	return value;
205	}
206
207	static u32 ql_read_page0_reg(struct ql3_adapter *qdev, u32 __iomem *reg)
208	{
209	if (qdev->current_page != 0)
210	ql_set_register_page(qdev, page: 0);
211	return readl(addr: reg);
212	}
213
214	static void ql_write_common_reg_l(struct ql3_adapter *qdev,
215	u32 __iomem *reg, u32 value)
216	{
217	unsigned long hw_flags;
218
219	spin_lock_irqsave(&qdev->hw_lock, hw_flags);
220	writel(val: value, addr: reg);
221	readl(addr: reg);
222	spin_unlock_irqrestore(lock: &qdev->hw_lock, flags: hw_flags);
223	}
224
225	static void ql_write_common_reg(struct ql3_adapter *qdev,
226	u32 __iomem *reg, u32 value)
227	{
228	writel(val: value, addr: reg);
229	readl(addr: reg);
230	}
231
232	static void ql_write_nvram_reg(struct ql3_adapter *qdev,
233	u32 __iomem *reg, u32 value)
234	{
235	writel(val: value, addr: reg);
236	readl(addr: reg);
237	udelay(1);
238	}
239
240	static void ql_write_page0_reg(struct ql3_adapter *qdev,
241	u32 __iomem *reg, u32 value)
242	{
243	if (qdev->current_page != 0)
244	ql_set_register_page(qdev, page: 0);
245	writel(val: value, addr: reg);
246	readl(addr: reg);
247	}
248
249	/*
250	* Caller holds hw_lock. Only called during init.
251	*/
252	static void ql_write_page1_reg(struct ql3_adapter *qdev,
253	u32 __iomem *reg, u32 value)
254	{
255	if (qdev->current_page != 1)
256	ql_set_register_page(qdev, page: 1);
257	writel(val: value, addr: reg);
258	readl(addr: reg);
259	}
260
261	/*
262	* Caller holds hw_lock. Only called during init.
263	*/
264	static void ql_write_page2_reg(struct ql3_adapter *qdev,
265	u32 __iomem *reg, u32 value)
266	{
267	if (qdev->current_page != 2)
268	ql_set_register_page(qdev, page: 2);
269	writel(val: value, addr: reg);
270	readl(addr: reg);
271	}
272
273	static void ql_disable_interrupts(struct ql3_adapter *qdev)
274	{
275	struct ql3xxx_port_registers __iomem *port_regs =
276	qdev->mem_map_registers;
277
278	ql_write_common_reg_l(qdev, reg: &port_regs->CommonRegs.ispInterruptMaskReg,
279	value: (ISP_IMR_ENABLE_INT << 16));
280
281	}
282
283	static void ql_enable_interrupts(struct ql3_adapter *qdev)
284	{
285	struct ql3xxx_port_registers __iomem *port_regs =
286	qdev->mem_map_registers;
287
288	ql_write_common_reg_l(qdev, reg: &port_regs->CommonRegs.ispInterruptMaskReg,
289	value: ((0xff << 16) | ISP_IMR_ENABLE_INT));
290
291	}
292
293	static void ql_release_to_lrg_buf_free_list(struct ql3_adapter *qdev,
294	struct ql_rcv_buf_cb *lrg_buf_cb)
295	{
296	dma_addr_t map;
297	int err;
298	lrg_buf_cb->next = NULL;
299
300	if (qdev->lrg_buf_free_tail == NULL) { /* The list is empty */
301	qdev->lrg_buf_free_head = qdev->lrg_buf_free_tail = lrg_buf_cb;
302	} else {
303	qdev->lrg_buf_free_tail->next = lrg_buf_cb;
304	qdev->lrg_buf_free_tail = lrg_buf_cb;
305	}
306
307	if (!lrg_buf_cb->skb) {
308	lrg_buf_cb->skb = netdev_alloc_skb(dev: qdev->ndev,
309	length: qdev->lrg_buffer_len);
310	if (unlikely(!lrg_buf_cb->skb)) {
311	qdev->lrg_buf_skb_check++;
312	} else {
313	/*
314	* We save some space to copy the ethhdr from first
315	* buffer
316	*/
317	skb_reserve(skb: lrg_buf_cb->skb, QL_HEADER_SPACE);
318	map = dma_map_single(&qdev->pdev->dev,
319	lrg_buf_cb->skb->data,
320	qdev->lrg_buffer_len - QL_HEADER_SPACE,
321	DMA_FROM_DEVICE);
322	err = dma_mapping_error(dev: &qdev->pdev->dev, dma_addr: map);
323	if (err) {
324	netdev_err(dev: qdev->ndev,
325	format: "PCI mapping failed with error: %d\n",
326	err);
327	dev_kfree_skb(lrg_buf_cb->skb);
328	lrg_buf_cb->skb = NULL;
329
330	qdev->lrg_buf_skb_check++;
331	return;
332	}
333
334	lrg_buf_cb->buf_phy_addr_low =
335	cpu_to_le32(LS_64BITS(map));
336	lrg_buf_cb->buf_phy_addr_high =
337	cpu_to_le32(MS_64BITS(map));
338	dma_unmap_addr_set(lrg_buf_cb, mapaddr, map);
339	dma_unmap_len_set(lrg_buf_cb, maplen,
340	qdev->lrg_buffer_len -
341	QL_HEADER_SPACE);
342	}
343	}
344
345	qdev->lrg_buf_free_count++;
346	}
347
348	static struct ql_rcv_buf_cb *ql_get_from_lrg_buf_free_list(struct ql3_adapter
349	*qdev)
350	{
351	struct ql_rcv_buf_cb *lrg_buf_cb = qdev->lrg_buf_free_head;
352
353	if (lrg_buf_cb != NULL) {
354	qdev->lrg_buf_free_head = lrg_buf_cb->next;
355	if (qdev->lrg_buf_free_head == NULL)
356	qdev->lrg_buf_free_tail = NULL;
357	qdev->lrg_buf_free_count--;
358	}
359
360	return lrg_buf_cb;
361	}
362
363	static u32 addrBits = EEPROM_NO_ADDR_BITS;
364	static u32 dataBits = EEPROM_NO_DATA_BITS;
365
366	static void fm93c56a_deselect(struct ql3_adapter *qdev);
367	static void eeprom_readword(struct ql3_adapter *qdev, u32 eepromAddr,
368	unsigned short *value);
369
370	/*
371	* Caller holds hw_lock.
372	*/
373	static void fm93c56a_select(struct ql3_adapter *qdev)
374	{
375	struct ql3xxx_port_registers __iomem *port_regs =
376	qdev->mem_map_registers;
377	__iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
378
379	qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_1;
380	ql_write_nvram_reg(qdev, reg: spir, value: ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
381	}
382
383	/*
384	* Caller holds hw_lock.
385	*/
386	static void fm93c56a_cmd(struct ql3_adapter *qdev, u32 cmd, u32 eepromAddr)
387	{
388	int i;
389	u32 mask;
390	u32 dataBit;
391	u32 previousBit;
392	struct ql3xxx_port_registers __iomem *port_regs =
393	qdev->mem_map_registers;
394	__iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
395
396	/* Clock in a zero, then do the start bit */
397	ql_write_nvram_reg(qdev, reg: spir,
398	value: (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
399	AUBURN_EEPROM_DO_1));
400	ql_write_nvram_reg(qdev, reg: spir,
401	value: (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
402	AUBURN_EEPROM_DO_1 | AUBURN_EEPROM_CLK_RISE));
403	ql_write_nvram_reg(qdev, reg: spir,
404	value: (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
405	AUBURN_EEPROM_DO_1 | AUBURN_EEPROM_CLK_FALL));
406
407	mask = 1 << (FM93C56A_CMD_BITS - 1);
408	/* Force the previous data bit to be different */
409	previousBit = 0xffff;
410	for (i = 0; i < FM93C56A_CMD_BITS; i++) {
411	dataBit = (cmd & mask)
412	? AUBURN_EEPROM_DO_1
413	: AUBURN_EEPROM_DO_0;
414	if (previousBit != dataBit) {
415	/* If the bit changed, change the DO state to match */
416	ql_write_nvram_reg(qdev, reg: spir,
417	value: (ISP_NVRAM_MASK |
418	qdev->eeprom_cmd_data | dataBit));
419	previousBit = dataBit;
420	}
421	ql_write_nvram_reg(qdev, reg: spir,
422	value: (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
423	dataBit | AUBURN_EEPROM_CLK_RISE));
424	ql_write_nvram_reg(qdev, reg: spir,
425	value: (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
426	dataBit | AUBURN_EEPROM_CLK_FALL));
427	cmd = cmd << 1;
428	}
429
430	mask = 1 << (addrBits - 1);
431	/* Force the previous data bit to be different */
432	previousBit = 0xffff;
433	for (i = 0; i < addrBits; i++) {
434	dataBit = (eepromAddr & mask) ? AUBURN_EEPROM_DO_1
435	: AUBURN_EEPROM_DO_0;
436	if (previousBit != dataBit) {
437	/*
438	* If the bit changed, then change the DO state to
439	* match
440	*/
441	ql_write_nvram_reg(qdev, reg: spir,
442	value: (ISP_NVRAM_MASK |
443	qdev->eeprom_cmd_data | dataBit));
444	previousBit = dataBit;
445	}
446	ql_write_nvram_reg(qdev, reg: spir,
447	value: (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
448	dataBit | AUBURN_EEPROM_CLK_RISE));
449	ql_write_nvram_reg(qdev, reg: spir,
450	value: (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
451	dataBit | AUBURN_EEPROM_CLK_FALL));
452	eepromAddr = eepromAddr << 1;
453	}
454	}
455
456	/*
457	* Caller holds hw_lock.
458	*/
459	static void fm93c56a_deselect(struct ql3_adapter *qdev)
460	{
461	struct ql3xxx_port_registers __iomem *port_regs =
462	qdev->mem_map_registers;
463	__iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
464
465	qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_0;
466	ql_write_nvram_reg(qdev, reg: spir, value: ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
467	}
468
469	/*
470	* Caller holds hw_lock.
471	*/
472	static void fm93c56a_datain(struct ql3_adapter *qdev, unsigned short *value)
473	{
474	int i;
475	u32 data = 0;
476	u32 dataBit;
477	struct ql3xxx_port_registers __iomem *port_regs =
478	qdev->mem_map_registers;
479	__iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
480
481	/* Read the data bits */
482	/* The first bit is a dummy. Clock right over it. */
483	for (i = 0; i < dataBits; i++) {
484	ql_write_nvram_reg(qdev, reg: spir,
485	value: ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
486	AUBURN_EEPROM_CLK_RISE);
487	ql_write_nvram_reg(qdev, reg: spir,
488	value: ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
489	AUBURN_EEPROM_CLK_FALL);
490	dataBit = (ql_read_common_reg(qdev, reg: spir) &
491	AUBURN_EEPROM_DI_1) ? 1 : 0;
492	data = (data << 1) | dataBit;
493	}
494	*value = (u16)data;
495	}
496
497	/*
498	* Caller holds hw_lock.
499	*/
500	static void eeprom_readword(struct ql3_adapter *qdev,
501	u32 eepromAddr, unsigned short *value)
502	{
503	fm93c56a_select(qdev);
504	fm93c56a_cmd(qdev, cmd: (int)FM93C56A_READ, eepromAddr);
505	fm93c56a_datain(qdev, value);
506	fm93c56a_deselect(qdev);
507	}
508
509	static void ql_set_mac_addr(struct net_device *ndev, u16 *addr)
510	{
511	__le16 buf[ETH_ALEN / 2];
512
513	buf[0] = cpu_to_le16(addr[0]);
514	buf[1] = cpu_to_le16(addr[1]);
515	buf[2] = cpu_to_le16(addr[2]);
516	eth_hw_addr_set(dev: ndev, addr: (u8 *)buf);
517	}
518
519	static int ql_get_nvram_params(struct ql3_adapter *qdev)
520	{
521	u16 *pEEPROMData;
522	u16 checksum = 0;
523	u32 index;
524	unsigned long hw_flags;
525
526	spin_lock_irqsave(&qdev->hw_lock, hw_flags);
527
528	pEEPROMData = (u16 *)&qdev->nvram_data;
529	qdev->eeprom_cmd_data = 0;
530	if (ql_sem_spinlock(qdev, sem_mask: QL_NVRAM_SEM_MASK,
531	sem_bits: (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
532	2) << 10)) {
533	pr_err("%s: Failed ql_sem_spinlock()\n", __func__);
534	spin_unlock_irqrestore(lock: &qdev->hw_lock, flags: hw_flags);
535	return -1;
536	}
537
538	for (index = 0; index < EEPROM_SIZE; index++) {
539	eeprom_readword(qdev, eepromAddr: index, value: pEEPROMData);
540	checksum += *pEEPROMData;
541	pEEPROMData++;
542	}
543	ql_sem_unlock(qdev, sem_mask: QL_NVRAM_SEM_MASK);
544
545	if (checksum != 0) {
546	netdev_err(dev: qdev->ndev, format: "checksum should be zero, is %x!!\n",
547	checksum);
548	spin_unlock_irqrestore(lock: &qdev->hw_lock, flags: hw_flags);
549	return -1;
550	}
551
552	spin_unlock_irqrestore(lock: &qdev->hw_lock, flags: hw_flags);
553	return checksum;
554	}
555
556	static const u32 PHYAddr[2] = {
557	PORT0_PHY_ADDRESS, PORT1_PHY_ADDRESS
558	};
559
560	static int ql_wait_for_mii_ready(struct ql3_adapter *qdev)
561	{
562	struct ql3xxx_port_registers __iomem *port_regs =
563	qdev->mem_map_registers;
564	u32 temp;
565	int count = 1000;
566
567	while (count) {
568	temp = ql_read_page0_reg(qdev, reg: &port_regs->macMIIStatusReg);
569	if (!(temp & MAC_MII_STATUS_BSY))
570	return 0;
571	udelay(10);
572	count--;
573	}
574	return -1;
575	}
576
577	static void ql_mii_enable_scan_mode(struct ql3_adapter *qdev)
578	{
579	struct ql3xxx_port_registers __iomem *port_regs =
580	qdev->mem_map_registers;
581	u32 scanControl;
582
583	if (qdev->numPorts > 1) {
584	/* Auto scan will cycle through multiple ports */
585	scanControl = MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC;
586	} else {
587	scanControl = MAC_MII_CONTROL_SC;
588	}
589
590	/*
591	* Scan register 1 of PHY/PETBI,
592	* Set up to scan both devices
593	* The autoscan starts from the first register, completes
594	* the last one before rolling over to the first
595	*/
596	ql_write_page0_reg(qdev, reg: &port_regs->macMIIMgmtAddrReg,
597	value: PHYAddr[0] | MII_SCAN_REGISTER);
598
599	ql_write_page0_reg(qdev, reg: &port_regs->macMIIMgmtControlReg,
600	value: (scanControl) |
601	((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS) << 16));
602	}
603
604	static u8 ql_mii_disable_scan_mode(struct ql3_adapter *qdev)
605	{
606	u8 ret;
607	struct ql3xxx_port_registers __iomem *port_regs =
608	qdev->mem_map_registers;
609
610	/* See if scan mode is enabled before we turn it off */
611	if (ql_read_page0_reg(qdev, reg: &port_regs->macMIIMgmtControlReg) &
612	(MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC)) {
613	/* Scan is enabled */
614	ret = 1;
615	} else {
616	/* Scan is disabled */
617	ret = 0;
618	}
619
620	/*
621	* When disabling scan mode you must first change the MII register
622	* address
623	*/
624	ql_write_page0_reg(qdev, reg: &port_regs->macMIIMgmtAddrReg,
625	value: PHYAddr[0] | MII_SCAN_REGISTER);
626
627	ql_write_page0_reg(qdev, reg: &port_regs->macMIIMgmtControlReg,
628	value: ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS |
629	MAC_MII_CONTROL_RC) << 16));
630
631	return ret;
632	}
633
634	static int ql_mii_write_reg_ex(struct ql3_adapter *qdev,
635	u16 regAddr, u16 value, u32 phyAddr)
636	{
637	struct ql3xxx_port_registers __iomem *port_regs =
638	qdev->mem_map_registers;
639	u8 scanWasEnabled;
640
641	scanWasEnabled = ql_mii_disable_scan_mode(qdev);
642
643	if (ql_wait_for_mii_ready(qdev)) {
644	netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
645	return -1;
646	}
647
648	ql_write_page0_reg(qdev, reg: &port_regs->macMIIMgmtAddrReg,
649	value: phyAddr | regAddr);
650
651	ql_write_page0_reg(qdev, reg: &port_regs->macMIIMgmtDataReg, value);
652
653	/* Wait for write to complete 9/10/04 SJP */
654	if (ql_wait_for_mii_ready(qdev)) {
655	netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
656	return -1;
657	}
658
659	if (scanWasEnabled)
660	ql_mii_enable_scan_mode(qdev);
661
662	return 0;
663	}
664
665	static int ql_mii_read_reg_ex(struct ql3_adapter *qdev, u16 regAddr,
666	u16 *value, u32 phyAddr)
667	{
668	struct ql3xxx_port_registers __iomem *port_regs =
669	qdev->mem_map_registers;
670	u8 scanWasEnabled;
671	u32 temp;
672
673	scanWasEnabled = ql_mii_disable_scan_mode(qdev);
674
675	if (ql_wait_for_mii_ready(qdev)) {
676	netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
677	return -1;
678	}
679
680	ql_write_page0_reg(qdev, reg: &port_regs->macMIIMgmtAddrReg,
681	value: phyAddr | regAddr);
682
683	ql_write_page0_reg(qdev, reg: &port_regs->macMIIMgmtControlReg,
684	value: (MAC_MII_CONTROL_RC << 16));
685
686	ql_write_page0_reg(qdev, reg: &port_regs->macMIIMgmtControlReg,
687	value: (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
688
689	/* Wait for the read to complete */
690	if (ql_wait_for_mii_ready(qdev)) {
691	netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
692	return -1;
693	}
694
695	temp = ql_read_page0_reg(qdev, reg: &port_regs->macMIIMgmtDataReg);
696	*value = (u16) temp;
697
698	if (scanWasEnabled)
699	ql_mii_enable_scan_mode(qdev);
700
701	return 0;
702	}
703
704	static int ql_mii_write_reg(struct ql3_adapter *qdev, u16 regAddr, u16 value)
705	{
706	struct ql3xxx_port_registers __iomem *port_regs =
707	qdev->mem_map_registers;
708
709	ql_mii_disable_scan_mode(qdev);
710
711	if (ql_wait_for_mii_ready(qdev)) {
712	netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
713	return -1;
714	}
715
716	ql_write_page0_reg(qdev, reg: &port_regs->macMIIMgmtAddrReg,
717	value: qdev->PHYAddr | regAddr);
718
719	ql_write_page0_reg(qdev, reg: &port_regs->macMIIMgmtDataReg, value);
720
721	/* Wait for write to complete. */
722	if (ql_wait_for_mii_ready(qdev)) {
723	netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
724	return -1;
725	}
726
727	ql_mii_enable_scan_mode(qdev);
728
729	return 0;
730	}
731
732	static int ql_mii_read_reg(struct ql3_adapter *qdev, u16 regAddr, u16 *value)
733	{
734	u32 temp;
735	struct ql3xxx_port_registers __iomem *port_regs =
736	qdev->mem_map_registers;
737
738	ql_mii_disable_scan_mode(qdev);
739
740	if (ql_wait_for_mii_ready(qdev)) {
741	netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
742	return -1;
743	}
744
745	ql_write_page0_reg(qdev, reg: &port_regs->macMIIMgmtAddrReg,
746	value: qdev->PHYAddr | regAddr);
747
748	ql_write_page0_reg(qdev, reg: &port_regs->macMIIMgmtControlReg,
749	value: (MAC_MII_CONTROL_RC << 16));
750
751	ql_write_page0_reg(qdev, reg: &port_regs->macMIIMgmtControlReg,
752	value: (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
753
754	/* Wait for the read to complete */
755	if (ql_wait_for_mii_ready(qdev)) {
756	netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
757	return -1;
758	}
759
760	temp = ql_read_page0_reg(qdev, reg: &port_regs->macMIIMgmtDataReg);
761	*value = (u16) temp;
762
763	ql_mii_enable_scan_mode(qdev);
764
765	return 0;
766	}
767
768	static void ql_petbi_reset(struct ql3_adapter *qdev)
769	{
770	ql_mii_write_reg(qdev, regAddr: PETBI_CONTROL_REG, value: PETBI_CTRL_SOFT_RESET);
771	}
772
773	static void ql_petbi_start_neg(struct ql3_adapter *qdev)
774	{
775	u16 reg;
776
777	/* Enable Auto-negotiation sense */
778	ql_mii_read_reg(qdev, regAddr: PETBI_TBI_CTRL, value: &reg);
779	reg |= PETBI_TBI_AUTO_SENSE;
780	ql_mii_write_reg(qdev, regAddr: PETBI_TBI_CTRL, value: reg);
781
782	ql_mii_write_reg(qdev, regAddr: PETBI_NEG_ADVER,
783	value: PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX);
784
785	ql_mii_write_reg(qdev, regAddr: PETBI_CONTROL_REG,
786	value: PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
787	PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000);
788
789	}
790
791	static void ql_petbi_reset_ex(struct ql3_adapter *qdev)
792	{
793	ql_mii_write_reg_ex(qdev, regAddr: PETBI_CONTROL_REG, value: PETBI_CTRL_SOFT_RESET,
794	phyAddr: PHYAddr[qdev->mac_index]);
795	}
796
797	static void ql_petbi_start_neg_ex(struct ql3_adapter *qdev)
798	{
799	u16 reg;
800
801	/* Enable Auto-negotiation sense */
802	ql_mii_read_reg_ex(qdev, regAddr: PETBI_TBI_CTRL, value: &reg,
803	phyAddr: PHYAddr[qdev->mac_index]);
804	reg |= PETBI_TBI_AUTO_SENSE;
805	ql_mii_write_reg_ex(qdev, regAddr: PETBI_TBI_CTRL, value: reg,
806	phyAddr: PHYAddr[qdev->mac_index]);
807
808	ql_mii_write_reg_ex(qdev, regAddr: PETBI_NEG_ADVER,
809	value: PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX,
810	phyAddr: PHYAddr[qdev->mac_index]);
811
812	ql_mii_write_reg_ex(qdev, regAddr: PETBI_CONTROL_REG,
813	value: PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
814	PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000,
815	phyAddr: PHYAddr[qdev->mac_index]);
816	}
817
818	static void ql_petbi_init(struct ql3_adapter *qdev)
819	{
820	ql_petbi_reset(qdev);
821	ql_petbi_start_neg(qdev);
822	}
823
824	static void ql_petbi_init_ex(struct ql3_adapter *qdev)
825	{
826	ql_petbi_reset_ex(qdev);
827	ql_petbi_start_neg_ex(qdev);
828	}
829
830	static int ql_is_petbi_neg_pause(struct ql3_adapter *qdev)
831	{
832	u16 reg;
833
834	if (ql_mii_read_reg(qdev, regAddr: PETBI_NEG_PARTNER, value: &reg) < 0)
835	return 0;
836
837	return (reg & PETBI_NEG_PAUSE_MASK) == PETBI_NEG_PAUSE;
838	}
839
840	static void phyAgereSpecificInit(struct ql3_adapter *qdev, u32 miiAddr)
841	{
842	netdev_info(dev: qdev->ndev, format: "enabling Agere specific PHY\n");
843	/* power down device bit 11 = 1 */
844	ql_mii_write_reg_ex(qdev, regAddr: 0x00, value: 0x1940, phyAddr: miiAddr);
845	/* enable diagnostic mode bit 2 = 1 */
846	ql_mii_write_reg_ex(qdev, regAddr: 0x12, value: 0x840e, phyAddr: miiAddr);
847	/* 1000MB amplitude adjust (see Agere errata) */
848	ql_mii_write_reg_ex(qdev, regAddr: 0x10, value: 0x8805, phyAddr: miiAddr);
849	/* 1000MB amplitude adjust (see Agere errata) */
850	ql_mii_write_reg_ex(qdev, regAddr: 0x11, value: 0xf03e, phyAddr: miiAddr);
851	/* 100MB amplitude adjust (see Agere errata) */
852	ql_mii_write_reg_ex(qdev, regAddr: 0x10, value: 0x8806, phyAddr: miiAddr);
853	/* 100MB amplitude adjust (see Agere errata) */
854	ql_mii_write_reg_ex(qdev, regAddr: 0x11, value: 0x003e, phyAddr: miiAddr);
855	/* 10MB amplitude adjust (see Agere errata) */
856	ql_mii_write_reg_ex(qdev, regAddr: 0x10, value: 0x8807, phyAddr: miiAddr);
857	/* 10MB amplitude adjust (see Agere errata) */
858	ql_mii_write_reg_ex(qdev, regAddr: 0x11, value: 0x1f00, phyAddr: miiAddr);
859	/* point to hidden reg 0x2806 */
860	ql_mii_write_reg_ex(qdev, regAddr: 0x10, value: 0x2806, phyAddr: miiAddr);
861	/* Write new PHYAD w/bit 5 set */
862	ql_mii_write_reg_ex(qdev, regAddr: 0x11,
863	value: 0x0020 | (PHYAddr[qdev->mac_index] >> 8), phyAddr: miiAddr);
864	/*
865	* Disable diagnostic mode bit 2 = 0
866	* Power up device bit 11 = 0
867	* Link up (on) and activity (blink)
868	*/
869	ql_mii_write_reg(qdev, regAddr: 0x12, value: 0x840a);
870	ql_mii_write_reg(qdev, regAddr: 0x00, value: 0x1140);
871	ql_mii_write_reg(qdev, regAddr: 0x1c, value: 0xfaf0);
872	}
873
874	static enum PHY_DEVICE_TYPE getPhyType(struct ql3_adapter *qdev,
875	u16 phyIdReg0, u16 phyIdReg1)
876	{
877	enum PHY_DEVICE_TYPE result = PHY_TYPE_UNKNOWN;
878	u32 oui;
879	u16 model;
880	int i;
881
882	if (phyIdReg0 == 0xffff)
883	return result;
884
885	if (phyIdReg1 == 0xffff)
886	return result;
887
888	/* oui is split between two registers */
889	oui = (phyIdReg0 << 6) | ((phyIdReg1 & PHY_OUI_1_MASK) >> 10);
890
891	model = (phyIdReg1 & PHY_MODEL_MASK) >> 4;
892
893	/* Scan table for this PHY */
894	for (i = 0; i < MAX_PHY_DEV_TYPES; i++) {
895	if ((oui == PHY_DEVICES[i].phyIdOUI) &&
896	(model == PHY_DEVICES[i].phyIdModel)) {
897	netdev_info(dev: qdev->ndev, format: "Phy: %s\n",
898	PHY_DEVICES[i].name);
899	result = PHY_DEVICES[i].phyDevice;
900	break;
901	}
902	}
903
904	return result;
905	}
906
907	static int ql_phy_get_speed(struct ql3_adapter *qdev)
908	{
909	u16 reg;
910
911	switch (qdev->phyType) {
912	case PHY_AGERE_ET1011C: {
913	if (ql_mii_read_reg(qdev, regAddr: 0x1A, value: &reg) < 0)
914	return 0;
915
916	reg = (reg >> 8) & 3;
917	break;
918	}
919	default:
920	if (ql_mii_read_reg(qdev, regAddr: AUX_CONTROL_STATUS, value: &reg) < 0)
921	return 0;
922
923	reg = (((reg & 0x18) >> 3) & 3);
924	}
925
926	switch (reg) {
927	case 2:
928	return SPEED_1000;
929	case 1:
930	return SPEED_100;
931	case 0:
932	return SPEED_10;
933	default:
934	return -1;
935	}
936	}
937
938	static int ql_is_full_dup(struct ql3_adapter *qdev)
939	{
940	u16 reg;
941
942	switch (qdev->phyType) {
943	case PHY_AGERE_ET1011C: {
944	if (ql_mii_read_reg(qdev, regAddr: 0x1A, value: &reg))
945	return 0;
946
947	return ((reg & 0x0080) && (reg & 0x1000)) != 0;
948	}
949	case PHY_VITESSE_VSC8211:
950	default: {
951	if (ql_mii_read_reg(qdev, regAddr: AUX_CONTROL_STATUS, value: &reg) < 0)
952	return 0;
953	return (reg & PHY_AUX_DUPLEX_STAT) != 0;
954	}
955	}
956	}
957
958	static int ql_is_phy_neg_pause(struct ql3_adapter *qdev)
959	{
960	u16 reg;
961
962	if (ql_mii_read_reg(qdev, regAddr: PHY_NEG_PARTNER, value: &reg) < 0)
963	return 0;
964
965	return (reg & PHY_NEG_PAUSE) != 0;
966	}
967
968	static int PHY_Setup(struct ql3_adapter *qdev)
969	{
970	u16 reg1;
971	u16 reg2;
972	bool agereAddrChangeNeeded = false;
973	u32 miiAddr = 0;
974	int err;
975
976	/* Determine the PHY we are using by reading the ID's */
977	err = ql_mii_read_reg(qdev, PHY_ID_0_REG, value: &reg1);
978	if (err != 0) {
979	netdev_err(dev: qdev->ndev, format: "Could not read from reg PHY_ID_0_REG\n");
980	return err;
981	}
982
983	err = ql_mii_read_reg(qdev, PHY_ID_1_REG, value: &reg2);
984	if (err != 0) {
985	netdev_err(dev: qdev->ndev, format: "Could not read from reg PHY_ID_1_REG\n");
986	return err;
987	}
988
989	/* Check if we have a Agere PHY */
990	if ((reg1 == 0xffff) || (reg2 == 0xffff)) {
991
992	/* Determine which MII address we should be using
993	determined by the index of the card */
994	if (qdev->mac_index == 0)
995	miiAddr = MII_AGERE_ADDR_1;
996	else
997	miiAddr = MII_AGERE_ADDR_2;
998
999	err = ql_mii_read_reg_ex(qdev, PHY_ID_0_REG, value: &reg1, phyAddr: miiAddr);
1000	if (err != 0) {
1001	netdev_err(dev: qdev->ndev,
1002	format: "Could not read from reg PHY_ID_0_REG after Agere detected\n");
1003	return err;
1004	}
1005
1006	err = ql_mii_read_reg_ex(qdev, PHY_ID_1_REG, value: &reg2, phyAddr: miiAddr);
1007	if (err != 0) {
1008	netdev_err(dev: qdev->ndev, format: "Could not read from reg PHY_ID_1_REG after Agere detected\n");
1009	return err;
1010	}
1011
1012	/* We need to remember to initialize the Agere PHY */
1013	agereAddrChangeNeeded = true;
1014	}
1015
1016	/* Determine the particular PHY we have on board to apply
1017	PHY specific initializations */
1018	qdev->phyType = getPhyType(qdev, phyIdReg0: reg1, phyIdReg1: reg2);
1019
1020	if ((qdev->phyType == PHY_AGERE_ET1011C) && agereAddrChangeNeeded) {
1021	/* need this here so address gets changed */
1022	phyAgereSpecificInit(qdev, miiAddr);
1023	} else if (qdev->phyType == PHY_TYPE_UNKNOWN) {
1024	netdev_err(dev: qdev->ndev, format: "PHY is unknown\n");
1025	return -EIO;
1026	}
1027
1028	return 0;
1029	}
1030
1031	/*
1032	* Caller holds hw_lock.
1033	*/
1034	static void ql_mac_enable(struct ql3_adapter *qdev, u32 enable)
1035	{
1036	struct ql3xxx_port_registers __iomem *port_regs =
1037	qdev->mem_map_registers;
1038	u32 value;
1039
1040	if (enable)
1041	value = (MAC_CONFIG_REG_PE | (MAC_CONFIG_REG_PE << 16));
1042	else
1043	value = (MAC_CONFIG_REG_PE << 16);
1044
1045	if (qdev->mac_index)
1046	ql_write_page0_reg(qdev, reg: &port_regs->mac1ConfigReg, value);
1047	else
1048	ql_write_page0_reg(qdev, reg: &port_regs->mac0ConfigReg, value);
1049	}
1050
1051	/*
1052	* Caller holds hw_lock.
1053	*/
1054	static void ql_mac_cfg_soft_reset(struct ql3_adapter *qdev, u32 enable)
1055	{
1056	struct ql3xxx_port_registers __iomem *port_regs =
1057	qdev->mem_map_registers;
1058	u32 value;
1059
1060	if (enable)
1061	value = (MAC_CONFIG_REG_SR | (MAC_CONFIG_REG_SR << 16));
1062	else
1063	value = (MAC_CONFIG_REG_SR << 16);
1064
1065	if (qdev->mac_index)
1066	ql_write_page0_reg(qdev, reg: &port_regs->mac1ConfigReg, value);
1067	else
1068	ql_write_page0_reg(qdev, reg: &port_regs->mac0ConfigReg, value);
1069	}
1070
1071	/*
1072	* Caller holds hw_lock.
1073	*/
1074	static void ql_mac_cfg_gig(struct ql3_adapter *qdev, u32 enable)
1075	{
1076	struct ql3xxx_port_registers __iomem *port_regs =
1077	qdev->mem_map_registers;
1078	u32 value;
1079
1080	if (enable)
1081	value = (MAC_CONFIG_REG_GM | (MAC_CONFIG_REG_GM << 16));
1082	else
1083	value = (MAC_CONFIG_REG_GM << 16);
1084
1085	if (qdev->mac_index)
1086	ql_write_page0_reg(qdev, reg: &port_regs->mac1ConfigReg, value);
1087	else
1088	ql_write_page0_reg(qdev, reg: &port_regs->mac0ConfigReg, value);
1089	}
1090
1091	/*
1092	* Caller holds hw_lock.
1093	*/
1094	static void ql_mac_cfg_full_dup(struct ql3_adapter *qdev, u32 enable)
1095	{
1096	struct ql3xxx_port_registers __iomem *port_regs =
1097	qdev->mem_map_registers;
1098	u32 value;
1099
1100	if (enable)
1101	value = (MAC_CONFIG_REG_FD | (MAC_CONFIG_REG_FD << 16));
1102	else
1103	value = (MAC_CONFIG_REG_FD << 16);
1104
1105	if (qdev->mac_index)
1106	ql_write_page0_reg(qdev, reg: &port_regs->mac1ConfigReg, value);
1107	else
1108	ql_write_page0_reg(qdev, reg: &port_regs->mac0ConfigReg, value);
1109	}
1110
1111	/*
1112	* Caller holds hw_lock.
1113	*/
1114	static void ql_mac_cfg_pause(struct ql3_adapter *qdev, u32 enable)
1115	{
1116	struct ql3xxx_port_registers __iomem *port_regs =
1117	qdev->mem_map_registers;
1118	u32 value;
1119
1120	if (enable)
1121	value =
1122	((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) |
1123	((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16));
1124	else
1125	value = ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16);
1126
1127	if (qdev->mac_index)
1128	ql_write_page0_reg(qdev, reg: &port_regs->mac1ConfigReg, value);
1129	else
1130	ql_write_page0_reg(qdev, reg: &port_regs->mac0ConfigReg, value);
1131	}
1132
1133	/*
1134	* Caller holds hw_lock.
1135	*/
1136	static int ql_is_fiber(struct ql3_adapter *qdev)
1137	{
1138	struct ql3xxx_port_registers __iomem *port_regs =
1139	qdev->mem_map_registers;
1140	u32 bitToCheck = 0;
1141	u32 temp;
1142
1143	switch (qdev->mac_index) {
1144	case 0:
1145	bitToCheck = PORT_STATUS_SM0;
1146	break;
1147	case 1:
1148	bitToCheck = PORT_STATUS_SM1;
1149	break;
1150	}
1151
1152	temp = ql_read_page0_reg(qdev, reg: &port_regs->portStatus);
1153	return (temp & bitToCheck) != 0;
1154	}
1155
1156	static int ql_is_auto_cfg(struct ql3_adapter *qdev)
1157	{
1158	u16 reg;
1159	ql_mii_read_reg(qdev, regAddr: 0x00, value: &reg);
1160	return (reg & 0x1000) != 0;
1161	}
1162
1163	/*
1164	* Caller holds hw_lock.
1165	*/
1166	static int ql_is_auto_neg_complete(struct ql3_adapter *qdev)
1167	{
1168	struct ql3xxx_port_registers __iomem *port_regs =
1169	qdev->mem_map_registers;
1170	u32 bitToCheck = 0;
1171	u32 temp;
1172
1173	switch (qdev->mac_index) {
1174	case 0:
1175	bitToCheck = PORT_STATUS_AC0;
1176	break;
1177	case 1:
1178	bitToCheck = PORT_STATUS_AC1;
1179	break;
1180	}
1181
1182	temp = ql_read_page0_reg(qdev, reg: &port_regs->portStatus);
1183	if (temp & bitToCheck) {
1184	netif_info(qdev, link, qdev->ndev, "Auto-Negotiate complete\n");
1185	return 1;
1186	}
1187	netif_info(qdev, link, qdev->ndev, "Auto-Negotiate incomplete\n");
1188	return 0;
1189	}
1190
1191	/*
1192	* ql_is_neg_pause() returns 1 if pause was negotiated to be on
1193	*/
1194	static int ql_is_neg_pause(struct ql3_adapter *qdev)
1195	{
1196	if (ql_is_fiber(qdev))
1197	return ql_is_petbi_neg_pause(qdev);
1198	else
1199	return ql_is_phy_neg_pause(qdev);
1200	}
1201
1202	static int ql_auto_neg_error(struct ql3_adapter *qdev)
1203	{
1204	struct ql3xxx_port_registers __iomem *port_regs =
1205	qdev->mem_map_registers;
1206	u32 bitToCheck = 0;
1207	u32 temp;
1208
1209	switch (qdev->mac_index) {
1210	case 0:
1211	bitToCheck = PORT_STATUS_AE0;
1212	break;
1213	case 1:
1214	bitToCheck = PORT_STATUS_AE1;
1215	break;
1216	}
1217	temp = ql_read_page0_reg(qdev, reg: &port_regs->portStatus);
1218	return (temp & bitToCheck) != 0;
1219	}
1220
1221	static u32 ql_get_link_speed(struct ql3_adapter *qdev)
1222	{
1223	if (ql_is_fiber(qdev))
1224	return SPEED_1000;
1225	else
1226	return ql_phy_get_speed(qdev);
1227	}
1228
1229	static int ql_is_link_full_dup(struct ql3_adapter *qdev)
1230	{
1231	if (ql_is_fiber(qdev))
1232	return 1;
1233	else
1234	return ql_is_full_dup(qdev);
1235	}
1236
1237	/*
1238	* Caller holds hw_lock.
1239	*/
1240	static int ql_link_down_detect(struct ql3_adapter *qdev)
1241	{
1242	struct ql3xxx_port_registers __iomem *port_regs =
1243	qdev->mem_map_registers;
1244	u32 bitToCheck = 0;
1245	u32 temp;
1246
1247	switch (qdev->mac_index) {
1248	case 0:
1249	bitToCheck = ISP_CONTROL_LINK_DN_0;
1250	break;
1251	case 1:
1252	bitToCheck = ISP_CONTROL_LINK_DN_1;
1253	break;
1254	}
1255
1256	temp =
1257	ql_read_common_reg(qdev, reg: &port_regs->CommonRegs.ispControlStatus);
1258	return (temp & bitToCheck) != 0;
1259	}
1260
1261	/*
1262	* Caller holds hw_lock.
1263	*/
1264	static int ql_link_down_detect_clear(struct ql3_adapter *qdev)
1265	{
1266	struct ql3xxx_port_registers __iomem *port_regs =
1267	qdev->mem_map_registers;
1268
1269	switch (qdev->mac_index) {
1270	case 0:
1271	ql_write_common_reg(qdev,
1272	reg: &port_regs->CommonRegs.ispControlStatus,
1273	value: (ISP_CONTROL_LINK_DN_0) |
1274	(ISP_CONTROL_LINK_DN_0 << 16));
1275	break;
1276
1277	case 1:
1278	ql_write_common_reg(qdev,
1279	reg: &port_regs->CommonRegs.ispControlStatus,
1280	value: (ISP_CONTROL_LINK_DN_1) |
1281	(ISP_CONTROL_LINK_DN_1 << 16));
1282	break;
1283
1284	default:
1285	return 1;
1286	}
1287
1288	return 0;
1289	}
1290
1291	/*
1292	* Caller holds hw_lock.
1293	*/
1294	static int ql_this_adapter_controls_port(struct ql3_adapter *qdev)
1295	{
1296	struct ql3xxx_port_registers __iomem *port_regs =
1297	qdev->mem_map_registers;
1298	u32 bitToCheck = 0;
1299	u32 temp;
1300
1301	switch (qdev->mac_index) {
1302	case 0:
1303	bitToCheck = PORT_STATUS_F1_ENABLED;
1304	break;
1305	case 1:
1306	bitToCheck = PORT_STATUS_F3_ENABLED;
1307	break;
1308	default:
1309	break;
1310	}
1311
1312	temp = ql_read_page0_reg(qdev, reg: &port_regs->portStatus);
1313	if (temp & bitToCheck) {
1314	netif_printk(qdev, link, KERN_DEBUG, qdev->ndev,
1315	"not link master\n");
1316	return 0;
1317	}
1318
1319	netif_printk(qdev, link, KERN_DEBUG, qdev->ndev, "link master\n");
1320	return 1;
1321	}
1322
1323	static void ql_phy_reset_ex(struct ql3_adapter *qdev)
1324	{
1325	ql_mii_write_reg_ex(qdev, regAddr: CONTROL_REG, value: PHY_CTRL_SOFT_RESET,
1326	phyAddr: PHYAddr[qdev->mac_index]);
1327	}
1328
1329	static void ql_phy_start_neg_ex(struct ql3_adapter *qdev)
1330	{
1331	u16 reg;
1332	u16 portConfiguration;
1333
1334	if (qdev->phyType == PHY_AGERE_ET1011C)
1335	ql_mii_write_reg(qdev, regAddr: 0x13, value: 0x0000);
1336	/* turn off external loopback */
1337
1338	if (qdev->mac_index == 0)
1339	portConfiguration =
1340	qdev->nvram_data.macCfg_port0.portConfiguration;
1341	else
1342	portConfiguration =
1343	qdev->nvram_data.macCfg_port1.portConfiguration;
1344
1345	/* Some HBA's in the field are set to 0 and they need to
1346	be reinterpreted with a default value */
1347	if (portConfiguration == 0)
1348	portConfiguration = PORT_CONFIG_DEFAULT;
1349
1350	/* Set the 1000 advertisements */
1351	ql_mii_read_reg_ex(qdev, regAddr: PHY_GIG_CONTROL, value: &reg,
1352	phyAddr: PHYAddr[qdev->mac_index]);
1353	reg &= ~PHY_GIG_ALL_PARAMS;
1354
1355	if (portConfiguration & PORT_CONFIG_1000MB_SPEED) {
1356	if (portConfiguration & PORT_CONFIG_FULL_DUPLEX_ENABLED)
1357	reg |= PHY_GIG_ADV_1000F;
1358	else
1359	reg |= PHY_GIG_ADV_1000H;
1360	}
1361
1362	ql_mii_write_reg_ex(qdev, regAddr: PHY_GIG_CONTROL, value: reg,
1363	phyAddr: PHYAddr[qdev->mac_index]);
1364
1365	/* Set the 10/100 & pause negotiation advertisements */
1366	ql_mii_read_reg_ex(qdev, regAddr: PHY_NEG_ADVER, value: &reg,
1367	phyAddr: PHYAddr[qdev->mac_index]);
1368	reg &= ~PHY_NEG_ALL_PARAMS;
1369
1370	if (portConfiguration & PORT_CONFIG_SYM_PAUSE_ENABLED)
1371	reg |= PHY_NEG_ASY_PAUSE | PHY_NEG_SYM_PAUSE;
1372
1373	if (portConfiguration & PORT_CONFIG_FULL_DUPLEX_ENABLED) {
1374	if (portConfiguration & PORT_CONFIG_100MB_SPEED)
1375	reg |= PHY_NEG_ADV_100F;
1376
1377	if (portConfiguration & PORT_CONFIG_10MB_SPEED)
1378	reg |= PHY_NEG_ADV_10F;
1379	}
1380
1381	if (portConfiguration & PORT_CONFIG_HALF_DUPLEX_ENABLED) {
1382	if (portConfiguration & PORT_CONFIG_100MB_SPEED)
1383	reg |= PHY_NEG_ADV_100H;
1384
1385	if (portConfiguration & PORT_CONFIG_10MB_SPEED)
1386	reg |= PHY_NEG_ADV_10H;
1387	}
1388
1389	if (portConfiguration & PORT_CONFIG_1000MB_SPEED)
1390	reg |= 1;
1391
1392	ql_mii_write_reg_ex(qdev, regAddr: PHY_NEG_ADVER, value: reg,
1393	phyAddr: PHYAddr[qdev->mac_index]);
1394
1395	ql_mii_read_reg_ex(qdev, regAddr: CONTROL_REG, value: &reg, phyAddr: PHYAddr[qdev->mac_index]);
1396
1397	ql_mii_write_reg_ex(qdev, regAddr: CONTROL_REG,
1398	value: reg | PHY_CTRL_RESTART_NEG | PHY_CTRL_AUTO_NEG,
1399	phyAddr: PHYAddr[qdev->mac_index]);
1400	}
1401
1402	static void ql_phy_init_ex(struct ql3_adapter *qdev)
1403	{
1404	ql_phy_reset_ex(qdev);
1405	PHY_Setup(qdev);
1406	ql_phy_start_neg_ex(qdev);
1407	}
1408
1409	/*
1410	* Caller holds hw_lock.
1411	*/
1412	static u32 ql_get_link_state(struct ql3_adapter *qdev)
1413	{
1414	struct ql3xxx_port_registers __iomem *port_regs =
1415	qdev->mem_map_registers;
1416	u32 bitToCheck = 0;
1417	u32 temp, linkState;
1418
1419	switch (qdev->mac_index) {
1420	case 0:
1421	bitToCheck = PORT_STATUS_UP0;
1422	break;
1423	case 1:
1424	bitToCheck = PORT_STATUS_UP1;
1425	break;
1426	}
1427
1428	temp = ql_read_page0_reg(qdev, reg: &port_regs->portStatus);
1429	if (temp & bitToCheck)
1430	linkState = LS_UP;
1431	else
1432	linkState = LS_DOWN;
1433
1434	return linkState;
1435	}
1436
1437	static int ql_port_start(struct ql3_adapter *qdev)
1438	{
1439	if (ql_sem_spinlock(qdev, sem_mask: QL_PHY_GIO_SEM_MASK,
1440	sem_bits: (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1441	2) << 7)) {
1442	netdev_err(dev: qdev->ndev, format: "Could not get hw lock for GIO\n");
1443	return -1;
1444	}
1445
1446	if (ql_is_fiber(qdev)) {
1447	ql_petbi_init(qdev);
1448	} else {
1449	/* Copper port */
1450	ql_phy_init_ex(qdev);
1451	}
1452
1453	ql_sem_unlock(qdev, sem_mask: QL_PHY_GIO_SEM_MASK);
1454	return 0;
1455	}
1456
1457	static int ql_finish_auto_neg(struct ql3_adapter *qdev)
1458	{
1459
1460	if (ql_sem_spinlock(qdev, sem_mask: QL_PHY_GIO_SEM_MASK,
1461	sem_bits: (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1462	2) << 7))
1463	return -1;
1464
1465	if (!ql_auto_neg_error(qdev)) {
1466	if (test_bit(QL_LINK_MASTER, &qdev->flags)) {
1467	/* configure the MAC */
1468	netif_printk(qdev, link, KERN_DEBUG, qdev->ndev,
1469	"Configuring link\n");
1470	ql_mac_cfg_soft_reset(qdev, enable: 1);
1471	ql_mac_cfg_gig(qdev,
1472	enable: (ql_get_link_speed
1473	(qdev) ==
1474	SPEED_1000));
1475	ql_mac_cfg_full_dup(qdev,
1476	enable: ql_is_link_full_dup
1477	(qdev));
1478	ql_mac_cfg_pause(qdev,
1479	enable: ql_is_neg_pause
1480	(qdev));
1481	ql_mac_cfg_soft_reset(qdev, enable: 0);
1482
1483	/* enable the MAC */
1484	netif_printk(qdev, link, KERN_DEBUG, qdev->ndev,
1485	"Enabling mac\n");
1486	ql_mac_enable(qdev, enable: 1);
1487	}
1488
1489	qdev->port_link_state = LS_UP;
1490	netif_start_queue(dev: qdev->ndev);
1491	netif_carrier_on(dev: qdev->ndev);
1492	netif_info(qdev, link, qdev->ndev,
1493	"Link is up at %d Mbps, %s duplex\n",
1494	ql_get_link_speed(qdev),
1495	ql_is_link_full_dup(qdev) ? "full" : "half");
1496
1497	} else { /* Remote error detected */
1498
1499	if (test_bit(QL_LINK_MASTER, &qdev->flags)) {
1500	netif_printk(qdev, link, KERN_DEBUG, qdev->ndev,
1501	"Remote error detected. Calling ql_port_start()\n");
1502	/*
1503	* ql_port_start() is shared code and needs
1504	* to lock the PHY on it's own.
1505	*/
1506	ql_sem_unlock(qdev, sem_mask: QL_PHY_GIO_SEM_MASK);
1507	if (ql_port_start(qdev)) /* Restart port */
1508	return -1;
1509	return 0;
1510	}
1511	}
1512	ql_sem_unlock(qdev, sem_mask: QL_PHY_GIO_SEM_MASK);
1513	return 0;
1514	}
1515
1516	static void ql_link_state_machine_work(struct work_struct *work)
1517	{
1518	struct ql3_adapter *qdev =
1519	container_of(work, struct ql3_adapter, link_state_work.work);
1520
1521	u32 curr_link_state;
1522	unsigned long hw_flags;
1523
1524	spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1525
1526	curr_link_state = ql_get_link_state(qdev);
1527
1528	if (test_bit(QL_RESET_ACTIVE, &qdev->flags)) {
1529	netif_info(qdev, link, qdev->ndev,
1530	"Reset in progress, skip processing link state\n");
1531
1532	spin_unlock_irqrestore(lock: &qdev->hw_lock, flags: hw_flags);
1533
1534	/* Restart timer on 2 second interval. */
1535	mod_timer(timer: &qdev->adapter_timer, expires: jiffies + HZ * 1);
1536
1537	return;
1538	}
1539
1540	switch (qdev->port_link_state) {
1541	default:
1542	if (test_bit(QL_LINK_MASTER, &qdev->flags))
1543	ql_port_start(qdev);
1544	qdev->port_link_state = LS_DOWN;
1545	fallthrough;
1546
1547	case LS_DOWN:
1548	if (curr_link_state == LS_UP) {
1549	netif_info(qdev, link, qdev->ndev, "Link is up\n");
1550	if (ql_is_auto_neg_complete(qdev))
1551	ql_finish_auto_neg(qdev);
1552
1553	if (qdev->port_link_state == LS_UP)
1554	ql_link_down_detect_clear(qdev);
1555
1556	qdev->port_link_state = LS_UP;
1557	}
1558	break;
1559
1560	case LS_UP:
1561	/*
1562	* See if the link is currently down or went down and came
1563	* back up
1564	*/
1565	if (curr_link_state == LS_DOWN) {
1566	netif_info(qdev, link, qdev->ndev, "Link is down\n");
1567	qdev->port_link_state = LS_DOWN;
1568	}
1569	if (ql_link_down_detect(qdev))
1570	qdev->port_link_state = LS_DOWN;
1571	break;
1572	}
1573	spin_unlock_irqrestore(lock: &qdev->hw_lock, flags: hw_flags);
1574
1575	/* Restart timer on 2 second interval. */
1576	mod_timer(timer: &qdev->adapter_timer, expires: jiffies + HZ * 1);
1577	}
1578
1579	/*
1580	* Caller must take hw_lock and QL_PHY_GIO_SEM.
1581	*/
1582	static void ql_get_phy_owner(struct ql3_adapter *qdev)
1583	{
1584	if (ql_this_adapter_controls_port(qdev))
1585	set_bit(nr: QL_LINK_MASTER, addr: &qdev->flags);
1586	else
1587	clear_bit(nr: QL_LINK_MASTER, addr: &qdev->flags);
1588	}
1589
1590	/*
1591	* Caller must take hw_lock and QL_PHY_GIO_SEM.
1592	*/
1593	static void ql_init_scan_mode(struct ql3_adapter *qdev)
1594	{
1595	ql_mii_enable_scan_mode(qdev);
1596
1597	if (test_bit(QL_LINK_OPTICAL, &qdev->flags)) {
1598	if (ql_this_adapter_controls_port(qdev))
1599	ql_petbi_init_ex(qdev);
1600	} else {
1601	if (ql_this_adapter_controls_port(qdev))
1602	ql_phy_init_ex(qdev);
1603	}
1604	}
1605
1606	/*
1607	* MII_Setup needs to be called before taking the PHY out of reset
1608	* so that the management interface clock speed can be set properly.
1609	* It would be better if we had a way to disable MDC until after the
1610	* PHY is out of reset, but we don't have that capability.
1611	*/
1612	static int ql_mii_setup(struct ql3_adapter *qdev)
1613	{
1614	u32 reg;
1615	struct ql3xxx_port_registers __iomem *port_regs =
1616	qdev->mem_map_registers;
1617
1618	if (ql_sem_spinlock(qdev, sem_mask: QL_PHY_GIO_SEM_MASK,
1619	sem_bits: (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1620	2) << 7))
1621	return -1;
1622
1623	if (qdev->device_id == QL3032_DEVICE_ID)
1624	ql_write_page0_reg(qdev,
1625	reg: &port_regs->macMIIMgmtControlReg, value: 0x0f00000);
1626
1627	/* Divide 125MHz clock by 28 to meet PHY timing requirements */
1628	reg = MAC_MII_CONTROL_CLK_SEL_DIV28;
1629
1630	ql_write_page0_reg(qdev, reg: &port_regs->macMIIMgmtControlReg,
1631	value: reg | ((MAC_MII_CONTROL_CLK_SEL_MASK) << 16));
1632
1633	ql_sem_unlock(qdev, sem_mask: QL_PHY_GIO_SEM_MASK);
1634	return 0;
1635	}
1636
1637	#define SUPPORTED_OPTICAL_MODES (SUPPORTED_1000baseT_Full | \
1638	SUPPORTED_FIBRE | \
1639	SUPPORTED_Autoneg)
1640	#define SUPPORTED_TP_MODES (SUPPORTED_10baseT_Half | \
1641	SUPPORTED_10baseT_Full | \
1642	SUPPORTED_100baseT_Half | \
1643	SUPPORTED_100baseT_Full | \
1644	SUPPORTED_1000baseT_Half | \
1645	SUPPORTED_1000baseT_Full | \
1646	SUPPORTED_Autoneg | \
1647	SUPPORTED_TP) \
1648
1649	static u32 ql_supported_modes(struct ql3_adapter *qdev)
1650	{
1651	if (test_bit(QL_LINK_OPTICAL, &qdev->flags))
1652	return SUPPORTED_OPTICAL_MODES;
1653
1654	return SUPPORTED_TP_MODES;
1655	}
1656
1657	static int ql_get_auto_cfg_status(struct ql3_adapter *qdev)
1658	{
1659	int status;
1660	unsigned long hw_flags;
1661	spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1662	if (ql_sem_spinlock(qdev, sem_mask: QL_PHY_GIO_SEM_MASK,
1663	sem_bits: (QL_RESOURCE_BITS_BASE_CODE |
1664	(qdev->mac_index) * 2) << 7)) {
1665	spin_unlock_irqrestore(lock: &qdev->hw_lock, flags: hw_flags);
1666	return 0;
1667	}
1668	status = ql_is_auto_cfg(qdev);
1669	ql_sem_unlock(qdev, sem_mask: QL_PHY_GIO_SEM_MASK);
1670	spin_unlock_irqrestore(lock: &qdev->hw_lock, flags: hw_flags);
1671	return status;
1672	}
1673
1674	static u32 ql_get_speed(struct ql3_adapter *qdev)
1675	{
1676	u32 status;
1677	unsigned long hw_flags;
1678	spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1679	if (ql_sem_spinlock(qdev, sem_mask: QL_PHY_GIO_SEM_MASK,
1680	sem_bits: (QL_RESOURCE_BITS_BASE_CODE |
1681	(qdev->mac_index) * 2) << 7)) {
1682	spin_unlock_irqrestore(lock: &qdev->hw_lock, flags: hw_flags);
1683	return 0;
1684	}
1685	status = ql_get_link_speed(qdev);
1686	ql_sem_unlock(qdev, sem_mask: QL_PHY_GIO_SEM_MASK);
1687	spin_unlock_irqrestore(lock: &qdev->hw_lock, flags: hw_flags);
1688	return status;
1689	}
1690
1691	static int ql_get_full_dup(struct ql3_adapter *qdev)
1692	{
1693	int status;
1694	unsigned long hw_flags;
1695	spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1696	if (ql_sem_spinlock(qdev, sem_mask: QL_PHY_GIO_SEM_MASK,
1697	sem_bits: (QL_RESOURCE_BITS_BASE_CODE |
1698	(qdev->mac_index) * 2) << 7)) {
1699	spin_unlock_irqrestore(lock: &qdev->hw_lock, flags: hw_flags);
1700	return 0;
1701	}
1702	status = ql_is_link_full_dup(qdev);
1703	ql_sem_unlock(qdev, sem_mask: QL_PHY_GIO_SEM_MASK);
1704	spin_unlock_irqrestore(lock: &qdev->hw_lock, flags: hw_flags);
1705	return status;
1706	}
1707
1708	static int ql_get_link_ksettings(struct net_device *ndev,
1709	struct ethtool_link_ksettings *cmd)
1710	{
1711	struct ql3_adapter *qdev = netdev_priv(dev: ndev);
1712	u32 supported, advertising;
1713
1714	supported = ql_supported_modes(qdev);
1715
1716	if (test_bit(QL_LINK_OPTICAL, &qdev->flags)) {
1717	cmd->base.port = PORT_FIBRE;
1718	} else {
1719	cmd->base.port = PORT_TP;
1720	cmd->base.phy_address = qdev->PHYAddr;
1721	}
1722	advertising = ql_supported_modes(qdev);
1723	cmd->base.autoneg = ql_get_auto_cfg_status(qdev);
1724	cmd->base.speed = ql_get_speed(qdev);
1725	cmd->base.duplex = ql_get_full_dup(qdev);
1726
1727	ethtool_convert_legacy_u32_to_link_mode(dst: cmd->link_modes.supported,
1728	legacy_u32: supported);
1729	ethtool_convert_legacy_u32_to_link_mode(dst: cmd->link_modes.advertising,
1730	legacy_u32: advertising);
1731
1732	return 0;
1733	}
1734
1735	static void ql_get_drvinfo(struct net_device *ndev,
1736	struct ethtool_drvinfo *drvinfo)
1737	{
1738	struct ql3_adapter *qdev = netdev_priv(dev: ndev);
1739	strscpy(p: drvinfo->driver, q: ql3xxx_driver_name, size: sizeof(drvinfo->driver));
1740	strscpy(p: drvinfo->version, q: ql3xxx_driver_version,
1741	size: sizeof(drvinfo->version));
1742	strscpy(p: drvinfo->bus_info, q: pci_name(pdev: qdev->pdev),
1743	size: sizeof(drvinfo->bus_info));
1744	}
1745
1746	static u32 ql_get_msglevel(struct net_device *ndev)
1747	{
1748	struct ql3_adapter *qdev = netdev_priv(dev: ndev);
1749	return qdev->msg_enable;
1750	}
1751
1752	static void ql_set_msglevel(struct net_device *ndev, u32 value)
1753	{
1754	struct ql3_adapter *qdev = netdev_priv(dev: ndev);
1755	qdev->msg_enable = value;
1756	}
1757
1758	static void ql_get_pauseparam(struct net_device *ndev,
1759	struct ethtool_pauseparam *pause)
1760	{
1761	struct ql3_adapter *qdev = netdev_priv(dev: ndev);
1762	struct ql3xxx_port_registers __iomem *port_regs =
1763	qdev->mem_map_registers;
1764
1765	u32 reg;
1766	if (qdev->mac_index == 0)
1767	reg = ql_read_page0_reg(qdev, reg: &port_regs->mac0ConfigReg);
1768	else
1769	reg = ql_read_page0_reg(qdev, reg: &port_regs->mac1ConfigReg);
1770
1771	pause->autoneg = ql_get_auto_cfg_status(qdev);
1772	pause->rx_pause = (reg & MAC_CONFIG_REG_RF) >> 2;
1773	pause->tx_pause = (reg & MAC_CONFIG_REG_TF) >> 1;
1774	}
1775
1776	static const struct ethtool_ops ql3xxx_ethtool_ops = {
1777	.get_drvinfo = ql_get_drvinfo,
1778	.get_link = ethtool_op_get_link,
1779	.get_msglevel = ql_get_msglevel,
1780	.set_msglevel = ql_set_msglevel,
1781	.get_pauseparam = ql_get_pauseparam,
1782	.get_link_ksettings = ql_get_link_ksettings,
1783	};
1784
1785	static int ql_populate_free_queue(struct ql3_adapter *qdev)
1786	{
1787	struct ql_rcv_buf_cb *lrg_buf_cb = qdev->lrg_buf_free_head;
1788	dma_addr_t map;
1789	int err;
1790
1791	while (lrg_buf_cb) {
1792	if (!lrg_buf_cb->skb) {
1793	lrg_buf_cb->skb =
1794	netdev_alloc_skb(dev: qdev->ndev,
1795	length: qdev->lrg_buffer_len);
1796	if (unlikely(!lrg_buf_cb->skb)) {
1797	netdev_printk(KERN_DEBUG, dev: qdev->ndev,
1798	format: "Failed netdev_alloc_skb()\n");
1799	break;
1800	} else {
1801	/*
1802	* We save some space to copy the ethhdr from
1803	* first buffer
1804	*/
1805	skb_reserve(skb: lrg_buf_cb->skb, QL_HEADER_SPACE);
1806	map = dma_map_single(&qdev->pdev->dev,
1807	lrg_buf_cb->skb->data,
1808	qdev->lrg_buffer_len - QL_HEADER_SPACE,
1809	DMA_FROM_DEVICE);
1810
1811	err = dma_mapping_error(dev: &qdev->pdev->dev, dma_addr: map);
1812	if (err) {
1813	netdev_err(dev: qdev->ndev,
1814	format: "PCI mapping failed with error: %d\n",
1815	err);
1816	dev_kfree_skb(lrg_buf_cb->skb);
1817	lrg_buf_cb->skb = NULL;
1818	break;
1819	}
1820
1821
1822	lrg_buf_cb->buf_phy_addr_low =
1823	cpu_to_le32(LS_64BITS(map));
1824	lrg_buf_cb->buf_phy_addr_high =
1825	cpu_to_le32(MS_64BITS(map));
1826	dma_unmap_addr_set(lrg_buf_cb, mapaddr, map);
1827	dma_unmap_len_set(lrg_buf_cb, maplen,
1828	qdev->lrg_buffer_len -
1829	QL_HEADER_SPACE);
1830	--qdev->lrg_buf_skb_check;
1831	if (!qdev->lrg_buf_skb_check)
1832	return 1;
1833	}
1834	}
1835	lrg_buf_cb = lrg_buf_cb->next;
1836	}
1837	return 0;
1838	}
1839
1840	/*
1841	* Caller holds hw_lock.
1842	*/
1843	static void ql_update_small_bufq_prod_index(struct ql3_adapter *qdev)
1844	{
1845	struct ql3xxx_port_registers __iomem *port_regs =
1846	qdev->mem_map_registers;
1847
1848	if (qdev->small_buf_release_cnt >= 16) {
1849	while (qdev->small_buf_release_cnt >= 16) {
1850	qdev->small_buf_q_producer_index++;
1851
1852	if (qdev->small_buf_q_producer_index ==
1853	NUM_SBUFQ_ENTRIES)
1854	qdev->small_buf_q_producer_index = 0;
1855	qdev->small_buf_release_cnt -= 8;
1856	}
1857	wmb();
1858	writel_relaxed(qdev->small_buf_q_producer_index,
1859	&port_regs->CommonRegs.rxSmallQProducerIndex);
1860	}
1861	}
1862
1863	/*
1864	* Caller holds hw_lock.
1865	*/
1866	static void ql_update_lrg_bufq_prod_index(struct ql3_adapter *qdev)
1867	{
1868	struct bufq_addr_element *lrg_buf_q_ele;
1869	int i;
1870	struct ql_rcv_buf_cb *lrg_buf_cb;
1871	struct ql3xxx_port_registers __iomem *port_regs =
1872	qdev->mem_map_registers;
1873
1874	if ((qdev->lrg_buf_free_count >= 8) &&
1875	(qdev->lrg_buf_release_cnt >= 16)) {
1876
1877	if (qdev->lrg_buf_skb_check)
1878	if (!ql_populate_free_queue(qdev))
1879	return;
1880
1881	lrg_buf_q_ele = qdev->lrg_buf_next_free;
1882
1883	while ((qdev->lrg_buf_release_cnt >= 16) &&
1884	(qdev->lrg_buf_free_count >= 8)) {
1885
1886	for (i = 0; i < 8; i++) {
1887	lrg_buf_cb =
1888	ql_get_from_lrg_buf_free_list(qdev);
1889	lrg_buf_q_ele->addr_high =
1890	lrg_buf_cb->buf_phy_addr_high;
1891	lrg_buf_q_ele->addr_low =
1892	lrg_buf_cb->buf_phy_addr_low;
1893	lrg_buf_q_ele++;
1894
1895	qdev->lrg_buf_release_cnt--;
1896	}
1897
1898	qdev->lrg_buf_q_producer_index++;
1899
1900	if (qdev->lrg_buf_q_producer_index ==
1901	qdev->num_lbufq_entries)
1902	qdev->lrg_buf_q_producer_index = 0;
1903
1904	if (qdev->lrg_buf_q_producer_index ==
1905	(qdev->num_lbufq_entries - 1)) {
1906	lrg_buf_q_ele = qdev->lrg_buf_q_virt_addr;
1907	}
1908	}
1909	wmb();
1910	qdev->lrg_buf_next_free = lrg_buf_q_ele;
1911	writel(val: qdev->lrg_buf_q_producer_index,
1912	addr: &port_regs->CommonRegs.rxLargeQProducerIndex);
1913	}
1914	}
1915
1916	static void ql_process_mac_tx_intr(struct ql3_adapter *qdev,
1917	struct ob_mac_iocb_rsp *mac_rsp)
1918	{
1919	struct ql_tx_buf_cb *tx_cb;
1920	int i;
1921
1922	if (mac_rsp->flags & OB_MAC_IOCB_RSP_S) {
1923	netdev_warn(dev: qdev->ndev,
1924	format: "Frame too short but it was padded and sent\n");
1925	}
1926
1927	tx_cb = &qdev->tx_buf[mac_rsp->transaction_id];
1928
1929	/* Check the transmit response flags for any errors */
1930	if (mac_rsp->flags & OB_MAC_IOCB_RSP_S) {
1931	netdev_err(dev: qdev->ndev,
1932	format: "Frame too short to be legal, frame not sent\n");
1933
1934	qdev->ndev->stats.tx_errors++;
1935	goto frame_not_sent;
1936	}
1937
1938	if (tx_cb->seg_count == 0) {
1939	netdev_err(dev: qdev->ndev, format: "tx_cb->seg_count == 0: %d\n",
1940	mac_rsp->transaction_id);
1941
1942	qdev->ndev->stats.tx_errors++;
1943	goto invalid_seg_count;
1944	}
1945
1946	dma_unmap_single(&qdev->pdev->dev,
1947	dma_unmap_addr(&tx_cb->map[0], mapaddr),
1948	dma_unmap_len(&tx_cb->map[0], maplen), DMA_TO_DEVICE);
1949	tx_cb->seg_count--;
1950	if (tx_cb->seg_count) {
1951	for (i = 1; i < tx_cb->seg_count; i++) {
1952	dma_unmap_page(&qdev->pdev->dev,
1953	dma_unmap_addr(&tx_cb->map[i], mapaddr),
1954	dma_unmap_len(&tx_cb->map[i], maplen),
1955	DMA_TO_DEVICE);
1956	}
1957	}
1958	qdev->ndev->stats.tx_packets++;
1959	qdev->ndev->stats.tx_bytes += tx_cb->skb->len;
1960
1961	frame_not_sent:
1962	dev_kfree_skb_irq(skb: tx_cb->skb);
1963	tx_cb->skb = NULL;
1964
1965	invalid_seg_count:
1966	atomic_inc(v: &qdev->tx_count);
1967	}
1968
1969	static void ql_get_sbuf(struct ql3_adapter *qdev)
1970	{
1971	if (++qdev->small_buf_index == NUM_SMALL_BUFFERS)
1972	qdev->small_buf_index = 0;
1973	qdev->small_buf_release_cnt++;
1974	}
1975
1976	static struct ql_rcv_buf_cb *ql_get_lbuf(struct ql3_adapter *qdev)
1977	{
1978	struct ql_rcv_buf_cb *lrg_buf_cb = NULL;
1979	lrg_buf_cb = &qdev->lrg_buf[qdev->lrg_buf_index];
1980	qdev->lrg_buf_release_cnt++;
1981	if (++qdev->lrg_buf_index == qdev->num_large_buffers)
1982	qdev->lrg_buf_index = 0;
1983	return lrg_buf_cb;
1984	}
1985
1986	/*
1987	* The difference between 3022 and 3032 for inbound completions:
1988	* 3022 uses two buffers per completion. The first buffer contains
1989	* (some) header info, the second the remainder of the headers plus
1990	* the data. For this chip we reserve some space at the top of the
1991	* receive buffer so that the header info in buffer one can be
1992	* prepended to the buffer two. Buffer two is the sent up while
1993	* buffer one is returned to the hardware to be reused.
1994	* 3032 receives all of it's data and headers in one buffer for a
1995	* simpler process. 3032 also supports checksum verification as
1996	* can be seen in ql_process_macip_rx_intr().
1997	*/
1998	static void ql_process_mac_rx_intr(struct ql3_adapter *qdev,
1999	struct ib_mac_iocb_rsp *ib_mac_rsp_ptr)
2000	{
2001	struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
2002	struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
2003	struct sk_buff *skb;
2004	u16 length = le16_to_cpu(ib_mac_rsp_ptr->length);
2005
2006	/*
2007	* Get the inbound address list (small buffer).
2008	*/
2009	ql_get_sbuf(qdev);
2010
2011	if (qdev->device_id == QL3022_DEVICE_ID)
2012	lrg_buf_cb1 = ql_get_lbuf(qdev);
2013
2014	/* start of second buffer */
2015	lrg_buf_cb2 = ql_get_lbuf(qdev);
2016	skb = lrg_buf_cb2->skb;
2017
2018	qdev->ndev->stats.rx_packets++;
2019	qdev->ndev->stats.rx_bytes += length;
2020
2021	skb_put(skb, len: length);
2022	dma_unmap_single(&qdev->pdev->dev,
2023	dma_unmap_addr(lrg_buf_cb2, mapaddr),
2024	dma_unmap_len(lrg_buf_cb2, maplen), DMA_FROM_DEVICE);
2025	prefetch(skb->data);
2026	skb_checksum_none_assert(skb);
2027	skb->protocol = eth_type_trans(skb, dev: qdev->ndev);
2028
2029	napi_gro_receive(napi: &qdev->napi, skb);
2030	lrg_buf_cb2->skb = NULL;
2031
2032	if (qdev->device_id == QL3022_DEVICE_ID)
2033	ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb: lrg_buf_cb1);
2034	ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb: lrg_buf_cb2);
2035	}
2036
2037	static void ql_process_macip_rx_intr(struct ql3_adapter *qdev,
2038	struct ib_ip_iocb_rsp *ib_ip_rsp_ptr)
2039	{
2040	struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
2041	struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
2042	struct sk_buff *skb1 = NULL, *skb2;
2043	struct net_device *ndev = qdev->ndev;
2044	u16 length = le16_to_cpu(ib_ip_rsp_ptr->length);
2045	u16 size = 0;
2046
2047	/*
2048	* Get the inbound address list (small buffer).
2049	*/
2050
2051	ql_get_sbuf(qdev);
2052
2053	if (qdev->device_id == QL3022_DEVICE_ID) {
2054	/* start of first buffer on 3022 */
2055	lrg_buf_cb1 = ql_get_lbuf(qdev);
2056	skb1 = lrg_buf_cb1->skb;
2057	size = ETH_HLEN;
2058	if (*((u16 *) skb1->data) != 0xFFFF)
2059	size += VLAN_ETH_HLEN - ETH_HLEN;
2060	}
2061
2062	/* start of second buffer */
2063	lrg_buf_cb2 = ql_get_lbuf(qdev);
2064	skb2 = lrg_buf_cb2->skb;
2065
2066	skb_put(skb: skb2, len: length); /* Just the second buffer length here. */
2067	dma_unmap_single(&qdev->pdev->dev,
2068	dma_unmap_addr(lrg_buf_cb2, mapaddr),
2069	dma_unmap_len(lrg_buf_cb2, maplen), DMA_FROM_DEVICE);
2070	prefetch(skb2->data);
2071
2072	skb_checksum_none_assert(skb: skb2);
2073	if (qdev->device_id == QL3022_DEVICE_ID) {
2074	/*
2075	* Copy the ethhdr from first buffer to second. This
2076	* is necessary for 3022 IP completions.
2077	*/
2078	skb_copy_from_linear_data_offset(skb: skb1, VLAN_ID_LEN,
2079	to: skb_push(skb: skb2, len: size), len: size);
2080	} else {
2081	u16 checksum = le16_to_cpu(ib_ip_rsp_ptr->checksum);
2082	if (checksum &
2083	(IB_IP_IOCB_RSP_3032_ICE |
2084	IB_IP_IOCB_RSP_3032_CE)) {
2085	netdev_err(dev: ndev,
2086	format: "%s: Bad checksum for this %s packet, checksum = %x\n",
2087	__func__,
2088	((checksum & IB_IP_IOCB_RSP_3032_TCP) ?
2089	"TCP" : "UDP"), checksum);
2090	} else if ((checksum & IB_IP_IOCB_RSP_3032_TCP) ||
2091	(checksum & IB_IP_IOCB_RSP_3032_UDP &&
2092	!(checksum & IB_IP_IOCB_RSP_3032_NUC))) {
2093	skb2->ip_summed = CHECKSUM_UNNECESSARY;
2094	}
2095	}
2096	skb2->protocol = eth_type_trans(skb: skb2, dev: qdev->ndev);
2097
2098	napi_gro_receive(napi: &qdev->napi, skb: skb2);
2099	ndev->stats.rx_packets++;
2100	ndev->stats.rx_bytes += length;
2101	lrg_buf_cb2->skb = NULL;
2102
2103	if (qdev->device_id == QL3022_DEVICE_ID)
2104	ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb: lrg_buf_cb1);
2105	ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb: lrg_buf_cb2);
2106	}
2107
2108	static int ql_tx_rx_clean(struct ql3_adapter *qdev, int budget)
2109	{
2110	struct net_rsp_iocb *net_rsp;
2111	struct net_device *ndev = qdev->ndev;
2112	int work_done = 0;
2113
2114	/* While there are entries in the completion queue. */
2115	while ((le32_to_cpu(*(qdev->prsp_producer_index)) !=
2116	qdev->rsp_consumer_index) && (work_done < budget)) {
2117
2118	net_rsp = qdev->rsp_current;
2119	rmb();
2120	/*
2121	* Fix 4032 chip's undocumented "feature" where bit-8 is set
2122	* if the inbound completion is for a VLAN.
2123	*/
2124	if (qdev->device_id == QL3032_DEVICE_ID)
2125	net_rsp->opcode &= 0x7f;
2126	switch (net_rsp->opcode) {
2127
2128	case OPCODE_OB_MAC_IOCB_FN0:
2129	case OPCODE_OB_MAC_IOCB_FN2:
2130	ql_process_mac_tx_intr(qdev, mac_rsp: (struct ob_mac_iocb_rsp *)
2131	net_rsp);
2132	break;
2133
2134	case OPCODE_IB_MAC_IOCB:
2135	case OPCODE_IB_3032_MAC_IOCB:
2136	ql_process_mac_rx_intr(qdev, ib_mac_rsp_ptr: (struct ib_mac_iocb_rsp *)
2137	net_rsp);
2138	work_done++;
2139	break;
2140
2141	case OPCODE_IB_IP_IOCB:
2142	case OPCODE_IB_3032_IP_IOCB:
2143	ql_process_macip_rx_intr(qdev, ib_ip_rsp_ptr: (struct ib_ip_iocb_rsp *)
2144	net_rsp);
2145	work_done++;
2146	break;
2147	default: {
2148	u32 *tmp = (u32 *)net_rsp;
2149	netdev_err(dev: ndev,
2150	format: "Hit default case, not handled!\n"
2151	" dropping the packet, opcode = %x\n"
2152	"0x%08lx 0x%08lx 0x%08lx 0x%08lx\n",
2153	net_rsp->opcode,
2154	(unsigned long int)tmp[0],
2155	(unsigned long int)tmp[1],
2156	(unsigned long int)tmp[2],
2157	(unsigned long int)tmp[3]);
2158	}
2159	}
2160
2161	qdev->rsp_consumer_index++;
2162
2163	if (qdev->rsp_consumer_index == NUM_RSP_Q_ENTRIES) {
2164	qdev->rsp_consumer_index = 0;
2165	qdev->rsp_current = qdev->rsp_q_virt_addr;
2166	} else {
2167	qdev->rsp_current++;
2168	}
2169
2170	}
2171
2172	return work_done;
2173	}
2174
2175	static int ql_poll(struct napi_struct *napi, int budget)
2176	{
2177	struct ql3_adapter *qdev = container_of(napi, struct ql3_adapter, napi);
2178	struct ql3xxx_port_registers __iomem *port_regs =
2179	qdev->mem_map_registers;
2180	int work_done;
2181
2182	work_done = ql_tx_rx_clean(qdev, budget);
2183
2184	if (work_done < budget && napi_complete_done(n: napi, work_done)) {
2185	unsigned long flags;
2186
2187	spin_lock_irqsave(&qdev->hw_lock, flags);
2188	ql_update_small_bufq_prod_index(qdev);
2189	ql_update_lrg_bufq_prod_index(qdev);
2190	writel(val: qdev->rsp_consumer_index,
2191	addr: &port_regs->CommonRegs.rspQConsumerIndex);
2192	spin_unlock_irqrestore(lock: &qdev->hw_lock, flags);
2193
2194	ql_enable_interrupts(qdev);
2195	}
2196	return work_done;
2197	}
2198
2199	static irqreturn_t ql3xxx_isr(int irq, void *dev_id)
2200	{
2201
2202	struct net_device *ndev = dev_id;
2203	struct ql3_adapter *qdev = netdev_priv(dev: ndev);
2204	struct ql3xxx_port_registers __iomem *port_regs =
2205	qdev->mem_map_registers;
2206	u32 value;
2207	int handled = 1;
2208	u32 var;
2209
2210	value = ql_read_common_reg_l(qdev,
2211	reg: &port_regs->CommonRegs.ispControlStatus);
2212
2213	if (value & (ISP_CONTROL_FE | ISP_CONTROL_RI)) {
2214	spin_lock(lock: &qdev->adapter_lock);
2215	netif_stop_queue(dev: qdev->ndev);
2216	netif_carrier_off(dev: qdev->ndev);
2217	ql_disable_interrupts(qdev);
2218	qdev->port_link_state = LS_DOWN;
2219	set_bit(nr: QL_RESET_ACTIVE, addr: &qdev->flags) ;
2220
2221	if (value & ISP_CONTROL_FE) {
2222	/*
2223	* Chip Fatal Error.
2224	*/
2225	var =
2226	ql_read_page0_reg_l(qdev,
2227	reg: &port_regs->PortFatalErrStatus);
2228	netdev_warn(dev: ndev,
2229	format: "Resetting chip. PortFatalErrStatus register = 0x%x\n",
2230	var);
2231	set_bit(nr: QL_RESET_START, addr: &qdev->flags) ;
2232	} else {
2233	/*
2234	* Soft Reset Requested.
2235	*/
2236	set_bit(nr: QL_RESET_PER_SCSI, addr: &qdev->flags) ;
2237	netdev_err(dev: ndev,
2238	format: "Another function issued a reset to the chip. ISR value = %x\n",
2239	value);
2240	}
2241	queue_delayed_work(wq: qdev->workqueue, dwork: &qdev->reset_work, delay: 0);
2242	spin_unlock(lock: &qdev->adapter_lock);
2243	} else if (value & ISP_IMR_DISABLE_CMPL_INT) {
2244	ql_disable_interrupts(qdev);
2245	if (likely(napi_schedule_prep(&qdev->napi)))
2246	__napi_schedule(n: &qdev->napi);
2247	} else
2248	return IRQ_NONE;
2249
2250	return IRQ_RETVAL(handled);
2251	}
2252
2253	/*
2254	* Get the total number of segments needed for the given number of fragments.
2255	* This is necessary because outbound address lists (OAL) will be used when
2256	* more than two frags are given. Each address list has 5 addr/len pairs.
2257	* The 5th pair in each OAL is used to point to the next OAL if more frags
2258	* are coming. That is why the frags:segment count ratio is not linear.
2259	*/
2260	static int ql_get_seg_count(struct ql3_adapter *qdev, unsigned short frags)
2261	{
2262	if (qdev->device_id == QL3022_DEVICE_ID)
2263	return 1;
2264
2265	if (frags <= 2)
2266	return frags + 1;
2267	else if (frags <= 6)
2268	return frags + 2;
2269	else if (frags <= 10)
2270	return frags + 3;
2271	else if (frags <= 14)
2272	return frags + 4;
2273	else if (frags <= 18)
2274	return frags + 5;
2275	return -1;
2276	}
2277
2278	static void ql_hw_csum_setup(const struct sk_buff *skb,
2279	struct ob_mac_iocb_req *mac_iocb_ptr)
2280	{
2281	const struct iphdr *ip = ip_hdr(skb);
2282
2283	mac_iocb_ptr->ip_hdr_off = skb_network_offset(skb);
2284	mac_iocb_ptr->ip_hdr_len = ip->ihl;
2285
2286	if (ip->protocol == IPPROTO_TCP) {
2287	mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_TC |
2288	OB_3032MAC_IOCB_REQ_IC;
2289	} else {
2290	mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_UC |
2291	OB_3032MAC_IOCB_REQ_IC;
2292	}
2293
2294	}
2295
2296	/*
2297	* Map the buffers for this transmit.
2298	* This will return NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
2299	*/
2300	static int ql_send_map(struct ql3_adapter *qdev,
2301	struct ob_mac_iocb_req *mac_iocb_ptr,
2302	struct ql_tx_buf_cb *tx_cb,
2303	struct sk_buff *skb)
2304	{
2305	struct oal *oal;
2306	struct oal_entry *oal_entry;
2307	int len = skb_headlen(skb);
2308	dma_addr_t map;
2309	int err;
2310	int completed_segs, i;
2311	int seg_cnt, seg = 0;
2312	int frag_cnt = (int)skb_shinfo(skb)->nr_frags;
2313
2314	seg_cnt = tx_cb->seg_count;
2315	/*
2316	* Map the skb buffer first.
2317	*/
2318	map = dma_map_single(&qdev->pdev->dev, skb->data, len, DMA_TO_DEVICE);
2319
2320	err = dma_mapping_error(dev: &qdev->pdev->dev, dma_addr: map);
2321	if (err) {
2322	netdev_err(dev: qdev->ndev, format: "PCI mapping failed with error: %d\n",
2323	err);
2324
2325	return NETDEV_TX_BUSY;
2326	}
2327
2328	oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
2329	oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2330	oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2331	oal_entry->len = cpu_to_le32(len);
2332	dma_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2333	dma_unmap_len_set(&tx_cb->map[seg], maplen, len);
2334	seg++;
2335
2336	if (seg_cnt == 1) {
2337	/* Terminate the last segment. */
2338	oal_entry->len |= cpu_to_le32(OAL_LAST_ENTRY);
2339	return NETDEV_TX_OK;
2340	}
2341	oal = tx_cb->oal;
2342	for (completed_segs = 0;
2343	completed_segs < frag_cnt;
2344	completed_segs++, seg++) {
2345	skb_frag_t *frag = &skb_shinfo(skb)->frags[completed_segs];
2346	oal_entry++;
2347	/*
2348	* Check for continuation requirements.
2349	* It's strange but necessary.
2350	* Continuation entry points to outbound address list.
2351	*/
2352	if ((seg == 2 && seg_cnt > 3) ||
2353	(seg == 7 && seg_cnt > 8) ||
2354	(seg == 12 && seg_cnt > 13) ||
2355	(seg == 17 && seg_cnt > 18)) {
2356	map = dma_map_single(&qdev->pdev->dev, oal,
2357	sizeof(struct oal),
2358	DMA_TO_DEVICE);
2359
2360	err = dma_mapping_error(dev: &qdev->pdev->dev, dma_addr: map);
2361	if (err) {
2362	netdev_err(dev: qdev->ndev,
2363	format: "PCI mapping outbound address list with error: %d\n",
2364	err);
2365	goto map_error;
2366	}
2367
2368	oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2369	oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2370	oal_entry->len = cpu_to_le32(sizeof(struct oal) |
2371	OAL_CONT_ENTRY);
2372	dma_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2373	dma_unmap_len_set(&tx_cb->map[seg], maplen,
2374	sizeof(struct oal));
2375	oal_entry = (struct oal_entry *)oal;
2376	oal++;
2377	seg++;
2378	}
2379
2380	map = skb_frag_dma_map(dev: &qdev->pdev->dev, frag, offset: 0, size: skb_frag_size(frag),
2381	dir: DMA_TO_DEVICE);
2382
2383	err = dma_mapping_error(dev: &qdev->pdev->dev, dma_addr: map);
2384	if (err) {
2385	netdev_err(dev: qdev->ndev,
2386	format: "PCI mapping frags failed with error: %d\n",
2387	err);
2388	goto map_error;
2389	}
2390
2391	oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2392	oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2393	oal_entry->len = cpu_to_le32(skb_frag_size(frag));
2394	dma_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2395	dma_unmap_len_set(&tx_cb->map[seg], maplen, skb_frag_size(frag));
2396	}
2397	/* Terminate the last segment. */
2398	oal_entry->len |= cpu_to_le32(OAL_LAST_ENTRY);
2399	return NETDEV_TX_OK;
2400
2401	map_error:
2402	/* A PCI mapping failed and now we will need to back out
2403	* We need to traverse through the oal's and associated pages which
2404	* have been mapped and now we must unmap them to clean up properly
2405	*/
2406
2407	seg = 1;
2408	oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
2409	oal = tx_cb->oal;
2410	for (i = 0; i < completed_segs; i++, seg++) {
2411	oal_entry++;
2412
2413	/*
2414	* Check for continuation requirements.
2415	* It's strange but necessary.
2416	*/
2417
2418	if ((seg == 2 && seg_cnt > 3) ||
2419	(seg == 7 && seg_cnt > 8) ||
2420	(seg == 12 && seg_cnt > 13) ||
2421	(seg == 17 && seg_cnt > 18)) {
2422	dma_unmap_single(&qdev->pdev->dev,
2423	dma_unmap_addr(&tx_cb->map[seg], mapaddr),
2424	dma_unmap_len(&tx_cb->map[seg], maplen),
2425	DMA_TO_DEVICE);
2426	oal++;
2427	seg++;
2428	}
2429
2430	dma_unmap_page(&qdev->pdev->dev,
2431	dma_unmap_addr(&tx_cb->map[seg], mapaddr),
2432	dma_unmap_len(&tx_cb->map[seg], maplen),
2433	DMA_TO_DEVICE);
2434	}
2435
2436	dma_unmap_single(&qdev->pdev->dev,
2437	dma_unmap_addr(&tx_cb->map[0], mapaddr),
2438	dma_unmap_addr(&tx_cb->map[0], maplen),
2439	DMA_TO_DEVICE);
2440
2441	return NETDEV_TX_BUSY;
2442
2443	}
2444
2445	/*
2446	* The difference between 3022 and 3032 sends:
2447	* 3022 only supports a simple single segment transmission.
2448	* 3032 supports checksumming and scatter/gather lists (fragments).
2449	* The 3032 supports sglists by using the 3 addr/len pairs (ALP)
2450	* in the IOCB plus a chain of outbound address lists (OAL) that
2451	* each contain 5 ALPs. The last ALP of the IOCB (3rd) or OAL (5th)
2452	* will be used to point to an OAL when more ALP entries are required.
2453	* The IOCB is always the top of the chain followed by one or more
2454	* OALs (when necessary).
2455	*/
2456	static netdev_tx_t ql3xxx_send(struct sk_buff *skb,
2457	struct net_device *ndev)
2458	{
2459	struct ql3_adapter *qdev = netdev_priv(dev: ndev);
2460	struct ql3xxx_port_registers __iomem *port_regs =
2461	qdev->mem_map_registers;
2462	struct ql_tx_buf_cb *tx_cb;
2463	u32 tot_len = skb->len;
2464	struct ob_mac_iocb_req *mac_iocb_ptr;
2465
2466	if (unlikely(atomic_read(&qdev->tx_count) < 2))
2467	return NETDEV_TX_BUSY;
2468
2469	tx_cb = &qdev->tx_buf[qdev->req_producer_index];
2470	tx_cb->seg_count = ql_get_seg_count(qdev,
2471	skb_shinfo(skb)->nr_frags);
2472	if (tx_cb->seg_count == -1) {
2473	netdev_err(dev: ndev, format: "%s: invalid segment count!\n", __func__);
2474	dev_kfree_skb_any(skb);
2475	return NETDEV_TX_OK;
2476	}
2477
2478	mac_iocb_ptr = tx_cb->queue_entry;
2479	memset((void *)mac_iocb_ptr, 0, sizeof(struct ob_mac_iocb_req));
2480	mac_iocb_ptr->opcode = qdev->mac_ob_opcode;
2481	mac_iocb_ptr->flags = OB_MAC_IOCB_REQ_X;
2482	mac_iocb_ptr->flags |= qdev->mb_bit_mask;
2483	mac_iocb_ptr->transaction_id = qdev->req_producer_index;
2484	mac_iocb_ptr->data_len = cpu_to_le16((u16) tot_len);
2485	tx_cb->skb = skb;
2486	if (qdev->device_id == QL3032_DEVICE_ID &&
2487	skb->ip_summed == CHECKSUM_PARTIAL)
2488	ql_hw_csum_setup(skb, mac_iocb_ptr);
2489
2490	if (ql_send_map(qdev, mac_iocb_ptr, tx_cb, skb) != NETDEV_TX_OK) {
2491	netdev_err(dev: ndev, format: "%s: Could not map the segments!\n", __func__);
2492	return NETDEV_TX_BUSY;
2493	}
2494
2495	wmb();
2496	qdev->req_producer_index++;
2497	if (qdev->req_producer_index == NUM_REQ_Q_ENTRIES)
2498	qdev->req_producer_index = 0;
2499	wmb();
2500	ql_write_common_reg_l(qdev,
2501	reg: &port_regs->CommonRegs.reqQProducerIndex,
2502	value: qdev->req_producer_index);
2503
2504	netif_printk(qdev, tx_queued, KERN_DEBUG, ndev,
2505	"tx queued, slot %d, len %d\n",
2506	qdev->req_producer_index, skb->len);
2507
2508	atomic_dec(v: &qdev->tx_count);
2509	return NETDEV_TX_OK;
2510	}
2511
2512	static int ql_alloc_net_req_rsp_queues(struct ql3_adapter *qdev)
2513	{
2514	qdev->req_q_size =
2515	(u32) (NUM_REQ_Q_ENTRIES * sizeof(struct ob_mac_iocb_req));
2516
2517	qdev->rsp_q_size = NUM_RSP_Q_ENTRIES * sizeof(struct net_rsp_iocb);
2518
2519	/* The barrier is required to ensure request and response queue
2520	* addr writes to the registers.
2521	*/
2522	wmb();
2523
2524	qdev->req_q_virt_addr =
2525	dma_alloc_coherent(dev: &qdev->pdev->dev, size: (size_t)qdev->req_q_size,
2526	dma_handle: &qdev->req_q_phy_addr, GFP_KERNEL);
2527
2528	if ((qdev->req_q_virt_addr == NULL) ||
2529	LS_64BITS(qdev->req_q_phy_addr) & (qdev->req_q_size - 1)) {
2530	netdev_err(dev: qdev->ndev, format: "reqQ failed\n");
2531	return -ENOMEM;
2532	}
2533
2534	qdev->rsp_q_virt_addr =
2535	dma_alloc_coherent(dev: &qdev->pdev->dev, size: (size_t)qdev->rsp_q_size,
2536	dma_handle: &qdev->rsp_q_phy_addr, GFP_KERNEL);
2537
2538	if ((qdev->rsp_q_virt_addr == NULL) ||
2539	LS_64BITS(qdev->rsp_q_phy_addr) & (qdev->rsp_q_size - 1)) {
2540	netdev_err(dev: qdev->ndev, format: "rspQ allocation failed\n");
2541	dma_free_coherent(dev: &qdev->pdev->dev, size: (size_t)qdev->req_q_size,
2542	cpu_addr: qdev->req_q_virt_addr, dma_handle: qdev->req_q_phy_addr);
2543	return -ENOMEM;
2544	}
2545
2546	set_bit(nr: QL_ALLOC_REQ_RSP_Q_DONE, addr: &qdev->flags);
2547
2548	return 0;
2549	}
2550
2551	static void ql_free_net_req_rsp_queues(struct ql3_adapter *qdev)
2552	{
2553	if (!test_bit(QL_ALLOC_REQ_RSP_Q_DONE, &qdev->flags)) {
2554	netdev_info(dev: qdev->ndev, format: "Already done\n");
2555	return;
2556	}
2557
2558	dma_free_coherent(dev: &qdev->pdev->dev, size: qdev->req_q_size,
2559	cpu_addr: qdev->req_q_virt_addr, dma_handle: qdev->req_q_phy_addr);
2560
2561	qdev->req_q_virt_addr = NULL;
2562
2563	dma_free_coherent(dev: &qdev->pdev->dev, size: qdev->rsp_q_size,
2564	cpu_addr: qdev->rsp_q_virt_addr, dma_handle: qdev->rsp_q_phy_addr);
2565
2566	qdev->rsp_q_virt_addr = NULL;
2567
2568	clear_bit(nr: QL_ALLOC_REQ_RSP_Q_DONE, addr: &qdev->flags);
2569	}
2570
2571	static int ql_alloc_buffer_queues(struct ql3_adapter *qdev)
2572	{
2573	/* Create Large Buffer Queue */
2574	qdev->lrg_buf_q_size =
2575	qdev->num_lbufq_entries * sizeof(struct lrg_buf_q_entry);
2576	if (qdev->lrg_buf_q_size < PAGE_SIZE)
2577	qdev->lrg_buf_q_alloc_size = PAGE_SIZE;
2578	else
2579	qdev->lrg_buf_q_alloc_size = qdev->lrg_buf_q_size * 2;
2580
2581	qdev->lrg_buf = kmalloc_array(n: qdev->num_large_buffers,
2582	size: sizeof(struct ql_rcv_buf_cb),
2583	GFP_KERNEL);
2584	if (qdev->lrg_buf == NULL)
2585	return -ENOMEM;
2586
2587	qdev->lrg_buf_q_alloc_virt_addr =
2588	dma_alloc_coherent(dev: &qdev->pdev->dev,
2589	size: qdev->lrg_buf_q_alloc_size,
2590	dma_handle: &qdev->lrg_buf_q_alloc_phy_addr, GFP_KERNEL);
2591
2592	if (qdev->lrg_buf_q_alloc_virt_addr == NULL) {
2593	netdev_err(dev: qdev->ndev, format: "lBufQ failed\n");
2594	return -ENOMEM;
2595	}
2596	qdev->lrg_buf_q_virt_addr = qdev->lrg_buf_q_alloc_virt_addr;
2597	qdev->lrg_buf_q_phy_addr = qdev->lrg_buf_q_alloc_phy_addr;
2598
2599	/* Create Small Buffer Queue */
2600	qdev->small_buf_q_size =
2601	NUM_SBUFQ_ENTRIES * sizeof(struct lrg_buf_q_entry);
2602	if (qdev->small_buf_q_size < PAGE_SIZE)
2603	qdev->small_buf_q_alloc_size = PAGE_SIZE;
2604	else
2605	qdev->small_buf_q_alloc_size = qdev->small_buf_q_size * 2;
2606
2607	qdev->small_buf_q_alloc_virt_addr =
2608	dma_alloc_coherent(dev: &qdev->pdev->dev,
2609	size: qdev->small_buf_q_alloc_size,
2610	dma_handle: &qdev->small_buf_q_alloc_phy_addr, GFP_KERNEL);
2611
2612	if (qdev->small_buf_q_alloc_virt_addr == NULL) {
2613	netdev_err(dev: qdev->ndev, format: "Small Buffer Queue allocation failed\n");
2614	dma_free_coherent(dev: &qdev->pdev->dev,
2615	size: qdev->lrg_buf_q_alloc_size,
2616	cpu_addr: qdev->lrg_buf_q_alloc_virt_addr,
2617	dma_handle: qdev->lrg_buf_q_alloc_phy_addr);
2618	return -ENOMEM;
2619	}
2620
2621	qdev->small_buf_q_virt_addr = qdev->small_buf_q_alloc_virt_addr;
2622	qdev->small_buf_q_phy_addr = qdev->small_buf_q_alloc_phy_addr;
2623	set_bit(nr: QL_ALLOC_BUFQS_DONE, addr: &qdev->flags);
2624	return 0;
2625	}
2626
2627	static void ql_free_buffer_queues(struct ql3_adapter *qdev)
2628	{
2629	if (!test_bit(QL_ALLOC_BUFQS_DONE, &qdev->flags)) {
2630	netdev_info(dev: qdev->ndev, format: "Already done\n");
2631	return;
2632	}
2633	kfree(objp: qdev->lrg_buf);
2634	dma_free_coherent(dev: &qdev->pdev->dev, size: qdev->lrg_buf_q_alloc_size,
2635	cpu_addr: qdev->lrg_buf_q_alloc_virt_addr,
2636	dma_handle: qdev->lrg_buf_q_alloc_phy_addr);
2637
2638	qdev->lrg_buf_q_virt_addr = NULL;
2639
2640	dma_free_coherent(dev: &qdev->pdev->dev, size: qdev->small_buf_q_alloc_size,
2641	cpu_addr: qdev->small_buf_q_alloc_virt_addr,
2642	dma_handle: qdev->small_buf_q_alloc_phy_addr);
2643
2644	qdev->small_buf_q_virt_addr = NULL;
2645
2646	clear_bit(nr: QL_ALLOC_BUFQS_DONE, addr: &qdev->flags);
2647	}
2648
2649	static int ql_alloc_small_buffers(struct ql3_adapter *qdev)
2650	{
2651	int i;
2652	struct bufq_addr_element *small_buf_q_entry;
2653
2654	/* Currently we allocate on one of memory and use it for smallbuffers */
2655	qdev->small_buf_total_size =
2656	(QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES *
2657	QL_SMALL_BUFFER_SIZE);
2658
2659	qdev->small_buf_virt_addr =
2660	dma_alloc_coherent(dev: &qdev->pdev->dev,
2661	size: qdev->small_buf_total_size,
2662	dma_handle: &qdev->small_buf_phy_addr, GFP_KERNEL);
2663
2664	if (qdev->small_buf_virt_addr == NULL) {
2665	netdev_err(dev: qdev->ndev, format: "Failed to get small buffer memory\n");
2666	return -ENOMEM;
2667	}
2668
2669	qdev->small_buf_phy_addr_low = LS_64BITS(qdev->small_buf_phy_addr);
2670	qdev->small_buf_phy_addr_high = MS_64BITS(qdev->small_buf_phy_addr);
2671
2672	small_buf_q_entry = qdev->small_buf_q_virt_addr;
2673
2674	/* Initialize the small buffer queue. */
2675	for (i = 0; i < (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES); i++) {
2676	small_buf_q_entry->addr_high =
2677	cpu_to_le32(qdev->small_buf_phy_addr_high);
2678	small_buf_q_entry->addr_low =
2679	cpu_to_le32(qdev->small_buf_phy_addr_low +
2680	(i * QL_SMALL_BUFFER_SIZE));
2681	small_buf_q_entry++;
2682	}
2683	qdev->small_buf_index = 0;
2684	set_bit(nr: QL_ALLOC_SMALL_BUF_DONE, addr: &qdev->flags);
2685	return 0;
2686	}
2687
2688	static void ql_free_small_buffers(struct ql3_adapter *qdev)
2689	{
2690	if (!test_bit(QL_ALLOC_SMALL_BUF_DONE, &qdev->flags)) {
2691	netdev_info(dev: qdev->ndev, format: "Already done\n");
2692	return;
2693	}
2694	if (qdev->small_buf_virt_addr != NULL) {
2695	dma_free_coherent(dev: &qdev->pdev->dev,
2696	size: qdev->small_buf_total_size,
2697	cpu_addr: qdev->small_buf_virt_addr,
2698	dma_handle: qdev->small_buf_phy_addr);
2699
2700	qdev->small_buf_virt_addr = NULL;
2701	}
2702	}
2703
2704	static void ql_free_large_buffers(struct ql3_adapter *qdev)
2705	{
2706	int i = 0;
2707	struct ql_rcv_buf_cb *lrg_buf_cb;
2708
2709	for (i = 0; i < qdev->num_large_buffers; i++) {
2710	lrg_buf_cb = &qdev->lrg_buf[i];
2711	if (lrg_buf_cb->skb) {
2712	dev_kfree_skb(lrg_buf_cb->skb);
2713	dma_unmap_single(&qdev->pdev->dev,
2714	dma_unmap_addr(lrg_buf_cb, mapaddr),
2715	dma_unmap_len(lrg_buf_cb, maplen),
2716	DMA_FROM_DEVICE);
2717	memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2718	} else {
2719	break;
2720	}
2721	}
2722	}
2723
2724	static void ql_init_large_buffers(struct ql3_adapter *qdev)
2725	{
2726	int i;
2727	struct ql_rcv_buf_cb *lrg_buf_cb;
2728	struct bufq_addr_element *buf_addr_ele = qdev->lrg_buf_q_virt_addr;
2729
2730	for (i = 0; i < qdev->num_large_buffers; i++) {
2731	lrg_buf_cb = &qdev->lrg_buf[i];
2732	buf_addr_ele->addr_high = lrg_buf_cb->buf_phy_addr_high;
2733	buf_addr_ele->addr_low = lrg_buf_cb->buf_phy_addr_low;
2734	buf_addr_ele++;
2735	}
2736	qdev->lrg_buf_index = 0;
2737	qdev->lrg_buf_skb_check = 0;
2738	}
2739
2740	static int ql_alloc_large_buffers(struct ql3_adapter *qdev)
2741	{
2742	int i;
2743	struct ql_rcv_buf_cb *lrg_buf_cb;
2744	struct sk_buff *skb;
2745	dma_addr_t map;
2746	int err;
2747
2748	for (i = 0; i < qdev->num_large_buffers; i++) {
2749	lrg_buf_cb = &qdev->lrg_buf[i];
2750	memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2751
2752	skb = netdev_alloc_skb(dev: qdev->ndev,
2753	length: qdev->lrg_buffer_len);
2754	if (unlikely(!skb)) {
2755	/* Better luck next round */
2756	netdev_err(dev: qdev->ndev,
2757	format: "large buff alloc failed for %d bytes at index %d\n",
2758	qdev->lrg_buffer_len * 2, i);
2759	ql_free_large_buffers(qdev);
2760	return -ENOMEM;
2761	} else {
2762	lrg_buf_cb->index = i;
2763	/*
2764	* We save some space to copy the ethhdr from first
2765	* buffer
2766	*/
2767	skb_reserve(skb, QL_HEADER_SPACE);
2768	map = dma_map_single(&qdev->pdev->dev, skb->data,
2769	qdev->lrg_buffer_len - QL_HEADER_SPACE,
2770	DMA_FROM_DEVICE);
2771
2772	err = dma_mapping_error(dev: &qdev->pdev->dev, dma_addr: map);
2773	if (err) {
2774	netdev_err(dev: qdev->ndev,
2775	format: "PCI mapping failed with error: %d\n",
2776	err);
2777	dev_kfree_skb_irq(skb);
2778	ql_free_large_buffers(qdev);
2779	return -ENOMEM;
2780	}
2781
2782	lrg_buf_cb->skb = skb;
2783	dma_unmap_addr_set(lrg_buf_cb, mapaddr, map);
2784	dma_unmap_len_set(lrg_buf_cb, maplen,
2785	qdev->lrg_buffer_len -
2786	QL_HEADER_SPACE);
2787	lrg_buf_cb->buf_phy_addr_low =
2788	cpu_to_le32(LS_64BITS(map));
2789	lrg_buf_cb->buf_phy_addr_high =
2790	cpu_to_le32(MS_64BITS(map));
2791	}
2792	}
2793	return 0;
2794	}
2795
2796	static void ql_free_send_free_list(struct ql3_adapter *qdev)
2797	{
2798	struct ql_tx_buf_cb *tx_cb;
2799	int i;
2800
2801	tx_cb = &qdev->tx_buf[0];
2802	for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
2803	kfree(objp: tx_cb->oal);
2804	tx_cb->oal = NULL;
2805	tx_cb++;
2806	}
2807	}
2808
2809	static int ql_create_send_free_list(struct ql3_adapter *qdev)
2810	{
2811	struct ql_tx_buf_cb *tx_cb;
2812	int i;
2813	struct ob_mac_iocb_req *req_q_curr = qdev->req_q_virt_addr;
2814
2815	/* Create free list of transmit buffers */
2816	for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
2817
2818	tx_cb = &qdev->tx_buf[i];
2819	tx_cb->skb = NULL;
2820	tx_cb->queue_entry = req_q_curr;
2821	req_q_curr++;
2822	tx_cb->oal = kmalloc(size: 512, GFP_KERNEL);
2823	if (tx_cb->oal == NULL)
2824	return -ENOMEM;
2825	}
2826	return 0;
2827	}
2828
2829	static int ql_alloc_mem_resources(struct ql3_adapter *qdev)
2830	{
2831	if (qdev->ndev->mtu == NORMAL_MTU_SIZE) {
2832	qdev->num_lbufq_entries = NUM_LBUFQ_ENTRIES;
2833	qdev->lrg_buffer_len = NORMAL_MTU_SIZE;
2834	} else if (qdev->ndev->mtu == JUMBO_MTU_SIZE) {
2835	/*
2836	* Bigger buffers, so less of them.
2837	*/
2838	qdev->num_lbufq_entries = JUMBO_NUM_LBUFQ_ENTRIES;
2839	qdev->lrg_buffer_len = JUMBO_MTU_SIZE;
2840	} else {
2841	netdev_err(dev: qdev->ndev, format: "Invalid mtu size: %d. Only %d and %d are accepted.\n",
2842	qdev->ndev->mtu, NORMAL_MTU_SIZE, JUMBO_MTU_SIZE);
2843	return -ENOMEM;
2844	}
2845	qdev->num_large_buffers =
2846	qdev->num_lbufq_entries * QL_ADDR_ELE_PER_BUFQ_ENTRY;
2847	qdev->lrg_buffer_len += VLAN_ETH_HLEN + VLAN_ID_LEN + QL_HEADER_SPACE;
2848	qdev->max_frame_size =
2849	(qdev->lrg_buffer_len - QL_HEADER_SPACE) + ETHERNET_CRC_SIZE;
2850
2851	/*
2852	* First allocate a page of shared memory and use it for shadow
2853	* locations of Network Request Queue Consumer Address Register and
2854	* Network Completion Queue Producer Index Register
2855	*/
2856	qdev->shadow_reg_virt_addr =
2857	dma_alloc_coherent(dev: &qdev->pdev->dev, PAGE_SIZE,
2858	dma_handle: &qdev->shadow_reg_phy_addr, GFP_KERNEL);
2859
2860	if (qdev->shadow_reg_virt_addr != NULL) {
2861	qdev->preq_consumer_index = qdev->shadow_reg_virt_addr;
2862	qdev->req_consumer_index_phy_addr_high =
2863	MS_64BITS(qdev->shadow_reg_phy_addr);
2864	qdev->req_consumer_index_phy_addr_low =
2865	LS_64BITS(qdev->shadow_reg_phy_addr);
2866
2867	qdev->prsp_producer_index =
2868	(__le32 *) (((u8 *) qdev->preq_consumer_index) + 8);
2869	qdev->rsp_producer_index_phy_addr_high =
2870	qdev->req_consumer_index_phy_addr_high;
2871	qdev->rsp_producer_index_phy_addr_low =
2872	qdev->req_consumer_index_phy_addr_low + 8;
2873	} else {
2874	netdev_err(dev: qdev->ndev, format: "shadowReg Alloc failed\n");
2875	return -ENOMEM;
2876	}
2877
2878	if (ql_alloc_net_req_rsp_queues(qdev) != 0) {
2879	netdev_err(dev: qdev->ndev, format: "ql_alloc_net_req_rsp_queues failed\n");
2880	goto err_req_rsp;
2881	}
2882
2883	if (ql_alloc_buffer_queues(qdev) != 0) {
2884	netdev_err(dev: qdev->ndev, format: "ql_alloc_buffer_queues failed\n");
2885	goto err_buffer_queues;
2886	}
2887
2888	if (ql_alloc_small_buffers(qdev) != 0) {
2889	netdev_err(dev: qdev->ndev, format: "ql_alloc_small_buffers failed\n");
2890	goto err_small_buffers;
2891	}
2892
2893	if (ql_alloc_large_buffers(qdev) != 0) {
2894	netdev_err(dev: qdev->ndev, format: "ql_alloc_large_buffers failed\n");
2895	goto err_small_buffers;
2896	}
2897
2898	/* Initialize the large buffer queue. */
2899	ql_init_large_buffers(qdev);
2900	if (ql_create_send_free_list(qdev))
2901	goto err_free_list;
2902
2903	qdev->rsp_current = qdev->rsp_q_virt_addr;
2904
2905	return 0;
2906	err_free_list:
2907	ql_free_send_free_list(qdev);
2908	err_small_buffers:
2909	ql_free_buffer_queues(qdev);
2910	err_buffer_queues:
2911	ql_free_net_req_rsp_queues(qdev);
2912	err_req_rsp:
2913	dma_free_coherent(dev: &qdev->pdev->dev, PAGE_SIZE,
2914	cpu_addr: qdev->shadow_reg_virt_addr,
2915	dma_handle: qdev->shadow_reg_phy_addr);
2916
2917	return -ENOMEM;
2918	}
2919
2920	static void ql_free_mem_resources(struct ql3_adapter *qdev)
2921	{
2922	ql_free_send_free_list(qdev);
2923	ql_free_large_buffers(qdev);
2924	ql_free_small_buffers(qdev);
2925	ql_free_buffer_queues(qdev);
2926	ql_free_net_req_rsp_queues(qdev);
2927	if (qdev->shadow_reg_virt_addr != NULL) {
2928	dma_free_coherent(dev: &qdev->pdev->dev, PAGE_SIZE,
2929	cpu_addr: qdev->shadow_reg_virt_addr,
2930	dma_handle: qdev->shadow_reg_phy_addr);
2931	qdev->shadow_reg_virt_addr = NULL;
2932	}
2933	}
2934
2935	static int ql_init_misc_registers(struct ql3_adapter *qdev)
2936	{
2937	struct ql3xxx_local_ram_registers __iomem *local_ram =
2938	(void __iomem *)qdev->mem_map_registers;
2939
2940	if (ql_sem_spinlock(qdev, sem_mask: QL_DDR_RAM_SEM_MASK,
2941	sem_bits: (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
2942	2) << 4))
2943	return -1;
2944
2945	ql_write_page2_reg(qdev,
2946	reg: &local_ram->bufletSize, value: qdev->nvram_data.bufletSize);
2947
2948	ql_write_page2_reg(qdev,
2949	reg: &local_ram->maxBufletCount,
2950	value: qdev->nvram_data.bufletCount);
2951
2952	ql_write_page2_reg(qdev,
2953	reg: &local_ram->freeBufletThresholdLow,
2954	value: (qdev->nvram_data.tcpWindowThreshold25 << 16) |
2955	(qdev->nvram_data.tcpWindowThreshold0));
2956
2957	ql_write_page2_reg(qdev,
2958	reg: &local_ram->freeBufletThresholdHigh,
2959	value: qdev->nvram_data.tcpWindowThreshold50);
2960
2961	ql_write_page2_reg(qdev,
2962	reg: &local_ram->ipHashTableBase,
2963	value: (qdev->nvram_data.ipHashTableBaseHi << 16) |
2964	qdev->nvram_data.ipHashTableBaseLo);
2965	ql_write_page2_reg(qdev,
2966	reg: &local_ram->ipHashTableCount,
2967	value: qdev->nvram_data.ipHashTableSize);
2968	ql_write_page2_reg(qdev,
2969	reg: &local_ram->tcpHashTableBase,
2970	value: (qdev->nvram_data.tcpHashTableBaseHi << 16) |
2971	qdev->nvram_data.tcpHashTableBaseLo);
2972	ql_write_page2_reg(qdev,
2973	reg: &local_ram->tcpHashTableCount,
2974	value: qdev->nvram_data.tcpHashTableSize);
2975	ql_write_page2_reg(qdev,
2976	reg: &local_ram->ncbBase,
2977	value: (qdev->nvram_data.ncbTableBaseHi << 16) |
2978	qdev->nvram_data.ncbTableBaseLo);
2979	ql_write_page2_reg(qdev,
2980	reg: &local_ram->maxNcbCount,
2981	value: qdev->nvram_data.ncbTableSize);
2982	ql_write_page2_reg(qdev,
2983	reg: &local_ram->drbBase,
2984	value: (qdev->nvram_data.drbTableBaseHi << 16) |
2985	qdev->nvram_data.drbTableBaseLo);
2986	ql_write_page2_reg(qdev,
2987	reg: &local_ram->maxDrbCount,
2988	value: qdev->nvram_data.drbTableSize);
2989	ql_sem_unlock(qdev, sem_mask: QL_DDR_RAM_SEM_MASK);
2990	return 0;
2991	}
2992
2993	static int ql_adapter_initialize(struct ql3_adapter *qdev)
2994	{
2995	u32 value;
2996	struct ql3xxx_port_registers __iomem *port_regs =
2997	qdev->mem_map_registers;
2998	__iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
2999	struct ql3xxx_host_memory_registers __iomem *hmem_regs =
3000	(void __iomem *)port_regs;
3001	u32 delay = 10;
3002	int status = 0;
3003
3004	if (ql_mii_setup(qdev))
3005	return -1;
3006
3007	/* Bring out PHY out of reset */
3008	ql_write_common_reg(qdev, reg: spir,
3009	value: (ISP_SERIAL_PORT_IF_WE |
3010	(ISP_SERIAL_PORT_IF_WE << 16)));
3011	/* Give the PHY time to come out of reset. */
3012	mdelay(100);
3013	qdev->port_link_state = LS_DOWN;
3014	netif_carrier_off(dev: qdev->ndev);
3015
3016	/* V2 chip fix for ARS-39168. */
3017	ql_write_common_reg(qdev, reg: spir,
3018	value: (ISP_SERIAL_PORT_IF_SDE |
3019	(ISP_SERIAL_PORT_IF_SDE << 16)));
3020
3021	/* Request Queue Registers */
3022	*((u32 *)(qdev->preq_consumer_index)) = 0;
3023	atomic_set(v: &qdev->tx_count, NUM_REQ_Q_ENTRIES);
3024	qdev->req_producer_index = 0;
3025
3026	ql_write_page1_reg(qdev,
3027	reg: &hmem_regs->reqConsumerIndexAddrHigh,
3028	value: qdev->req_consumer_index_phy_addr_high);
3029	ql_write_page1_reg(qdev,
3030	reg: &hmem_regs->reqConsumerIndexAddrLow,
3031	value: qdev->req_consumer_index_phy_addr_low);
3032
3033	ql_write_page1_reg(qdev,
3034	reg: &hmem_regs->reqBaseAddrHigh,
3035	MS_64BITS(qdev->req_q_phy_addr));
3036	ql_write_page1_reg(qdev,
3037	reg: &hmem_regs->reqBaseAddrLow,
3038	LS_64BITS(qdev->req_q_phy_addr));
3039	ql_write_page1_reg(qdev, reg: &hmem_regs->reqLength, NUM_REQ_Q_ENTRIES);
3040
3041	/* Response Queue Registers */
3042	*((__le16 *) (qdev->prsp_producer_index)) = 0;
3043	qdev->rsp_consumer_index = 0;
3044	qdev->rsp_current = qdev->rsp_q_virt_addr;
3045
3046	ql_write_page1_reg(qdev,
3047	reg: &hmem_regs->rspProducerIndexAddrHigh,
3048	value: qdev->rsp_producer_index_phy_addr_high);
3049
3050	ql_write_page1_reg(qdev,
3051	reg: &hmem_regs->rspProducerIndexAddrLow,
3052	value: qdev->rsp_producer_index_phy_addr_low);
3053
3054	ql_write_page1_reg(qdev,
3055	reg: &hmem_regs->rspBaseAddrHigh,
3056	MS_64BITS(qdev->rsp_q_phy_addr));
3057
3058	ql_write_page1_reg(qdev,
3059	reg: &hmem_regs->rspBaseAddrLow,
3060	LS_64BITS(qdev->rsp_q_phy_addr));
3061
3062	ql_write_page1_reg(qdev, reg: &hmem_regs->rspLength, NUM_RSP_Q_ENTRIES);
3063
3064	/* Large Buffer Queue */
3065	ql_write_page1_reg(qdev,
3066	reg: &hmem_regs->rxLargeQBaseAddrHigh,
3067	MS_64BITS(qdev->lrg_buf_q_phy_addr));
3068
3069	ql_write_page1_reg(qdev,
3070	reg: &hmem_regs->rxLargeQBaseAddrLow,
3071	LS_64BITS(qdev->lrg_buf_q_phy_addr));
3072
3073	ql_write_page1_reg(qdev,
3074	reg: &hmem_regs->rxLargeQLength,
3075	value: qdev->num_lbufq_entries);
3076
3077	ql_write_page1_reg(qdev,
3078	reg: &hmem_regs->rxLargeBufferLength,
3079	value: qdev->lrg_buffer_len);
3080
3081	/* Small Buffer Queue */
3082	ql_write_page1_reg(qdev,
3083	reg: &hmem_regs->rxSmallQBaseAddrHigh,
3084	MS_64BITS(qdev->small_buf_q_phy_addr));
3085
3086	ql_write_page1_reg(qdev,
3087	reg: &hmem_regs->rxSmallQBaseAddrLow,
3088	LS_64BITS(qdev->small_buf_q_phy_addr));
3089
3090	ql_write_page1_reg(qdev, reg: &hmem_regs->rxSmallQLength, NUM_SBUFQ_ENTRIES);
3091	ql_write_page1_reg(qdev,
3092	reg: &hmem_regs->rxSmallBufferLength,
3093	QL_SMALL_BUFFER_SIZE);
3094
3095	qdev->small_buf_q_producer_index = NUM_SBUFQ_ENTRIES - 1;
3096	qdev->small_buf_release_cnt = 8;
3097	qdev->lrg_buf_q_producer_index = qdev->num_lbufq_entries - 1;
3098	qdev->lrg_buf_release_cnt = 8;
3099	qdev->lrg_buf_next_free = qdev->lrg_buf_q_virt_addr;
3100	qdev->small_buf_index = 0;
3101	qdev->lrg_buf_index = 0;
3102	qdev->lrg_buf_free_count = 0;
3103	qdev->lrg_buf_free_head = NULL;
3104	qdev->lrg_buf_free_tail = NULL;
3105
3106	ql_write_common_reg(qdev,
3107	reg: &port_regs->CommonRegs.
3108	rxSmallQProducerIndex,
3109	value: qdev->small_buf_q_producer_index);
3110	ql_write_common_reg(qdev,
3111	reg: &port_regs->CommonRegs.
3112	rxLargeQProducerIndex,
3113	value: qdev->lrg_buf_q_producer_index);
3114
3115	/*
3116	* Find out if the chip has already been initialized. If it has, then
3117	* we skip some of the initialization.
3118	*/
3119	clear_bit(nr: QL_LINK_MASTER, addr: &qdev->flags);
3120	value = ql_read_page0_reg(qdev, reg: &port_regs->portStatus);
3121	if ((value & PORT_STATUS_IC) == 0) {
3122
3123	/* Chip has not been configured yet, so let it rip. */
3124	if (ql_init_misc_registers(qdev)) {
3125	status = -1;
3126	goto out;
3127	}
3128
3129	value = qdev->nvram_data.tcpMaxWindowSize;
3130	ql_write_page0_reg(qdev, reg: &port_regs->tcpMaxWindow, value);
3131
3132	value = (0xFFFF << 16) | qdev->nvram_data.extHwConfig;
3133
3134	if (ql_sem_spinlock(qdev, sem_mask: QL_FLASH_SEM_MASK,
3135	sem_bits: (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
3136	* 2) << 13)) {
3137	status = -1;
3138	goto out;
3139	}
3140	ql_write_page0_reg(qdev, reg: &port_regs->ExternalHWConfig, value);
3141	ql_write_page0_reg(qdev, reg: &port_regs->InternalChipConfig,
3142	value: (((INTERNAL_CHIP_SD | INTERNAL_CHIP_WE) <<
3143	16) | (INTERNAL_CHIP_SD |
3144	INTERNAL_CHIP_WE)));
3145	ql_sem_unlock(qdev, sem_mask: QL_FLASH_SEM_MASK);
3146	}
3147
3148	if (qdev->mac_index)
3149	ql_write_page0_reg(qdev,
3150	reg: &port_regs->mac1MaxFrameLengthReg,
3151	value: qdev->max_frame_size);
3152	else
3153	ql_write_page0_reg(qdev,
3154	reg: &port_regs->mac0MaxFrameLengthReg,
3155	value: qdev->max_frame_size);
3156
3157	if (ql_sem_spinlock(qdev, sem_mask: QL_PHY_GIO_SEM_MASK,
3158	sem_bits: (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
3159	2) << 7)) {
3160	status = -1;
3161	goto out;
3162	}
3163
3164	PHY_Setup(qdev);
3165	ql_init_scan_mode(qdev);
3166	ql_get_phy_owner(qdev);
3167
3168	/* Load the MAC Configuration */
3169
3170	/* Program lower 32 bits of the MAC address */
3171	ql_write_page0_reg(qdev, reg: &port_regs->macAddrIndirectPtrReg,
3172	value: (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
3173	ql_write_page0_reg(qdev, reg: &port_regs->macAddrDataReg,
3174	value: ((qdev->ndev->dev_addr[2] << 24)
3175	| (qdev->ndev->dev_addr[3] << 16)
3176	| (qdev->ndev->dev_addr[4] << 8)
3177	| qdev->ndev->dev_addr[5]));
3178
3179	/* Program top 16 bits of the MAC address */
3180	ql_write_page0_reg(qdev, reg: &port_regs->macAddrIndirectPtrReg,
3181	value: ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
3182	ql_write_page0_reg(qdev, reg: &port_regs->macAddrDataReg,
3183	value: ((qdev->ndev->dev_addr[0] << 8)
3184	| qdev->ndev->dev_addr[1]));
3185
3186	/* Enable Primary MAC */
3187	ql_write_page0_reg(qdev, reg: &port_regs->macAddrIndirectPtrReg,
3188	value: ((MAC_ADDR_INDIRECT_PTR_REG_PE << 16) |
3189	MAC_ADDR_INDIRECT_PTR_REG_PE));
3190
3191	/* Clear Primary and Secondary IP addresses */
3192	ql_write_page0_reg(qdev, reg: &port_regs->ipAddrIndexReg,
3193	value: ((IP_ADDR_INDEX_REG_MASK << 16) |
3194	(qdev->mac_index << 2)));
3195	ql_write_page0_reg(qdev, reg: &port_regs->ipAddrDataReg, value: 0);
3196
3197	ql_write_page0_reg(qdev, reg: &port_regs->ipAddrIndexReg,
3198	value: ((IP_ADDR_INDEX_REG_MASK << 16) |
3199	((qdev->mac_index << 2) + 1)));
3200	ql_write_page0_reg(qdev, reg: &port_regs->ipAddrDataReg, value: 0);
3201
3202	ql_sem_unlock(qdev, sem_mask: QL_PHY_GIO_SEM_MASK);
3203
3204	/* Indicate Configuration Complete */
3205	ql_write_page0_reg(qdev,
3206	reg: &port_regs->portControl,
3207	value: ((PORT_CONTROL_CC << 16) | PORT_CONTROL_CC));
3208
3209	do {
3210	value = ql_read_page0_reg(qdev, reg: &port_regs->portStatus);
3211	if (value & PORT_STATUS_IC)
3212	break;
3213	spin_unlock_irq(lock: &qdev->hw_lock);
3214	msleep(msecs: 500);
3215	spin_lock_irq(lock: &qdev->hw_lock);
3216	} while (--delay);
3217
3218	if (delay == 0) {
3219	netdev_err(dev: qdev->ndev, format: "Hw Initialization timeout\n");
3220	status = -1;
3221	goto out;
3222	}
3223
3224	/* Enable Ethernet Function */
3225	if (qdev->device_id == QL3032_DEVICE_ID) {
3226	value =
3227	(QL3032_PORT_CONTROL_EF | QL3032_PORT_CONTROL_KIE |
3228	QL3032_PORT_CONTROL_EIv6 | QL3032_PORT_CONTROL_EIv4 |
3229	QL3032_PORT_CONTROL_ET);
3230	ql_write_page0_reg(qdev, reg: &port_regs->functionControl,
3231	value: ((value << 16) | value));
3232	} else {
3233	value =
3234	(PORT_CONTROL_EF | PORT_CONTROL_ET | PORT_CONTROL_EI |
3235	PORT_CONTROL_HH);
3236	ql_write_page0_reg(qdev, reg: &port_regs->portControl,
3237	value: ((value << 16) | value));
3238	}
3239
3240
3241	out:
3242	return status;
3243	}
3244
3245	/*
3246	* Caller holds hw_lock.
3247	*/
3248	static int ql_adapter_reset(struct ql3_adapter *qdev)
3249	{
3250	struct ql3xxx_port_registers __iomem *port_regs =
3251	qdev->mem_map_registers;
3252	int status = 0;
3253	u16 value;
3254	int max_wait_time;
3255
3256	set_bit(nr: QL_RESET_ACTIVE, addr: &qdev->flags);
3257	clear_bit(nr: QL_RESET_DONE, addr: &qdev->flags);
3258
3259	/*
3260	* Issue soft reset to chip.
3261	*/
3262	netdev_printk(KERN_DEBUG, dev: qdev->ndev, format: "Issue soft reset to chip\n");
3263	ql_write_common_reg(qdev,
3264	reg: &port_regs->CommonRegs.ispControlStatus,
3265	value: ((ISP_CONTROL_SR << 16) | ISP_CONTROL_SR));
3266
3267	/* Wait 3 seconds for reset to complete. */
3268	netdev_printk(KERN_DEBUG, dev: qdev->ndev,
3269	format: "Wait 10 milliseconds for reset to complete\n");
3270
3271	/* Wait until the firmware tells us the Soft Reset is done */
3272	max_wait_time = 5;
3273	do {
3274	value =
3275	ql_read_common_reg(qdev,
3276	reg: &port_regs->CommonRegs.ispControlStatus);
3277	if ((value & ISP_CONTROL_SR) == 0)
3278	break;
3279
3280	mdelay(1000);
3281	} while ((--max_wait_time));
3282
3283	/*
3284	* Also, make sure that the Network Reset Interrupt bit has been
3285	* cleared after the soft reset has taken place.
3286	*/
3287	value =
3288	ql_read_common_reg(qdev, reg: &port_regs->CommonRegs.ispControlStatus);
3289	if (value & ISP_CONTROL_RI) {
3290	netdev_printk(KERN_DEBUG, dev: qdev->ndev,
3291	format: "clearing RI after reset\n");
3292	ql_write_common_reg(qdev,
3293	reg: &port_regs->CommonRegs.
3294	ispControlStatus,
3295	value: ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3296	}
3297
3298	if (max_wait_time == 0) {
3299	/* Issue Force Soft Reset */
3300	ql_write_common_reg(qdev,
3301	reg: &port_regs->CommonRegs.
3302	ispControlStatus,
3303	value: ((ISP_CONTROL_FSR << 16) |
3304	ISP_CONTROL_FSR));
3305	/*
3306	* Wait until the firmware tells us the Force Soft Reset is
3307	* done
3308	*/
3309	max_wait_time = 5;
3310	do {
3311	value = ql_read_common_reg(qdev,
3312	reg: &port_regs->CommonRegs.
3313	ispControlStatus);
3314	if ((value & ISP_CONTROL_FSR) == 0)
3315	break;
3316	mdelay(1000);
3317	} while ((--max_wait_time));
3318	}
3319	if (max_wait_time == 0)
3320	status = 1;
3321
3322	clear_bit(nr: QL_RESET_ACTIVE, addr: &qdev->flags);
3323	set_bit(nr: QL_RESET_DONE, addr: &qdev->flags);
3324	return status;
3325	}
3326
3327	static void ql_set_mac_info(struct ql3_adapter *qdev)
3328	{
3329	struct ql3xxx_port_registers __iomem *port_regs =
3330	qdev->mem_map_registers;
3331	u32 value, port_status;
3332	u8 func_number;
3333
3334	/* Get the function number */
3335	value =
3336	ql_read_common_reg_l(qdev, reg: &port_regs->CommonRegs.ispControlStatus);
3337	func_number = (u8) ((value >> 4) & OPCODE_FUNC_ID_MASK);
3338	port_status = ql_read_page0_reg(qdev, reg: &port_regs->portStatus);
3339	switch (value & ISP_CONTROL_FN_MASK) {
3340	case ISP_CONTROL_FN0_NET:
3341	qdev->mac_index = 0;
3342	qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
3343	qdev->mb_bit_mask = FN0_MA_BITS_MASK;
3344	qdev->PHYAddr = PORT0_PHY_ADDRESS;
3345	if (port_status & PORT_STATUS_SM0)
3346	set_bit(nr: QL_LINK_OPTICAL, addr: &qdev->flags);
3347	else
3348	clear_bit(nr: QL_LINK_OPTICAL, addr: &qdev->flags);
3349	break;
3350
3351	case ISP_CONTROL_FN1_NET:
3352	qdev->mac_index = 1;
3353	qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
3354	qdev->mb_bit_mask = FN1_MA_BITS_MASK;
3355	qdev->PHYAddr = PORT1_PHY_ADDRESS;
3356	if (port_status & PORT_STATUS_SM1)
3357	set_bit(nr: QL_LINK_OPTICAL, addr: &qdev->flags);
3358	else
3359	clear_bit(nr: QL_LINK_OPTICAL, addr: &qdev->flags);
3360	break;
3361
3362	case ISP_CONTROL_FN0_SCSI:
3363	case ISP_CONTROL_FN1_SCSI:
3364	default:
3365	netdev_printk(KERN_DEBUG, dev: qdev->ndev,
3366	format: "Invalid function number, ispControlStatus = 0x%x\n",
3367	value);
3368	break;
3369	}
3370	qdev->numPorts = qdev->nvram_data.version_and_numPorts >> 8;
3371	}
3372
3373	static void ql_display_dev_info(struct net_device *ndev)
3374	{
3375	struct ql3_adapter *qdev = netdev_priv(dev: ndev);
3376	struct pci_dev *pdev = qdev->pdev;
3377
3378	netdev_info(dev: ndev,
3379	format: "%s Adapter %d RevisionID %d found %s on PCI slot %d\n",
3380	DRV_NAME, qdev->index, qdev->chip_rev_id,
3381	qdev->device_id == QL3032_DEVICE_ID ? "QLA3032" : "QLA3022",
3382	qdev->pci_slot);
3383	netdev_info(dev: ndev, format: "%s Interface\n",
3384	test_bit(QL_LINK_OPTICAL, &qdev->flags) ? "OPTICAL" : "COPPER");
3385
3386	/*
3387	* Print PCI bus width/type.
3388	*/
3389	netdev_info(dev: ndev, format: "Bus interface is %s %s\n",
3390	((qdev->pci_width == 64) ? "64-bit" : "32-bit"),
3391	((qdev->pci_x) ? "PCI-X" : "PCI"));
3392
3393	netdev_info(dev: ndev, format: "mem IO base address adjusted = 0x%p\n",
3394	qdev->mem_map_registers);
3395	netdev_info(dev: ndev, format: "Interrupt number = %d\n", pdev->irq);
3396
3397	netif_info(qdev, probe, ndev, "MAC address %pM\n", ndev->dev_addr);
3398	}
3399
3400	static int ql_adapter_down(struct ql3_adapter *qdev, int do_reset)
3401	{
3402	struct net_device *ndev = qdev->ndev;
3403	int retval = 0;
3404
3405	netif_stop_queue(dev: ndev);
3406	netif_carrier_off(dev: ndev);
3407
3408	clear_bit(nr: QL_ADAPTER_UP, addr: &qdev->flags);
3409	clear_bit(nr: QL_LINK_MASTER, addr: &qdev->flags);
3410
3411	ql_disable_interrupts(qdev);
3412
3413	free_irq(qdev->pdev->irq, ndev);
3414
3415	if (qdev->msi && test_bit(QL_MSI_ENABLED, &qdev->flags)) {
3416	netdev_info(dev: qdev->ndev, format: "calling pci_disable_msi()\n");
3417	clear_bit(nr: QL_MSI_ENABLED, addr: &qdev->flags);
3418	pci_disable_msi(dev: qdev->pdev);
3419	}
3420
3421	del_timer_sync(timer: &qdev->adapter_timer);
3422
3423	napi_disable(n: &qdev->napi);
3424
3425	if (do_reset) {
3426	int soft_reset;
3427	unsigned long hw_flags;
3428
3429	spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3430	if (ql_wait_for_drvr_lock(qdev)) {
3431	soft_reset = ql_adapter_reset(qdev);
3432	if (soft_reset) {
3433	netdev_err(dev: ndev, format: "ql_adapter_reset(%d) FAILED!\n",
3434	qdev->index);
3435	}
3436	netdev_err(dev: ndev,
3437	format: "Releasing driver lock via chip reset\n");
3438	} else {
3439	netdev_err(dev: ndev,
3440	format: "Could not acquire driver lock to do reset!\n");
3441	retval = -1;
3442	}
3443	spin_unlock_irqrestore(lock: &qdev->hw_lock, flags: hw_flags);
3444	}
3445	ql_free_mem_resources(qdev);
3446	return retval;
3447	}
3448
3449	static int ql_adapter_up(struct ql3_adapter *qdev)
3450	{
3451	struct net_device *ndev = qdev->ndev;
3452	int err;
3453	unsigned long irq_flags = IRQF_SHARED;
3454	unsigned long hw_flags;
3455
3456	if (ql_alloc_mem_resources(qdev)) {
3457	netdev_err(dev: ndev, format: "Unable to allocate buffers\n");
3458	return -ENOMEM;
3459	}
3460
3461	if (qdev->msi) {
3462	if (pci_enable_msi(dev: qdev->pdev)) {
3463	netdev_err(dev: ndev,
3464	format: "User requested MSI, but MSI failed to initialize. Continuing without MSI.\n");
3465	qdev->msi = 0;
3466	} else {
3467	netdev_info(dev: ndev, format: "MSI Enabled...\n");
3468	set_bit(nr: QL_MSI_ENABLED, addr: &qdev->flags);
3469	irq_flags &= ~IRQF_SHARED;
3470	}
3471	}
3472
3473	err = request_irq(irq: qdev->pdev->irq, handler: ql3xxx_isr,
3474	flags: irq_flags, name: ndev->name, dev: ndev);
3475	if (err) {
3476	netdev_err(dev: ndev,
3477	format: "Failed to reserve interrupt %d - already in use\n",
3478	qdev->pdev->irq);
3479	goto err_irq;
3480	}
3481
3482	spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3483
3484	if (!ql_wait_for_drvr_lock(qdev)) {
3485	netdev_err(dev: ndev, format: "Could not acquire driver lock\n");
3486	err = -ENODEV;
3487	goto err_lock;
3488	}
3489
3490	err = ql_adapter_initialize(qdev);
3491	if (err) {
3492	netdev_err(dev: ndev, format: "Unable to initialize adapter\n");
3493	goto err_init;
3494	}
3495	ql_sem_unlock(qdev, sem_mask: QL_DRVR_SEM_MASK);
3496
3497	spin_unlock_irqrestore(lock: &qdev->hw_lock, flags: hw_flags);
3498
3499	set_bit(nr: QL_ADAPTER_UP, addr: &qdev->flags);
3500
3501	mod_timer(timer: &qdev->adapter_timer, expires: jiffies + HZ * 1);
3502
3503	napi_enable(n: &qdev->napi);
3504	ql_enable_interrupts(qdev);
3505	return 0;
3506
3507	err_init:
3508	ql_sem_unlock(qdev, sem_mask: QL_DRVR_SEM_MASK);
3509	err_lock:
3510	spin_unlock_irqrestore(lock: &qdev->hw_lock, flags: hw_flags);
3511	free_irq(qdev->pdev->irq, ndev);
3512	err_irq:
3513	if (qdev->msi && test_bit(QL_MSI_ENABLED, &qdev->flags)) {
3514	netdev_info(dev: ndev, format: "calling pci_disable_msi()\n");
3515	clear_bit(nr: QL_MSI_ENABLED, addr: &qdev->flags);
3516	pci_disable_msi(dev: qdev->pdev);
3517	}
3518	return err;
3519	}
3520
3521	static int ql_cycle_adapter(struct ql3_adapter *qdev, int reset)
3522	{
3523	if (ql_adapter_down(qdev, do_reset: reset) || ql_adapter_up(qdev)) {
3524	netdev_err(dev: qdev->ndev,
3525	format: "Driver up/down cycle failed, closing device\n");
3526	rtnl_lock();
3527	dev_close(dev: qdev->ndev);
3528	rtnl_unlock();
3529	return -1;
3530	}
3531	return 0;
3532	}
3533
3534	static int ql3xxx_close(struct net_device *ndev)
3535	{
3536	struct ql3_adapter *qdev = netdev_priv(dev: ndev);
3537
3538	/*
3539	* Wait for device to recover from a reset.
3540	* (Rarely happens, but possible.)
3541	*/
3542	while (!test_bit(QL_ADAPTER_UP, &qdev->flags))
3543	msleep(msecs: 50);
3544
3545	ql_adapter_down(qdev, QL_DO_RESET);
3546	return 0;
3547	}
3548
3549	static int ql3xxx_open(struct net_device *ndev)
3550	{
3551	struct ql3_adapter *qdev = netdev_priv(dev: ndev);
3552	return ql_adapter_up(qdev);
3553	}
3554
3555	static int ql3xxx_set_mac_address(struct net_device *ndev, void *p)
3556	{
3557	struct ql3_adapter *qdev = netdev_priv(dev: ndev);
3558	struct ql3xxx_port_registers __iomem *port_regs =
3559	qdev->mem_map_registers;
3560	struct sockaddr *addr = p;
3561	unsigned long hw_flags;
3562
3563	if (netif_running(dev: ndev))
3564	return -EBUSY;
3565
3566	if (!is_valid_ether_addr(addr: addr->sa_data))
3567	return -EADDRNOTAVAIL;
3568
3569	eth_hw_addr_set(dev: ndev, addr: addr->sa_data);
3570
3571	spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3572	/* Program lower 32 bits of the MAC address */
3573	ql_write_page0_reg(qdev, reg: &port_regs->macAddrIndirectPtrReg,
3574	value: (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
3575	ql_write_page0_reg(qdev, reg: &port_regs->macAddrDataReg,
3576	value: ((ndev->dev_addr[2] << 24) | (ndev->
3577	dev_addr[3] << 16) |
3578	(ndev->dev_addr[4] << 8) | ndev->dev_addr[5]));
3579
3580	/* Program top 16 bits of the MAC address */
3581	ql_write_page0_reg(qdev, reg: &port_regs->macAddrIndirectPtrReg,
3582	value: ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
3583	ql_write_page0_reg(qdev, reg: &port_regs->macAddrDataReg,
3584	value: ((ndev->dev_addr[0] << 8) | ndev->dev_addr[1]));
3585	spin_unlock_irqrestore(lock: &qdev->hw_lock, flags: hw_flags);
3586
3587	return 0;
3588	}
3589
3590	static void ql3xxx_tx_timeout(struct net_device *ndev, unsigned int txqueue)
3591	{
3592	struct ql3_adapter *qdev = netdev_priv(dev: ndev);
3593
3594	netdev_err(dev: ndev, format: "Resetting...\n");
3595	/*
3596	* Stop the queues, we've got a problem.
3597	*/
3598	netif_stop_queue(dev: ndev);
3599
3600	/*
3601	* Wake up the worker to process this event.
3602	*/
3603	queue_delayed_work(wq: qdev->workqueue, dwork: &qdev->tx_timeout_work, delay: 0);
3604	}
3605
3606	static void ql_reset_work(struct work_struct *work)
3607	{
3608	struct ql3_adapter *qdev =
3609	container_of(work, struct ql3_adapter, reset_work.work);
3610	struct net_device *ndev = qdev->ndev;
3611	u32 value;
3612	struct ql_tx_buf_cb *tx_cb;
3613	int max_wait_time, i;
3614	struct ql3xxx_port_registers __iomem *port_regs =
3615	qdev->mem_map_registers;
3616	unsigned long hw_flags;
3617
3618	if (test_bit(QL_RESET_PER_SCSI, &qdev->flags) ||
3619	test_bit(QL_RESET_START, &qdev->flags)) {
3620	clear_bit(nr: QL_LINK_MASTER, addr: &qdev->flags);
3621
3622	/*
3623	* Loop through the active list and return the skb.
3624	*/
3625	for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
3626	int j;
3627	tx_cb = &qdev->tx_buf[i];
3628	if (tx_cb->skb) {
3629	netdev_printk(KERN_DEBUG, dev: ndev,
3630	format: "Freeing lost SKB\n");
3631	dma_unmap_single(&qdev->pdev->dev,
3632	dma_unmap_addr(&tx_cb->map[0], mapaddr),
3633	dma_unmap_len(&tx_cb->map[0], maplen),
3634	DMA_TO_DEVICE);
3635	for (j = 1; j < tx_cb->seg_count; j++) {
3636	dma_unmap_page(&qdev->pdev->dev,
3637	dma_unmap_addr(&tx_cb->map[j], mapaddr),
3638	dma_unmap_len(&tx_cb->map[j], maplen),
3639	DMA_TO_DEVICE);
3640	}
3641	dev_kfree_skb(tx_cb->skb);
3642	tx_cb->skb = NULL;
3643	}
3644	}
3645
3646	netdev_err(dev: ndev, format: "Clearing NRI after reset\n");
3647	spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3648	ql_write_common_reg(qdev,
3649	reg: &port_regs->CommonRegs.
3650	ispControlStatus,
3651	value: ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3652	/*
3653	* Wait the for Soft Reset to Complete.
3654	*/
3655	max_wait_time = 10;
3656	do {
3657	value = ql_read_common_reg(qdev,
3658	reg: &port_regs->CommonRegs.
3659
3660	ispControlStatus);
3661	if ((value & ISP_CONTROL_SR) == 0) {
3662	netdev_printk(KERN_DEBUG, dev: ndev,
3663	format: "reset completed\n");
3664	break;
3665	}
3666
3667	if (value & ISP_CONTROL_RI) {
3668	netdev_printk(KERN_DEBUG, dev: ndev,
3669	format: "clearing NRI after reset\n");
3670	ql_write_common_reg(qdev,
3671	reg: &port_regs->
3672	CommonRegs.
3673	ispControlStatus,
3674	value: ((ISP_CONTROL_RI <<
3675	16) | ISP_CONTROL_RI));
3676	}
3677
3678	spin_unlock_irqrestore(lock: &qdev->hw_lock, flags: hw_flags);
3679	ssleep(seconds: 1);
3680	spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3681	} while (--max_wait_time);
3682	spin_unlock_irqrestore(lock: &qdev->hw_lock, flags: hw_flags);
3683
3684	if (value & ISP_CONTROL_SR) {
3685
3686	/*
3687	* Set the reset flags and clear the board again.
3688	* Nothing else to do...
3689	*/
3690	netdev_err(dev: ndev,
3691	format: "Timed out waiting for reset to complete\n");
3692	netdev_err(dev: ndev, format: "Do a reset\n");
3693	clear_bit(nr: QL_RESET_PER_SCSI, addr: &qdev->flags);
3694	clear_bit(nr: QL_RESET_START, addr: &qdev->flags);
3695	ql_cycle_adapter(qdev, QL_DO_RESET);
3696	return;
3697	}
3698
3699	clear_bit(nr: QL_RESET_ACTIVE, addr: &qdev->flags);
3700	clear_bit(nr: QL_RESET_PER_SCSI, addr: &qdev->flags);
3701	clear_bit(nr: QL_RESET_START, addr: &qdev->flags);
3702	ql_cycle_adapter(qdev, QL_NO_RESET);
3703	}
3704	}
3705
3706	static void ql_tx_timeout_work(struct work_struct *work)
3707	{
3708	struct ql3_adapter *qdev =
3709	container_of(work, struct ql3_adapter, tx_timeout_work.work);
3710
3711	ql_cycle_adapter(qdev, QL_DO_RESET);
3712	}
3713
3714	static void ql_get_board_info(struct ql3_adapter *qdev)
3715	{
3716	struct ql3xxx_port_registers __iomem *port_regs =
3717	qdev->mem_map_registers;
3718	u32 value;
3719
3720	value = ql_read_page0_reg_l(qdev, reg: &port_regs->portStatus);
3721
3722	qdev->chip_rev_id = ((value & PORT_STATUS_REV_ID_MASK) >> 12);
3723	if (value & PORT_STATUS_64)
3724	qdev->pci_width = 64;
3725	else
3726	qdev->pci_width = 32;
3727	if (value & PORT_STATUS_X)
3728	qdev->pci_x = 1;
3729	else
3730	qdev->pci_x = 0;
3731	qdev->pci_slot = (u8) PCI_SLOT(qdev->pdev->devfn);
3732	}
3733
3734	static void ql3xxx_timer(struct timer_list *t)
3735	{
3736	struct ql3_adapter *qdev = from_timer(qdev, t, adapter_timer);
3737	queue_delayed_work(wq: qdev->workqueue, dwork: &qdev->link_state_work, delay: 0);
3738	}
3739
3740	static const struct net_device_ops ql3xxx_netdev_ops = {
3741	.ndo_open = ql3xxx_open,
3742	.ndo_start_xmit = ql3xxx_send,
3743	.ndo_stop = ql3xxx_close,
3744	.ndo_validate_addr = eth_validate_addr,
3745	.ndo_set_mac_address = ql3xxx_set_mac_address,
3746	.ndo_tx_timeout = ql3xxx_tx_timeout,
3747	};
3748
3749	static int ql3xxx_probe(struct pci_dev *pdev,
3750	const struct pci_device_id *pci_entry)
3751	{
3752	struct net_device *ndev = NULL;
3753	struct ql3_adapter *qdev = NULL;
3754	static int cards_found;
3755	int err;
3756
3757	err = pci_enable_device(dev: pdev);
3758	if (err) {
3759	pr_err("%s cannot enable PCI device\n", pci_name(pdev));
3760	goto err_out;
3761	}
3762
3763	err = pci_request_regions(pdev, DRV_NAME);
3764	if (err) {
3765	pr_err("%s cannot obtain PCI resources\n", pci_name(pdev));
3766	goto err_out_disable_pdev;
3767	}
3768
3769	pci_set_master(dev: pdev);
3770
3771	err = dma_set_mask_and_coherent(dev: &pdev->dev, DMA_BIT_MASK(64));
3772	if (err) {
3773	pr_err("%s no usable DMA configuration\n", pci_name(pdev));
3774	goto err_out_free_regions;
3775	}
3776
3777	ndev = alloc_etherdev(sizeof(struct ql3_adapter));
3778	if (!ndev) {
3779	err = -ENOMEM;
3780	goto err_out_free_regions;
3781	}
3782
3783	SET_NETDEV_DEV(ndev, &pdev->dev);
3784
3785	pci_set_drvdata(pdev, data: ndev);
3786
3787	qdev = netdev_priv(dev: ndev);
3788	qdev->index = cards_found;
3789	qdev->ndev = ndev;
3790	qdev->pdev = pdev;
3791	qdev->device_id = pci_entry->device;
3792	qdev->port_link_state = LS_DOWN;
3793	if (msi)
3794	qdev->msi = 1;
3795
3796	qdev->msg_enable = netif_msg_init(debug_value: debug, default_msg_enable_bits: default_msg);
3797
3798	ndev->features |= NETIF_F_HIGHDMA;
3799	if (qdev->device_id == QL3032_DEVICE_ID)
3800	ndev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3801
3802	qdev->mem_map_registers = pci_ioremap_bar(pdev, bar: 1);
3803	if (!qdev->mem_map_registers) {
3804	pr_err("%s: cannot map device registers\n", pci_name(pdev));
3805	err = -EIO;
3806	goto err_out_free_ndev;
3807	}
3808
3809	spin_lock_init(&qdev->adapter_lock);
3810	spin_lock_init(&qdev->hw_lock);
3811
3812	/* Set driver entry points */
3813	ndev->netdev_ops = &ql3xxx_netdev_ops;
3814	ndev->ethtool_ops = &ql3xxx_ethtool_ops;
3815	ndev->watchdog_timeo = 5 * HZ;
3816
3817	netif_napi_add(dev: ndev, napi: &qdev->napi, poll: ql_poll);
3818
3819	ndev->irq = pdev->irq;
3820
3821	/* make sure the EEPROM is good */
3822	if (ql_get_nvram_params(qdev)) {
3823	pr_alert("%s: Adapter #%d, Invalid NVRAM parameters\n",
3824	__func__, qdev->index);
3825	err = -EIO;
3826	goto err_out_iounmap;
3827	}
3828
3829	ql_set_mac_info(qdev);
3830
3831	/* Validate and set parameters */
3832	if (qdev->mac_index) {
3833	ndev->mtu = qdev->nvram_data.macCfg_port1.etherMtu_mac ;
3834	ql_set_mac_addr(ndev, addr: qdev->nvram_data.funcCfg_fn2.macAddress);
3835	} else {
3836	ndev->mtu = qdev->nvram_data.macCfg_port0.etherMtu_mac ;
3837	ql_set_mac_addr(ndev, addr: qdev->nvram_data.funcCfg_fn0.macAddress);
3838	}
3839
3840	ndev->tx_queue_len = NUM_REQ_Q_ENTRIES;
3841
3842	/* Record PCI bus information. */
3843	ql_get_board_info(qdev);
3844
3845	/*
3846	* Set the Maximum Memory Read Byte Count value. We do this to handle
3847	* jumbo frames.
3848	*/
3849	if (qdev->pci_x)
3850	pci_write_config_word(dev: pdev, where: (int)0x4e, val: (u16) 0x0036);
3851
3852	err = register_netdev(dev: ndev);
3853	if (err) {
3854	pr_err("%s: cannot register net device\n", pci_name(pdev));
3855	goto err_out_iounmap;
3856	}
3857
3858	/* we're going to reset, so assume we have no link for now */
3859
3860	netif_carrier_off(dev: ndev);
3861	netif_stop_queue(dev: ndev);
3862
3863	qdev->workqueue = create_singlethread_workqueue(ndev->name);
3864	if (!qdev->workqueue) {
3865	unregister_netdev(dev: ndev);
3866	err = -ENOMEM;
3867	goto err_out_iounmap;
3868	}
3869
3870	INIT_DELAYED_WORK(&qdev->reset_work, ql_reset_work);
3871	INIT_DELAYED_WORK(&qdev->tx_timeout_work, ql_tx_timeout_work);
3872	INIT_DELAYED_WORK(&qdev->link_state_work, ql_link_state_machine_work);
3873
3874	timer_setup(&qdev->adapter_timer, ql3xxx_timer, 0);
3875	qdev->adapter_timer.expires = jiffies + HZ * 2; /* two second delay */
3876
3877	if (!cards_found) {
3878	pr_alert("%s\n", DRV_STRING);
3879	pr_alert("Driver name: %s, Version: %s\n",
3880	DRV_NAME, DRV_VERSION);
3881	}
3882	ql_display_dev_info(ndev);
3883
3884	cards_found++;
3885	return 0;
3886
3887	err_out_iounmap:
3888	iounmap(addr: qdev->mem_map_registers);
3889	err_out_free_ndev:
3890	free_netdev(dev: ndev);
3891	err_out_free_regions:
3892	pci_release_regions(pdev);
3893	err_out_disable_pdev:
3894	pci_disable_device(dev: pdev);
3895	err_out:
3896	return err;
3897	}
3898
3899	static void ql3xxx_remove(struct pci_dev *pdev)
3900	{
3901	struct net_device *ndev = pci_get_drvdata(pdev);
3902	struct ql3_adapter *qdev = netdev_priv(dev: ndev);
3903
3904	unregister_netdev(dev: ndev);
3905
3906	ql_disable_interrupts(qdev);
3907
3908	if (qdev->workqueue) {
3909	cancel_delayed_work(dwork: &qdev->reset_work);
3910	cancel_delayed_work(dwork: &qdev->tx_timeout_work);
3911	destroy_workqueue(wq: qdev->workqueue);
3912	qdev->workqueue = NULL;
3913	}
3914
3915	iounmap(addr: qdev->mem_map_registers);
3916	pci_release_regions(pdev);
3917	free_netdev(dev: ndev);
3918	}
3919
3920	static struct pci_driver ql3xxx_driver = {
3921
3922	.name = DRV_NAME,
3923	.id_table = ql3xxx_pci_tbl,
3924	.probe = ql3xxx_probe,
3925	.remove = ql3xxx_remove,
3926	};
3927
3928	module_pci_driver(ql3xxx_driver);
3929