| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 2 | /*************************************************************************** |
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| 3 | * |
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| 4 | * Copyright (C) 2007,2008 SMSC |
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| 5 | * |
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| 6 | *************************************************************************** |
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| 7 | */ |
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| 8 | |
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| 9 | #ifndef _SMSC9420_H |
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| 10 | #define _SMSC9420_H |
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| 11 | |
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| 12 | #define TX_RING_SIZE (32) |
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| 13 | #define RX_RING_SIZE (128) |
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| 14 | |
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| 15 | /* interrupt deassertion in multiples of 10us */ |
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| 16 | #define INT_DEAS_TIME (50) |
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| 17 | |
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| 18 | #define SMSC_BAR (3) |
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| 19 | |
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| 20 | #ifdef __BIG_ENDIAN |
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| 21 | /* Register set is duplicated for BE at an offset of 0x200 */ |
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| 22 | #define LAN9420_CPSR_ENDIAN_OFFSET (0x200) |
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| 23 | #else |
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| 24 | #define LAN9420_CPSR_ENDIAN_OFFSET (0) |
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| 25 | #endif |
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| 26 | |
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| 27 | #define PCI_VENDOR_ID_9420 (0x1055) |
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| 28 | #define PCI_DEVICE_ID_9420 (0xE420) |
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| 29 | |
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| 30 | #define LAN_REGISTER_EXTENT (0x400) |
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| 31 | |
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| 32 | #define SMSC9420_EEPROM_SIZE ((u32)11) |
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| 33 | #define SMSC9420_EEPROM_MAGIC (0x9420) |
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| 34 | |
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| 35 | #define PKT_BUF_SZ (VLAN_ETH_FRAME_LEN + NET_IP_ALIGN + 4) |
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| 36 | |
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| 37 | /***********************************************/ |
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| 38 | /* DMA Controller Control and Status Registers */ |
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| 39 | /***********************************************/ |
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| 40 | #define BUS_MODE (0x00) |
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| 41 | #define BUS_MODE_SWR_ (BIT(0)) |
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| 42 | #define BUS_MODE_DMA_BURST_LENGTH_1 (BIT(8)) |
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| 43 | #define BUS_MODE_DMA_BURST_LENGTH_2 (BIT(9)) |
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| 44 | #define BUS_MODE_DMA_BURST_LENGTH_4 (BIT(10)) |
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| 45 | #define BUS_MODE_DMA_BURST_LENGTH_8 (BIT(11)) |
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| 46 | #define BUS_MODE_DMA_BURST_LENGTH_16 (BIT(12)) |
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| 47 | #define BUS_MODE_DMA_BURST_LENGTH_32 (BIT(13)) |
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| 48 | #define BUS_MODE_DBO_ (BIT(20)) |
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| 49 | |
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| 50 | #define TX_POLL_DEMAND (0x04) |
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| 51 | |
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| 52 | #define RX_POLL_DEMAND (0x08) |
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| 53 | |
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| 54 | #define RX_BASE_ADDR (0x0C) |
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| 55 | |
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| 56 | #define TX_BASE_ADDR (0x10) |
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| 57 | |
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| 58 | #define DMAC_STATUS (0x14) |
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| 59 | #define DMAC_STS_TS_ (7 << 20) |
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| 60 | #define DMAC_STS_RS_ (7 << 17) |
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| 61 | #define DMAC_STS_NIS_ (BIT(16)) |
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| 62 | #define DMAC_STS_AIS_ (BIT(15)) |
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| 63 | #define DMAC_STS_RWT_ (BIT(9)) |
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| 64 | #define DMAC_STS_RXPS_ (BIT(8)) |
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| 65 | #define DMAC_STS_RXBU_ (BIT(7)) |
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| 66 | #define DMAC_STS_RX_ (BIT(6)) |
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| 67 | #define DMAC_STS_TXUNF_ (BIT(5)) |
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| 68 | #define DMAC_STS_TXBU_ (BIT(2)) |
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| 69 | #define DMAC_STS_TXPS_ (BIT(1)) |
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| 70 | #define DMAC_STS_TX_ (BIT(0)) |
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| 71 | |
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| 72 | #define DMAC_CONTROL (0x18) |
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| 73 | #define DMAC_CONTROL_TTM_ (BIT(22)) |
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| 74 | #define DMAC_CONTROL_SF_ (BIT(21)) |
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| 75 | #define DMAC_CONTROL_ST_ (BIT(13)) |
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| 76 | #define DMAC_CONTROL_OSF_ (BIT(2)) |
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| 77 | #define DMAC_CONTROL_SR_ (BIT(1)) |
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| 78 | |
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| 79 | #define DMAC_INTR_ENA (0x1C) |
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| 80 | #define DMAC_INTR_ENA_NIS_ (BIT(16)) |
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| 81 | #define DMAC_INTR_ENA_AIS_ (BIT(15)) |
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| 82 | #define DMAC_INTR_ENA_RWT_ (BIT(9)) |
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| 83 | #define DMAC_INTR_ENA_RXPS_ (BIT(8)) |
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| 84 | #define DMAC_INTR_ENA_RXBU_ (BIT(7)) |
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| 85 | #define DMAC_INTR_ENA_RX_ (BIT(6)) |
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| 86 | #define DMAC_INTR_ENA_TXBU_ (BIT(2)) |
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| 87 | #define DMAC_INTR_ENA_TXPS_ (BIT(1)) |
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| 88 | #define DMAC_INTR_ENA_TX_ (BIT(0)) |
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| 89 | |
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| 90 | #define MISS_FRAME_CNTR (0x20) |
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| 91 | |
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| 92 | #define TX_BUFF_ADDR (0x50) |
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| 93 | |
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| 94 | #define RX_BUFF_ADDR (0x54) |
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| 95 | |
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| 96 | /* Transmit Descriptor Bit Defs */ |
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| 97 | #define TDES0_OWN_ (0x80000000) |
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| 98 | #define TDES0_ERROR_SUMMARY_ (0x00008000) |
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| 99 | #define TDES0_LOSS_OF_CARRIER_ (0x00000800) |
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| 100 | #define TDES0_NO_CARRIER_ (0x00000400) |
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| 101 | #define TDES0_LATE_COLLISION_ (0x00000200) |
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| 102 | #define TDES0_EXCESSIVE_COLLISIONS_ (0x00000100) |
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| 103 | #define TDES0_HEARTBEAT_FAIL_ (0x00000080) |
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| 104 | #define TDES0_COLLISION_COUNT_MASK_ (0x00000078) |
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| 105 | #define TDES0_COLLISION_COUNT_SHFT_ (3) |
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| 106 | #define TDES0_EXCESSIVE_DEFERRAL_ (0x00000004) |
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| 107 | #define TDES0_DEFERRED_ (0x00000001) |
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| 108 | |
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| 109 | #define TDES1_IC_ 0x80000000 |
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| 110 | #define TDES1_LS_ 0x40000000 |
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| 111 | #define TDES1_FS_ 0x20000000 |
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| 112 | #define TDES1_TXCSEN_ 0x08000000 |
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| 113 | #define TDES1_TER_ (BIT(25)) |
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| 114 | #define TDES1_TCH_ 0x01000000 |
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| 115 | |
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| 116 | /* Receive Descriptor 0 Bit Defs */ |
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| 117 | #define RDES0_OWN_ (0x80000000) |
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| 118 | #define RDES0_FRAME_LENGTH_MASK_ (0x07FF0000) |
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| 119 | #define RDES0_FRAME_LENGTH_SHFT_ (16) |
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| 120 | #define RDES0_ERROR_SUMMARY_ (0x00008000) |
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| 121 | #define RDES0_DESCRIPTOR_ERROR_ (0x00004000) |
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| 122 | #define RDES0_LENGTH_ERROR_ (0x00001000) |
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| 123 | #define RDES0_RUNT_FRAME_ (0x00000800) |
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| 124 | #define RDES0_MULTICAST_FRAME_ (0x00000400) |
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| 125 | #define RDES0_FIRST_DESCRIPTOR_ (0x00000200) |
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| 126 | #define RDES0_LAST_DESCRIPTOR_ (0x00000100) |
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| 127 | #define RDES0_FRAME_TOO_LONG_ (0x00000080) |
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| 128 | #define RDES0_COLLISION_SEEN_ (0x00000040) |
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| 129 | #define RDES0_FRAME_TYPE_ (0x00000020) |
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| 130 | #define RDES0_WATCHDOG_TIMEOUT_ (0x00000010) |
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| 131 | #define RDES0_MII_ERROR_ (0x00000008) |
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| 132 | #define RDES0_DRIBBLING_BIT_ (0x00000004) |
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| 133 | #define RDES0_CRC_ERROR_ (0x00000002) |
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| 134 | |
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| 135 | /* Receive Descriptor 1 Bit Defs */ |
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| 136 | #define RDES1_RER_ (0x02000000) |
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| 137 | |
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| 138 | /***********************************************/ |
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| 139 | /* MAC Control and Status Registers */ |
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| 140 | /***********************************************/ |
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| 141 | #define MAC_CR (0x80) |
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| 142 | #define MAC_CR_RXALL_ (0x80000000) |
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| 143 | #define MAC_CR_DIS_RXOWN_ (0x00800000) |
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| 144 | #define MAC_CR_LOOPBK_ (0x00200000) |
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| 145 | #define MAC_CR_FDPX_ (0x00100000) |
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| 146 | #define MAC_CR_MCPAS_ (0x00080000) |
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| 147 | #define MAC_CR_PRMS_ (0x00040000) |
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| 148 | #define MAC_CR_INVFILT_ (0x00020000) |
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| 149 | #define MAC_CR_PASSBAD_ (0x00010000) |
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| 150 | #define MAC_CR_HFILT_ (0x00008000) |
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| 151 | #define MAC_CR_HPFILT_ (0x00002000) |
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| 152 | #define MAC_CR_LCOLL_ (0x00001000) |
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| 153 | #define MAC_CR_DIS_BCAST_ (0x00000800) |
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| 154 | #define MAC_CR_DIS_RTRY_ (0x00000400) |
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| 155 | #define MAC_CR_PADSTR_ (0x00000100) |
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| 156 | #define MAC_CR_BOLMT_MSK (0x000000C0) |
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| 157 | #define MAC_CR_MFCHK_ (0x00000020) |
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| 158 | #define MAC_CR_TXEN_ (0x00000008) |
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| 159 | #define MAC_CR_RXEN_ (0x00000004) |
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| 160 | |
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| 161 | #define ADDRH (0x84) |
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| 162 | |
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| 163 | #define ADDRL (0x88) |
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| 164 | |
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| 165 | #define HASHH (0x8C) |
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| 166 | |
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| 167 | #define HASHL (0x90) |
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| 168 | |
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| 169 | #define MII_ACCESS (0x94) |
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| 170 | #define MII_ACCESS_MII_BUSY_ (0x00000001) |
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| 171 | #define MII_ACCESS_MII_WRITE_ (0x00000002) |
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| 172 | #define MII_ACCESS_MII_READ_ (0x00000000) |
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| 173 | #define MII_ACCESS_INDX_MSK_ (0x000007C0) |
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| 174 | #define MII_ACCESS_PHYADDR_MSK_ (0x0000F8C0) |
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| 175 | #define MII_ACCESS_INDX_SHFT_CNT (6) |
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| 176 | #define MII_ACCESS_PHYADDR_SHFT_CNT (11) |
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| 177 | |
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| 178 | #define MII_DATA (0x98) |
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| 179 | |
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| 180 | #define FLOW (0x9C) |
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| 181 | |
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| 182 | #define VLAN1 (0xA0) |
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| 183 | |
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| 184 | #define VLAN2 (0xA4) |
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| 185 | |
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| 186 | #define WUFF (0xA8) |
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| 187 | |
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| 188 | #define WUCSR (0xAC) |
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| 189 | |
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| 190 | #define COE_CR (0xB0) |
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| 191 | #define TX_COE_EN (0x00010000) |
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| 192 | #define RX_COE_MODE (0x00000002) |
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| 193 | #define RX_COE_EN (0x00000001) |
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| 194 | |
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| 195 | /***********************************************/ |
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| 196 | /* System Control and Status Registers */ |
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| 197 | /***********************************************/ |
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| 198 | #define ID_REV (0xC0) |
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| 199 | |
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| 200 | #define INT_CTL (0xC4) |
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| 201 | #define INT_CTL_SW_INT_EN_ (0x00008000) |
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| 202 | #define INT_CTL_SBERR_INT_EN_ (1 << 12) |
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| 203 | #define INT_CTL_MBERR_INT_EN_ (1 << 13) |
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| 204 | #define INT_CTL_GPT_INT_EN_ (0x00000008) |
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| 205 | #define INT_CTL_PHY_INT_EN_ (0x00000004) |
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| 206 | #define INT_CTL_WAKE_INT_EN_ (0x00000002) |
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| 207 | |
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| 208 | #define INT_STAT (0xC8) |
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| 209 | #define INT_STAT_SW_INT_ (1 << 15) |
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| 210 | #define INT_STAT_MBERR_INT_ (1 << 13) |
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| 211 | #define INT_STAT_SBERR_INT_ (1 << 12) |
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| 212 | #define INT_STAT_GPT_INT_ (1 << 3) |
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| 213 | #define INT_STAT_PHY_INT_ (0x00000004) |
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| 214 | #define INT_STAT_WAKE_INT_ (0x00000002) |
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| 215 | #define INT_STAT_DMAC_INT_ (0x00000001) |
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| 216 | |
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| 217 | #define INT_CFG (0xCC) |
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| 218 | #define INT_CFG_IRQ_INT_ (0x00080000) |
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| 219 | #define INT_CFG_IRQ_EN_ (0x00040000) |
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| 220 | #define INT_CFG_INT_DEAS_CLR_ (0x00000200) |
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| 221 | #define INT_CFG_INT_DEAS_MASK (0x000000FF) |
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| 222 | |
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| 223 | #define GPIO_CFG (0xD0) |
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| 224 | #define GPIO_CFG_LED_3_ (0x40000000) |
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| 225 | #define GPIO_CFG_LED_2_ (0x20000000) |
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| 226 | #define GPIO_CFG_LED_1_ (0x10000000) |
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| 227 | #define GPIO_CFG_EEPR_EN_ (0x00700000) |
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| 228 | |
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| 229 | #define GPT_CFG (0xD4) |
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| 230 | #define GPT_CFG_TIMER_EN_ (0x20000000) |
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| 231 | |
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| 232 | #define GPT_CNT (0xD8) |
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| 233 | |
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| 234 | #define BUS_CFG (0xDC) |
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| 235 | #define BUS_CFG_RXTXWEIGHT_1_1 (0 << 25) |
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| 236 | #define BUS_CFG_RXTXWEIGHT_2_1 (1 << 25) |
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| 237 | #define BUS_CFG_RXTXWEIGHT_3_1 (2 << 25) |
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| 238 | #define BUS_CFG_RXTXWEIGHT_4_1 (3 << 25) |
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| 239 | |
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| 240 | #define PMT_CTRL (0xE0) |
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| 241 | |
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| 242 | #define FREE_RUN (0xF4) |
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| 243 | |
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| 244 | #define E2P_CMD (0xF8) |
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| 245 | #define E2P_CMD_EPC_BUSY_ (0x80000000) |
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| 246 | #define E2P_CMD_EPC_CMD_ (0x70000000) |
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| 247 | #define E2P_CMD_EPC_CMD_READ_ (0x00000000) |
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| 248 | #define E2P_CMD_EPC_CMD_EWDS_ (0x10000000) |
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| 249 | #define E2P_CMD_EPC_CMD_EWEN_ (0x20000000) |
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| 250 | #define E2P_CMD_EPC_CMD_WRITE_ (0x30000000) |
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| 251 | #define E2P_CMD_EPC_CMD_WRAL_ (0x40000000) |
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| 252 | #define E2P_CMD_EPC_CMD_ERASE_ (0x50000000) |
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| 253 | #define E2P_CMD_EPC_CMD_ERAL_ (0x60000000) |
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| 254 | #define E2P_CMD_EPC_CMD_RELOAD_ (0x70000000) |
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| 255 | #define E2P_CMD_EPC_TIMEOUT_ (0x00000200) |
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| 256 | #define E2P_CMD_MAC_ADDR_LOADED_ (0x00000100) |
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| 257 | #define E2P_CMD_EPC_ADDR_ (0x000000FF) |
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| 258 | |
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| 259 | #define E2P_DATA (0xFC) |
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| 260 | #define E2P_DATA_EEPROM_DATA_ (0x000000FF) |
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| 261 | |
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| 262 | #endif /* _SMSC9420_H */ |
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| 263 | |
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