1/* SPDX-License-Identifier: GPL-2.0-only */
2/*******************************************************************************
3 STMMAC Common Header File
4
5 Copyright (C) 2007-2009 STMicroelectronics Ltd
6
7
8 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
9*******************************************************************************/
10
11#ifndef __COMMON_H__
12#define __COMMON_H__
13
14#include <linux/etherdevice.h>
15#include <linux/netdevice.h>
16#include <linux/stmmac.h>
17#include <linux/phy.h>
18#include <linux/pcs/pcs-xpcs.h>
19#include <linux/module.h>
20#if IS_ENABLED(CONFIG_VLAN_8021Q)
21#define STMMAC_VLAN_TAG_USED
22#include <linux/if_vlan.h>
23#endif
24
25#include "descs.h"
26#include "hwif.h"
27#include "mmc.h"
28
29/* Synopsys Core versions */
30#define DWMAC_CORE_3_40 0x34
31#define DWMAC_CORE_3_50 0x35
32#define DWMAC_CORE_4_00 0x40
33#define DWMAC_CORE_4_10 0x41
34#define DWMAC_CORE_5_00 0x50
35#define DWMAC_CORE_5_10 0x51
36#define DWMAC_CORE_5_20 0x52
37#define DWXGMAC_CORE_2_10 0x21
38#define DWXGMAC_CORE_2_20 0x22
39#define DWXLGMAC_CORE_2_00 0x20
40
41/* Device ID */
42#define DWXGMAC_ID 0x76
43#define DWXLGMAC_ID 0x27
44
45#define STMMAC_CHAN0 0 /* Always supported and default for all chips */
46
47/* TX and RX Descriptor Length, these need to be power of two.
48 * TX descriptor length less than 64 may cause transmit queue timed out error.
49 * RX descriptor length less than 64 may cause inconsistent Rx chain error.
50 */
51#define DMA_MIN_TX_SIZE 64
52#define DMA_MAX_TX_SIZE 1024
53#define DMA_DEFAULT_TX_SIZE 512
54#define DMA_MIN_RX_SIZE 64
55#define DMA_MAX_RX_SIZE 1024
56#define DMA_DEFAULT_RX_SIZE 512
57#define STMMAC_GET_ENTRY(x, size) ((x + 1) & (size - 1))
58
59#undef FRAME_FILTER_DEBUG
60/* #define FRAME_FILTER_DEBUG */
61
62struct stmmac_txq_stats {
63 u64 tx_bytes;
64 u64 tx_packets;
65 u64 tx_pkt_n;
66 u64 tx_normal_irq_n;
67 u64 napi_poll;
68 u64 tx_clean;
69 u64 tx_set_ic_bit;
70 u64 tx_tso_frames;
71 u64 tx_tso_nfrags;
72 struct u64_stats_sync syncp;
73} ____cacheline_aligned_in_smp;
74
75struct stmmac_rxq_stats {
76 u64 rx_bytes;
77 u64 rx_packets;
78 u64 rx_pkt_n;
79 u64 rx_normal_irq_n;
80 u64 napi_poll;
81 struct u64_stats_sync syncp;
82} ____cacheline_aligned_in_smp;
83
84/* Extra statistic and debug information exposed by ethtool */
85struct stmmac_extra_stats {
86 /* Transmit errors */
87 unsigned long tx_underflow ____cacheline_aligned;
88 unsigned long tx_carrier;
89 unsigned long tx_losscarrier;
90 unsigned long vlan_tag;
91 unsigned long tx_deferred;
92 unsigned long tx_vlan;
93 unsigned long tx_jabber;
94 unsigned long tx_frame_flushed;
95 unsigned long tx_payload_error;
96 unsigned long tx_ip_header_error;
97 unsigned long tx_collision;
98 /* Receive errors */
99 unsigned long rx_desc;
100 unsigned long sa_filter_fail;
101 unsigned long overflow_error;
102 unsigned long ipc_csum_error;
103 unsigned long rx_collision;
104 unsigned long rx_crc_errors;
105 unsigned long dribbling_bit;
106 unsigned long rx_length;
107 unsigned long rx_mii;
108 unsigned long rx_multicast;
109 unsigned long rx_gmac_overflow;
110 unsigned long rx_watchdog;
111 unsigned long da_rx_filter_fail;
112 unsigned long sa_rx_filter_fail;
113 unsigned long rx_missed_cntr;
114 unsigned long rx_overflow_cntr;
115 unsigned long rx_vlan;
116 unsigned long rx_split_hdr_pkt_n;
117 /* Tx/Rx IRQ error info */
118 unsigned long tx_undeflow_irq;
119 unsigned long tx_process_stopped_irq;
120 unsigned long tx_jabber_irq;
121 unsigned long rx_overflow_irq;
122 unsigned long rx_buf_unav_irq;
123 unsigned long rx_process_stopped_irq;
124 unsigned long rx_watchdog_irq;
125 unsigned long tx_early_irq;
126 unsigned long fatal_bus_error_irq;
127 /* Tx/Rx IRQ Events */
128 unsigned long rx_early_irq;
129 unsigned long threshold;
130 unsigned long irq_receive_pmt_irq_n;
131 /* MMC info */
132 unsigned long mmc_tx_irq_n;
133 unsigned long mmc_rx_irq_n;
134 unsigned long mmc_rx_csum_offload_irq_n;
135 /* EEE */
136 unsigned long irq_tx_path_in_lpi_mode_n;
137 unsigned long irq_tx_path_exit_lpi_mode_n;
138 unsigned long irq_rx_path_in_lpi_mode_n;
139 unsigned long irq_rx_path_exit_lpi_mode_n;
140 unsigned long phy_eee_wakeup_error_n;
141 /* Extended RDES status */
142 unsigned long ip_hdr_err;
143 unsigned long ip_payload_err;
144 unsigned long ip_csum_bypassed;
145 unsigned long ipv4_pkt_rcvd;
146 unsigned long ipv6_pkt_rcvd;
147 unsigned long no_ptp_rx_msg_type_ext;
148 unsigned long ptp_rx_msg_type_sync;
149 unsigned long ptp_rx_msg_type_follow_up;
150 unsigned long ptp_rx_msg_type_delay_req;
151 unsigned long ptp_rx_msg_type_delay_resp;
152 unsigned long ptp_rx_msg_type_pdelay_req;
153 unsigned long ptp_rx_msg_type_pdelay_resp;
154 unsigned long ptp_rx_msg_type_pdelay_follow_up;
155 unsigned long ptp_rx_msg_type_announce;
156 unsigned long ptp_rx_msg_type_management;
157 unsigned long ptp_rx_msg_pkt_reserved_type;
158 unsigned long ptp_frame_type;
159 unsigned long ptp_ver;
160 unsigned long timestamp_dropped;
161 unsigned long av_pkt_rcvd;
162 unsigned long av_tagged_pkt_rcvd;
163 unsigned long vlan_tag_priority_val;
164 unsigned long l3_filter_match;
165 unsigned long l4_filter_match;
166 unsigned long l3_l4_filter_no_match;
167 /* PCS */
168 unsigned long irq_pcs_ane_n;
169 unsigned long irq_pcs_link_n;
170 unsigned long irq_rgmii_n;
171 unsigned long pcs_link;
172 unsigned long pcs_duplex;
173 unsigned long pcs_speed;
174 /* debug register */
175 unsigned long mtl_tx_status_fifo_full;
176 unsigned long mtl_tx_fifo_not_empty;
177 unsigned long mmtl_fifo_ctrl;
178 unsigned long mtl_tx_fifo_read_ctrl_write;
179 unsigned long mtl_tx_fifo_read_ctrl_wait;
180 unsigned long mtl_tx_fifo_read_ctrl_read;
181 unsigned long mtl_tx_fifo_read_ctrl_idle;
182 unsigned long mac_tx_in_pause;
183 unsigned long mac_tx_frame_ctrl_xfer;
184 unsigned long mac_tx_frame_ctrl_idle;
185 unsigned long mac_tx_frame_ctrl_wait;
186 unsigned long mac_tx_frame_ctrl_pause;
187 unsigned long mac_gmii_tx_proto_engine;
188 unsigned long mtl_rx_fifo_fill_level_full;
189 unsigned long mtl_rx_fifo_fill_above_thresh;
190 unsigned long mtl_rx_fifo_fill_below_thresh;
191 unsigned long mtl_rx_fifo_fill_level_empty;
192 unsigned long mtl_rx_fifo_read_ctrl_flush;
193 unsigned long mtl_rx_fifo_read_ctrl_read_data;
194 unsigned long mtl_rx_fifo_read_ctrl_status;
195 unsigned long mtl_rx_fifo_read_ctrl_idle;
196 unsigned long mtl_rx_fifo_ctrl_active;
197 unsigned long mac_rx_frame_ctrl_fifo;
198 unsigned long mac_gmii_rx_proto_engine;
199 /* EST */
200 unsigned long mtl_est_cgce;
201 unsigned long mtl_est_hlbs;
202 unsigned long mtl_est_hlbf;
203 unsigned long mtl_est_btre;
204 unsigned long mtl_est_btrlm;
205 /* per queue statistics */
206 struct stmmac_txq_stats txq_stats[MTL_MAX_TX_QUEUES];
207 struct stmmac_rxq_stats rxq_stats[MTL_MAX_RX_QUEUES];
208 unsigned long rx_dropped;
209 unsigned long rx_errors;
210 unsigned long tx_dropped;
211 unsigned long tx_errors;
212};
213
214/* Safety Feature statistics exposed by ethtool */
215struct stmmac_safety_stats {
216 unsigned long mac_errors[32];
217 unsigned long mtl_errors[32];
218 unsigned long dma_errors[32];
219};
220
221/* Number of fields in Safety Stats */
222#define STMMAC_SAFETY_FEAT_SIZE \
223 (sizeof(struct stmmac_safety_stats) / sizeof(unsigned long))
224
225/* CSR Frequency Access Defines*/
226#define CSR_F_35M 35000000
227#define CSR_F_60M 60000000
228#define CSR_F_100M 100000000
229#define CSR_F_150M 150000000
230#define CSR_F_250M 250000000
231#define CSR_F_300M 300000000
232
233#define MAC_CSR_H_FRQ_MASK 0x20
234
235#define HASH_TABLE_SIZE 64
236#define PAUSE_TIME 0xffff
237
238/* Flow Control defines */
239#define FLOW_OFF 0
240#define FLOW_RX 1
241#define FLOW_TX 2
242#define FLOW_AUTO (FLOW_TX | FLOW_RX)
243
244/* PCS defines */
245#define STMMAC_PCS_RGMII (1 << 0)
246#define STMMAC_PCS_SGMII (1 << 1)
247#define STMMAC_PCS_TBI (1 << 2)
248#define STMMAC_PCS_RTBI (1 << 3)
249
250#define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */
251
252/* DMA HW feature register fields */
253#define DMA_HW_FEAT_MIISEL 0x00000001 /* 10/100 Mbps Support */
254#define DMA_HW_FEAT_GMIISEL 0x00000002 /* 1000 Mbps Support */
255#define DMA_HW_FEAT_HDSEL 0x00000004 /* Half-Duplex Support */
256#define DMA_HW_FEAT_EXTHASHEN 0x00000008 /* Expanded DA Hash Filter */
257#define DMA_HW_FEAT_HASHSEL 0x00000010 /* HASH Filter */
258#define DMA_HW_FEAT_ADDMAC 0x00000020 /* Multiple MAC Addr Reg */
259#define DMA_HW_FEAT_PCSSEL 0x00000040 /* PCS registers */
260#define DMA_HW_FEAT_L3L4FLTREN 0x00000080 /* Layer 3 & Layer 4 Feature */
261#define DMA_HW_FEAT_SMASEL 0x00000100 /* SMA(MDIO) Interface */
262#define DMA_HW_FEAT_RWKSEL 0x00000200 /* PMT Remote Wakeup */
263#define DMA_HW_FEAT_MGKSEL 0x00000400 /* PMT Magic Packet */
264#define DMA_HW_FEAT_MMCSEL 0x00000800 /* RMON Module */
265#define DMA_HW_FEAT_TSVER1SEL 0x00001000 /* Only IEEE 1588-2002 */
266#define DMA_HW_FEAT_TSVER2SEL 0x00002000 /* IEEE 1588-2008 PTPv2 */
267#define DMA_HW_FEAT_EEESEL 0x00004000 /* Energy Efficient Ethernet */
268#define DMA_HW_FEAT_AVSEL 0x00008000 /* AV Feature */
269#define DMA_HW_FEAT_TXCOESEL 0x00010000 /* Checksum Offload in Tx */
270#define DMA_HW_FEAT_RXTYP1COE 0x00020000 /* IP COE (Type 1) in Rx */
271#define DMA_HW_FEAT_RXTYP2COE 0x00040000 /* IP COE (Type 2) in Rx */
272#define DMA_HW_FEAT_RXFIFOSIZE 0x00080000 /* Rx FIFO > 2048 Bytes */
273#define DMA_HW_FEAT_RXCHCNT 0x00300000 /* No. additional Rx Channels */
274#define DMA_HW_FEAT_TXCHCNT 0x00c00000 /* No. additional Tx Channels */
275#define DMA_HW_FEAT_ENHDESSEL 0x01000000 /* Alternate Descriptor */
276/* Timestamping with Internal System Time */
277#define DMA_HW_FEAT_INTTSEN 0x02000000
278#define DMA_HW_FEAT_FLEXIPPSEN 0x04000000 /* Flexible PPS Output */
279#define DMA_HW_FEAT_SAVLANINS 0x08000000 /* Source Addr or VLAN */
280#define DMA_HW_FEAT_ACTPHYIF 0x70000000 /* Active/selected PHY iface */
281#define DEFAULT_DMA_PBL 8
282
283/* MSI defines */
284#define STMMAC_MSI_VEC_MAX 32
285
286/* PCS status and mask defines */
287#define PCS_ANE_IRQ BIT(2) /* PCS Auto-Negotiation */
288#define PCS_LINK_IRQ BIT(1) /* PCS Link */
289#define PCS_RGSMIIIS_IRQ BIT(0) /* RGMII or SMII Interrupt */
290
291/* Max/Min RI Watchdog Timer count value */
292#define MAX_DMA_RIWT 0xff
293#define MIN_DMA_RIWT 0x10
294#define DEF_DMA_RIWT 0xa0
295/* Tx coalesce parameters */
296#define STMMAC_COAL_TX_TIMER 5000
297#define STMMAC_MAX_COAL_TX_TICK 100000
298#define STMMAC_TX_MAX_FRAMES 256
299#define STMMAC_TX_FRAMES 25
300#define STMMAC_RX_FRAMES 0
301
302/* Packets types */
303enum packets_types {
304 PACKET_AVCPQ = 0x1, /* AV Untagged Control packets */
305 PACKET_PTPQ = 0x2, /* PTP Packets */
306 PACKET_DCBCPQ = 0x3, /* DCB Control Packets */
307 PACKET_UPQ = 0x4, /* Untagged Packets */
308 PACKET_MCBCQ = 0x5, /* Multicast & Broadcast Packets */
309};
310
311/* Rx IPC status */
312enum rx_frame_status {
313 good_frame = 0x0,
314 discard_frame = 0x1,
315 csum_none = 0x2,
316 llc_snap = 0x4,
317 dma_own = 0x8,
318 rx_not_ls = 0x10,
319};
320
321/* Tx status */
322enum tx_frame_status {
323 tx_done = 0x0,
324 tx_not_ls = 0x1,
325 tx_err = 0x2,
326 tx_dma_own = 0x4,
327 tx_err_bump_tc = 0x8,
328};
329
330enum dma_irq_status {
331 tx_hard_error = 0x1,
332 tx_hard_error_bump_tc = 0x2,
333 handle_rx = 0x4,
334 handle_tx = 0x8,
335};
336
337enum dma_irq_dir {
338 DMA_DIR_RX = 0x1,
339 DMA_DIR_TX = 0x2,
340 DMA_DIR_RXTX = 0x3,
341};
342
343enum request_irq_err {
344 REQ_IRQ_ERR_ALL,
345 REQ_IRQ_ERR_TX,
346 REQ_IRQ_ERR_RX,
347 REQ_IRQ_ERR_SFTY_UE,
348 REQ_IRQ_ERR_SFTY_CE,
349 REQ_IRQ_ERR_LPI,
350 REQ_IRQ_ERR_WOL,
351 REQ_IRQ_ERR_MAC,
352 REQ_IRQ_ERR_NO,
353};
354
355/* EEE and LPI defines */
356#define CORE_IRQ_TX_PATH_IN_LPI_MODE (1 << 0)
357#define CORE_IRQ_TX_PATH_EXIT_LPI_MODE (1 << 1)
358#define CORE_IRQ_RX_PATH_IN_LPI_MODE (1 << 2)
359#define CORE_IRQ_RX_PATH_EXIT_LPI_MODE (1 << 3)
360
361/* FPE defines */
362#define FPE_EVENT_UNKNOWN 0
363#define FPE_EVENT_TRSP BIT(0)
364#define FPE_EVENT_TVER BIT(1)
365#define FPE_EVENT_RRSP BIT(2)
366#define FPE_EVENT_RVER BIT(3)
367
368#define CORE_IRQ_MTL_RX_OVERFLOW BIT(8)
369
370/* Physical Coding Sublayer */
371struct rgmii_adv {
372 unsigned int pause;
373 unsigned int duplex;
374 unsigned int lp_pause;
375 unsigned int lp_duplex;
376};
377
378#define STMMAC_PCS_PAUSE 1
379#define STMMAC_PCS_ASYM_PAUSE 2
380
381/* DMA HW capabilities */
382struct dma_features {
383 unsigned int mbps_10_100;
384 unsigned int mbps_1000;
385 unsigned int half_duplex;
386 unsigned int hash_filter;
387 unsigned int multi_addr;
388 unsigned int pcs;
389 unsigned int sma_mdio;
390 unsigned int pmt_remote_wake_up;
391 unsigned int pmt_magic_frame;
392 unsigned int rmon;
393 /* IEEE 1588-2002 */
394 unsigned int time_stamp;
395 /* IEEE 1588-2008 */
396 unsigned int atime_stamp;
397 /* 802.3az - Energy-Efficient Ethernet (EEE) */
398 unsigned int eee;
399 unsigned int av;
400 unsigned int hash_tb_sz;
401 unsigned int tsoen;
402 /* TX and RX csum */
403 unsigned int tx_coe;
404 unsigned int rx_coe;
405 unsigned int rx_coe_type1;
406 unsigned int rx_coe_type2;
407 unsigned int rxfifo_over_2048;
408 /* TX and RX number of channels */
409 unsigned int number_rx_channel;
410 unsigned int number_tx_channel;
411 /* TX and RX number of queues */
412 unsigned int number_rx_queues;
413 unsigned int number_tx_queues;
414 /* PPS output */
415 unsigned int pps_out_num;
416 /* Number of Traffic Classes */
417 unsigned int numtc;
418 /* DCB Feature Enable */
419 unsigned int dcben;
420 /* IEEE 1588 High Word Register Enable */
421 unsigned int advthword;
422 /* PTP Offload Enable */
423 unsigned int ptoen;
424 /* One-Step Timestamping Enable */
425 unsigned int osten;
426 /* Priority-Based Flow Control Enable */
427 unsigned int pfcen;
428 /* Alternate (enhanced) DESC mode */
429 unsigned int enh_desc;
430 /* TX and RX FIFO sizes */
431 unsigned int tx_fifo_size;
432 unsigned int rx_fifo_size;
433 /* Automotive Safety Package */
434 unsigned int asp;
435 /* RX Parser */
436 unsigned int frpsel;
437 unsigned int frpbs;
438 unsigned int frpes;
439 unsigned int addr64;
440 unsigned int host_dma_width;
441 unsigned int rssen;
442 unsigned int vlhash;
443 unsigned int sphen;
444 unsigned int vlins;
445 unsigned int dvlan;
446 unsigned int l3l4fnum;
447 unsigned int arpoffsel;
448 /* One Step for PTP over UDP/IP Feature Enable */
449 unsigned int pou_ost_en;
450 /* Tx Timestamp FIFO Depth */
451 unsigned int ttsfd;
452 /* Queue/Channel-Based VLAN tag insertion on Tx */
453 unsigned int cbtisel;
454 /* Supported Parallel Instruction Processor Engines */
455 unsigned int frppipe_num;
456 /* Number of Extended VLAN Tag Filters */
457 unsigned int nrvf_num;
458 /* TSN Features */
459 unsigned int estwid;
460 unsigned int estdep;
461 unsigned int estsel;
462 unsigned int fpesel;
463 unsigned int tbssel;
464 /* Number of DMA channels enabled for TBS */
465 unsigned int tbs_ch_num;
466 /* Per-Stream Filtering Enable */
467 unsigned int sgfsel;
468 /* Numbers of Auxiliary Snapshot Inputs */
469 unsigned int aux_snapshot_n;
470 /* Timestamp System Time Source */
471 unsigned int tssrc;
472 /* Enhanced DMA Enable */
473 unsigned int edma;
474 /* Different Descriptor Cache Enable */
475 unsigned int ediffc;
476 /* VxLAN/NVGRE Enable */
477 unsigned int vxn;
478 /* Debug Memory Interface Enable */
479 unsigned int dbgmem;
480 /* Number of Policing Counters */
481 unsigned int pcsel;
482};
483
484/* RX Buffer size must be multiple of 4/8/16 bytes */
485#define BUF_SIZE_16KiB 16368
486#define BUF_SIZE_8KiB 8188
487#define BUF_SIZE_4KiB 4096
488#define BUF_SIZE_2KiB 2048
489
490/* Power Down and WOL */
491#define PMT_NOT_SUPPORTED 0
492#define PMT_SUPPORTED 1
493
494/* Common MAC defines */
495#define MAC_CTRL_REG 0x00000000 /* MAC Control */
496#define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */
497#define MAC_ENABLE_RX 0x00000004 /* Receiver Enable */
498
499/* Default LPI timers */
500#define STMMAC_DEFAULT_LIT_LS 0x3E8
501#define STMMAC_DEFAULT_TWT_LS 0x1E
502#define STMMAC_ET_MAX 0xFFFFF
503
504#define STMMAC_CHAIN_MODE 0x1
505#define STMMAC_RING_MODE 0x2
506
507#define JUMBO_LEN 9000
508
509/* Receive Side Scaling */
510#define STMMAC_RSS_HASH_KEY_SIZE 40
511#define STMMAC_RSS_MAX_TABLE_SIZE 256
512
513/* VLAN */
514#define STMMAC_VLAN_NONE 0x0
515#define STMMAC_VLAN_REMOVE 0x1
516#define STMMAC_VLAN_INSERT 0x2
517#define STMMAC_VLAN_REPLACE 0x3
518
519extern const struct stmmac_desc_ops enh_desc_ops;
520extern const struct stmmac_desc_ops ndesc_ops;
521
522struct mac_device_info;
523
524extern const struct stmmac_hwtimestamp stmmac_ptp;
525extern const struct stmmac_mode_ops dwmac4_ring_mode_ops;
526
527struct mac_link {
528 u32 speed_mask;
529 u32 speed10;
530 u32 speed100;
531 u32 speed1000;
532 u32 speed2500;
533 u32 duplex;
534 struct {
535 u32 speed2500;
536 u32 speed5000;
537 u32 speed10000;
538 } xgmii;
539 struct {
540 u32 speed25000;
541 u32 speed40000;
542 u32 speed50000;
543 u32 speed100000;
544 } xlgmii;
545};
546
547struct mii_regs {
548 unsigned int addr; /* MII Address */
549 unsigned int data; /* MII Data */
550 unsigned int addr_shift; /* MII address shift */
551 unsigned int reg_shift; /* MII reg shift */
552 unsigned int addr_mask; /* MII address mask */
553 unsigned int reg_mask; /* MII reg mask */
554 unsigned int clk_csr_shift;
555 unsigned int clk_csr_mask;
556};
557
558struct mac_device_info {
559 const struct stmmac_ops *mac;
560 const struct stmmac_desc_ops *desc;
561 const struct stmmac_dma_ops *dma;
562 const struct stmmac_mode_ops *mode;
563 const struct stmmac_hwtimestamp *ptp;
564 const struct stmmac_tc_ops *tc;
565 const struct stmmac_mmc_ops *mmc;
566 struct dw_xpcs *xpcs;
567 struct phylink_pcs *lynx_pcs; /* Lynx external PCS */
568 struct mii_regs mii; /* MII register Addresses */
569 struct mac_link link;
570 void __iomem *pcsr; /* vpointer to device CSRs */
571 unsigned int multicast_filter_bins;
572 unsigned int unicast_filter_entries;
573 unsigned int mcast_bits_log2;
574 unsigned int rx_csum;
575 unsigned int pcs;
576 unsigned int pmt;
577 unsigned int ps;
578 unsigned int xlgmac;
579 unsigned int num_vlan;
580 u32 vlan_filter[32];
581 bool vlan_fail_q_en;
582 u8 vlan_fail_q;
583};
584
585struct stmmac_rx_routing {
586 u32 reg_mask;
587 u32 reg_shift;
588};
589
590int dwmac100_setup(struct stmmac_priv *priv);
591int dwmac1000_setup(struct stmmac_priv *priv);
592int dwmac4_setup(struct stmmac_priv *priv);
593int dwxgmac2_setup(struct stmmac_priv *priv);
594int dwxlgmac2_setup(struct stmmac_priv *priv);
595
596void stmmac_set_mac_addr(void __iomem *ioaddr, const u8 addr[6],
597 unsigned int high, unsigned int low);
598void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
599 unsigned int high, unsigned int low);
600void stmmac_set_mac(void __iomem *ioaddr, bool enable);
601
602void stmmac_dwmac4_set_mac_addr(void __iomem *ioaddr, const u8 addr[6],
603 unsigned int high, unsigned int low);
604void stmmac_dwmac4_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
605 unsigned int high, unsigned int low);
606void stmmac_dwmac4_set_mac(void __iomem *ioaddr, bool enable);
607
608void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr);
609
610extern const struct stmmac_mode_ops ring_mode_ops;
611extern const struct stmmac_mode_ops chain_mode_ops;
612extern const struct stmmac_desc_ops dwmac4_desc_ops;
613
614#endif /* __COMMON_H__ */
615

source code of linux/drivers/net/ethernet/stmicro/stmmac/common.h