1 | /* Synopsys DesignWare Core Enterprise Ethernet (XLGMAC) Driver |
2 | * |
3 | * Copyright (c) 2017 Synopsys, Inc. (www.synopsys.com) |
4 | * |
5 | * This program is dual-licensed; you may select either version 2 of |
6 | * the GNU General Public License ("GPL") or BSD license ("BSD"). |
7 | * |
8 | * This Synopsys DWC XLGMAC software driver and associated documentation |
9 | * (hereinafter the "Software") is an unsupported proprietary work of |
10 | * Synopsys, Inc. unless otherwise expressly agreed to in writing between |
11 | * Synopsys and you. The Software IS NOT an item of Licensed Software or a |
12 | * Licensed Product under any End User Software License Agreement or |
13 | * Agreement for Licensed Products with Synopsys or any supplement thereto. |
14 | * Synopsys is a registered trademark of Synopsys, Inc. Other names included |
15 | * in the SOFTWARE may be the trademarks of their respective owners. |
16 | */ |
17 | |
18 | #include <linux/kernel.h> |
19 | #include <linux/module.h> |
20 | |
21 | #include "dwc-xlgmac.h" |
22 | #include "dwc-xlgmac-reg.h" |
23 | |
24 | MODULE_LICENSE("Dual BSD/GPL" ); |
25 | |
26 | static int debug = -1; |
27 | module_param(debug, int, 0644); |
28 | MODULE_PARM_DESC(debug, "DWC ethernet debug level (0=none,...,16=all)" ); |
29 | static const u32 default_msg_level = (NETIF_MSG_LINK | NETIF_MSG_IFDOWN | |
30 | NETIF_MSG_IFUP); |
31 | |
32 | static unsigned char dev_addr[6] = {0, 0x55, 0x7b, 0xb5, 0x7d, 0xf7}; |
33 | |
34 | static void xlgmac_read_mac_addr(struct xlgmac_pdata *pdata) |
35 | { |
36 | struct net_device *netdev = pdata->netdev; |
37 | |
38 | /* Currently it uses a static mac address for test */ |
39 | memcpy(pdata->mac_addr, dev_addr, netdev->addr_len); |
40 | } |
41 | |
42 | static void xlgmac_default_config(struct xlgmac_pdata *pdata) |
43 | { |
44 | pdata->tx_osp_mode = DMA_OSP_ENABLE; |
45 | pdata->tx_sf_mode = MTL_TSF_ENABLE; |
46 | pdata->rx_sf_mode = MTL_RSF_DISABLE; |
47 | pdata->pblx8 = DMA_PBL_X8_ENABLE; |
48 | pdata->tx_pbl = DMA_PBL_32; |
49 | pdata->rx_pbl = DMA_PBL_32; |
50 | pdata->tx_threshold = MTL_TX_THRESHOLD_128; |
51 | pdata->rx_threshold = MTL_RX_THRESHOLD_128; |
52 | pdata->tx_pause = 1; |
53 | pdata->rx_pause = 1; |
54 | pdata->phy_speed = SPEED_25000; |
55 | pdata->sysclk_rate = XLGMAC_SYSCLOCK; |
56 | |
57 | strscpy(p: pdata->drv_name, XLGMAC_DRV_NAME, size: sizeof(pdata->drv_name)); |
58 | strscpy(p: pdata->drv_ver, XLGMAC_DRV_VERSION, size: sizeof(pdata->drv_ver)); |
59 | } |
60 | |
61 | static void xlgmac_init_all_ops(struct xlgmac_pdata *pdata) |
62 | { |
63 | xlgmac_init_desc_ops(desc_ops: &pdata->desc_ops); |
64 | xlgmac_init_hw_ops(hw_ops: &pdata->hw_ops); |
65 | } |
66 | |
67 | static int xlgmac_init(struct xlgmac_pdata *pdata) |
68 | { |
69 | struct xlgmac_hw_ops *hw_ops = &pdata->hw_ops; |
70 | struct net_device *netdev = pdata->netdev; |
71 | unsigned int i; |
72 | int ret; |
73 | |
74 | /* Set default configuration data */ |
75 | xlgmac_default_config(pdata); |
76 | |
77 | /* Set irq, base_addr, MAC address, */ |
78 | netdev->irq = pdata->dev_irq; |
79 | netdev->base_addr = (unsigned long)pdata->mac_regs; |
80 | xlgmac_read_mac_addr(pdata); |
81 | eth_hw_addr_set(dev: netdev, addr: pdata->mac_addr); |
82 | |
83 | /* Set all the function pointers */ |
84 | xlgmac_init_all_ops(pdata); |
85 | |
86 | /* Issue software reset to device */ |
87 | hw_ops->exit(pdata); |
88 | |
89 | /* Populate the hardware features */ |
90 | xlgmac_get_all_hw_features(pdata); |
91 | xlgmac_print_all_hw_features(pdata); |
92 | |
93 | /* TODO: Set the PHY mode to XLGMII */ |
94 | |
95 | /* Set the DMA mask */ |
96 | ret = dma_set_mask_and_coherent(dev: pdata->dev, |
97 | DMA_BIT_MASK(pdata->hw_feat.dma_width)); |
98 | if (ret) { |
99 | dev_err(pdata->dev, "dma_set_mask_and_coherent failed\n" ); |
100 | return ret; |
101 | } |
102 | |
103 | /* Channel and ring params initializtion |
104 | * pdata->channel_count; |
105 | * pdata->tx_ring_count; |
106 | * pdata->rx_ring_count; |
107 | * pdata->tx_desc_count; |
108 | * pdata->rx_desc_count; |
109 | */ |
110 | BUILD_BUG_ON_NOT_POWER_OF_2(XLGMAC_TX_DESC_CNT); |
111 | pdata->tx_desc_count = XLGMAC_TX_DESC_CNT; |
112 | if (pdata->tx_desc_count & (pdata->tx_desc_count - 1)) { |
113 | dev_err(pdata->dev, "tx descriptor count (%d) is not valid\n" , |
114 | pdata->tx_desc_count); |
115 | ret = -EINVAL; |
116 | return ret; |
117 | } |
118 | BUILD_BUG_ON_NOT_POWER_OF_2(XLGMAC_RX_DESC_CNT); |
119 | pdata->rx_desc_count = XLGMAC_RX_DESC_CNT; |
120 | if (pdata->rx_desc_count & (pdata->rx_desc_count - 1)) { |
121 | dev_err(pdata->dev, "rx descriptor count (%d) is not valid\n" , |
122 | pdata->rx_desc_count); |
123 | ret = -EINVAL; |
124 | return ret; |
125 | } |
126 | |
127 | pdata->tx_ring_count = min_t(unsigned int, num_online_cpus(), |
128 | pdata->hw_feat.tx_ch_cnt); |
129 | pdata->tx_ring_count = min_t(unsigned int, pdata->tx_ring_count, |
130 | pdata->hw_feat.tx_q_cnt); |
131 | pdata->tx_q_count = pdata->tx_ring_count; |
132 | ret = netif_set_real_num_tx_queues(dev: netdev, txq: pdata->tx_q_count); |
133 | if (ret) { |
134 | dev_err(pdata->dev, "error setting real tx queue count\n" ); |
135 | return ret; |
136 | } |
137 | |
138 | pdata->rx_ring_count = min_t(unsigned int, |
139 | netif_get_num_default_rss_queues(), |
140 | pdata->hw_feat.rx_ch_cnt); |
141 | pdata->rx_ring_count = min_t(unsigned int, pdata->rx_ring_count, |
142 | pdata->hw_feat.rx_q_cnt); |
143 | pdata->rx_q_count = pdata->rx_ring_count; |
144 | ret = netif_set_real_num_rx_queues(dev: netdev, rxq: pdata->rx_q_count); |
145 | if (ret) { |
146 | dev_err(pdata->dev, "error setting real rx queue count\n" ); |
147 | return ret; |
148 | } |
149 | |
150 | pdata->channel_count = |
151 | max_t(unsigned int, pdata->tx_ring_count, pdata->rx_ring_count); |
152 | |
153 | /* Initialize RSS hash key and lookup table */ |
154 | netdev_rss_key_fill(buffer: pdata->rss_key, len: sizeof(pdata->rss_key)); |
155 | |
156 | for (i = 0; i < XLGMAC_RSS_MAX_TABLE_SIZE; i++) |
157 | pdata->rss_table[i] = XLGMAC_SET_REG_BITS( |
158 | pdata->rss_table[i], |
159 | MAC_RSSDR_DMCH_POS, |
160 | MAC_RSSDR_DMCH_LEN, |
161 | i % pdata->rx_ring_count); |
162 | |
163 | pdata->rss_options = XLGMAC_SET_REG_BITS( |
164 | pdata->rss_options, |
165 | MAC_RSSCR_IP2TE_POS, |
166 | MAC_RSSCR_IP2TE_LEN, 1); |
167 | pdata->rss_options = XLGMAC_SET_REG_BITS( |
168 | pdata->rss_options, |
169 | MAC_RSSCR_TCP4TE_POS, |
170 | MAC_RSSCR_TCP4TE_LEN, 1); |
171 | pdata->rss_options = XLGMAC_SET_REG_BITS( |
172 | pdata->rss_options, |
173 | MAC_RSSCR_UDP4TE_POS, |
174 | MAC_RSSCR_UDP4TE_LEN, 1); |
175 | |
176 | /* Set device operations */ |
177 | netdev->netdev_ops = xlgmac_get_netdev_ops(); |
178 | netdev->ethtool_ops = xlgmac_get_ethtool_ops(); |
179 | |
180 | /* Set device features */ |
181 | if (pdata->hw_feat.tso) { |
182 | netdev->hw_features = NETIF_F_TSO; |
183 | netdev->hw_features |= NETIF_F_TSO6; |
184 | netdev->hw_features |= NETIF_F_SG; |
185 | netdev->hw_features |= NETIF_F_IP_CSUM; |
186 | netdev->hw_features |= NETIF_F_IPV6_CSUM; |
187 | } else if (pdata->hw_feat.tx_coe) { |
188 | netdev->hw_features = NETIF_F_IP_CSUM; |
189 | netdev->hw_features |= NETIF_F_IPV6_CSUM; |
190 | } |
191 | |
192 | if (pdata->hw_feat.rx_coe) { |
193 | netdev->hw_features |= NETIF_F_RXCSUM; |
194 | netdev->hw_features |= NETIF_F_GRO; |
195 | } |
196 | |
197 | if (pdata->hw_feat.rss) |
198 | netdev->hw_features |= NETIF_F_RXHASH; |
199 | |
200 | netdev->vlan_features |= netdev->hw_features; |
201 | |
202 | netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX; |
203 | if (pdata->hw_feat.sa_vlan_ins) |
204 | netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX; |
205 | if (pdata->hw_feat.vlhash) |
206 | netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; |
207 | |
208 | netdev->features |= netdev->hw_features; |
209 | pdata->netdev_features = netdev->features; |
210 | |
211 | netdev->priv_flags |= IFF_UNICAST_FLT; |
212 | |
213 | /* Use default watchdog timeout */ |
214 | netdev->watchdog_timeo = 0; |
215 | |
216 | /* Tx coalesce parameters initialization */ |
217 | pdata->tx_usecs = XLGMAC_INIT_DMA_TX_USECS; |
218 | pdata->tx_frames = XLGMAC_INIT_DMA_TX_FRAMES; |
219 | |
220 | /* Rx coalesce parameters initialization */ |
221 | pdata->rx_riwt = hw_ops->usec_to_riwt(pdata, XLGMAC_INIT_DMA_RX_USECS); |
222 | pdata->rx_usecs = XLGMAC_INIT_DMA_RX_USECS; |
223 | pdata->rx_frames = XLGMAC_INIT_DMA_RX_FRAMES; |
224 | |
225 | return 0; |
226 | } |
227 | |
228 | int xlgmac_drv_probe(struct device *dev, struct xlgmac_resources *res) |
229 | { |
230 | struct xlgmac_pdata *pdata; |
231 | struct net_device *netdev; |
232 | int ret; |
233 | |
234 | netdev = alloc_etherdev_mq(sizeof(struct xlgmac_pdata), |
235 | XLGMAC_MAX_DMA_CHANNELS); |
236 | |
237 | if (!netdev) { |
238 | dev_err(dev, "alloc_etherdev failed\n" ); |
239 | return -ENOMEM; |
240 | } |
241 | |
242 | SET_NETDEV_DEV(netdev, dev); |
243 | dev_set_drvdata(dev, data: netdev); |
244 | pdata = netdev_priv(dev: netdev); |
245 | pdata->dev = dev; |
246 | pdata->netdev = netdev; |
247 | |
248 | pdata->dev_irq = res->irq; |
249 | pdata->mac_regs = res->addr; |
250 | |
251 | mutex_init(&pdata->rss_mutex); |
252 | pdata->msg_enable = netif_msg_init(debug_value: debug, default_msg_enable_bits: default_msg_level); |
253 | |
254 | ret = xlgmac_init(pdata); |
255 | if (ret) { |
256 | dev_err(dev, "xlgmac init failed\n" ); |
257 | goto err_free_netdev; |
258 | } |
259 | |
260 | ret = register_netdev(dev: netdev); |
261 | if (ret) { |
262 | dev_err(dev, "net device registration failed\n" ); |
263 | goto err_free_netdev; |
264 | } |
265 | |
266 | return 0; |
267 | |
268 | err_free_netdev: |
269 | free_netdev(dev: netdev); |
270 | |
271 | return ret; |
272 | } |
273 | |
274 | int xlgmac_drv_remove(struct device *dev) |
275 | { |
276 | struct net_device *netdev = dev_get_drvdata(dev); |
277 | |
278 | unregister_netdev(dev: netdev); |
279 | free_netdev(dev: netdev); |
280 | |
281 | return 0; |
282 | } |
283 | |
284 | void xlgmac_dump_tx_desc(struct xlgmac_pdata *pdata, |
285 | struct xlgmac_ring *ring, |
286 | unsigned int idx, |
287 | unsigned int count, |
288 | unsigned int flag) |
289 | { |
290 | struct xlgmac_desc_data *desc_data; |
291 | struct xlgmac_dma_desc *dma_desc; |
292 | |
293 | while (count--) { |
294 | desc_data = XLGMAC_GET_DESC_DATA(ring, idx); |
295 | dma_desc = desc_data->dma_desc; |
296 | |
297 | netdev_dbg(pdata->netdev, "TX: dma_desc=%p, dma_desc_addr=%pad\n" , |
298 | desc_data->dma_desc, &desc_data->dma_desc_addr); |
299 | netdev_dbg(pdata->netdev, |
300 | "TX_NORMAL_DESC[%d %s] = %08x:%08x:%08x:%08x\n" , idx, |
301 | (flag == 1) ? "QUEUED FOR TX" : "TX BY DEVICE" , |
302 | le32_to_cpu(dma_desc->desc0), |
303 | le32_to_cpu(dma_desc->desc1), |
304 | le32_to_cpu(dma_desc->desc2), |
305 | le32_to_cpu(dma_desc->desc3)); |
306 | |
307 | idx++; |
308 | } |
309 | } |
310 | |
311 | void xlgmac_dump_rx_desc(struct xlgmac_pdata *pdata, |
312 | struct xlgmac_ring *ring, |
313 | unsigned int idx) |
314 | { |
315 | struct xlgmac_desc_data *desc_data; |
316 | struct xlgmac_dma_desc *dma_desc; |
317 | |
318 | desc_data = XLGMAC_GET_DESC_DATA(ring, idx); |
319 | dma_desc = desc_data->dma_desc; |
320 | |
321 | netdev_dbg(pdata->netdev, "RX: dma_desc=%p, dma_desc_addr=%pad\n" , |
322 | desc_data->dma_desc, &desc_data->dma_desc_addr); |
323 | netdev_dbg(pdata->netdev, |
324 | "RX_NORMAL_DESC[%d RX BY DEVICE] = %08x:%08x:%08x:%08x\n" , |
325 | idx, |
326 | le32_to_cpu(dma_desc->desc0), |
327 | le32_to_cpu(dma_desc->desc1), |
328 | le32_to_cpu(dma_desc->desc2), |
329 | le32_to_cpu(dma_desc->desc3)); |
330 | } |
331 | |
332 | void xlgmac_print_pkt(struct net_device *netdev, |
333 | struct sk_buff *skb, bool tx_rx) |
334 | { |
335 | struct ethhdr *eth = (struct ethhdr *)skb->data; |
336 | unsigned char buffer[128]; |
337 | unsigned int i; |
338 | |
339 | netdev_dbg(netdev, "\n************** SKB dump ****************\n" ); |
340 | |
341 | netdev_dbg(netdev, "%s packet of %d bytes\n" , |
342 | (tx_rx ? "TX" : "RX" ), skb->len); |
343 | |
344 | netdev_dbg(netdev, "Dst MAC addr: %pM\n" , eth->h_dest); |
345 | netdev_dbg(netdev, "Src MAC addr: %pM\n" , eth->h_source); |
346 | netdev_dbg(netdev, "Protocol: %#06hx\n" , ntohs(eth->h_proto)); |
347 | |
348 | for (i = 0; i < skb->len; i += 32) { |
349 | unsigned int len = min(skb->len - i, 32U); |
350 | |
351 | hex_dump_to_buffer(buf: &skb->data[i], len, rowsize: 32, groupsize: 1, |
352 | linebuf: buffer, linebuflen: sizeof(buffer), ascii: false); |
353 | netdev_dbg(netdev, " %#06x: %s\n" , i, buffer); |
354 | } |
355 | |
356 | netdev_dbg(netdev, "\n************** SKB dump ****************\n" ); |
357 | } |
358 | |
359 | void xlgmac_get_all_hw_features(struct xlgmac_pdata *pdata) |
360 | { |
361 | struct xlgmac_hw_features *hw_feat = &pdata->hw_feat; |
362 | unsigned int mac_hfr0, mac_hfr1, mac_hfr2; |
363 | |
364 | mac_hfr0 = readl(addr: pdata->mac_regs + MAC_HWF0R); |
365 | mac_hfr1 = readl(addr: pdata->mac_regs + MAC_HWF1R); |
366 | mac_hfr2 = readl(addr: pdata->mac_regs + MAC_HWF2R); |
367 | |
368 | memset(hw_feat, 0, sizeof(*hw_feat)); |
369 | |
370 | hw_feat->version = readl(addr: pdata->mac_regs + MAC_VR); |
371 | |
372 | /* Hardware feature register 0 */ |
373 | hw_feat->phyifsel = XLGMAC_GET_REG_BITS(mac_hfr0, |
374 | MAC_HWF0R_PHYIFSEL_POS, |
375 | MAC_HWF0R_PHYIFSEL_LEN); |
376 | hw_feat->vlhash = XLGMAC_GET_REG_BITS(mac_hfr0, |
377 | MAC_HWF0R_VLHASH_POS, |
378 | MAC_HWF0R_VLHASH_LEN); |
379 | hw_feat->sma = XLGMAC_GET_REG_BITS(mac_hfr0, |
380 | MAC_HWF0R_SMASEL_POS, |
381 | MAC_HWF0R_SMASEL_LEN); |
382 | hw_feat->rwk = XLGMAC_GET_REG_BITS(mac_hfr0, |
383 | MAC_HWF0R_RWKSEL_POS, |
384 | MAC_HWF0R_RWKSEL_LEN); |
385 | hw_feat->mgk = XLGMAC_GET_REG_BITS(mac_hfr0, |
386 | MAC_HWF0R_MGKSEL_POS, |
387 | MAC_HWF0R_MGKSEL_LEN); |
388 | hw_feat->mmc = XLGMAC_GET_REG_BITS(mac_hfr0, |
389 | MAC_HWF0R_MMCSEL_POS, |
390 | MAC_HWF0R_MMCSEL_LEN); |
391 | hw_feat->aoe = XLGMAC_GET_REG_BITS(mac_hfr0, |
392 | MAC_HWF0R_ARPOFFSEL_POS, |
393 | MAC_HWF0R_ARPOFFSEL_LEN); |
394 | hw_feat->ts = XLGMAC_GET_REG_BITS(mac_hfr0, |
395 | MAC_HWF0R_TSSEL_POS, |
396 | MAC_HWF0R_TSSEL_LEN); |
397 | hw_feat->eee = XLGMAC_GET_REG_BITS(mac_hfr0, |
398 | MAC_HWF0R_EEESEL_POS, |
399 | MAC_HWF0R_EEESEL_LEN); |
400 | hw_feat->tx_coe = XLGMAC_GET_REG_BITS(mac_hfr0, |
401 | MAC_HWF0R_TXCOESEL_POS, |
402 | MAC_HWF0R_TXCOESEL_LEN); |
403 | hw_feat->rx_coe = XLGMAC_GET_REG_BITS(mac_hfr0, |
404 | MAC_HWF0R_RXCOESEL_POS, |
405 | MAC_HWF0R_RXCOESEL_LEN); |
406 | hw_feat->addn_mac = XLGMAC_GET_REG_BITS(mac_hfr0, |
407 | MAC_HWF0R_ADDMACADRSEL_POS, |
408 | MAC_HWF0R_ADDMACADRSEL_LEN); |
409 | hw_feat->ts_src = XLGMAC_GET_REG_BITS(mac_hfr0, |
410 | MAC_HWF0R_TSSTSSEL_POS, |
411 | MAC_HWF0R_TSSTSSEL_LEN); |
412 | hw_feat->sa_vlan_ins = XLGMAC_GET_REG_BITS(mac_hfr0, |
413 | MAC_HWF0R_SAVLANINS_POS, |
414 | MAC_HWF0R_SAVLANINS_LEN); |
415 | |
416 | /* Hardware feature register 1 */ |
417 | hw_feat->rx_fifo_size = XLGMAC_GET_REG_BITS(mac_hfr1, |
418 | MAC_HWF1R_RXFIFOSIZE_POS, |
419 | MAC_HWF1R_RXFIFOSIZE_LEN); |
420 | hw_feat->tx_fifo_size = XLGMAC_GET_REG_BITS(mac_hfr1, |
421 | MAC_HWF1R_TXFIFOSIZE_POS, |
422 | MAC_HWF1R_TXFIFOSIZE_LEN); |
423 | hw_feat->adv_ts_hi = XLGMAC_GET_REG_BITS(mac_hfr1, |
424 | MAC_HWF1R_ADVTHWORD_POS, |
425 | MAC_HWF1R_ADVTHWORD_LEN); |
426 | hw_feat->dma_width = XLGMAC_GET_REG_BITS(mac_hfr1, |
427 | MAC_HWF1R_ADDR64_POS, |
428 | MAC_HWF1R_ADDR64_LEN); |
429 | hw_feat->dcb = XLGMAC_GET_REG_BITS(mac_hfr1, |
430 | MAC_HWF1R_DCBEN_POS, |
431 | MAC_HWF1R_DCBEN_LEN); |
432 | hw_feat->sph = XLGMAC_GET_REG_BITS(mac_hfr1, |
433 | MAC_HWF1R_SPHEN_POS, |
434 | MAC_HWF1R_SPHEN_LEN); |
435 | hw_feat->tso = XLGMAC_GET_REG_BITS(mac_hfr1, |
436 | MAC_HWF1R_TSOEN_POS, |
437 | MAC_HWF1R_TSOEN_LEN); |
438 | hw_feat->dma_debug = XLGMAC_GET_REG_BITS(mac_hfr1, |
439 | MAC_HWF1R_DBGMEMA_POS, |
440 | MAC_HWF1R_DBGMEMA_LEN); |
441 | hw_feat->rss = XLGMAC_GET_REG_BITS(mac_hfr1, |
442 | MAC_HWF1R_RSSEN_POS, |
443 | MAC_HWF1R_RSSEN_LEN); |
444 | hw_feat->tc_cnt = XLGMAC_GET_REG_BITS(mac_hfr1, |
445 | MAC_HWF1R_NUMTC_POS, |
446 | MAC_HWF1R_NUMTC_LEN); |
447 | hw_feat->hash_table_size = XLGMAC_GET_REG_BITS(mac_hfr1, |
448 | MAC_HWF1R_HASHTBLSZ_POS, |
449 | MAC_HWF1R_HASHTBLSZ_LEN); |
450 | hw_feat->l3l4_filter_num = XLGMAC_GET_REG_BITS(mac_hfr1, |
451 | MAC_HWF1R_L3L4FNUM_POS, |
452 | MAC_HWF1R_L3L4FNUM_LEN); |
453 | |
454 | /* Hardware feature register 2 */ |
455 | hw_feat->rx_q_cnt = XLGMAC_GET_REG_BITS(mac_hfr2, |
456 | MAC_HWF2R_RXQCNT_POS, |
457 | MAC_HWF2R_RXQCNT_LEN); |
458 | hw_feat->tx_q_cnt = XLGMAC_GET_REG_BITS(mac_hfr2, |
459 | MAC_HWF2R_TXQCNT_POS, |
460 | MAC_HWF2R_TXQCNT_LEN); |
461 | hw_feat->rx_ch_cnt = XLGMAC_GET_REG_BITS(mac_hfr2, |
462 | MAC_HWF2R_RXCHCNT_POS, |
463 | MAC_HWF2R_RXCHCNT_LEN); |
464 | hw_feat->tx_ch_cnt = XLGMAC_GET_REG_BITS(mac_hfr2, |
465 | MAC_HWF2R_TXCHCNT_POS, |
466 | MAC_HWF2R_TXCHCNT_LEN); |
467 | hw_feat->pps_out_num = XLGMAC_GET_REG_BITS(mac_hfr2, |
468 | MAC_HWF2R_PPSOUTNUM_POS, |
469 | MAC_HWF2R_PPSOUTNUM_LEN); |
470 | hw_feat->aux_snap_num = XLGMAC_GET_REG_BITS(mac_hfr2, |
471 | MAC_HWF2R_AUXSNAPNUM_POS, |
472 | MAC_HWF2R_AUXSNAPNUM_LEN); |
473 | |
474 | /* Translate the Hash Table size into actual number */ |
475 | switch (hw_feat->hash_table_size) { |
476 | case 0: |
477 | break; |
478 | case 1: |
479 | hw_feat->hash_table_size = 64; |
480 | break; |
481 | case 2: |
482 | hw_feat->hash_table_size = 128; |
483 | break; |
484 | case 3: |
485 | hw_feat->hash_table_size = 256; |
486 | break; |
487 | } |
488 | |
489 | /* Translate the address width setting into actual number */ |
490 | switch (hw_feat->dma_width) { |
491 | case 0: |
492 | hw_feat->dma_width = 32; |
493 | break; |
494 | case 1: |
495 | hw_feat->dma_width = 40; |
496 | break; |
497 | case 2: |
498 | hw_feat->dma_width = 48; |
499 | break; |
500 | default: |
501 | hw_feat->dma_width = 32; |
502 | } |
503 | |
504 | /* The Queue, Channel and TC counts are zero based so increment them |
505 | * to get the actual number |
506 | */ |
507 | hw_feat->rx_q_cnt++; |
508 | hw_feat->tx_q_cnt++; |
509 | hw_feat->rx_ch_cnt++; |
510 | hw_feat->tx_ch_cnt++; |
511 | hw_feat->tc_cnt++; |
512 | } |
513 | |
514 | void xlgmac_print_all_hw_features(struct xlgmac_pdata *pdata) |
515 | { |
516 | char __maybe_unused *str = NULL; |
517 | |
518 | XLGMAC_PR("\n" ); |
519 | XLGMAC_PR("=====================================================\n" ); |
520 | XLGMAC_PR("\n" ); |
521 | XLGMAC_PR("HW support following features\n" ); |
522 | XLGMAC_PR("\n" ); |
523 | /* HW Feature Register0 */ |
524 | XLGMAC_PR("VLAN Hash Filter Selected : %s\n" , |
525 | pdata->hw_feat.vlhash ? "YES" : "NO" ); |
526 | XLGMAC_PR("SMA (MDIO) Interface : %s\n" , |
527 | pdata->hw_feat.sma ? "YES" : "NO" ); |
528 | XLGMAC_PR("PMT Remote Wake-up Packet Enable : %s\n" , |
529 | pdata->hw_feat.rwk ? "YES" : "NO" ); |
530 | XLGMAC_PR("PMT Magic Packet Enable : %s\n" , |
531 | pdata->hw_feat.mgk ? "YES" : "NO" ); |
532 | XLGMAC_PR("RMON/MMC Module Enable : %s\n" , |
533 | pdata->hw_feat.mmc ? "YES" : "NO" ); |
534 | XLGMAC_PR("ARP Offload Enabled : %s\n" , |
535 | pdata->hw_feat.aoe ? "YES" : "NO" ); |
536 | XLGMAC_PR("IEEE 1588-2008 Timestamp Enabled : %s\n" , |
537 | pdata->hw_feat.ts ? "YES" : "NO" ); |
538 | XLGMAC_PR("Energy Efficient Ethernet Enabled : %s\n" , |
539 | pdata->hw_feat.eee ? "YES" : "NO" ); |
540 | XLGMAC_PR("Transmit Checksum Offload Enabled : %s\n" , |
541 | pdata->hw_feat.tx_coe ? "YES" : "NO" ); |
542 | XLGMAC_PR("Receive Checksum Offload Enabled : %s\n" , |
543 | pdata->hw_feat.rx_coe ? "YES" : "NO" ); |
544 | XLGMAC_PR("Additional MAC Addresses 1-31 Selected : %s\n" , |
545 | pdata->hw_feat.addn_mac ? "YES" : "NO" ); |
546 | |
547 | switch (pdata->hw_feat.ts_src) { |
548 | case 0: |
549 | str = "RESERVED" ; |
550 | break; |
551 | case 1: |
552 | str = "INTERNAL" ; |
553 | break; |
554 | case 2: |
555 | str = "EXTERNAL" ; |
556 | break; |
557 | case 3: |
558 | str = "BOTH" ; |
559 | break; |
560 | } |
561 | XLGMAC_PR("Timestamp System Time Source : %s\n" , str); |
562 | |
563 | XLGMAC_PR("Source Address or VLAN Insertion Enable : %s\n" , |
564 | pdata->hw_feat.sa_vlan_ins ? "YES" : "NO" ); |
565 | |
566 | /* HW Feature Register1 */ |
567 | switch (pdata->hw_feat.rx_fifo_size) { |
568 | case 0: |
569 | str = "128 bytes" ; |
570 | break; |
571 | case 1: |
572 | str = "256 bytes" ; |
573 | break; |
574 | case 2: |
575 | str = "512 bytes" ; |
576 | break; |
577 | case 3: |
578 | str = "1 KBytes" ; |
579 | break; |
580 | case 4: |
581 | str = "2 KBytes" ; |
582 | break; |
583 | case 5: |
584 | str = "4 KBytes" ; |
585 | break; |
586 | case 6: |
587 | str = "8 KBytes" ; |
588 | break; |
589 | case 7: |
590 | str = "16 KBytes" ; |
591 | break; |
592 | case 8: |
593 | str = "32 kBytes" ; |
594 | break; |
595 | case 9: |
596 | str = "64 KBytes" ; |
597 | break; |
598 | case 10: |
599 | str = "128 KBytes" ; |
600 | break; |
601 | case 11: |
602 | str = "256 KBytes" ; |
603 | break; |
604 | default: |
605 | str = "RESERVED" ; |
606 | } |
607 | XLGMAC_PR("MTL Receive FIFO Size : %s\n" , str); |
608 | |
609 | switch (pdata->hw_feat.tx_fifo_size) { |
610 | case 0: |
611 | str = "128 bytes" ; |
612 | break; |
613 | case 1: |
614 | str = "256 bytes" ; |
615 | break; |
616 | case 2: |
617 | str = "512 bytes" ; |
618 | break; |
619 | case 3: |
620 | str = "1 KBytes" ; |
621 | break; |
622 | case 4: |
623 | str = "2 KBytes" ; |
624 | break; |
625 | case 5: |
626 | str = "4 KBytes" ; |
627 | break; |
628 | case 6: |
629 | str = "8 KBytes" ; |
630 | break; |
631 | case 7: |
632 | str = "16 KBytes" ; |
633 | break; |
634 | case 8: |
635 | str = "32 kBytes" ; |
636 | break; |
637 | case 9: |
638 | str = "64 KBytes" ; |
639 | break; |
640 | case 10: |
641 | str = "128 KBytes" ; |
642 | break; |
643 | case 11: |
644 | str = "256 KBytes" ; |
645 | break; |
646 | default: |
647 | str = "RESERVED" ; |
648 | } |
649 | XLGMAC_PR("MTL Transmit FIFO Size : %s\n" , str); |
650 | |
651 | XLGMAC_PR("IEEE 1588 High Word Register Enable : %s\n" , |
652 | pdata->hw_feat.adv_ts_hi ? "YES" : "NO" ); |
653 | XLGMAC_PR("Address width : %u\n" , |
654 | pdata->hw_feat.dma_width); |
655 | XLGMAC_PR("DCB Feature Enable : %s\n" , |
656 | pdata->hw_feat.dcb ? "YES" : "NO" ); |
657 | XLGMAC_PR("Split Header Feature Enable : %s\n" , |
658 | pdata->hw_feat.sph ? "YES" : "NO" ); |
659 | XLGMAC_PR("TCP Segmentation Offload Enable : %s\n" , |
660 | pdata->hw_feat.tso ? "YES" : "NO" ); |
661 | XLGMAC_PR("DMA Debug Registers Enabled : %s\n" , |
662 | pdata->hw_feat.dma_debug ? "YES" : "NO" ); |
663 | XLGMAC_PR("RSS Feature Enabled : %s\n" , |
664 | pdata->hw_feat.rss ? "YES" : "NO" ); |
665 | XLGMAC_PR("Number of Traffic classes : %u\n" , |
666 | (pdata->hw_feat.tc_cnt)); |
667 | XLGMAC_PR("Hash Table Size : %u\n" , |
668 | pdata->hw_feat.hash_table_size); |
669 | XLGMAC_PR("Total number of L3 or L4 Filters : %u\n" , |
670 | pdata->hw_feat.l3l4_filter_num); |
671 | |
672 | /* HW Feature Register2 */ |
673 | XLGMAC_PR("Number of MTL Receive Queues : %u\n" , |
674 | pdata->hw_feat.rx_q_cnt); |
675 | XLGMAC_PR("Number of MTL Transmit Queues : %u\n" , |
676 | pdata->hw_feat.tx_q_cnt); |
677 | XLGMAC_PR("Number of DMA Receive Channels : %u\n" , |
678 | pdata->hw_feat.rx_ch_cnt); |
679 | XLGMAC_PR("Number of DMA Transmit Channels : %u\n" , |
680 | pdata->hw_feat.tx_ch_cnt); |
681 | |
682 | switch (pdata->hw_feat.pps_out_num) { |
683 | case 0: |
684 | str = "No PPS output" ; |
685 | break; |
686 | case 1: |
687 | str = "1 PPS output" ; |
688 | break; |
689 | case 2: |
690 | str = "2 PPS output" ; |
691 | break; |
692 | case 3: |
693 | str = "3 PPS output" ; |
694 | break; |
695 | case 4: |
696 | str = "4 PPS output" ; |
697 | break; |
698 | default: |
699 | str = "RESERVED" ; |
700 | } |
701 | XLGMAC_PR("Number of PPS Outputs : %s\n" , str); |
702 | |
703 | switch (pdata->hw_feat.aux_snap_num) { |
704 | case 0: |
705 | str = "No auxiliary input" ; |
706 | break; |
707 | case 1: |
708 | str = "1 auxiliary input" ; |
709 | break; |
710 | case 2: |
711 | str = "2 auxiliary input" ; |
712 | break; |
713 | case 3: |
714 | str = "3 auxiliary input" ; |
715 | break; |
716 | case 4: |
717 | str = "4 auxiliary input" ; |
718 | break; |
719 | default: |
720 | str = "RESERVED" ; |
721 | } |
722 | XLGMAC_PR("Number of Auxiliary Snapshot Inputs : %s" , str); |
723 | |
724 | XLGMAC_PR("\n" ); |
725 | XLGMAC_PR("=====================================================\n" ); |
726 | XLGMAC_PR("\n" ); |
727 | } |
728 | |