1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | #ifndef _RRUNNER_H_ |
3 | #define _RRUNNER_H_ |
4 | |
5 | #include <linux/interrupt.h> |
6 | |
7 | #if ((BITS_PER_LONG != 32) && (BITS_PER_LONG != 64)) |
8 | #error "BITS_PER_LONG not defined or not valid" |
9 | #endif |
10 | |
11 | |
12 | struct rr_regs { |
13 | |
14 | u32 pad0[16]; |
15 | |
16 | u32 HostCtrl; |
17 | u32 LocalCtrl; |
18 | u32 Pc; |
19 | u32 BrkPt; |
20 | |
21 | /* Timer increments every 0.97 micro-seconds (unsigned int) */ |
22 | u32 Timer_Hi; |
23 | u32 Timer; |
24 | u32 TimerRef; |
25 | u32 PciState; |
26 | |
27 | u32 Event; |
28 | u32 MbEvent; |
29 | |
30 | u32 WinBase; |
31 | u32 WinData; |
32 | u32 RX_state; |
33 | u32 TX_state; |
34 | |
35 | u32 Overhead; |
36 | u32 ExtIo; |
37 | |
38 | u32 DmaWriteHostHi; |
39 | u32 DmaWriteHostLo; |
40 | |
41 | u32 pad1[2]; |
42 | |
43 | u32 DmaReadHostHi; |
44 | u32 DmaReadHostLo; |
45 | |
46 | u32 pad2; |
47 | |
48 | u32 DmaReadLen; |
49 | u32 DmaWriteState; |
50 | |
51 | u32 DmaWriteLcl; |
52 | u32 DmaWriteIPchecksum; |
53 | u32 DmaWriteLen; |
54 | u32 DmaReadState; |
55 | u32 DmaReadLcl; |
56 | u32 DmaReadIPchecksum; |
57 | u32 pad3; |
58 | |
59 | u32 RxBase; |
60 | u32 RxPrd; |
61 | u32 RxCon; |
62 | |
63 | u32 pad4; |
64 | |
65 | u32 TxBase; |
66 | u32 TxPrd; |
67 | u32 TxCon; |
68 | |
69 | u32 pad5; |
70 | |
71 | u32 RxIndPro; |
72 | u32 RxIndCon; |
73 | u32 RxIndRef; |
74 | |
75 | u32 pad6; |
76 | |
77 | u32 TxIndPro; |
78 | u32 TxIndCon; |
79 | u32 TxIndRef; |
80 | |
81 | u32 pad7[17]; |
82 | |
83 | u32 DrCmndPro; |
84 | u32 DrCmndCon; |
85 | u32 DrCmndRef; |
86 | |
87 | u32 pad8; |
88 | |
89 | u32 DwCmndPro; |
90 | u32 DwCmndCon; |
91 | u32 DwCmndRef; |
92 | |
93 | u32 AssistState; |
94 | |
95 | u32 DrDataPro; |
96 | u32 DrDataCon; |
97 | u32 DrDataRef; |
98 | |
99 | u32 pad9; |
100 | |
101 | u32 DwDataPro; |
102 | u32 DwDataCon; |
103 | u32 DwDataRef; |
104 | |
105 | u32 pad10[33]; |
106 | |
107 | u32 EvtCon; |
108 | |
109 | u32 pad11[5]; |
110 | |
111 | u32 TxPi; |
112 | u32 IpRxPi; |
113 | |
114 | u32 pad11a[8]; |
115 | |
116 | u32 CmdRing[16]; |
117 | |
118 | /* The ULA is in two registers the high order two bytes of the first |
119 | * word contain the RunCode features. |
120 | * ula0 res res byte0 byte1 |
121 | * ula1 byte2 byte3 byte4 byte5 |
122 | */ |
123 | u32 Ula0; |
124 | u32 Ula1; |
125 | |
126 | u32 RxRingHi; |
127 | u32 RxRingLo; |
128 | |
129 | u32 InfoPtrHi; |
130 | u32 InfoPtrLo; |
131 | |
132 | u32 Mode; |
133 | |
134 | u32 ConRetry; |
135 | u32 ConRetryTmr; |
136 | |
137 | u32 ConTmout; |
138 | u32 CtatTmr; |
139 | |
140 | u32 MaxRxRng; |
141 | |
142 | u32 IntrTmr; |
143 | u32 TxDataMvTimeout; |
144 | u32 RxDataMvTimeout; |
145 | |
146 | u32 EvtPrd; |
147 | u32 TraceIdx; |
148 | |
149 | u32 Fail1; |
150 | u32 Fail2; |
151 | |
152 | u32 DrvPrm; |
153 | |
154 | u32 FilterLA; |
155 | |
156 | u32 FwRev; |
157 | u32 FwRes1; |
158 | u32 FwRes2; |
159 | u32 FwRes3; |
160 | |
161 | u32 WriteDmaThresh; |
162 | u32 ReadDmaThresh; |
163 | |
164 | u32 pad12[325]; |
165 | u32 Window[512]; |
166 | }; |
167 | |
168 | /* |
169 | * Host control register bits. |
170 | */ |
171 | |
172 | #define RR_INT 0x01 |
173 | #define RR_CLEAR_INT 0x02 |
174 | #define NO_SWAP 0x04000004 |
175 | #define NO_SWAP1 0x00000004 |
176 | #define PCI_RESET_NIC 0x08 |
177 | #define HALT_NIC 0x10 |
178 | #define SSTEP_NIC 0x20 |
179 | #define MEM_READ_MULTI 0x40 |
180 | #define NIC_HALTED 0x100 |
181 | #define HALT_INST 0x200 |
182 | #define PARITY_ERR 0x400 |
183 | #define INVALID_INST_B 0x800 |
184 | #define RR_REV_2 0x20000000 |
185 | #define RR_REV_MASK 0xf0000000 |
186 | |
187 | /* |
188 | * Local control register bits. |
189 | */ |
190 | |
191 | #define INTA_STATE 0x01 |
192 | #define CLEAR_INTA 0x02 |
193 | #define FAST_EEPROM_ACCESS 0x08 |
194 | #define 0x100 |
195 | #define 0x200 |
196 | #define ENABLE_PARITY 0x400 |
197 | #define FORCE_DMA_PARITY_ERROR 0x800 |
198 | #define ENABLE_EEPROM_WRITE 0x1000 |
199 | #define ENABLE_DATA_CACHE 0x2000 |
200 | #define SRAM_LO_PARITY_ERR 0x4000 |
201 | #define SRAM_HI_PARITY_ERR 0x8000 |
202 | |
203 | /* |
204 | * PCI state bits. |
205 | */ |
206 | |
207 | #define FORCE_PCI_RESET 0x01 |
208 | #define PROVIDE_LENGTH 0x02 |
209 | #define MASK_DMA_READ_MAX 0x1C |
210 | #define RBURST_DISABLE 0x00 |
211 | #define RBURST_4 0x04 |
212 | #define RBURST_16 0x08 |
213 | #define RBURST_32 0x0C |
214 | #define RBURST_64 0x10 |
215 | #define RBURST_128 0x14 |
216 | #define RBURST_256 0x18 |
217 | #define RBURST_1024 0x1C |
218 | #define MASK_DMA_WRITE_MAX 0xE0 |
219 | #define WBURST_DISABLE 0x00 |
220 | #define WBURST_4 0x20 |
221 | #define WBURST_16 0x40 |
222 | #define WBURST_32 0x60 |
223 | #define WBURST_64 0x80 |
224 | #define WBURST_128 0xa0 |
225 | #define WBURST_256 0xc0 |
226 | #define WBURST_1024 0xe0 |
227 | #define MASK_MIN_DMA 0xFF00 |
228 | #define FIFO_RETRY_ENABLE 0x10000 |
229 | |
230 | /* |
231 | * Event register |
232 | */ |
233 | |
234 | #define DMA_WRITE_DONE 0x10000 |
235 | #define DMA_READ_DONE 0x20000 |
236 | #define DMA_WRITE_ERR 0x40000 |
237 | #define DMA_READ_ERR 0x80000 |
238 | |
239 | /* |
240 | * Receive state |
241 | * |
242 | * RoadRunner HIPPI Receive State Register controls and monitors the |
243 | * HIPPI receive interface in the NIC. Look at err bits when a HIPPI |
244 | * receive Error Event occurs. |
245 | */ |
246 | |
247 | #define ENABLE_NEW_CON 0x01 |
248 | #define RESET_RECV 0x02 |
249 | #define RECV_ALL 0x00 |
250 | #define RECV_1K 0x20 |
251 | #define RECV_2K 0x40 |
252 | #define RECV_4K 0x60 |
253 | #define RECV_8K 0x80 |
254 | #define RECV_16K 0xa0 |
255 | #define RECV_32K 0xc0 |
256 | #define RECV_64K 0xe0 |
257 | |
258 | /* |
259 | * Transmit status. |
260 | */ |
261 | |
262 | #define ENA_XMIT 0x01 |
263 | #define PERM_CON 0x02 |
264 | |
265 | /* |
266 | * DMA write state |
267 | */ |
268 | |
269 | #define RESET_DMA 0x01 |
270 | #define NO_SWAP_DMA 0x02 |
271 | #define DMA_ACTIVE 0x04 |
272 | #define THRESH_MASK 0x1F |
273 | #define DMA_ERROR_MASK 0xff000000 |
274 | |
275 | /* |
276 | * Gooddies stored in the ULA registers. |
277 | */ |
278 | |
279 | #define TRACE_ON_WHAT_BIT 0x00020000 /* Traces on */ |
280 | #define ONEM_BUF_WHAT_BIT 0x00040000 /* 1Meg vs 256K */ |
281 | #define CHAR_API_WHAT_BIT 0x00080000 /* Char API vs network only */ |
282 | #define CMD_EVT_WHAT_BIT 0x00200000 /* Command event */ |
283 | #define LONG_TX_WHAT_BIT 0x00400000 |
284 | #define LONG_RX_WHAT_BIT 0x00800000 |
285 | #define WHAT_BIT_MASK 0xFFFD0000 /* Feature bit mask */ |
286 | |
287 | /* |
288 | * Mode status |
289 | */ |
290 | |
291 | #define EVENT_OVFL 0x80000000 |
292 | #define FATAL_ERR 0x40000000 |
293 | #define LOOP_BACK 0x01 |
294 | #define MODE_PH 0x02 |
295 | #define MODE_FP 0x00 |
296 | #define PTR64BIT 0x04 |
297 | #define PTR32BIT 0x00 |
298 | #define PTR_WD_SWAP 0x08 |
299 | #define PTR_WD_NOSWAP 0x00 |
300 | #define POST_WARN_EVENT 0x10 |
301 | #define ERR_TERM 0x20 |
302 | #define DIRECT_CONN 0x40 |
303 | #define NO_NIC_WATCHDOG 0x80 |
304 | #define SWAP_DATA 0x100 |
305 | #define SWAP_CONTROL 0x200 |
306 | #define NIC_HALT_ON_ERR 0x400 |
307 | #define NIC_NO_RESTART 0x800 |
308 | #define HALF_DUP_TX 0x1000 |
309 | #define HALF_DUP_RX 0x2000 |
310 | |
311 | |
312 | /* |
313 | * Error codes |
314 | */ |
315 | |
316 | /* Host Error Codes - values of fail1 */ |
317 | #define ERR_UNKNOWN_MBOX 0x1001 |
318 | #define ERR_UNKNOWN_CMD 0x1002 |
319 | #define ERR_MAX_RING 0x1003 |
320 | #define ERR_RING_CLOSED 0x1004 |
321 | #define ERR_RING_OPEN 0x1005 |
322 | /* Firmware internal errors */ |
323 | #define ERR_EVENT_RING_FULL 0x01 |
324 | #define ERR_DW_PEND_CMND_FULL 0x02 |
325 | #define ERR_DR_PEND_CMND_FULL 0x03 |
326 | #define ERR_DW_PEND_DATA_FULL 0x04 |
327 | #define ERR_DR_PEND_DATA_FULL 0x05 |
328 | #define ERR_ILLEGAL_JUMP 0x06 |
329 | #define ERR_UNIMPLEMENTED 0x07 |
330 | #define ERR_TX_INFO_FULL 0x08 |
331 | #define ERR_RX_INFO_FULL 0x09 |
332 | #define ERR_ILLEGAL_MODE 0x0A |
333 | #define ERR_MAIN_TIMEOUT 0x0B |
334 | #define ERR_EVENT_BITS 0x0C |
335 | #define ERR_UNPEND_FULL 0x0D |
336 | #define ERR_TIMER_QUEUE_FULL 0x0E |
337 | #define ERR_TIMER_QUEUE_EMPTY 0x0F |
338 | #define ERR_TIMER_NO_FREE 0x10 |
339 | #define ERR_INTR_START 0x11 |
340 | #define ERR_BAD_STARTUP 0x12 |
341 | #define ERR_NO_PKT_END 0x13 |
342 | #define ERR_HALTED_ON_ERR 0x14 |
343 | /* Hardware NIC Errors */ |
344 | #define ERR_WRITE_DMA 0x0101 |
345 | #define ERR_READ_DMA 0x0102 |
346 | #define ERR_EXT_SERIAL 0x0103 |
347 | #define ERR_TX_INT_PARITY 0x0104 |
348 | |
349 | |
350 | /* |
351 | * Event definitions |
352 | */ |
353 | |
354 | #define EVT_RING_ENTRIES 64 |
355 | #define EVT_RING_SIZE (EVT_RING_ENTRIES * sizeof(struct event)) |
356 | |
357 | struct event { |
358 | #ifdef __LITTLE_ENDIAN |
359 | u16 index; |
360 | u8 ring; |
361 | u8 code; |
362 | #else |
363 | u8 code; |
364 | u8 ring; |
365 | u16 index; |
366 | #endif |
367 | u32 timestamp; |
368 | }; |
369 | |
370 | /* |
371 | * General Events |
372 | */ |
373 | |
374 | #define E_NIC_UP 0x01 |
375 | #define E_WATCHDOG 0x02 |
376 | |
377 | #define E_STAT_UPD 0x04 |
378 | #define E_INVAL_CMD 0x05 |
379 | #define E_SET_CMD_CONS 0x06 |
380 | #define E_LINK_ON 0x07 |
381 | #define E_LINK_OFF 0x08 |
382 | #define E_INTERN_ERR 0x09 |
383 | #define E_HOST_ERR 0x0A |
384 | #define E_STATS_UPDATE 0x0B |
385 | #define E_REJECTING 0x0C |
386 | |
387 | /* |
388 | * Send Events |
389 | */ |
390 | #define E_CON_REJ 0x13 |
391 | #define E_CON_TMOUT 0x14 |
392 | #define E_CON_NC_TMOUT 0x15 /* I , Connection No Campon Timeout */ |
393 | #define E_DISC_ERR 0x16 |
394 | #define E_INT_PRTY 0x17 |
395 | #define E_TX_IDLE 0x18 |
396 | #define E_TX_LINK_DROP 0x19 |
397 | #define E_TX_INV_RNG 0x1A |
398 | #define E_TX_INV_BUF 0x1B |
399 | #define E_TX_INV_DSC 0x1C |
400 | |
401 | /* |
402 | * Destination Events |
403 | */ |
404 | /* |
405 | * General Receive events |
406 | */ |
407 | #define E_VAL_RNG 0x20 |
408 | #define E_RX_RNG_ENER 0x21 |
409 | #define E_INV_RNG 0x22 |
410 | #define E_RX_RNG_SPC 0x23 |
411 | #define E_RX_RNG_OUT 0x24 |
412 | #define E_PKT_DISCARD 0x25 |
413 | #define E_INFO_EVT 0x27 |
414 | |
415 | /* |
416 | * Data corrupted events |
417 | */ |
418 | #define E_RX_PAR_ERR 0x2B |
419 | #define E_RX_LLRC_ERR 0x2C |
420 | #define E_IP_CKSM_ERR 0x2D |
421 | #define E_DTA_CKSM_ERR 0x2E |
422 | #define E_SHT_BST 0x2F |
423 | |
424 | /* |
425 | * Data lost events |
426 | */ |
427 | #define E_LST_LNK_ERR 0x30 |
428 | #define E_FLG_SYN_ERR 0x31 |
429 | #define E_FRM_ERR 0x32 |
430 | #define E_RX_IDLE 0x33 |
431 | #define E_PKT_LN_ERR 0x34 |
432 | #define E_STATE_ERR 0x35 |
433 | #define E_UNEXP_DATA 0x3C |
434 | |
435 | /* |
436 | * Fatal events |
437 | */ |
438 | #define E_RX_INV_BUF 0x36 |
439 | #define E_RX_INV_DSC 0x37 |
440 | #define E_RNG_BLK 0x38 |
441 | |
442 | /* |
443 | * Warning events |
444 | */ |
445 | #define E_RX_TO 0x39 |
446 | #define E_BFR_SPC 0x3A |
447 | #define E_INV_ULP 0x3B |
448 | |
449 | #define E_NOT_IMPLEMENTED 0x40 |
450 | |
451 | |
452 | /* |
453 | * Commands |
454 | */ |
455 | |
456 | #define CMD_RING_ENTRIES 16 |
457 | |
458 | struct cmd { |
459 | #ifdef __LITTLE_ENDIAN |
460 | u16 index; |
461 | u8 ring; |
462 | u8 code; |
463 | #else |
464 | u8 code; |
465 | u8 ring; |
466 | u16 index; |
467 | #endif |
468 | }; |
469 | |
470 | #define C_START_FW 0x01 |
471 | #define C_UPD_STAT 0x02 |
472 | #define C_WATCHDOG 0x05 |
473 | #define C_DEL_RNG 0x09 |
474 | #define C_NEW_RNG 0x0A |
475 | #define C_CONN 0x0D |
476 | |
477 | |
478 | /* |
479 | * Mode bits |
480 | */ |
481 | |
482 | #define PACKET_BAD 0x01 /* Packet had link-layer error */ |
483 | #define INTERRUPT 0x02 |
484 | #define TX_IP_CKSUM 0x04 |
485 | #define PACKET_END 0x08 |
486 | #define PACKET_START 0x10 |
487 | #define SAME_IFIELD 0x80 |
488 | |
489 | |
490 | typedef struct { |
491 | #if (BITS_PER_LONG == 64) |
492 | u64 addrlo; |
493 | #else |
494 | u32 addrhi; |
495 | u32 addrlo; |
496 | #endif |
497 | } rraddr; |
498 | |
499 | |
500 | static inline void set_rraddr(rraddr *ra, dma_addr_t addr) |
501 | { |
502 | unsigned long baddr = addr; |
503 | #if (BITS_PER_LONG == 64) |
504 | ra->addrlo = baddr; |
505 | #else |
506 | /* Don't bother setting zero every time */ |
507 | ra->addrlo = baddr; |
508 | #endif |
509 | mb(); |
510 | } |
511 | |
512 | |
513 | static inline void set_rxaddr(struct rr_regs __iomem *regs, volatile dma_addr_t addr) |
514 | { |
515 | unsigned long baddr = addr; |
516 | #if (BITS_PER_LONG == 64) && defined(__LITTLE_ENDIAN) |
517 | writel(val: baddr & 0xffffffff, addr: ®s->RxRingHi); |
518 | writel(val: baddr >> 32, addr: ®s->RxRingLo); |
519 | #elif (BITS_PER_LONG == 64) |
520 | writel(baddr >> 32, ®s->RxRingHi); |
521 | writel(baddr & 0xffffffff, ®s->RxRingLo); |
522 | #else |
523 | writel(0, ®s->RxRingHi); |
524 | writel(baddr, ®s->RxRingLo); |
525 | #endif |
526 | mb(); |
527 | } |
528 | |
529 | |
530 | static inline void set_infoaddr(struct rr_regs __iomem *regs, volatile dma_addr_t addr) |
531 | { |
532 | unsigned long baddr = addr; |
533 | #if (BITS_PER_LONG == 64) && defined(__LITTLE_ENDIAN) |
534 | writel(val: baddr & 0xffffffff, addr: ®s->InfoPtrHi); |
535 | writel(val: baddr >> 32, addr: ®s->InfoPtrLo); |
536 | #elif (BITS_PER_LONG == 64) |
537 | writel(baddr >> 32, ®s->InfoPtrHi); |
538 | writel(baddr & 0xffffffff, ®s->InfoPtrLo); |
539 | #else |
540 | writel(0, ®s->InfoPtrHi); |
541 | writel(baddr, ®s->InfoPtrLo); |
542 | #endif |
543 | mb(); |
544 | } |
545 | |
546 | |
547 | /* |
548 | * TX ring |
549 | */ |
550 | |
551 | #ifdef CONFIG_ROADRUNNER_LARGE_RINGS |
552 | #define TX_RING_ENTRIES 32 |
553 | #else |
554 | #define TX_RING_ENTRIES 16 |
555 | #endif |
556 | #define TX_TOTAL_SIZE (TX_RING_ENTRIES * sizeof(struct tx_desc)) |
557 | |
558 | struct tx_desc{ |
559 | rraddr addr; |
560 | u32 res; |
561 | #ifdef __LITTLE_ENDIAN |
562 | u16 size; |
563 | u8 pad; |
564 | u8 mode; |
565 | #else |
566 | u8 mode; |
567 | u8 pad; |
568 | u16 size; |
569 | #endif |
570 | }; |
571 | |
572 | |
573 | #ifdef CONFIG_ROADRUNNER_LARGE_RINGS |
574 | #define RX_RING_ENTRIES 32 |
575 | #else |
576 | #define RX_RING_ENTRIES 16 |
577 | #endif |
578 | #define RX_TOTAL_SIZE (RX_RING_ENTRIES * sizeof(struct rx_desc)) |
579 | |
580 | struct rx_desc{ |
581 | rraddr addr; |
582 | u32 res; |
583 | #ifdef __LITTLE_ENDIAN |
584 | u16 size; |
585 | u8 pad; |
586 | u8 mode; |
587 | #else |
588 | u8 mode; |
589 | u8 pad; |
590 | u16 size; |
591 | #endif |
592 | }; |
593 | |
594 | |
595 | /* |
596 | * ioctl's |
597 | */ |
598 | |
599 | #define SIOCRRPFW SIOCDEVPRIVATE /* put firmware */ |
600 | #define SIOCRRGFW SIOCDEVPRIVATE+1 /* get firmware */ |
601 | #define SIOCRRID SIOCDEVPRIVATE+2 /* identify */ |
602 | |
603 | |
604 | struct seg_hdr { |
605 | u32 seg_start; |
606 | u32 seg_len; |
607 | u32 seg_eestart; |
608 | }; |
609 | |
610 | |
611 | #define EEPROM_BASE 0x80000000 |
612 | #define EEPROM_WORDS 8192 |
613 | #define EEPROM_BYTES (EEPROM_WORDS * sizeof(u32)) |
614 | |
615 | struct eeprom_boot { |
616 | u32 key1; |
617 | u32 key2; |
618 | u32 sram_size; |
619 | struct seg_hdr loader; |
620 | u32 init_chksum; |
621 | u32 reserved1; |
622 | }; |
623 | |
624 | struct eeprom_manf { |
625 | u32 ; |
626 | u32 Firmware; |
627 | u32 BoardRevision; |
628 | u32 RoadrunnerRev; |
629 | char OpticsPart[8]; |
630 | u32 OpticsRev; |
631 | u32 pad1; |
632 | char SramPart[8]; |
633 | u32 SramRev; |
634 | u32 pad2; |
635 | char EepromPart[8]; |
636 | u32 EepromRev; |
637 | u32 EepromSize; |
638 | char PalPart[8]; |
639 | u32 PalRev; |
640 | u32 pad3; |
641 | char PalCodeFile[12]; |
642 | u32 PalCodeRev; |
643 | char BoardULA[8]; |
644 | char SerialNo[8]; |
645 | char MfgDate[8]; |
646 | char MfgTime[8]; |
647 | char ModifyDate[8]; |
648 | u32 ModCount; |
649 | u32 pad4[13]; |
650 | }; |
651 | |
652 | |
653 | struct eeprom_phase_info { |
654 | char phase1File[12]; |
655 | u32 phase1Rev; |
656 | char phase1Date[8]; |
657 | char phase2File[12]; |
658 | u32 phase2Rev; |
659 | char phase2Date[8]; |
660 | u32 reserved7[4]; |
661 | }; |
662 | |
663 | struct eeprom_rncd_info { |
664 | u32 FwStart; |
665 | u32 FwRev; |
666 | char FwDate[8]; |
667 | u32 AddrRunCodeSegs; |
668 | u32 FileNames; |
669 | char File[13][8]; |
670 | }; |
671 | |
672 | |
673 | /* Phase 1 region (starts are word offset 0x80) */ |
674 | struct phase1_hdr{ |
675 | u32 jump; |
676 | u32 noop; |
677 | struct seg_hdr phase2Seg; |
678 | }; |
679 | |
680 | struct eeprom { |
681 | struct eeprom_boot boot; |
682 | u32 pad1[8]; |
683 | struct eeprom_manf manf; |
684 | struct eeprom_phase_info phase_info; |
685 | struct eeprom_rncd_info rncd_info; |
686 | u32 pad2[15]; |
687 | u32 hdr_checksum; |
688 | struct phase1_hdr phase1; |
689 | }; |
690 | |
691 | |
692 | struct rr_stats { |
693 | u32 NicTimeStamp; |
694 | u32 RngCreated; |
695 | u32 RngDeleted; |
696 | u32 IntrGen; |
697 | u32 NEvtOvfl; |
698 | u32 InvCmd; |
699 | u32 DmaReadErrs; |
700 | u32 DmaWriteErrs; |
701 | u32 StatUpdtT; |
702 | u32 StatUpdtC; |
703 | u32 WatchDog; |
704 | u32 Trace; |
705 | |
706 | /* Serial HIPPI */ |
707 | u32 LnkRdyEst; |
708 | u32 GLinkErr; |
709 | u32 AltFlgErr; |
710 | u32 OvhdBit8Sync; |
711 | u32 RmtSerPrtyErr; |
712 | u32 RmtParPrtyErr; |
713 | u32 RmtLoopBk; |
714 | u32 pad1; |
715 | |
716 | /* HIPPI tx */ |
717 | u32 ConEst; |
718 | u32 ConRejS; |
719 | u32 ConRetry; |
720 | u32 ConTmOut; |
721 | u32 SndConDiscon; |
722 | u32 SndParErr; |
723 | u32 PktSnt; |
724 | u32 pad2[2]; |
725 | u32 ShFBstSnt; |
726 | u64 BytSent; |
727 | u32 TxTimeout; |
728 | u32 pad3[3]; |
729 | |
730 | /* HIPPI rx */ |
731 | u32 ConAcc; |
732 | u32 ConRejdiPrty; |
733 | u32 ConRejd64b; |
734 | u32 ConRejdBuf; |
735 | u32 RxConDiscon; |
736 | u32 RxConNoData; |
737 | u32 PktRx; |
738 | u32 pad4[2]; |
739 | u32 ShFBstRx; |
740 | u64 BytRx; |
741 | u32 RxParErr; |
742 | u32 RxLLRCerr; |
743 | u32 RxBstSZerr; |
744 | u32 RxStateErr; |
745 | u32 RxRdyErr; |
746 | u32 RxInvULP; |
747 | u32 RxSpcBuf; |
748 | u32 RxSpcDesc; |
749 | u32 RxRngSpc; |
750 | u32 RxRngFull; |
751 | u32 RxPktLenErr; |
752 | u32 RxCksmErr; |
753 | u32 RxPktDrp; |
754 | u32 RngLowSpc; |
755 | u32 RngDataClose; |
756 | u32 RxTimeout; |
757 | u32 RxIdle; |
758 | }; |
759 | |
760 | |
761 | /* |
762 | * This struct is shared with the NIC firmware. |
763 | */ |
764 | struct ring_ctrl { |
765 | rraddr rngptr; |
766 | #ifdef __LITTLE_ENDIAN |
767 | u16 entries; |
768 | u8 pad; |
769 | u8 entry_size; |
770 | u16 pi; |
771 | u16 mode; |
772 | #else |
773 | u8 entry_size; |
774 | u8 pad; |
775 | u16 entries; |
776 | u16 mode; |
777 | u16 pi; |
778 | #endif |
779 | }; |
780 | |
781 | struct rr_info { |
782 | union { |
783 | struct rr_stats stats; |
784 | u32 stati[128]; |
785 | } s; |
786 | struct ring_ctrl evt_ctrl; |
787 | struct ring_ctrl cmd_ctrl; |
788 | struct ring_ctrl tx_ctrl; |
789 | u8 pad[464]; |
790 | u8 trace[3072]; |
791 | }; |
792 | |
793 | /* |
794 | * The linux structure for the RoadRunner. |
795 | * |
796 | * RX/TX descriptors are put first to make sure they are properly |
797 | * aligned and do not cross cache-line boundaries. |
798 | */ |
799 | |
800 | struct rr_private |
801 | { |
802 | struct rx_desc *rx_ring; |
803 | struct tx_desc *tx_ring; |
804 | struct event *evt_ring; |
805 | dma_addr_t tx_ring_dma; |
806 | dma_addr_t rx_ring_dma; |
807 | dma_addr_t evt_ring_dma; |
808 | /* Alignment ok ? */ |
809 | struct sk_buff *rx_skbuff[RX_RING_ENTRIES]; |
810 | struct sk_buff *tx_skbuff[TX_RING_ENTRIES]; |
811 | struct rr_regs __iomem *regs; /* Register base */ |
812 | struct ring_ctrl *rx_ctrl; /* Receive ring control */ |
813 | struct rr_info *info; /* Shared info page */ |
814 | dma_addr_t rx_ctrl_dma; |
815 | dma_addr_t info_dma; |
816 | spinlock_t lock; |
817 | struct timer_list timer; |
818 | u32 cur_rx, cur_cmd, cur_evt; |
819 | u32 dirty_rx, dirty_tx; |
820 | u32 tx_full; |
821 | u32 fw_rev; |
822 | volatile short fw_running; |
823 | struct pci_dev *pci_dev; |
824 | }; |
825 | |
826 | |
827 | /* |
828 | * Prototypes |
829 | */ |
830 | static int rr_init(struct net_device *dev); |
831 | static int rr_init1(struct net_device *dev); |
832 | static irqreturn_t rr_interrupt(int irq, void *dev_id); |
833 | |
834 | static int rr_open(struct net_device *dev); |
835 | static netdev_tx_t rr_start_xmit(struct sk_buff *skb, |
836 | struct net_device *dev); |
837 | static int rr_close(struct net_device *dev); |
838 | static int rr_siocdevprivate(struct net_device *dev, struct ifreq *rq, |
839 | void __user *data, int cmd); |
840 | static unsigned int rr_read_eeprom(struct rr_private *rrpriv, |
841 | unsigned long offset, |
842 | unsigned char *buf, |
843 | unsigned long length); |
844 | static u32 rr_read_eeprom_word(struct rr_private *rrpriv, size_t offset); |
845 | static int rr_load_firmware(struct net_device *dev); |
846 | static inline void rr_raz_tx(struct rr_private *, struct net_device *); |
847 | static inline void rr_raz_rx(struct rr_private *, struct net_device *); |
848 | #endif /* _RRUNNER_H_ */ |
849 | |