1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * drivers/net/phy/at803x.c
4 *
5 * Driver for Qualcomm Atheros AR803x PHY
6 *
7 * Author: Matus Ujhelyi <ujhelyi.m@gmail.com>
8 */
9
10#include <linux/phy.h>
11#include <linux/module.h>
12#include <linux/string.h>
13#include <linux/netdevice.h>
14#include <linux/etherdevice.h>
15#include <linux/ethtool_netlink.h>
16#include <linux/bitfield.h>
17#include <linux/regulator/of_regulator.h>
18#include <linux/regulator/driver.h>
19#include <linux/regulator/consumer.h>
20#include <linux/of.h>
21#include <linux/phylink.h>
22#include <linux/sfp.h>
23#include <dt-bindings/net/qca-ar803x.h>
24
25#define AT803X_SPECIFIC_FUNCTION_CONTROL 0x10
26#define AT803X_SFC_ASSERT_CRS BIT(11)
27#define AT803X_SFC_FORCE_LINK BIT(10)
28#define AT803X_SFC_MDI_CROSSOVER_MODE_M GENMASK(6, 5)
29#define AT803X_SFC_AUTOMATIC_CROSSOVER 0x3
30#define AT803X_SFC_MANUAL_MDIX 0x1
31#define AT803X_SFC_MANUAL_MDI 0x0
32#define AT803X_SFC_SQE_TEST BIT(2)
33#define AT803X_SFC_POLARITY_REVERSAL BIT(1)
34#define AT803X_SFC_DISABLE_JABBER BIT(0)
35
36#define AT803X_SPECIFIC_STATUS 0x11
37#define AT803X_SS_SPEED_MASK GENMASK(15, 14)
38#define AT803X_SS_SPEED_1000 2
39#define AT803X_SS_SPEED_100 1
40#define AT803X_SS_SPEED_10 0
41#define AT803X_SS_DUPLEX BIT(13)
42#define AT803X_SS_SPEED_DUPLEX_RESOLVED BIT(11)
43#define AT803X_SS_MDIX BIT(6)
44
45#define QCA808X_SS_SPEED_MASK GENMASK(9, 7)
46#define QCA808X_SS_SPEED_2500 4
47
48#define AT803X_INTR_ENABLE 0x12
49#define AT803X_INTR_ENABLE_AUTONEG_ERR BIT(15)
50#define AT803X_INTR_ENABLE_SPEED_CHANGED BIT(14)
51#define AT803X_INTR_ENABLE_DUPLEX_CHANGED BIT(13)
52#define AT803X_INTR_ENABLE_PAGE_RECEIVED BIT(12)
53#define AT803X_INTR_ENABLE_LINK_FAIL BIT(11)
54#define AT803X_INTR_ENABLE_LINK_SUCCESS BIT(10)
55#define AT803X_INTR_ENABLE_LINK_FAIL_BX BIT(8)
56#define AT803X_INTR_ENABLE_LINK_SUCCESS_BX BIT(7)
57#define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE BIT(5)
58#define AT803X_INTR_ENABLE_POLARITY_CHANGED BIT(1)
59#define AT803X_INTR_ENABLE_WOL BIT(0)
60
61#define AT803X_INTR_STATUS 0x13
62
63#define AT803X_SMART_SPEED 0x14
64#define AT803X_SMART_SPEED_ENABLE BIT(5)
65#define AT803X_SMART_SPEED_RETRY_LIMIT_MASK GENMASK(4, 2)
66#define AT803X_SMART_SPEED_BYPASS_TIMER BIT(1)
67#define AT803X_CDT 0x16
68#define AT803X_CDT_MDI_PAIR_MASK GENMASK(9, 8)
69#define AT803X_CDT_ENABLE_TEST BIT(0)
70#define AT803X_CDT_STATUS 0x1c
71#define AT803X_CDT_STATUS_STAT_NORMAL 0
72#define AT803X_CDT_STATUS_STAT_SHORT 1
73#define AT803X_CDT_STATUS_STAT_OPEN 2
74#define AT803X_CDT_STATUS_STAT_FAIL 3
75#define AT803X_CDT_STATUS_STAT_MASK GENMASK(9, 8)
76#define AT803X_CDT_STATUS_DELTA_TIME_MASK GENMASK(7, 0)
77#define AT803X_LED_CONTROL 0x18
78
79#define AT803X_PHY_MMD3_WOL_CTRL 0x8012
80#define AT803X_WOL_EN BIT(5)
81#define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C
82#define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B
83#define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A
84#define AT803X_REG_CHIP_CONFIG 0x1f
85#define AT803X_BT_BX_REG_SEL 0x8000
86
87#define AT803X_DEBUG_ADDR 0x1D
88#define AT803X_DEBUG_DATA 0x1E
89
90#define AT803X_MODE_CFG_MASK 0x0F
91#define AT803X_MODE_CFG_BASET_RGMII 0x00
92#define AT803X_MODE_CFG_BASET_SGMII 0x01
93#define AT803X_MODE_CFG_BX1000_RGMII_50OHM 0x02
94#define AT803X_MODE_CFG_BX1000_RGMII_75OHM 0x03
95#define AT803X_MODE_CFG_BX1000_CONV_50OHM 0x04
96#define AT803X_MODE_CFG_BX1000_CONV_75OHM 0x05
97#define AT803X_MODE_CFG_FX100_RGMII_50OHM 0x06
98#define AT803X_MODE_CFG_FX100_CONV_50OHM 0x07
99#define AT803X_MODE_CFG_RGMII_AUTO_MDET 0x0B
100#define AT803X_MODE_CFG_FX100_RGMII_75OHM 0x0E
101#define AT803X_MODE_CFG_FX100_CONV_75OHM 0x0F
102
103#define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/
104#define AT803X_PSSR_MR_AN_COMPLETE 0x0200
105
106#define AT803X_DEBUG_ANALOG_TEST_CTRL 0x00
107#define QCA8327_DEBUG_MANU_CTRL_EN BIT(2)
108#define QCA8337_DEBUG_MANU_CTRL_EN GENMASK(3, 2)
109#define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15)
110
111#define AT803X_DEBUG_SYSTEM_CTRL_MODE 0x05
112#define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8)
113
114#define AT803X_DEBUG_REG_HIB_CTRL 0x0b
115#define AT803X_DEBUG_HIB_CTRL_SEL_RST_80U BIT(10)
116#define AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE BIT(13)
117#define AT803X_DEBUG_HIB_CTRL_PS_HIB_EN BIT(15)
118
119#define AT803X_DEBUG_REG_3C 0x3C
120
121#define AT803X_DEBUG_REG_GREEN 0x3D
122#define AT803X_DEBUG_GATE_CLK_IN1000 BIT(6)
123
124#define AT803X_DEBUG_REG_1F 0x1F
125#define AT803X_DEBUG_PLL_ON BIT(2)
126#define AT803X_DEBUG_RGMII_1V8 BIT(3)
127
128#define MDIO_AZ_DEBUG 0x800D
129
130/* AT803x supports either the XTAL input pad, an internal PLL or the
131 * DSP as clock reference for the clock output pad. The XTAL reference
132 * is only used for 25 MHz output, all other frequencies need the PLL.
133 * The DSP as a clock reference is used in synchronous ethernet
134 * applications.
135 *
136 * By default the PLL is only enabled if there is a link. Otherwise
137 * the PHY will go into low power state and disabled the PLL. You can
138 * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always
139 * enabled.
140 */
141#define AT803X_MMD7_CLK25M 0x8016
142#define AT803X_CLK_OUT_MASK GENMASK(4, 2)
143#define AT803X_CLK_OUT_25MHZ_XTAL 0
144#define AT803X_CLK_OUT_25MHZ_DSP 1
145#define AT803X_CLK_OUT_50MHZ_PLL 2
146#define AT803X_CLK_OUT_50MHZ_DSP 3
147#define AT803X_CLK_OUT_62_5MHZ_PLL 4
148#define AT803X_CLK_OUT_62_5MHZ_DSP 5
149#define AT803X_CLK_OUT_125MHZ_PLL 6
150#define AT803X_CLK_OUT_125MHZ_DSP 7
151
152/* The AR8035 has another mask which is compatible with the AR8031/AR8033 mask
153 * but doesn't support choosing between XTAL/PLL and DSP.
154 */
155#define AT8035_CLK_OUT_MASK GENMASK(4, 3)
156
157#define AT803X_CLK_OUT_STRENGTH_MASK GENMASK(8, 7)
158#define AT803X_CLK_OUT_STRENGTH_FULL 0
159#define AT803X_CLK_OUT_STRENGTH_HALF 1
160#define AT803X_CLK_OUT_STRENGTH_QUARTER 2
161
162#define AT803X_DEFAULT_DOWNSHIFT 5
163#define AT803X_MIN_DOWNSHIFT 2
164#define AT803X_MAX_DOWNSHIFT 9
165
166#define AT803X_MMD3_SMARTEEE_CTL1 0x805b
167#define AT803X_MMD3_SMARTEEE_CTL2 0x805c
168#define AT803X_MMD3_SMARTEEE_CTL3 0x805d
169#define AT803X_MMD3_SMARTEEE_CTL3_LPI_EN BIT(8)
170
171#define ATH9331_PHY_ID 0x004dd041
172#define ATH8030_PHY_ID 0x004dd076
173#define ATH8031_PHY_ID 0x004dd074
174#define ATH8032_PHY_ID 0x004dd023
175#define ATH8035_PHY_ID 0x004dd072
176#define AT8030_PHY_ID_MASK 0xffffffef
177
178#define QCA8081_PHY_ID 0x004dd101
179
180#define QCA8327_A_PHY_ID 0x004dd033
181#define QCA8327_B_PHY_ID 0x004dd034
182#define QCA8337_PHY_ID 0x004dd036
183#define QCA9561_PHY_ID 0x004dd042
184#define QCA8K_PHY_ID_MASK 0xffffffff
185
186#define QCA8K_DEVFLAGS_REVISION_MASK GENMASK(2, 0)
187
188#define AT803X_PAGE_FIBER 0
189#define AT803X_PAGE_COPPER 1
190
191/* don't turn off internal PLL */
192#define AT803X_KEEP_PLL_ENABLED BIT(0)
193#define AT803X_DISABLE_SMARTEEE BIT(1)
194
195/* disable hibernation mode */
196#define AT803X_DISABLE_HIBERNATION_MODE BIT(2)
197
198/* ADC threshold */
199#define QCA808X_PHY_DEBUG_ADC_THRESHOLD 0x2c80
200#define QCA808X_ADC_THRESHOLD_MASK GENMASK(7, 0)
201#define QCA808X_ADC_THRESHOLD_80MV 0
202#define QCA808X_ADC_THRESHOLD_100MV 0xf0
203#define QCA808X_ADC_THRESHOLD_200MV 0x0f
204#define QCA808X_ADC_THRESHOLD_300MV 0xff
205
206/* CLD control */
207#define QCA808X_PHY_MMD3_ADDR_CLD_CTRL7 0x8007
208#define QCA808X_8023AZ_AFE_CTRL_MASK GENMASK(8, 4)
209#define QCA808X_8023AZ_AFE_EN 0x90
210
211/* AZ control */
212#define QCA808X_PHY_MMD3_AZ_TRAINING_CTRL 0x8008
213#define QCA808X_MMD3_AZ_TRAINING_VAL 0x1c32
214
215#define QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB 0x8014
216#define QCA808X_MSE_THRESHOLD_20DB_VALUE 0x529
217
218#define QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB 0x800E
219#define QCA808X_MSE_THRESHOLD_17DB_VALUE 0x341
220
221#define QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB 0x801E
222#define QCA808X_MSE_THRESHOLD_27DB_VALUE 0x419
223
224#define QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB 0x8020
225#define QCA808X_MSE_THRESHOLD_28DB_VALUE 0x341
226
227#define QCA808X_PHY_MMD7_TOP_OPTION1 0x901c
228#define QCA808X_TOP_OPTION1_DATA 0x0
229
230#define QCA808X_PHY_MMD3_DEBUG_1 0xa100
231#define QCA808X_MMD3_DEBUG_1_VALUE 0x9203
232#define QCA808X_PHY_MMD3_DEBUG_2 0xa101
233#define QCA808X_MMD3_DEBUG_2_VALUE 0x48ad
234#define QCA808X_PHY_MMD3_DEBUG_3 0xa103
235#define QCA808X_MMD3_DEBUG_3_VALUE 0x1698
236#define QCA808X_PHY_MMD3_DEBUG_4 0xa105
237#define QCA808X_MMD3_DEBUG_4_VALUE 0x8001
238#define QCA808X_PHY_MMD3_DEBUG_5 0xa106
239#define QCA808X_MMD3_DEBUG_5_VALUE 0x1111
240#define QCA808X_PHY_MMD3_DEBUG_6 0xa011
241#define QCA808X_MMD3_DEBUG_6_VALUE 0x5f85
242
243/* master/slave seed config */
244#define QCA808X_PHY_DEBUG_LOCAL_SEED 9
245#define QCA808X_MASTER_SLAVE_SEED_ENABLE BIT(1)
246#define QCA808X_MASTER_SLAVE_SEED_CFG GENMASK(12, 2)
247#define QCA808X_MASTER_SLAVE_SEED_RANGE 0x32
248
249/* Hibernation yields lower power consumpiton in contrast with normal operation mode.
250 * when the copper cable is unplugged, the PHY enters into hibernation mode in about 10s.
251 */
252#define QCA808X_DBG_AN_TEST 0xb
253#define QCA808X_HIBERNATION_EN BIT(15)
254
255#define QCA808X_CDT_ENABLE_TEST BIT(15)
256#define QCA808X_CDT_INTER_CHECK_DIS BIT(13)
257#define QCA808X_CDT_LENGTH_UNIT BIT(10)
258
259#define QCA808X_MMD3_CDT_STATUS 0x8064
260#define QCA808X_MMD3_CDT_DIAG_PAIR_A 0x8065
261#define QCA808X_MMD3_CDT_DIAG_PAIR_B 0x8066
262#define QCA808X_MMD3_CDT_DIAG_PAIR_C 0x8067
263#define QCA808X_MMD3_CDT_DIAG_PAIR_D 0x8068
264#define QCA808X_CDT_DIAG_LENGTH GENMASK(7, 0)
265
266#define QCA808X_CDT_CODE_PAIR_A GENMASK(15, 12)
267#define QCA808X_CDT_CODE_PAIR_B GENMASK(11, 8)
268#define QCA808X_CDT_CODE_PAIR_C GENMASK(7, 4)
269#define QCA808X_CDT_CODE_PAIR_D GENMASK(3, 0)
270#define QCA808X_CDT_STATUS_STAT_FAIL 0
271#define QCA808X_CDT_STATUS_STAT_NORMAL 1
272#define QCA808X_CDT_STATUS_STAT_OPEN 2
273#define QCA808X_CDT_STATUS_STAT_SHORT 3
274
275/* QCA808X 1G chip type */
276#define QCA808X_PHY_MMD7_CHIP_TYPE 0x901d
277#define QCA808X_PHY_CHIP_TYPE_1G BIT(0)
278
279#define QCA8081_PHY_SERDES_MMD1_FIFO_CTRL 0x9072
280#define QCA8081_PHY_FIFO_RSTN BIT(11)
281
282MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver");
283MODULE_AUTHOR("Matus Ujhelyi");
284MODULE_LICENSE("GPL");
285
286enum stat_access_type {
287 PHY,
288 MMD
289};
290
291struct at803x_hw_stat {
292 const char *string;
293 u8 reg;
294 u32 mask;
295 enum stat_access_type access_type;
296};
297
298static struct at803x_hw_stat at803x_hw_stats[] = {
299 { "phy_idle_errors", 0xa, GENMASK(7, 0), PHY},
300 { "phy_receive_errors", 0x15, GENMASK(15, 0), PHY},
301 { "eee_wake_errors", 0x16, GENMASK(15, 0), MMD},
302};
303
304struct at803x_priv {
305 int flags;
306 u16 clk_25m_reg;
307 u16 clk_25m_mask;
308 u8 smarteee_lpi_tw_1g;
309 u8 smarteee_lpi_tw_100m;
310 bool is_fiber;
311 bool is_1000basex;
312 struct regulator_dev *vddio_rdev;
313 struct regulator_dev *vddh_rdev;
314 u64 stats[ARRAY_SIZE(at803x_hw_stats)];
315};
316
317struct at803x_context {
318 u16 bmcr;
319 u16 advertise;
320 u16 control1000;
321 u16 int_enable;
322 u16 smart_speed;
323 u16 led_control;
324};
325
326static int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data)
327{
328 int ret;
329
330 ret = phy_write(phydev, AT803X_DEBUG_ADDR, val: reg);
331 if (ret < 0)
332 return ret;
333
334 return phy_write(phydev, AT803X_DEBUG_DATA, val: data);
335}
336
337static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg)
338{
339 int ret;
340
341 ret = phy_write(phydev, AT803X_DEBUG_ADDR, val: reg);
342 if (ret < 0)
343 return ret;
344
345 return phy_read(phydev, AT803X_DEBUG_DATA);
346}
347
348static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
349 u16 clear, u16 set)
350{
351 u16 val;
352 int ret;
353
354 ret = at803x_debug_reg_read(phydev, reg);
355 if (ret < 0)
356 return ret;
357
358 val = ret & 0xffff;
359 val &= ~clear;
360 val |= set;
361
362 return phy_write(phydev, AT803X_DEBUG_DATA, val);
363}
364
365static int at803x_write_page(struct phy_device *phydev, int page)
366{
367 int mask;
368 int set;
369
370 if (page == AT803X_PAGE_COPPER) {
371 set = AT803X_BT_BX_REG_SEL;
372 mask = 0;
373 } else {
374 set = 0;
375 mask = AT803X_BT_BX_REG_SEL;
376 }
377
378 return __phy_modify(phydev, AT803X_REG_CHIP_CONFIG, mask, set);
379}
380
381static int at803x_read_page(struct phy_device *phydev)
382{
383 int ccr = __phy_read(phydev, AT803X_REG_CHIP_CONFIG);
384
385 if (ccr < 0)
386 return ccr;
387
388 if (ccr & AT803X_BT_BX_REG_SEL)
389 return AT803X_PAGE_COPPER;
390
391 return AT803X_PAGE_FIBER;
392}
393
394static int at803x_enable_rx_delay(struct phy_device *phydev)
395{
396 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, clear: 0,
397 AT803X_DEBUG_RX_CLK_DLY_EN);
398}
399
400static int at803x_enable_tx_delay(struct phy_device *phydev)
401{
402 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, clear: 0,
403 AT803X_DEBUG_TX_CLK_DLY_EN);
404}
405
406static int at803x_disable_rx_delay(struct phy_device *phydev)
407{
408 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
409 AT803X_DEBUG_RX_CLK_DLY_EN, set: 0);
410}
411
412static int at803x_disable_tx_delay(struct phy_device *phydev)
413{
414 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE,
415 AT803X_DEBUG_TX_CLK_DLY_EN, set: 0);
416}
417
418/* save relevant PHY registers to private copy */
419static void at803x_context_save(struct phy_device *phydev,
420 struct at803x_context *context)
421{
422 context->bmcr = phy_read(phydev, MII_BMCR);
423 context->advertise = phy_read(phydev, MII_ADVERTISE);
424 context->control1000 = phy_read(phydev, MII_CTRL1000);
425 context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE);
426 context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED);
427 context->led_control = phy_read(phydev, AT803X_LED_CONTROL);
428}
429
430/* restore relevant PHY registers from private copy */
431static void at803x_context_restore(struct phy_device *phydev,
432 const struct at803x_context *context)
433{
434 phy_write(phydev, MII_BMCR, val: context->bmcr);
435 phy_write(phydev, MII_ADVERTISE, val: context->advertise);
436 phy_write(phydev, MII_CTRL1000, val: context->control1000);
437 phy_write(phydev, AT803X_INTR_ENABLE, val: context->int_enable);
438 phy_write(phydev, AT803X_SMART_SPEED, val: context->smart_speed);
439 phy_write(phydev, AT803X_LED_CONTROL, val: context->led_control);
440}
441
442static int at803x_set_wol(struct phy_device *phydev,
443 struct ethtool_wolinfo *wol)
444{
445 int ret, irq_enabled;
446
447 if (wol->wolopts & WAKE_MAGIC) {
448 struct net_device *ndev = phydev->attached_dev;
449 const u8 *mac;
450 unsigned int i;
451 static const unsigned int offsets[] = {
452 AT803X_LOC_MAC_ADDR_32_47_OFFSET,
453 AT803X_LOC_MAC_ADDR_16_31_OFFSET,
454 AT803X_LOC_MAC_ADDR_0_15_OFFSET,
455 };
456
457 if (!ndev)
458 return -ENODEV;
459
460 mac = (const u8 *) ndev->dev_addr;
461
462 if (!is_valid_ether_addr(addr: mac))
463 return -EINVAL;
464
465 for (i = 0; i < 3; i++)
466 phy_write_mmd(phydev, MDIO_MMD_PCS, regnum: offsets[i],
467 val: mac[(i * 2) + 1] | (mac[(i * 2)] << 8));
468
469 /* Enable WOL function for 1588 */
470 if (phydev->drv->phy_id == ATH8031_PHY_ID) {
471 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS,
472 AT803X_PHY_MMD3_WOL_CTRL,
473 mask: 0, AT803X_WOL_EN);
474 if (ret)
475 return ret;
476 }
477 /* Enable WOL interrupt */
478 ret = phy_modify(phydev, AT803X_INTR_ENABLE, mask: 0, AT803X_INTR_ENABLE_WOL);
479 if (ret)
480 return ret;
481 } else {
482 /* Disable WoL function for 1588 */
483 if (phydev->drv->phy_id == ATH8031_PHY_ID) {
484 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS,
485 AT803X_PHY_MMD3_WOL_CTRL,
486 AT803X_WOL_EN, set: 0);
487 if (ret)
488 return ret;
489 }
490 /* Disable WOL interrupt */
491 ret = phy_modify(phydev, AT803X_INTR_ENABLE, AT803X_INTR_ENABLE_WOL, set: 0);
492 if (ret)
493 return ret;
494 }
495
496 /* Clear WOL status */
497 ret = phy_read(phydev, AT803X_INTR_STATUS);
498 if (ret < 0)
499 return ret;
500
501 /* Check if there are other interrupts except for WOL triggered when PHY is
502 * in interrupt mode, only the interrupts enabled by AT803X_INTR_ENABLE can
503 * be passed up to the interrupt PIN.
504 */
505 irq_enabled = phy_read(phydev, AT803X_INTR_ENABLE);
506 if (irq_enabled < 0)
507 return irq_enabled;
508
509 irq_enabled &= ~AT803X_INTR_ENABLE_WOL;
510 if (ret & irq_enabled && !phy_polling_mode(phydev))
511 phy_trigger_machine(phydev);
512
513 return 0;
514}
515
516static void at803x_get_wol(struct phy_device *phydev,
517 struct ethtool_wolinfo *wol)
518{
519 int value;
520
521 wol->supported = WAKE_MAGIC;
522 wol->wolopts = 0;
523
524 value = phy_read(phydev, AT803X_INTR_ENABLE);
525 if (value < 0)
526 return;
527
528 if (value & AT803X_INTR_ENABLE_WOL)
529 wol->wolopts |= WAKE_MAGIC;
530}
531
532static int at803x_get_sset_count(struct phy_device *phydev)
533{
534 return ARRAY_SIZE(at803x_hw_stats);
535}
536
537static void at803x_get_strings(struct phy_device *phydev, u8 *data)
538{
539 int i;
540
541 for (i = 0; i < ARRAY_SIZE(at803x_hw_stats); i++) {
542 strscpy(p: data + i * ETH_GSTRING_LEN,
543 q: at803x_hw_stats[i].string, ETH_GSTRING_LEN);
544 }
545}
546
547static u64 at803x_get_stat(struct phy_device *phydev, int i)
548{
549 struct at803x_hw_stat stat = at803x_hw_stats[i];
550 struct at803x_priv *priv = phydev->priv;
551 int val;
552 u64 ret;
553
554 if (stat.access_type == MMD)
555 val = phy_read_mmd(phydev, MDIO_MMD_PCS, regnum: stat.reg);
556 else
557 val = phy_read(phydev, regnum: stat.reg);
558
559 if (val < 0) {
560 ret = U64_MAX;
561 } else {
562 val = val & stat.mask;
563 priv->stats[i] += val;
564 ret = priv->stats[i];
565 }
566
567 return ret;
568}
569
570static void at803x_get_stats(struct phy_device *phydev,
571 struct ethtool_stats *stats, u64 *data)
572{
573 int i;
574
575 for (i = 0; i < ARRAY_SIZE(at803x_hw_stats); i++)
576 data[i] = at803x_get_stat(phydev, i);
577}
578
579static int at803x_suspend(struct phy_device *phydev)
580{
581 int value;
582 int wol_enabled;
583
584 value = phy_read(phydev, AT803X_INTR_ENABLE);
585 wol_enabled = value & AT803X_INTR_ENABLE_WOL;
586
587 if (wol_enabled)
588 value = BMCR_ISOLATE;
589 else
590 value = BMCR_PDOWN;
591
592 phy_modify(phydev, MII_BMCR, mask: 0, set: value);
593
594 return 0;
595}
596
597static int at803x_resume(struct phy_device *phydev)
598{
599 return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, set: 0);
600}
601
602static int at803x_rgmii_reg_set_voltage_sel(struct regulator_dev *rdev,
603 unsigned int selector)
604{
605 struct phy_device *phydev = rdev_get_drvdata(rdev);
606
607 if (selector)
608 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
609 clear: 0, AT803X_DEBUG_RGMII_1V8);
610 else
611 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
612 AT803X_DEBUG_RGMII_1V8, set: 0);
613}
614
615static int at803x_rgmii_reg_get_voltage_sel(struct regulator_dev *rdev)
616{
617 struct phy_device *phydev = rdev_get_drvdata(rdev);
618 int val;
619
620 val = at803x_debug_reg_read(phydev, AT803X_DEBUG_REG_1F);
621 if (val < 0)
622 return val;
623
624 return (val & AT803X_DEBUG_RGMII_1V8) ? 1 : 0;
625}
626
627static const struct regulator_ops vddio_regulator_ops = {
628 .list_voltage = regulator_list_voltage_table,
629 .set_voltage_sel = at803x_rgmii_reg_set_voltage_sel,
630 .get_voltage_sel = at803x_rgmii_reg_get_voltage_sel,
631};
632
633static const unsigned int vddio_voltage_table[] = {
634 1500000,
635 1800000,
636};
637
638static const struct regulator_desc vddio_desc = {
639 .name = "vddio",
640 .of_match = of_match_ptr("vddio-regulator"),
641 .n_voltages = ARRAY_SIZE(vddio_voltage_table),
642 .volt_table = vddio_voltage_table,
643 .ops = &vddio_regulator_ops,
644 .type = REGULATOR_VOLTAGE,
645 .owner = THIS_MODULE,
646};
647
648static const struct regulator_ops vddh_regulator_ops = {
649};
650
651static const struct regulator_desc vddh_desc = {
652 .name = "vddh",
653 .of_match = of_match_ptr("vddh-regulator"),
654 .n_voltages = 1,
655 .fixed_uV = 2500000,
656 .ops = &vddh_regulator_ops,
657 .type = REGULATOR_VOLTAGE,
658 .owner = THIS_MODULE,
659};
660
661static int at8031_register_regulators(struct phy_device *phydev)
662{
663 struct at803x_priv *priv = phydev->priv;
664 struct device *dev = &phydev->mdio.dev;
665 struct regulator_config config = { };
666
667 config.dev = dev;
668 config.driver_data = phydev;
669
670 priv->vddio_rdev = devm_regulator_register(dev, regulator_desc: &vddio_desc, config: &config);
671 if (IS_ERR(ptr: priv->vddio_rdev)) {
672 phydev_err(phydev, "failed to register VDDIO regulator\n");
673 return PTR_ERR(ptr: priv->vddio_rdev);
674 }
675
676 priv->vddh_rdev = devm_regulator_register(dev, regulator_desc: &vddh_desc, config: &config);
677 if (IS_ERR(ptr: priv->vddh_rdev)) {
678 phydev_err(phydev, "failed to register VDDH regulator\n");
679 return PTR_ERR(ptr: priv->vddh_rdev);
680 }
681
682 return 0;
683}
684
685static int at803x_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
686{
687 struct phy_device *phydev = upstream;
688 __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_support);
689 __ETHTOOL_DECLARE_LINK_MODE_MASK(sfp_support);
690 DECLARE_PHY_INTERFACE_MASK(interfaces);
691 phy_interface_t iface;
692
693 linkmode_zero(dst: phy_support);
694 phylink_set(phy_support, 1000baseX_Full);
695 phylink_set(phy_support, 1000baseT_Full);
696 phylink_set(phy_support, Autoneg);
697 phylink_set(phy_support, Pause);
698 phylink_set(phy_support, Asym_Pause);
699
700 linkmode_zero(dst: sfp_support);
701 sfp_parse_support(bus: phydev->sfp_bus, id, support: sfp_support, interfaces);
702 /* Some modules support 10G modes as well as others we support.
703 * Mask out non-supported modes so the correct interface is picked.
704 */
705 linkmode_and(dst: sfp_support, a: phy_support, b: sfp_support);
706
707 if (linkmode_empty(src: sfp_support)) {
708 dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n");
709 return -EINVAL;
710 }
711
712 iface = sfp_select_interface(bus: phydev->sfp_bus, link_modes: sfp_support);
713
714 /* Only 1000Base-X is supported by AR8031/8033 as the downstream SerDes
715 * interface for use with SFP modules.
716 * However, some copper modules detected as having a preferred SGMII
717 * interface do default to and function in 1000Base-X mode, so just
718 * print a warning and allow such modules, as they may have some chance
719 * of working.
720 */
721 if (iface == PHY_INTERFACE_MODE_SGMII)
722 dev_warn(&phydev->mdio.dev, "module may not function if 1000Base-X not supported\n");
723 else if (iface != PHY_INTERFACE_MODE_1000BASEX)
724 return -EINVAL;
725
726 return 0;
727}
728
729static const struct sfp_upstream_ops at803x_sfp_ops = {
730 .attach = phy_sfp_attach,
731 .detach = phy_sfp_detach,
732 .module_insert = at803x_sfp_insert,
733};
734
735static int at803x_parse_dt(struct phy_device *phydev)
736{
737 struct device_node *node = phydev->mdio.dev.of_node;
738 struct at803x_priv *priv = phydev->priv;
739 u32 freq, strength, tw;
740 unsigned int sel;
741 int ret;
742
743 if (!IS_ENABLED(CONFIG_OF_MDIO))
744 return 0;
745
746 if (of_property_read_bool(np: node, propname: "qca,disable-smarteee"))
747 priv->flags |= AT803X_DISABLE_SMARTEEE;
748
749 if (of_property_read_bool(np: node, propname: "qca,disable-hibernation-mode"))
750 priv->flags |= AT803X_DISABLE_HIBERNATION_MODE;
751
752 if (!of_property_read_u32(np: node, propname: "qca,smarteee-tw-us-1g", out_value: &tw)) {
753 if (!tw || tw > 255) {
754 phydev_err(phydev, "invalid qca,smarteee-tw-us-1g\n");
755 return -EINVAL;
756 }
757 priv->smarteee_lpi_tw_1g = tw;
758 }
759
760 if (!of_property_read_u32(np: node, propname: "qca,smarteee-tw-us-100m", out_value: &tw)) {
761 if (!tw || tw > 255) {
762 phydev_err(phydev, "invalid qca,smarteee-tw-us-100m\n");
763 return -EINVAL;
764 }
765 priv->smarteee_lpi_tw_100m = tw;
766 }
767
768 ret = of_property_read_u32(np: node, propname: "qca,clk-out-frequency", out_value: &freq);
769 if (!ret) {
770 switch (freq) {
771 case 25000000:
772 sel = AT803X_CLK_OUT_25MHZ_XTAL;
773 break;
774 case 50000000:
775 sel = AT803X_CLK_OUT_50MHZ_PLL;
776 break;
777 case 62500000:
778 sel = AT803X_CLK_OUT_62_5MHZ_PLL;
779 break;
780 case 125000000:
781 sel = AT803X_CLK_OUT_125MHZ_PLL;
782 break;
783 default:
784 phydev_err(phydev, "invalid qca,clk-out-frequency\n");
785 return -EINVAL;
786 }
787
788 priv->clk_25m_reg |= FIELD_PREP(AT803X_CLK_OUT_MASK, sel);
789 priv->clk_25m_mask |= AT803X_CLK_OUT_MASK;
790
791 /* Fixup for the AR8030/AR8035. This chip has another mask and
792 * doesn't support the DSP reference. Eg. the lowest bit of the
793 * mask. The upper two bits select the same frequencies. Mask
794 * the lowest bit here.
795 *
796 * Warning:
797 * There was no datasheet for the AR8030 available so this is
798 * just a guess. But the AR8035 is listed as pin compatible
799 * to the AR8030 so there might be a good chance it works on
800 * the AR8030 too.
801 */
802 if (phydev->drv->phy_id == ATH8030_PHY_ID ||
803 phydev->drv->phy_id == ATH8035_PHY_ID) {
804 priv->clk_25m_reg &= AT8035_CLK_OUT_MASK;
805 priv->clk_25m_mask &= AT8035_CLK_OUT_MASK;
806 }
807 }
808
809 ret = of_property_read_u32(np: node, propname: "qca,clk-out-strength", out_value: &strength);
810 if (!ret) {
811 priv->clk_25m_mask |= AT803X_CLK_OUT_STRENGTH_MASK;
812 switch (strength) {
813 case AR803X_STRENGTH_FULL:
814 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_FULL;
815 break;
816 case AR803X_STRENGTH_HALF:
817 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_HALF;
818 break;
819 case AR803X_STRENGTH_QUARTER:
820 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_QUARTER;
821 break;
822 default:
823 phydev_err(phydev, "invalid qca,clk-out-strength\n");
824 return -EINVAL;
825 }
826 }
827
828 /* Only supported on AR8031/AR8033, the AR8030/AR8035 use strapping
829 * options.
830 */
831 if (phydev->drv->phy_id == ATH8031_PHY_ID) {
832 if (of_property_read_bool(np: node, propname: "qca,keep-pll-enabled"))
833 priv->flags |= AT803X_KEEP_PLL_ENABLED;
834
835 ret = at8031_register_regulators(phydev);
836 if (ret < 0)
837 return ret;
838
839 ret = devm_regulator_get_enable_optional(dev: &phydev->mdio.dev,
840 id: "vddio");
841 if (ret) {
842 phydev_err(phydev, "failed to get VDDIO regulator\n");
843 return ret;
844 }
845
846 /* Only AR8031/8033 support 1000Base-X for SFP modules */
847 ret = phy_sfp_probe(phydev, ops: &at803x_sfp_ops);
848 if (ret < 0)
849 return ret;
850 }
851
852 return 0;
853}
854
855static int at803x_probe(struct phy_device *phydev)
856{
857 struct device *dev = &phydev->mdio.dev;
858 struct at803x_priv *priv;
859 int ret;
860
861 priv = devm_kzalloc(dev, size: sizeof(*priv), GFP_KERNEL);
862 if (!priv)
863 return -ENOMEM;
864
865 phydev->priv = priv;
866
867 ret = at803x_parse_dt(phydev);
868 if (ret)
869 return ret;
870
871 if (phydev->drv->phy_id == ATH8031_PHY_ID) {
872 int ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG);
873 int mode_cfg;
874
875 if (ccr < 0)
876 return ccr;
877 mode_cfg = ccr & AT803X_MODE_CFG_MASK;
878
879 switch (mode_cfg) {
880 case AT803X_MODE_CFG_BX1000_RGMII_50OHM:
881 case AT803X_MODE_CFG_BX1000_RGMII_75OHM:
882 priv->is_1000basex = true;
883 fallthrough;
884 case AT803X_MODE_CFG_FX100_RGMII_50OHM:
885 case AT803X_MODE_CFG_FX100_RGMII_75OHM:
886 priv->is_fiber = true;
887 break;
888 }
889
890 /* Disable WoL in 1588 register which is enabled
891 * by default
892 */
893 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS,
894 AT803X_PHY_MMD3_WOL_CTRL,
895 AT803X_WOL_EN, set: 0);
896 if (ret)
897 return ret;
898 }
899
900 return 0;
901}
902
903static int at803x_get_features(struct phy_device *phydev)
904{
905 struct at803x_priv *priv = phydev->priv;
906 int err;
907
908 err = genphy_read_abilities(phydev);
909 if (err)
910 return err;
911
912 if (phydev->drv->phy_id != ATH8031_PHY_ID)
913 return 0;
914
915 /* AR8031/AR8033 have different status registers
916 * for copper and fiber operation. However, the
917 * extended status register is the same for both
918 * operation modes.
919 *
920 * As a result of that, ESTATUS_1000_XFULL is set
921 * to 1 even when operating in copper TP mode.
922 *
923 * Remove this mode from the supported link modes
924 * when not operating in 1000BaseX mode.
925 */
926 if (!priv->is_1000basex)
927 linkmode_clear_bit(nr: ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
928 addr: phydev->supported);
929
930 return 0;
931}
932
933static int at803x_smarteee_config(struct phy_device *phydev)
934{
935 struct at803x_priv *priv = phydev->priv;
936 u16 mask = 0, val = 0;
937 int ret;
938
939 if (priv->flags & AT803X_DISABLE_SMARTEEE)
940 return phy_modify_mmd(phydev, MDIO_MMD_PCS,
941 AT803X_MMD3_SMARTEEE_CTL3,
942 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, set: 0);
943
944 if (priv->smarteee_lpi_tw_1g) {
945 mask |= 0xff00;
946 val |= priv->smarteee_lpi_tw_1g << 8;
947 }
948 if (priv->smarteee_lpi_tw_100m) {
949 mask |= 0x00ff;
950 val |= priv->smarteee_lpi_tw_100m;
951 }
952 if (!mask)
953 return 0;
954
955 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL1,
956 mask, set: val);
957 if (ret)
958 return ret;
959
960 return phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL3,
961 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN,
962 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN);
963}
964
965static int at803x_clk_out_config(struct phy_device *phydev)
966{
967 struct at803x_priv *priv = phydev->priv;
968
969 if (!priv->clk_25m_mask)
970 return 0;
971
972 return phy_modify_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M,
973 mask: priv->clk_25m_mask, set: priv->clk_25m_reg);
974}
975
976static int at8031_pll_config(struct phy_device *phydev)
977{
978 struct at803x_priv *priv = phydev->priv;
979
980 /* The default after hardware reset is PLL OFF. After a soft reset, the
981 * values are retained.
982 */
983 if (priv->flags & AT803X_KEEP_PLL_ENABLED)
984 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
985 clear: 0, AT803X_DEBUG_PLL_ON);
986 else
987 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
988 AT803X_DEBUG_PLL_ON, set: 0);
989}
990
991static int at803x_hibernation_mode_config(struct phy_device *phydev)
992{
993 struct at803x_priv *priv = phydev->priv;
994
995 /* The default after hardware reset is hibernation mode enabled. After
996 * software reset, the value is retained.
997 */
998 if (!(priv->flags & AT803X_DISABLE_HIBERNATION_MODE))
999 return 0;
1000
1001 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL,
1002 AT803X_DEBUG_HIB_CTRL_PS_HIB_EN, set: 0);
1003}
1004
1005static int at803x_config_init(struct phy_device *phydev)
1006{
1007 struct at803x_priv *priv = phydev->priv;
1008 int ret;
1009
1010 if (phydev->drv->phy_id == ATH8031_PHY_ID) {
1011 /* Some bootloaders leave the fiber page selected.
1012 * Switch to the appropriate page (fiber or copper), as otherwise we
1013 * read the PHY capabilities from the wrong page.
1014 */
1015 phy_lock_mdio_bus(phydev);
1016 ret = at803x_write_page(phydev,
1017 page: priv->is_fiber ? AT803X_PAGE_FIBER :
1018 AT803X_PAGE_COPPER);
1019 phy_unlock_mdio_bus(phydev);
1020 if (ret)
1021 return ret;
1022
1023 ret = at8031_pll_config(phydev);
1024 if (ret < 0)
1025 return ret;
1026 }
1027
1028 /* The RX and TX delay default is:
1029 * after HW reset: RX delay enabled and TX delay disabled
1030 * after SW reset: RX delay enabled, while TX delay retains the
1031 * value before reset.
1032 */
1033 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
1034 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
1035 ret = at803x_enable_rx_delay(phydev);
1036 else
1037 ret = at803x_disable_rx_delay(phydev);
1038 if (ret < 0)
1039 return ret;
1040
1041 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
1042 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
1043 ret = at803x_enable_tx_delay(phydev);
1044 else
1045 ret = at803x_disable_tx_delay(phydev);
1046 if (ret < 0)
1047 return ret;
1048
1049 ret = at803x_smarteee_config(phydev);
1050 if (ret < 0)
1051 return ret;
1052
1053 ret = at803x_clk_out_config(phydev);
1054 if (ret < 0)
1055 return ret;
1056
1057 ret = at803x_hibernation_mode_config(phydev);
1058 if (ret < 0)
1059 return ret;
1060
1061 /* Ar803x extended next page bit is enabled by default. Cisco
1062 * multigig switches read this bit and attempt to negotiate 10Gbps
1063 * rates even if the next page bit is disabled. This is incorrect
1064 * behaviour but we still need to accommodate it. XNP is only needed
1065 * for 10Gbps support, so disable XNP.
1066 */
1067 return phy_modify(phydev, MII_ADVERTISE, MDIO_AN_CTRL1_XNP, set: 0);
1068}
1069
1070static int at803x_ack_interrupt(struct phy_device *phydev)
1071{
1072 int err;
1073
1074 err = phy_read(phydev, AT803X_INTR_STATUS);
1075
1076 return (err < 0) ? err : 0;
1077}
1078
1079static int at803x_config_intr(struct phy_device *phydev)
1080{
1081 struct at803x_priv *priv = phydev->priv;
1082 int err;
1083 int value;
1084
1085 value = phy_read(phydev, AT803X_INTR_ENABLE);
1086
1087 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
1088 /* Clear any pending interrupts */
1089 err = at803x_ack_interrupt(phydev);
1090 if (err)
1091 return err;
1092
1093 value |= AT803X_INTR_ENABLE_AUTONEG_ERR;
1094 value |= AT803X_INTR_ENABLE_SPEED_CHANGED;
1095 value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED;
1096 value |= AT803X_INTR_ENABLE_LINK_FAIL;
1097 value |= AT803X_INTR_ENABLE_LINK_SUCCESS;
1098 if (priv->is_fiber) {
1099 value |= AT803X_INTR_ENABLE_LINK_FAIL_BX;
1100 value |= AT803X_INTR_ENABLE_LINK_SUCCESS_BX;
1101 }
1102
1103 err = phy_write(phydev, AT803X_INTR_ENABLE, val: value);
1104 } else {
1105 err = phy_write(phydev, AT803X_INTR_ENABLE, val: 0);
1106 if (err)
1107 return err;
1108
1109 /* Clear any pending interrupts */
1110 err = at803x_ack_interrupt(phydev);
1111 }
1112
1113 return err;
1114}
1115
1116static irqreturn_t at803x_handle_interrupt(struct phy_device *phydev)
1117{
1118 int irq_status, int_enabled;
1119
1120 irq_status = phy_read(phydev, AT803X_INTR_STATUS);
1121 if (irq_status < 0) {
1122 phy_error(phydev);
1123 return IRQ_NONE;
1124 }
1125
1126 /* Read the current enabled interrupts */
1127 int_enabled = phy_read(phydev, AT803X_INTR_ENABLE);
1128 if (int_enabled < 0) {
1129 phy_error(phydev);
1130 return IRQ_NONE;
1131 }
1132
1133 /* See if this was one of our enabled interrupts */
1134 if (!(irq_status & int_enabled))
1135 return IRQ_NONE;
1136
1137 phy_trigger_machine(phydev);
1138
1139 return IRQ_HANDLED;
1140}
1141
1142static void at803x_link_change_notify(struct phy_device *phydev)
1143{
1144 /*
1145 * Conduct a hardware reset for AT8030 every time a link loss is
1146 * signalled. This is necessary to circumvent a hardware bug that
1147 * occurs when the cable is unplugged while TX packets are pending
1148 * in the FIFO. In such cases, the FIFO enters an error mode it
1149 * cannot recover from by software.
1150 */
1151 if (phydev->state == PHY_NOLINK && phydev->mdio.reset_gpio) {
1152 struct at803x_context context;
1153
1154 at803x_context_save(phydev, context: &context);
1155
1156 phy_device_reset(phydev, value: 1);
1157 msleep(msecs: 1);
1158 phy_device_reset(phydev, value: 0);
1159 msleep(msecs: 1);
1160
1161 at803x_context_restore(phydev, context: &context);
1162
1163 phydev_dbg(phydev, "%s(): phy was reset\n", __func__);
1164 }
1165}
1166
1167static int at803x_read_specific_status(struct phy_device *phydev)
1168{
1169 int ss;
1170
1171 /* Read the AT8035 PHY-Specific Status register, which indicates the
1172 * speed and duplex that the PHY is actually using, irrespective of
1173 * whether we are in autoneg mode or not.
1174 */
1175 ss = phy_read(phydev, AT803X_SPECIFIC_STATUS);
1176 if (ss < 0)
1177 return ss;
1178
1179 if (ss & AT803X_SS_SPEED_DUPLEX_RESOLVED) {
1180 int sfc, speed;
1181
1182 sfc = phy_read(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL);
1183 if (sfc < 0)
1184 return sfc;
1185
1186 /* qca8081 takes the different bits for speed value from at803x */
1187 if (phydev->drv->phy_id == QCA8081_PHY_ID)
1188 speed = FIELD_GET(QCA808X_SS_SPEED_MASK, ss);
1189 else
1190 speed = FIELD_GET(AT803X_SS_SPEED_MASK, ss);
1191
1192 switch (speed) {
1193 case AT803X_SS_SPEED_10:
1194 phydev->speed = SPEED_10;
1195 break;
1196 case AT803X_SS_SPEED_100:
1197 phydev->speed = SPEED_100;
1198 break;
1199 case AT803X_SS_SPEED_1000:
1200 phydev->speed = SPEED_1000;
1201 break;
1202 case QCA808X_SS_SPEED_2500:
1203 phydev->speed = SPEED_2500;
1204 break;
1205 }
1206 if (ss & AT803X_SS_DUPLEX)
1207 phydev->duplex = DUPLEX_FULL;
1208 else
1209 phydev->duplex = DUPLEX_HALF;
1210
1211 if (ss & AT803X_SS_MDIX)
1212 phydev->mdix = ETH_TP_MDI_X;
1213 else
1214 phydev->mdix = ETH_TP_MDI;
1215
1216 switch (FIELD_GET(AT803X_SFC_MDI_CROSSOVER_MODE_M, sfc)) {
1217 case AT803X_SFC_MANUAL_MDI:
1218 phydev->mdix_ctrl = ETH_TP_MDI;
1219 break;
1220 case AT803X_SFC_MANUAL_MDIX:
1221 phydev->mdix_ctrl = ETH_TP_MDI_X;
1222 break;
1223 case AT803X_SFC_AUTOMATIC_CROSSOVER:
1224 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1225 break;
1226 }
1227 }
1228
1229 return 0;
1230}
1231
1232static int at803x_read_status(struct phy_device *phydev)
1233{
1234 struct at803x_priv *priv = phydev->priv;
1235 int err, old_link = phydev->link;
1236
1237 if (priv->is_1000basex)
1238 return genphy_c37_read_status(phydev);
1239
1240 /* Update the link, but return if there was an error */
1241 err = genphy_update_link(phydev);
1242 if (err)
1243 return err;
1244
1245 /* why bother the PHY if nothing can have changed */
1246 if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link)
1247 return 0;
1248
1249 phydev->speed = SPEED_UNKNOWN;
1250 phydev->duplex = DUPLEX_UNKNOWN;
1251 phydev->pause = 0;
1252 phydev->asym_pause = 0;
1253
1254 err = genphy_read_lpa(phydev);
1255 if (err < 0)
1256 return err;
1257
1258 err = at803x_read_specific_status(phydev);
1259 if (err < 0)
1260 return err;
1261
1262 if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete)
1263 phy_resolve_aneg_pause(phydev);
1264
1265 return 0;
1266}
1267
1268static int at803x_config_mdix(struct phy_device *phydev, u8 ctrl)
1269{
1270 u16 val;
1271
1272 switch (ctrl) {
1273 case ETH_TP_MDI:
1274 val = AT803X_SFC_MANUAL_MDI;
1275 break;
1276 case ETH_TP_MDI_X:
1277 val = AT803X_SFC_MANUAL_MDIX;
1278 break;
1279 case ETH_TP_MDI_AUTO:
1280 val = AT803X_SFC_AUTOMATIC_CROSSOVER;
1281 break;
1282 default:
1283 return 0;
1284 }
1285
1286 return phy_modify_changed(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL,
1287 AT803X_SFC_MDI_CROSSOVER_MODE_M,
1288 FIELD_PREP(AT803X_SFC_MDI_CROSSOVER_MODE_M, val));
1289}
1290
1291static int at803x_config_aneg(struct phy_device *phydev)
1292{
1293 struct at803x_priv *priv = phydev->priv;
1294 int ret;
1295
1296 ret = at803x_config_mdix(phydev, ctrl: phydev->mdix_ctrl);
1297 if (ret < 0)
1298 return ret;
1299
1300 /* Changes of the midx bits are disruptive to the normal operation;
1301 * therefore any changes to these registers must be followed by a
1302 * software reset to take effect.
1303 */
1304 if (ret == 1) {
1305 ret = genphy_soft_reset(phydev);
1306 if (ret < 0)
1307 return ret;
1308 }
1309
1310 if (priv->is_1000basex)
1311 return genphy_c37_config_aneg(phydev);
1312
1313 /* Do not restart auto-negotiation by setting ret to 0 defautly,
1314 * when calling __genphy_config_aneg later.
1315 */
1316 ret = 0;
1317
1318 if (phydev->drv->phy_id == QCA8081_PHY_ID) {
1319 int phy_ctrl = 0;
1320
1321 /* The reg MII_BMCR also needs to be configured for force mode, the
1322 * genphy_config_aneg is also needed.
1323 */
1324 if (phydev->autoneg == AUTONEG_DISABLE)
1325 genphy_c45_pma_setup_forced(phydev);
1326
1327 if (linkmode_test_bit(nr: ETHTOOL_LINK_MODE_2500baseT_Full_BIT, addr: phydev->advertising))
1328 phy_ctrl = MDIO_AN_10GBT_CTRL_ADV2_5G;
1329
1330 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
1331 MDIO_AN_10GBT_CTRL_ADV2_5G, set: phy_ctrl);
1332 if (ret < 0)
1333 return ret;
1334 }
1335
1336 return __genphy_config_aneg(phydev, changed: ret);
1337}
1338
1339static int at803x_get_downshift(struct phy_device *phydev, u8 *d)
1340{
1341 int val;
1342
1343 val = phy_read(phydev, AT803X_SMART_SPEED);
1344 if (val < 0)
1345 return val;
1346
1347 if (val & AT803X_SMART_SPEED_ENABLE)
1348 *d = FIELD_GET(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, val) + 2;
1349 else
1350 *d = DOWNSHIFT_DEV_DISABLE;
1351
1352 return 0;
1353}
1354
1355static int at803x_set_downshift(struct phy_device *phydev, u8 cnt)
1356{
1357 u16 mask, set;
1358 int ret;
1359
1360 switch (cnt) {
1361 case DOWNSHIFT_DEV_DEFAULT_COUNT:
1362 cnt = AT803X_DEFAULT_DOWNSHIFT;
1363 fallthrough;
1364 case AT803X_MIN_DOWNSHIFT ... AT803X_MAX_DOWNSHIFT:
1365 set = AT803X_SMART_SPEED_ENABLE |
1366 AT803X_SMART_SPEED_BYPASS_TIMER |
1367 FIELD_PREP(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, cnt - 2);
1368 mask = AT803X_SMART_SPEED_RETRY_LIMIT_MASK;
1369 break;
1370 case DOWNSHIFT_DEV_DISABLE:
1371 set = 0;
1372 mask = AT803X_SMART_SPEED_ENABLE |
1373 AT803X_SMART_SPEED_BYPASS_TIMER;
1374 break;
1375 default:
1376 return -EINVAL;
1377 }
1378
1379 ret = phy_modify_changed(phydev, AT803X_SMART_SPEED, mask, set);
1380
1381 /* After changing the smart speed settings, we need to perform a
1382 * software reset, use phy_init_hw() to make sure we set the
1383 * reapply any values which might got lost during software reset.
1384 */
1385 if (ret == 1)
1386 ret = phy_init_hw(phydev);
1387
1388 return ret;
1389}
1390
1391static int at803x_get_tunable(struct phy_device *phydev,
1392 struct ethtool_tunable *tuna, void *data)
1393{
1394 switch (tuna->id) {
1395 case ETHTOOL_PHY_DOWNSHIFT:
1396 return at803x_get_downshift(phydev, d: data);
1397 default:
1398 return -EOPNOTSUPP;
1399 }
1400}
1401
1402static int at803x_set_tunable(struct phy_device *phydev,
1403 struct ethtool_tunable *tuna, const void *data)
1404{
1405 switch (tuna->id) {
1406 case ETHTOOL_PHY_DOWNSHIFT:
1407 return at803x_set_downshift(phydev, cnt: *(const u8 *)data);
1408 default:
1409 return -EOPNOTSUPP;
1410 }
1411}
1412
1413static int at803x_cable_test_result_trans(u16 status)
1414{
1415 switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) {
1416 case AT803X_CDT_STATUS_STAT_NORMAL:
1417 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
1418 case AT803X_CDT_STATUS_STAT_SHORT:
1419 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
1420 case AT803X_CDT_STATUS_STAT_OPEN:
1421 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
1422 case AT803X_CDT_STATUS_STAT_FAIL:
1423 default:
1424 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
1425 }
1426}
1427
1428static bool at803x_cdt_test_failed(u16 status)
1429{
1430 return FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status) ==
1431 AT803X_CDT_STATUS_STAT_FAIL;
1432}
1433
1434static bool at803x_cdt_fault_length_valid(u16 status)
1435{
1436 switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) {
1437 case AT803X_CDT_STATUS_STAT_OPEN:
1438 case AT803X_CDT_STATUS_STAT_SHORT:
1439 return true;
1440 }
1441 return false;
1442}
1443
1444static int at803x_cdt_fault_length(u16 status)
1445{
1446 int dt;
1447
1448 /* According to the datasheet the distance to the fault is
1449 * DELTA_TIME * 0.824 meters.
1450 *
1451 * The author suspect the correct formula is:
1452 *
1453 * fault_distance = DELTA_TIME * (c * VF) / 125MHz / 2
1454 *
1455 * where c is the speed of light, VF is the velocity factor of
1456 * the twisted pair cable, 125MHz the counter frequency and
1457 * we need to divide by 2 because the hardware will measure the
1458 * round trip time to the fault and back to the PHY.
1459 *
1460 * With a VF of 0.69 we get the factor 0.824 mentioned in the
1461 * datasheet.
1462 */
1463 dt = FIELD_GET(AT803X_CDT_STATUS_DELTA_TIME_MASK, status);
1464
1465 return (dt * 824) / 10;
1466}
1467
1468static int at803x_cdt_start(struct phy_device *phydev, int pair)
1469{
1470 u16 cdt;
1471
1472 /* qca8081 takes the different bit 15 to enable CDT test */
1473 if (phydev->drv->phy_id == QCA8081_PHY_ID)
1474 cdt = QCA808X_CDT_ENABLE_TEST |
1475 QCA808X_CDT_LENGTH_UNIT |
1476 QCA808X_CDT_INTER_CHECK_DIS;
1477 else
1478 cdt = FIELD_PREP(AT803X_CDT_MDI_PAIR_MASK, pair) |
1479 AT803X_CDT_ENABLE_TEST;
1480
1481 return phy_write(phydev, AT803X_CDT, val: cdt);
1482}
1483
1484static int at803x_cdt_wait_for_completion(struct phy_device *phydev)
1485{
1486 int val, ret;
1487 u16 cdt_en;
1488
1489 if (phydev->drv->phy_id == QCA8081_PHY_ID)
1490 cdt_en = QCA808X_CDT_ENABLE_TEST;
1491 else
1492 cdt_en = AT803X_CDT_ENABLE_TEST;
1493
1494 /* One test run takes about 25ms */
1495 ret = phy_read_poll_timeout(phydev, AT803X_CDT, val,
1496 !(val & cdt_en),
1497 30000, 100000, true);
1498
1499 return ret < 0 ? ret : 0;
1500}
1501
1502static int at803x_cable_test_one_pair(struct phy_device *phydev, int pair)
1503{
1504 static const int ethtool_pair[] = {
1505 ETHTOOL_A_CABLE_PAIR_A,
1506 ETHTOOL_A_CABLE_PAIR_B,
1507 ETHTOOL_A_CABLE_PAIR_C,
1508 ETHTOOL_A_CABLE_PAIR_D,
1509 };
1510 int ret, val;
1511
1512 ret = at803x_cdt_start(phydev, pair);
1513 if (ret)
1514 return ret;
1515
1516 ret = at803x_cdt_wait_for_completion(phydev);
1517 if (ret)
1518 return ret;
1519
1520 val = phy_read(phydev, AT803X_CDT_STATUS);
1521 if (val < 0)
1522 return val;
1523
1524 if (at803x_cdt_test_failed(status: val))
1525 return 0;
1526
1527 ethnl_cable_test_result(phydev, pair: ethtool_pair[pair],
1528 result: at803x_cable_test_result_trans(status: val));
1529
1530 if (at803x_cdt_fault_length_valid(status: val))
1531 ethnl_cable_test_fault_length(phydev, pair: ethtool_pair[pair],
1532 cm: at803x_cdt_fault_length(status: val));
1533
1534 return 1;
1535}
1536
1537static int at803x_cable_test_get_status(struct phy_device *phydev,
1538 bool *finished)
1539{
1540 unsigned long pair_mask;
1541 int retries = 20;
1542 int pair, ret;
1543
1544 if (phydev->phy_id == ATH9331_PHY_ID ||
1545 phydev->phy_id == ATH8032_PHY_ID ||
1546 phydev->phy_id == QCA9561_PHY_ID)
1547 pair_mask = 0x3;
1548 else
1549 pair_mask = 0xf;
1550
1551 *finished = false;
1552
1553 /* According to the datasheet the CDT can be performed when
1554 * there is no link partner or when the link partner is
1555 * auto-negotiating. Starting the test will restart the AN
1556 * automatically. It seems that doing this repeatedly we will
1557 * get a slot where our link partner won't disturb our
1558 * measurement.
1559 */
1560 while (pair_mask && retries--) {
1561 for_each_set_bit(pair, &pair_mask, 4) {
1562 ret = at803x_cable_test_one_pair(phydev, pair);
1563 if (ret < 0)
1564 return ret;
1565 if (ret)
1566 clear_bit(nr: pair, addr: &pair_mask);
1567 }
1568 if (pair_mask)
1569 msleep(msecs: 250);
1570 }
1571
1572 *finished = true;
1573
1574 return 0;
1575}
1576
1577static int at803x_cable_test_start(struct phy_device *phydev)
1578{
1579 /* Enable auto-negotiation, but advertise no capabilities, no link
1580 * will be established. A restart of the auto-negotiation is not
1581 * required, because the cable test will automatically break the link.
1582 */
1583 phy_write(phydev, MII_BMCR, BMCR_ANENABLE);
1584 phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA);
1585 if (phydev->phy_id != ATH9331_PHY_ID &&
1586 phydev->phy_id != ATH8032_PHY_ID &&
1587 phydev->phy_id != QCA9561_PHY_ID)
1588 phy_write(phydev, MII_CTRL1000, val: 0);
1589
1590 /* we do all the (time consuming) work later */
1591 return 0;
1592}
1593
1594static int qca83xx_config_init(struct phy_device *phydev)
1595{
1596 u8 switch_revision;
1597
1598 switch_revision = phydev->dev_flags & QCA8K_DEVFLAGS_REVISION_MASK;
1599
1600 switch (switch_revision) {
1601 case 1:
1602 /* For 100M waveform */
1603 at803x_debug_reg_write(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, data: 0x02ea);
1604 /* Turn on Gigabit clock */
1605 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, data: 0x68a0);
1606 break;
1607
1608 case 2:
1609 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val: 0x0);
1610 fallthrough;
1611 case 4:
1612 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, val: 0x803f);
1613 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, data: 0x6860);
1614 at803x_debug_reg_write(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, data: 0x2c46);
1615 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3C, data: 0x6000);
1616 break;
1617 }
1618
1619 /* QCA8327 require DAC amplitude adjustment for 100m set to +6%.
1620 * Disable on init and enable only with 100m speed following
1621 * qca original source code.
1622 */
1623 if (phydev->drv->phy_id == QCA8327_A_PHY_ID ||
1624 phydev->drv->phy_id == QCA8327_B_PHY_ID)
1625 at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
1626 QCA8327_DEBUG_MANU_CTRL_EN, set: 0);
1627
1628 /* Following original QCA sourcecode set port to prefer master */
1629 phy_set_bits(phydev, MII_CTRL1000, CTL1000_PREFER_MASTER);
1630
1631 return 0;
1632}
1633
1634static void qca83xx_link_change_notify(struct phy_device *phydev)
1635{
1636 /* QCA8337 doesn't require DAC Amplitude adjustement */
1637 if (phydev->drv->phy_id == QCA8337_PHY_ID)
1638 return;
1639
1640 /* Set DAC Amplitude adjustment to +6% for 100m on link running */
1641 if (phydev->state == PHY_RUNNING) {
1642 if (phydev->speed == SPEED_100)
1643 at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
1644 QCA8327_DEBUG_MANU_CTRL_EN,
1645 QCA8327_DEBUG_MANU_CTRL_EN);
1646 } else {
1647 /* Reset DAC Amplitude adjustment */
1648 at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
1649 QCA8327_DEBUG_MANU_CTRL_EN, set: 0);
1650 }
1651}
1652
1653static int qca83xx_resume(struct phy_device *phydev)
1654{
1655 int ret, val;
1656
1657 /* Skip reset if not suspended */
1658 if (!phydev->suspended)
1659 return 0;
1660
1661 /* Reinit the port, reset values set by suspend */
1662 qca83xx_config_init(phydev);
1663
1664 /* Reset the port on port resume */
1665 phy_set_bits(phydev, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
1666
1667 /* On resume from suspend the switch execute a reset and
1668 * restart auto-negotiation. Wait for reset to complete.
1669 */
1670 ret = phy_read_poll_timeout(phydev, MII_BMCR, val, !(val & BMCR_RESET),
1671 50000, 600000, true);
1672 if (ret)
1673 return ret;
1674
1675 msleep(msecs: 1);
1676
1677 return 0;
1678}
1679
1680static int qca83xx_suspend(struct phy_device *phydev)
1681{
1682 u16 mask = 0;
1683
1684 /* Only QCA8337 support actual suspend.
1685 * QCA8327 cause port unreliability when phy suspend
1686 * is set.
1687 */
1688 if (phydev->drv->phy_id == QCA8337_PHY_ID) {
1689 genphy_suspend(phydev);
1690 } else {
1691 mask |= ~(BMCR_SPEED1000 | BMCR_FULLDPLX);
1692 phy_modify(phydev, MII_BMCR, mask, set: 0);
1693 }
1694
1695 at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_GREEN,
1696 AT803X_DEBUG_GATE_CLK_IN1000, set: 0);
1697
1698 at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL,
1699 AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE |
1700 AT803X_DEBUG_HIB_CTRL_SEL_RST_80U, set: 0);
1701
1702 return 0;
1703}
1704
1705static int qca808x_phy_fast_retrain_config(struct phy_device *phydev)
1706{
1707 int ret;
1708
1709 /* Enable fast retrain */
1710 ret = genphy_c45_fast_retrain(phydev, enable: true);
1711 if (ret)
1712 return ret;
1713
1714 phy_write_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_TOP_OPTION1,
1715 QCA808X_TOP_OPTION1_DATA);
1716 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB,
1717 QCA808X_MSE_THRESHOLD_20DB_VALUE);
1718 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB,
1719 QCA808X_MSE_THRESHOLD_17DB_VALUE);
1720 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB,
1721 QCA808X_MSE_THRESHOLD_27DB_VALUE);
1722 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB,
1723 QCA808X_MSE_THRESHOLD_28DB_VALUE);
1724 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_1,
1725 QCA808X_MMD3_DEBUG_1_VALUE);
1726 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_4,
1727 QCA808X_MMD3_DEBUG_4_VALUE);
1728 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_5,
1729 QCA808X_MMD3_DEBUG_5_VALUE);
1730 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_3,
1731 QCA808X_MMD3_DEBUG_3_VALUE);
1732 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_6,
1733 QCA808X_MMD3_DEBUG_6_VALUE);
1734 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_2,
1735 QCA808X_MMD3_DEBUG_2_VALUE);
1736
1737 return 0;
1738}
1739
1740static int qca808x_phy_ms_seed_enable(struct phy_device *phydev, bool enable)
1741{
1742 u16 seed_value;
1743
1744 if (!enable)
1745 return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED,
1746 QCA808X_MASTER_SLAVE_SEED_ENABLE, set: 0);
1747
1748 seed_value = get_random_u32_below(QCA808X_MASTER_SLAVE_SEED_RANGE);
1749 return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED,
1750 QCA808X_MASTER_SLAVE_SEED_CFG | QCA808X_MASTER_SLAVE_SEED_ENABLE,
1751 FIELD_PREP(QCA808X_MASTER_SLAVE_SEED_CFG, seed_value) |
1752 QCA808X_MASTER_SLAVE_SEED_ENABLE);
1753}
1754
1755static bool qca808x_is_prefer_master(struct phy_device *phydev)
1756{
1757 return (phydev->master_slave_get == MASTER_SLAVE_CFG_MASTER_FORCE) ||
1758 (phydev->master_slave_get == MASTER_SLAVE_CFG_MASTER_PREFERRED);
1759}
1760
1761static bool qca808x_has_fast_retrain_or_slave_seed(struct phy_device *phydev)
1762{
1763 return linkmode_test_bit(nr: ETHTOOL_LINK_MODE_2500baseT_Full_BIT, addr: phydev->supported);
1764}
1765
1766static int qca808x_config_init(struct phy_device *phydev)
1767{
1768 int ret;
1769
1770 /* Active adc&vga on 802.3az for the link 1000M and 100M */
1771 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_ADDR_CLD_CTRL7,
1772 QCA808X_8023AZ_AFE_CTRL_MASK, QCA808X_8023AZ_AFE_EN);
1773 if (ret)
1774 return ret;
1775
1776 /* Adjust the threshold on 802.3az for the link 1000M */
1777 ret = phy_write_mmd(phydev, MDIO_MMD_PCS,
1778 QCA808X_PHY_MMD3_AZ_TRAINING_CTRL, QCA808X_MMD3_AZ_TRAINING_VAL);
1779 if (ret)
1780 return ret;
1781
1782 if (qca808x_has_fast_retrain_or_slave_seed(phydev)) {
1783 /* Config the fast retrain for the link 2500M */
1784 ret = qca808x_phy_fast_retrain_config(phydev);
1785 if (ret)
1786 return ret;
1787
1788 ret = genphy_read_master_slave(phydev);
1789 if (ret < 0)
1790 return ret;
1791
1792 if (!qca808x_is_prefer_master(phydev)) {
1793 /* Enable seed and configure lower ramdom seed to make phy
1794 * linked as slave mode.
1795 */
1796 ret = qca808x_phy_ms_seed_enable(phydev, enable: true);
1797 if (ret)
1798 return ret;
1799 }
1800 }
1801
1802 /* Configure adc threshold as 100mv for the link 10M */
1803 return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_ADC_THRESHOLD,
1804 QCA808X_ADC_THRESHOLD_MASK, QCA808X_ADC_THRESHOLD_100MV);
1805}
1806
1807static int qca808x_read_status(struct phy_device *phydev)
1808{
1809 int ret;
1810
1811 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT);
1812 if (ret < 0)
1813 return ret;
1814
1815 linkmode_mod_bit(nr: ETHTOOL_LINK_MODE_2500baseT_Full_BIT, addr: phydev->lp_advertising,
1816 set: ret & MDIO_AN_10GBT_STAT_LP2_5G);
1817
1818 ret = genphy_read_status(phydev);
1819 if (ret)
1820 return ret;
1821
1822 ret = at803x_read_specific_status(phydev);
1823 if (ret < 0)
1824 return ret;
1825
1826 if (phydev->link) {
1827 if (phydev->speed == SPEED_2500)
1828 phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
1829 else
1830 phydev->interface = PHY_INTERFACE_MODE_SGMII;
1831 } else {
1832 /* generate seed as a lower random value to make PHY linked as SLAVE easily,
1833 * except for master/slave configuration fault detected or the master mode
1834 * preferred.
1835 *
1836 * the reason for not putting this code into the function link_change_notify is
1837 * the corner case where the link partner is also the qca8081 PHY and the seed
1838 * value is configured as the same value, the link can't be up and no link change
1839 * occurs.
1840 */
1841 if (qca808x_has_fast_retrain_or_slave_seed(phydev)) {
1842 if (phydev->master_slave_state == MASTER_SLAVE_STATE_ERR ||
1843 qca808x_is_prefer_master(phydev)) {
1844 qca808x_phy_ms_seed_enable(phydev, enable: false);
1845 } else {
1846 qca808x_phy_ms_seed_enable(phydev, enable: true);
1847 }
1848 }
1849 }
1850
1851 return 0;
1852}
1853
1854static int qca808x_soft_reset(struct phy_device *phydev)
1855{
1856 int ret;
1857
1858 ret = genphy_soft_reset(phydev);
1859 if (ret < 0)
1860 return ret;
1861
1862 if (qca808x_has_fast_retrain_or_slave_seed(phydev))
1863 ret = qca808x_phy_ms_seed_enable(phydev, enable: true);
1864
1865 return ret;
1866}
1867
1868static bool qca808x_cdt_fault_length_valid(int cdt_code)
1869{
1870 switch (cdt_code) {
1871 case QCA808X_CDT_STATUS_STAT_SHORT:
1872 case QCA808X_CDT_STATUS_STAT_OPEN:
1873 return true;
1874 default:
1875 return false;
1876 }
1877}
1878
1879static int qca808x_cable_test_result_trans(int cdt_code)
1880{
1881 switch (cdt_code) {
1882 case QCA808X_CDT_STATUS_STAT_NORMAL:
1883 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
1884 case QCA808X_CDT_STATUS_STAT_SHORT:
1885 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
1886 case QCA808X_CDT_STATUS_STAT_OPEN:
1887 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
1888 case QCA808X_CDT_STATUS_STAT_FAIL:
1889 default:
1890 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
1891 }
1892}
1893
1894static int qca808x_cdt_fault_length(struct phy_device *phydev, int pair)
1895{
1896 int val;
1897 u32 cdt_length_reg = 0;
1898
1899 switch (pair) {
1900 case ETHTOOL_A_CABLE_PAIR_A:
1901 cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_A;
1902 break;
1903 case ETHTOOL_A_CABLE_PAIR_B:
1904 cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_B;
1905 break;
1906 case ETHTOOL_A_CABLE_PAIR_C:
1907 cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_C;
1908 break;
1909 case ETHTOOL_A_CABLE_PAIR_D:
1910 cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_D;
1911 break;
1912 default:
1913 return -EINVAL;
1914 }
1915
1916 val = phy_read_mmd(phydev, MDIO_MMD_PCS, regnum: cdt_length_reg);
1917 if (val < 0)
1918 return val;
1919
1920 return (FIELD_GET(QCA808X_CDT_DIAG_LENGTH, val) * 824) / 10;
1921}
1922
1923static int qca808x_cable_test_start(struct phy_device *phydev)
1924{
1925 int ret;
1926
1927 /* perform CDT with the following configs:
1928 * 1. disable hibernation.
1929 * 2. force PHY working in MDI mode.
1930 * 3. for PHY working in 1000BaseT.
1931 * 4. configure the threshold.
1932 */
1933
1934 ret = at803x_debug_reg_mask(phydev, QCA808X_DBG_AN_TEST, QCA808X_HIBERNATION_EN, set: 0);
1935 if (ret < 0)
1936 return ret;
1937
1938 ret = at803x_config_mdix(phydev, ETH_TP_MDI);
1939 if (ret < 0)
1940 return ret;
1941
1942 /* Force 1000base-T needs to configure PMA/PMD and MII_BMCR */
1943 phydev->duplex = DUPLEX_FULL;
1944 phydev->speed = SPEED_1000;
1945 ret = genphy_c45_pma_setup_forced(phydev);
1946 if (ret < 0)
1947 return ret;
1948
1949 ret = genphy_setup_forced(phydev);
1950 if (ret < 0)
1951 return ret;
1952
1953 /* configure the thresholds for open, short, pair ok test */
1954 phy_write_mmd(phydev, MDIO_MMD_PCS, regnum: 0x8074, val: 0xc040);
1955 phy_write_mmd(phydev, MDIO_MMD_PCS, regnum: 0x8076, val: 0xc040);
1956 phy_write_mmd(phydev, MDIO_MMD_PCS, regnum: 0x8077, val: 0xa060);
1957 phy_write_mmd(phydev, MDIO_MMD_PCS, regnum: 0x8078, val: 0xc050);
1958 phy_write_mmd(phydev, MDIO_MMD_PCS, regnum: 0x807a, val: 0xc060);
1959 phy_write_mmd(phydev, MDIO_MMD_PCS, regnum: 0x807e, val: 0xb060);
1960
1961 return 0;
1962}
1963
1964static int qca808x_cable_test_get_status(struct phy_device *phydev, bool *finished)
1965{
1966 int ret, val;
1967 int pair_a, pair_b, pair_c, pair_d;
1968
1969 *finished = false;
1970
1971 ret = at803x_cdt_start(phydev, pair: 0);
1972 if (ret)
1973 return ret;
1974
1975 ret = at803x_cdt_wait_for_completion(phydev);
1976 if (ret)
1977 return ret;
1978
1979 val = phy_read_mmd(phydev, MDIO_MMD_PCS, QCA808X_MMD3_CDT_STATUS);
1980 if (val < 0)
1981 return val;
1982
1983 pair_a = FIELD_GET(QCA808X_CDT_CODE_PAIR_A, val);
1984 pair_b = FIELD_GET(QCA808X_CDT_CODE_PAIR_B, val);
1985 pair_c = FIELD_GET(QCA808X_CDT_CODE_PAIR_C, val);
1986 pair_d = FIELD_GET(QCA808X_CDT_CODE_PAIR_D, val);
1987
1988 ethnl_cable_test_result(phydev, pair: ETHTOOL_A_CABLE_PAIR_A,
1989 result: qca808x_cable_test_result_trans(cdt_code: pair_a));
1990 ethnl_cable_test_result(phydev, pair: ETHTOOL_A_CABLE_PAIR_B,
1991 result: qca808x_cable_test_result_trans(cdt_code: pair_b));
1992 ethnl_cable_test_result(phydev, pair: ETHTOOL_A_CABLE_PAIR_C,
1993 result: qca808x_cable_test_result_trans(cdt_code: pair_c));
1994 ethnl_cable_test_result(phydev, pair: ETHTOOL_A_CABLE_PAIR_D,
1995 result: qca808x_cable_test_result_trans(cdt_code: pair_d));
1996
1997 if (qca808x_cdt_fault_length_valid(cdt_code: pair_a))
1998 ethnl_cable_test_fault_length(phydev, pair: ETHTOOL_A_CABLE_PAIR_A,
1999 cm: qca808x_cdt_fault_length(phydev, pair: ETHTOOL_A_CABLE_PAIR_A));
2000 if (qca808x_cdt_fault_length_valid(cdt_code: pair_b))
2001 ethnl_cable_test_fault_length(phydev, pair: ETHTOOL_A_CABLE_PAIR_B,
2002 cm: qca808x_cdt_fault_length(phydev, pair: ETHTOOL_A_CABLE_PAIR_B));
2003 if (qca808x_cdt_fault_length_valid(cdt_code: pair_c))
2004 ethnl_cable_test_fault_length(phydev, pair: ETHTOOL_A_CABLE_PAIR_C,
2005 cm: qca808x_cdt_fault_length(phydev, pair: ETHTOOL_A_CABLE_PAIR_C));
2006 if (qca808x_cdt_fault_length_valid(cdt_code: pair_d))
2007 ethnl_cable_test_fault_length(phydev, pair: ETHTOOL_A_CABLE_PAIR_D,
2008 cm: qca808x_cdt_fault_length(phydev, pair: ETHTOOL_A_CABLE_PAIR_D));
2009
2010 *finished = true;
2011
2012 return 0;
2013}
2014
2015static int qca808x_get_features(struct phy_device *phydev)
2016{
2017 int ret;
2018
2019 ret = genphy_c45_pma_read_abilities(phydev);
2020 if (ret)
2021 return ret;
2022
2023 /* The autoneg ability is not existed in bit3 of MMD7.1,
2024 * but it is supported by qca808x PHY, so we add it here
2025 * manually.
2026 */
2027 linkmode_set_bit(nr: ETHTOOL_LINK_MODE_Autoneg_BIT, addr: phydev->supported);
2028
2029 /* As for the qca8081 1G version chip, the 2500baseT ability is also
2030 * existed in the bit0 of MMD1.21, we need to remove it manually if
2031 * it is the qca8081 1G chip according to the bit0 of MMD7.0x901d.
2032 */
2033 ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_CHIP_TYPE);
2034 if (ret < 0)
2035 return ret;
2036
2037 if (QCA808X_PHY_CHIP_TYPE_1G & ret)
2038 linkmode_clear_bit(nr: ETHTOOL_LINK_MODE_2500baseT_Full_BIT, addr: phydev->supported);
2039
2040 return 0;
2041}
2042
2043static void qca808x_link_change_notify(struct phy_device *phydev)
2044{
2045 /* Assert interface sgmii fifo on link down, deassert it on link up,
2046 * the interface device address is always phy address added by 1.
2047 */
2048 mdiobus_c45_modify_changed(bus: phydev->mdio.bus, addr: phydev->mdio.addr + 1,
2049 MDIO_MMD_PMAPMD, QCA8081_PHY_SERDES_MMD1_FIFO_CTRL,
2050 QCA8081_PHY_FIFO_RSTN, set: phydev->link ? QCA8081_PHY_FIFO_RSTN : 0);
2051}
2052
2053static struct phy_driver at803x_driver[] = {
2054{
2055 /* Qualcomm Atheros AR8035 */
2056 PHY_ID_MATCH_EXACT(ATH8035_PHY_ID),
2057 .name = "Qualcomm Atheros AR8035",
2058 .flags = PHY_POLL_CABLE_TEST,
2059 .probe = at803x_probe,
2060 .config_aneg = at803x_config_aneg,
2061 .config_init = at803x_config_init,
2062 .soft_reset = genphy_soft_reset,
2063 .set_wol = at803x_set_wol,
2064 .get_wol = at803x_get_wol,
2065 .suspend = at803x_suspend,
2066 .resume = at803x_resume,
2067 /* PHY_GBIT_FEATURES */
2068 .read_status = at803x_read_status,
2069 .config_intr = at803x_config_intr,
2070 .handle_interrupt = at803x_handle_interrupt,
2071 .get_tunable = at803x_get_tunable,
2072 .set_tunable = at803x_set_tunable,
2073 .cable_test_start = at803x_cable_test_start,
2074 .cable_test_get_status = at803x_cable_test_get_status,
2075}, {
2076 /* Qualcomm Atheros AR8030 */
2077 .phy_id = ATH8030_PHY_ID,
2078 .name = "Qualcomm Atheros AR8030",
2079 .phy_id_mask = AT8030_PHY_ID_MASK,
2080 .probe = at803x_probe,
2081 .config_init = at803x_config_init,
2082 .link_change_notify = at803x_link_change_notify,
2083 .set_wol = at803x_set_wol,
2084 .get_wol = at803x_get_wol,
2085 .suspend = at803x_suspend,
2086 .resume = at803x_resume,
2087 /* PHY_BASIC_FEATURES */
2088 .config_intr = at803x_config_intr,
2089 .handle_interrupt = at803x_handle_interrupt,
2090}, {
2091 /* Qualcomm Atheros AR8031/AR8033 */
2092 PHY_ID_MATCH_EXACT(ATH8031_PHY_ID),
2093 .name = "Qualcomm Atheros AR8031/AR8033",
2094 .flags = PHY_POLL_CABLE_TEST,
2095 .probe = at803x_probe,
2096 .config_init = at803x_config_init,
2097 .config_aneg = at803x_config_aneg,
2098 .soft_reset = genphy_soft_reset,
2099 .set_wol = at803x_set_wol,
2100 .get_wol = at803x_get_wol,
2101 .suspend = at803x_suspend,
2102 .resume = at803x_resume,
2103 .read_page = at803x_read_page,
2104 .write_page = at803x_write_page,
2105 .get_features = at803x_get_features,
2106 .read_status = at803x_read_status,
2107 .config_intr = &at803x_config_intr,
2108 .handle_interrupt = at803x_handle_interrupt,
2109 .get_tunable = at803x_get_tunable,
2110 .set_tunable = at803x_set_tunable,
2111 .cable_test_start = at803x_cable_test_start,
2112 .cable_test_get_status = at803x_cable_test_get_status,
2113}, {
2114 /* Qualcomm Atheros AR8032 */
2115 PHY_ID_MATCH_EXACT(ATH8032_PHY_ID),
2116 .name = "Qualcomm Atheros AR8032",
2117 .probe = at803x_probe,
2118 .flags = PHY_POLL_CABLE_TEST,
2119 .config_init = at803x_config_init,
2120 .link_change_notify = at803x_link_change_notify,
2121 .suspend = at803x_suspend,
2122 .resume = at803x_resume,
2123 /* PHY_BASIC_FEATURES */
2124 .config_intr = at803x_config_intr,
2125 .handle_interrupt = at803x_handle_interrupt,
2126 .cable_test_start = at803x_cable_test_start,
2127 .cable_test_get_status = at803x_cable_test_get_status,
2128}, {
2129 /* ATHEROS AR9331 */
2130 PHY_ID_MATCH_EXACT(ATH9331_PHY_ID),
2131 .name = "Qualcomm Atheros AR9331 built-in PHY",
2132 .probe = at803x_probe,
2133 .suspend = at803x_suspend,
2134 .resume = at803x_resume,
2135 .flags = PHY_POLL_CABLE_TEST,
2136 /* PHY_BASIC_FEATURES */
2137 .config_intr = &at803x_config_intr,
2138 .handle_interrupt = at803x_handle_interrupt,
2139 .cable_test_start = at803x_cable_test_start,
2140 .cable_test_get_status = at803x_cable_test_get_status,
2141 .read_status = at803x_read_status,
2142 .soft_reset = genphy_soft_reset,
2143 .config_aneg = at803x_config_aneg,
2144}, {
2145 /* Qualcomm Atheros QCA9561 */
2146 PHY_ID_MATCH_EXACT(QCA9561_PHY_ID),
2147 .name = "Qualcomm Atheros QCA9561 built-in PHY",
2148 .probe = at803x_probe,
2149 .suspend = at803x_suspend,
2150 .resume = at803x_resume,
2151 .flags = PHY_POLL_CABLE_TEST,
2152 /* PHY_BASIC_FEATURES */
2153 .config_intr = &at803x_config_intr,
2154 .handle_interrupt = at803x_handle_interrupt,
2155 .cable_test_start = at803x_cable_test_start,
2156 .cable_test_get_status = at803x_cable_test_get_status,
2157 .read_status = at803x_read_status,
2158 .soft_reset = genphy_soft_reset,
2159 .config_aneg = at803x_config_aneg,
2160}, {
2161 /* QCA8337 */
2162 .phy_id = QCA8337_PHY_ID,
2163 .phy_id_mask = QCA8K_PHY_ID_MASK,
2164 .name = "Qualcomm Atheros 8337 internal PHY",
2165 /* PHY_GBIT_FEATURES */
2166 .link_change_notify = qca83xx_link_change_notify,
2167 .probe = at803x_probe,
2168 .flags = PHY_IS_INTERNAL,
2169 .config_init = qca83xx_config_init,
2170 .soft_reset = genphy_soft_reset,
2171 .get_sset_count = at803x_get_sset_count,
2172 .get_strings = at803x_get_strings,
2173 .get_stats = at803x_get_stats,
2174 .suspend = qca83xx_suspend,
2175 .resume = qca83xx_resume,
2176}, {
2177 /* QCA8327-A from switch QCA8327-AL1A */
2178 .phy_id = QCA8327_A_PHY_ID,
2179 .phy_id_mask = QCA8K_PHY_ID_MASK,
2180 .name = "Qualcomm Atheros 8327-A internal PHY",
2181 /* PHY_GBIT_FEATURES */
2182 .link_change_notify = qca83xx_link_change_notify,
2183 .probe = at803x_probe,
2184 .flags = PHY_IS_INTERNAL,
2185 .config_init = qca83xx_config_init,
2186 .soft_reset = genphy_soft_reset,
2187 .get_sset_count = at803x_get_sset_count,
2188 .get_strings = at803x_get_strings,
2189 .get_stats = at803x_get_stats,
2190 .suspend = qca83xx_suspend,
2191 .resume = qca83xx_resume,
2192}, {
2193 /* QCA8327-B from switch QCA8327-BL1A */
2194 .phy_id = QCA8327_B_PHY_ID,
2195 .phy_id_mask = QCA8K_PHY_ID_MASK,
2196 .name = "Qualcomm Atheros 8327-B internal PHY",
2197 /* PHY_GBIT_FEATURES */
2198 .link_change_notify = qca83xx_link_change_notify,
2199 .probe = at803x_probe,
2200 .flags = PHY_IS_INTERNAL,
2201 .config_init = qca83xx_config_init,
2202 .soft_reset = genphy_soft_reset,
2203 .get_sset_count = at803x_get_sset_count,
2204 .get_strings = at803x_get_strings,
2205 .get_stats = at803x_get_stats,
2206 .suspend = qca83xx_suspend,
2207 .resume = qca83xx_resume,
2208}, {
2209 /* Qualcomm QCA8081 */
2210 PHY_ID_MATCH_EXACT(QCA8081_PHY_ID),
2211 .name = "Qualcomm QCA8081",
2212 .flags = PHY_POLL_CABLE_TEST,
2213 .probe = at803x_probe,
2214 .config_intr = at803x_config_intr,
2215 .handle_interrupt = at803x_handle_interrupt,
2216 .get_tunable = at803x_get_tunable,
2217 .set_tunable = at803x_set_tunable,
2218 .set_wol = at803x_set_wol,
2219 .get_wol = at803x_get_wol,
2220 .get_features = qca808x_get_features,
2221 .config_aneg = at803x_config_aneg,
2222 .suspend = genphy_suspend,
2223 .resume = genphy_resume,
2224 .read_status = qca808x_read_status,
2225 .config_init = qca808x_config_init,
2226 .soft_reset = qca808x_soft_reset,
2227 .cable_test_start = qca808x_cable_test_start,
2228 .cable_test_get_status = qca808x_cable_test_get_status,
2229 .link_change_notify = qca808x_link_change_notify,
2230}, };
2231
2232module_phy_driver(at803x_driver);
2233
2234static struct mdio_device_id __maybe_unused atheros_tbl[] = {
2235 { ATH8030_PHY_ID, AT8030_PHY_ID_MASK },
2236 { PHY_ID_MATCH_EXACT(ATH8031_PHY_ID) },
2237 { PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) },
2238 { PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) },
2239 { PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) },
2240 { PHY_ID_MATCH_EXACT(QCA8337_PHY_ID) },
2241 { PHY_ID_MATCH_EXACT(QCA8327_A_PHY_ID) },
2242 { PHY_ID_MATCH_EXACT(QCA8327_B_PHY_ID) },
2243 { PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) },
2244 { PHY_ID_MATCH_EXACT(QCA8081_PHY_ID) },
2245 { }
2246};
2247
2248MODULE_DEVICE_TABLE(mdio, atheros_tbl);
2249

source code of linux/drivers/net/phy/at803x.c