1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | /* |
3 | * drivers/net/phy/micrel.c |
4 | * |
5 | * Driver for Micrel PHYs |
6 | * |
7 | * Author: David J. Choi |
8 | * |
9 | * Copyright (c) 2010-2013 Micrel, Inc. |
10 | * Copyright (c) 2014 Johan Hovold <johan@kernel.org> |
11 | * |
12 | * Support : Micrel Phys: |
13 | * Giga phys: ksz9021, ksz9031, ksz9131, lan8841, lan8814 |
14 | * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041 |
15 | * ksz8021, ksz8031, ksz8051, |
16 | * ksz8081, ksz8091, |
17 | * ksz8061, |
18 | * Switch : ksz8873, ksz886x |
19 | * ksz9477, lan8804 |
20 | */ |
21 | |
22 | #include <linux/bitfield.h> |
23 | #include <linux/ethtool_netlink.h> |
24 | #include <linux/kernel.h> |
25 | #include <linux/module.h> |
26 | #include <linux/phy.h> |
27 | #include <linux/micrel_phy.h> |
28 | #include <linux/of.h> |
29 | #include <linux/clk.h> |
30 | #include <linux/delay.h> |
31 | #include <linux/ptp_clock_kernel.h> |
32 | #include <linux/ptp_clock.h> |
33 | #include <linux/ptp_classify.h> |
34 | #include <linux/net_tstamp.h> |
35 | #include <linux/gpio/consumer.h> |
36 | |
37 | /* Operation Mode Strap Override */ |
38 | #define MII_KSZPHY_OMSO 0x16 |
39 | #define KSZPHY_OMSO_FACTORY_TEST BIT(15) |
40 | #define KSZPHY_OMSO_B_CAST_OFF BIT(9) |
41 | #define KSZPHY_OMSO_NAND_TREE_ON BIT(5) |
42 | #define KSZPHY_OMSO_RMII_OVERRIDE BIT(1) |
43 | #define KSZPHY_OMSO_MII_OVERRIDE BIT(0) |
44 | |
45 | /* general Interrupt control/status reg in vendor specific block. */ |
46 | #define MII_KSZPHY_INTCS 0x1B |
47 | #define KSZPHY_INTCS_JABBER BIT(15) |
48 | #define KSZPHY_INTCS_RECEIVE_ERR BIT(14) |
49 | #define KSZPHY_INTCS_PAGE_RECEIVE BIT(13) |
50 | #define KSZPHY_INTCS_PARELLEL BIT(12) |
51 | #define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11) |
52 | #define KSZPHY_INTCS_LINK_DOWN BIT(10) |
53 | #define KSZPHY_INTCS_REMOTE_FAULT BIT(9) |
54 | #define KSZPHY_INTCS_LINK_UP BIT(8) |
55 | #define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\ |
56 | KSZPHY_INTCS_LINK_DOWN) |
57 | #define KSZPHY_INTCS_LINK_DOWN_STATUS BIT(2) |
58 | #define KSZPHY_INTCS_LINK_UP_STATUS BIT(0) |
59 | #define KSZPHY_INTCS_STATUS (KSZPHY_INTCS_LINK_DOWN_STATUS |\ |
60 | KSZPHY_INTCS_LINK_UP_STATUS) |
61 | |
62 | /* LinkMD Control/Status */ |
63 | #define KSZ8081_LMD 0x1d |
64 | #define KSZ8081_LMD_ENABLE_TEST BIT(15) |
65 | #define KSZ8081_LMD_STAT_NORMAL 0 |
66 | #define KSZ8081_LMD_STAT_OPEN 1 |
67 | #define KSZ8081_LMD_STAT_SHORT 2 |
68 | #define KSZ8081_LMD_STAT_FAIL 3 |
69 | #define KSZ8081_LMD_STAT_MASK GENMASK(14, 13) |
70 | /* Short cable (<10 meter) has been detected by LinkMD */ |
71 | #define KSZ8081_LMD_SHORT_INDICATOR BIT(12) |
72 | #define KSZ8081_LMD_DELTA_TIME_MASK GENMASK(8, 0) |
73 | |
74 | #define KSZ9x31_LMD 0x12 |
75 | #define KSZ9x31_LMD_VCT_EN BIT(15) |
76 | #define KSZ9x31_LMD_VCT_DIS_TX BIT(14) |
77 | #define KSZ9x31_LMD_VCT_PAIR(n) (((n) & 0x3) << 12) |
78 | #define KSZ9x31_LMD_VCT_SEL_RESULT 0 |
79 | #define KSZ9x31_LMD_VCT_SEL_THRES_HI BIT(10) |
80 | #define KSZ9x31_LMD_VCT_SEL_THRES_LO BIT(11) |
81 | #define KSZ9x31_LMD_VCT_SEL_MASK GENMASK(11, 10) |
82 | #define KSZ9x31_LMD_VCT_ST_NORMAL 0 |
83 | #define KSZ9x31_LMD_VCT_ST_OPEN 1 |
84 | #define KSZ9x31_LMD_VCT_ST_SHORT 2 |
85 | #define KSZ9x31_LMD_VCT_ST_FAIL 3 |
86 | #define KSZ9x31_LMD_VCT_ST_MASK GENMASK(9, 8) |
87 | #define KSZ9x31_LMD_VCT_DATA_REFLECTED_INVALID BIT(7) |
88 | #define KSZ9x31_LMD_VCT_DATA_SIG_WAIT_TOO_LONG BIT(6) |
89 | #define KSZ9x31_LMD_VCT_DATA_MASK100 BIT(5) |
90 | #define KSZ9x31_LMD_VCT_DATA_NLP_FLP BIT(4) |
91 | #define KSZ9x31_LMD_VCT_DATA_LO_PULSE_MASK GENMASK(3, 2) |
92 | #define KSZ9x31_LMD_VCT_DATA_HI_PULSE_MASK GENMASK(1, 0) |
93 | #define KSZ9x31_LMD_VCT_DATA_MASK GENMASK(7, 0) |
94 | |
95 | #define KSZPHY_WIRE_PAIR_MASK 0x3 |
96 | |
97 | #define LAN8814_CABLE_DIAG 0x12 |
98 | #define LAN8814_CABLE_DIAG_STAT_MASK GENMASK(9, 8) |
99 | #define LAN8814_CABLE_DIAG_VCT_DATA_MASK GENMASK(7, 0) |
100 | #define LAN8814_PAIR_BIT_SHIFT 12 |
101 | |
102 | #define LAN8814_WIRE_PAIR_MASK 0xF |
103 | |
104 | /* Lan8814 general Interrupt control/status reg in GPHY specific block. */ |
105 | #define LAN8814_INTC 0x18 |
106 | #define LAN8814_INTS 0x1B |
107 | |
108 | #define LAN8814_INT_LINK_DOWN BIT(2) |
109 | #define LAN8814_INT_LINK_UP BIT(0) |
110 | #define LAN8814_INT_LINK (LAN8814_INT_LINK_UP |\ |
111 | LAN8814_INT_LINK_DOWN) |
112 | |
113 | #define LAN8814_INTR_CTRL_REG 0x34 |
114 | #define LAN8814_INTR_CTRL_REG_POLARITY BIT(1) |
115 | #define LAN8814_INTR_CTRL_REG_INTR_ENABLE BIT(0) |
116 | |
117 | /* Represents 1ppm adjustment in 2^32 format with |
118 | * each nsec contains 4 clock cycles. |
119 | * The value is calculated as following: (1/1000000)/((2^-32)/4) |
120 | */ |
121 | #define LAN8814_1PPM_FORMAT 17179 |
122 | |
123 | #define PTP_RX_MOD 0x024F |
124 | #define PTP_RX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_ BIT(3) |
125 | #define PTP_RX_TIMESTAMP_EN 0x024D |
126 | #define PTP_TX_TIMESTAMP_EN 0x028D |
127 | |
128 | #define PTP_TIMESTAMP_EN_SYNC_ BIT(0) |
129 | #define PTP_TIMESTAMP_EN_DREQ_ BIT(1) |
130 | #define PTP_TIMESTAMP_EN_PDREQ_ BIT(2) |
131 | #define PTP_TIMESTAMP_EN_PDRES_ BIT(3) |
132 | |
133 | #define PTP_TX_PARSE_L2_ADDR_EN 0x0284 |
134 | #define PTP_RX_PARSE_L2_ADDR_EN 0x0244 |
135 | |
136 | #define PTP_TX_PARSE_IP_ADDR_EN 0x0285 |
137 | #define PTP_RX_PARSE_IP_ADDR_EN 0x0245 |
138 | #define LTC_HARD_RESET 0x023F |
139 | #define LTC_HARD_RESET_ BIT(0) |
140 | |
141 | #define TSU_HARD_RESET 0x02C1 |
142 | #define TSU_HARD_RESET_ BIT(0) |
143 | |
144 | #define PTP_CMD_CTL 0x0200 |
145 | #define PTP_CMD_CTL_PTP_DISABLE_ BIT(0) |
146 | #define PTP_CMD_CTL_PTP_ENABLE_ BIT(1) |
147 | #define PTP_CMD_CTL_PTP_CLOCK_READ_ BIT(3) |
148 | #define PTP_CMD_CTL_PTP_CLOCK_LOAD_ BIT(4) |
149 | #define PTP_CMD_CTL_PTP_LTC_STEP_SEC_ BIT(5) |
150 | #define PTP_CMD_CTL_PTP_LTC_STEP_NSEC_ BIT(6) |
151 | |
152 | #define PTP_CLOCK_SET_SEC_MID 0x0206 |
153 | #define PTP_CLOCK_SET_SEC_LO 0x0207 |
154 | #define PTP_CLOCK_SET_NS_HI 0x0208 |
155 | #define PTP_CLOCK_SET_NS_LO 0x0209 |
156 | |
157 | #define PTP_CLOCK_READ_SEC_MID 0x022A |
158 | #define PTP_CLOCK_READ_SEC_LO 0x022B |
159 | #define PTP_CLOCK_READ_NS_HI 0x022C |
160 | #define PTP_CLOCK_READ_NS_LO 0x022D |
161 | |
162 | #define PTP_OPERATING_MODE 0x0241 |
163 | #define PTP_OPERATING_MODE_STANDALONE_ BIT(0) |
164 | |
165 | #define PTP_TX_MOD 0x028F |
166 | #define PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_ BIT(12) |
167 | #define PTP_TX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_ BIT(3) |
168 | |
169 | #define PTP_RX_PARSE_CONFIG 0x0242 |
170 | #define PTP_RX_PARSE_CONFIG_LAYER2_EN_ BIT(0) |
171 | #define PTP_RX_PARSE_CONFIG_IPV4_EN_ BIT(1) |
172 | #define PTP_RX_PARSE_CONFIG_IPV6_EN_ BIT(2) |
173 | |
174 | #define PTP_TX_PARSE_CONFIG 0x0282 |
175 | #define PTP_TX_PARSE_CONFIG_LAYER2_EN_ BIT(0) |
176 | #define PTP_TX_PARSE_CONFIG_IPV4_EN_ BIT(1) |
177 | #define PTP_TX_PARSE_CONFIG_IPV6_EN_ BIT(2) |
178 | |
179 | #define PTP_CLOCK_RATE_ADJ_HI 0x020C |
180 | #define PTP_CLOCK_RATE_ADJ_LO 0x020D |
181 | #define PTP_CLOCK_RATE_ADJ_DIR_ BIT(15) |
182 | |
183 | #define PTP_LTC_STEP_ADJ_HI 0x0212 |
184 | #define PTP_LTC_STEP_ADJ_LO 0x0213 |
185 | #define PTP_LTC_STEP_ADJ_DIR_ BIT(15) |
186 | |
187 | #define LAN8814_INTR_STS_REG 0x0033 |
188 | #define LAN8814_INTR_STS_REG_1588_TSU0_ BIT(0) |
189 | #define LAN8814_INTR_STS_REG_1588_TSU1_ BIT(1) |
190 | #define LAN8814_INTR_STS_REG_1588_TSU2_ BIT(2) |
191 | #define LAN8814_INTR_STS_REG_1588_TSU3_ BIT(3) |
192 | |
193 | #define PTP_CAP_INFO 0x022A |
194 | #define PTP_CAP_INFO_TX_TS_CNT_GET_(reg_val) (((reg_val) & 0x0f00) >> 8) |
195 | #define PTP_CAP_INFO_RX_TS_CNT_GET_(reg_val) ((reg_val) & 0x000f) |
196 | |
197 | #define PTP_TX_EGRESS_SEC_HI 0x0296 |
198 | #define PTP_TX_EGRESS_SEC_LO 0x0297 |
199 | #define PTP_TX_EGRESS_NS_HI 0x0294 |
200 | #define PTP_TX_EGRESS_NS_LO 0x0295 |
201 | #define 0x0299 |
202 | |
203 | #define PTP_RX_INGRESS_SEC_HI 0x0256 |
204 | #define PTP_RX_INGRESS_SEC_LO 0x0257 |
205 | #define PTP_RX_INGRESS_NS_HI 0x0254 |
206 | #define PTP_RX_INGRESS_NS_LO 0x0255 |
207 | #define 0x0259 |
208 | |
209 | #define PTP_TSU_INT_EN 0x0200 |
210 | #define PTP_TSU_INT_EN_PTP_TX_TS_OVRFL_EN_ BIT(3) |
211 | #define PTP_TSU_INT_EN_PTP_TX_TS_EN_ BIT(2) |
212 | #define PTP_TSU_INT_EN_PTP_RX_TS_OVRFL_EN_ BIT(1) |
213 | #define PTP_TSU_INT_EN_PTP_RX_TS_EN_ BIT(0) |
214 | |
215 | #define PTP_TSU_INT_STS 0x0201 |
216 | #define PTP_TSU_INT_STS_PTP_TX_TS_OVRFL_INT_ BIT(3) |
217 | #define PTP_TSU_INT_STS_PTP_TX_TS_EN_ BIT(2) |
218 | #define PTP_TSU_INT_STS_PTP_RX_TS_OVRFL_INT_ BIT(1) |
219 | #define PTP_TSU_INT_STS_PTP_RX_TS_EN_ BIT(0) |
220 | |
221 | #define LAN8814_LED_CTRL_1 0x0 |
222 | #define LAN8814_LED_CTRL_1_KSZ9031_LED_MODE_ BIT(6) |
223 | |
224 | /* PHY Control 1 */ |
225 | #define MII_KSZPHY_CTRL_1 0x1e |
226 | #define KSZ8081_CTRL1_MDIX_STAT BIT(4) |
227 | |
228 | /* PHY Control 2 / PHY Control (if no PHY Control 1) */ |
229 | #define MII_KSZPHY_CTRL_2 0x1f |
230 | #define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2 |
231 | /* bitmap of PHY register to set interrupt mode */ |
232 | #define KSZ8081_CTRL2_HP_MDIX BIT(15) |
233 | #define KSZ8081_CTRL2_MDI_MDI_X_SELECT BIT(14) |
234 | #define KSZ8081_CTRL2_DISABLE_AUTO_MDIX BIT(13) |
235 | #define KSZ8081_CTRL2_FORCE_LINK BIT(11) |
236 | #define KSZ8081_CTRL2_POWER_SAVING BIT(10) |
237 | #define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9) |
238 | #define KSZPHY_RMII_REF_CLK_SEL BIT(7) |
239 | |
240 | /* Write/read to/from extended registers */ |
241 | #define MII_KSZPHY_EXTREG 0x0b |
242 | #define KSZPHY_EXTREG_WRITE 0x8000 |
243 | |
244 | #define MII_KSZPHY_EXTREG_WRITE 0x0c |
245 | #define MII_KSZPHY_EXTREG_READ 0x0d |
246 | |
247 | /* Extended registers */ |
248 | #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104 |
249 | #define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105 |
250 | #define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106 |
251 | |
252 | #define PS_TO_REG 200 |
253 | #define FIFO_SIZE 8 |
254 | |
255 | /* Delay used to get the second part from the LTC */ |
256 | #define LAN8841_GET_SEC_LTC_DELAY (500 * NSEC_PER_MSEC) |
257 | |
258 | struct kszphy_hw_stat { |
259 | const char *string; |
260 | u8 reg; |
261 | u8 bits; |
262 | }; |
263 | |
264 | static struct kszphy_hw_stat kszphy_hw_stats[] = { |
265 | { "phy_receive_errors" , 21, 16}, |
266 | { "phy_idle_errors" , 10, 8 }, |
267 | }; |
268 | |
269 | struct kszphy_type { |
270 | u32 led_mode_reg; |
271 | u16 interrupt_level_mask; |
272 | u16 cable_diag_reg; |
273 | unsigned long pair_mask; |
274 | u16 disable_dll_tx_bit; |
275 | u16 disable_dll_rx_bit; |
276 | u16 disable_dll_mask; |
277 | bool has_broadcast_disable; |
278 | bool has_nand_tree_disable; |
279 | bool has_rmii_ref_clk_sel; |
280 | }; |
281 | |
282 | /* Shared structure between the PHYs of the same package. */ |
283 | struct lan8814_shared_priv { |
284 | struct phy_device *phydev; |
285 | struct ptp_clock *ptp_clock; |
286 | struct ptp_clock_info ptp_clock_info; |
287 | |
288 | /* Reference counter to how many ports in the package are enabling the |
289 | * timestamping |
290 | */ |
291 | u8 ref; |
292 | |
293 | /* Lock for ptp_clock and ref */ |
294 | struct mutex shared_lock; |
295 | }; |
296 | |
297 | struct lan8814_ptp_rx_ts { |
298 | struct list_head list; |
299 | u32 seconds; |
300 | u32 nsec; |
301 | u16 seq_id; |
302 | }; |
303 | |
304 | struct kszphy_ptp_priv { |
305 | struct mii_timestamper mii_ts; |
306 | struct phy_device *phydev; |
307 | |
308 | struct sk_buff_head tx_queue; |
309 | struct sk_buff_head rx_queue; |
310 | |
311 | struct list_head rx_ts_list; |
312 | /* Lock for Rx ts fifo */ |
313 | spinlock_t rx_ts_lock; |
314 | |
315 | int hwts_tx_type; |
316 | enum hwtstamp_rx_filters rx_filter; |
317 | int layer; |
318 | int version; |
319 | |
320 | struct ptp_clock *ptp_clock; |
321 | struct ptp_clock_info ptp_clock_info; |
322 | /* Lock for ptp_clock */ |
323 | struct mutex ptp_lock; |
324 | struct ptp_pin_desc *pin_config; |
325 | |
326 | s64 seconds; |
327 | /* Lock for accessing seconds */ |
328 | spinlock_t seconds_lock; |
329 | }; |
330 | |
331 | struct kszphy_priv { |
332 | struct kszphy_ptp_priv ptp_priv; |
333 | const struct kszphy_type *type; |
334 | int led_mode; |
335 | u16 vct_ctrl1000; |
336 | bool rmii_ref_clk_sel; |
337 | bool rmii_ref_clk_sel_val; |
338 | u64 stats[ARRAY_SIZE(kszphy_hw_stats)]; |
339 | }; |
340 | |
341 | static const struct kszphy_type lan8814_type = { |
342 | .led_mode_reg = ~LAN8814_LED_CTRL_1, |
343 | .cable_diag_reg = LAN8814_CABLE_DIAG, |
344 | .pair_mask = LAN8814_WIRE_PAIR_MASK, |
345 | }; |
346 | |
347 | static const struct kszphy_type ksz886x_type = { |
348 | .cable_diag_reg = KSZ8081_LMD, |
349 | .pair_mask = KSZPHY_WIRE_PAIR_MASK, |
350 | }; |
351 | |
352 | static const struct kszphy_type ksz8021_type = { |
353 | .led_mode_reg = MII_KSZPHY_CTRL_2, |
354 | .has_broadcast_disable = true, |
355 | .has_nand_tree_disable = true, |
356 | .has_rmii_ref_clk_sel = true, |
357 | }; |
358 | |
359 | static const struct kszphy_type ksz8041_type = { |
360 | .led_mode_reg = MII_KSZPHY_CTRL_1, |
361 | }; |
362 | |
363 | static const struct kszphy_type ksz8051_type = { |
364 | .led_mode_reg = MII_KSZPHY_CTRL_2, |
365 | .has_nand_tree_disable = true, |
366 | }; |
367 | |
368 | static const struct kszphy_type ksz8081_type = { |
369 | .led_mode_reg = MII_KSZPHY_CTRL_2, |
370 | .has_broadcast_disable = true, |
371 | .has_nand_tree_disable = true, |
372 | .has_rmii_ref_clk_sel = true, |
373 | }; |
374 | |
375 | static const struct kszphy_type ks8737_type = { |
376 | .interrupt_level_mask = BIT(14), |
377 | }; |
378 | |
379 | static const struct kszphy_type ksz9021_type = { |
380 | .interrupt_level_mask = BIT(14), |
381 | }; |
382 | |
383 | static const struct kszphy_type ksz9131_type = { |
384 | .interrupt_level_mask = BIT(14), |
385 | .disable_dll_tx_bit = BIT(12), |
386 | .disable_dll_rx_bit = BIT(12), |
387 | .disable_dll_mask = BIT_MASK(12), |
388 | }; |
389 | |
390 | static const struct kszphy_type lan8841_type = { |
391 | .disable_dll_tx_bit = BIT(14), |
392 | .disable_dll_rx_bit = BIT(14), |
393 | .disable_dll_mask = BIT_MASK(14), |
394 | .cable_diag_reg = LAN8814_CABLE_DIAG, |
395 | .pair_mask = LAN8814_WIRE_PAIR_MASK, |
396 | }; |
397 | |
398 | static int kszphy_extended_write(struct phy_device *phydev, |
399 | u32 regnum, u16 val) |
400 | { |
401 | phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum); |
402 | return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val); |
403 | } |
404 | |
405 | static int kszphy_extended_read(struct phy_device *phydev, |
406 | u32 regnum) |
407 | { |
408 | phy_write(phydev, MII_KSZPHY_EXTREG, val: regnum); |
409 | return phy_read(phydev, MII_KSZPHY_EXTREG_READ); |
410 | } |
411 | |
412 | static int kszphy_ack_interrupt(struct phy_device *phydev) |
413 | { |
414 | /* bit[7..0] int status, which is a read and clear register. */ |
415 | int rc; |
416 | |
417 | rc = phy_read(phydev, MII_KSZPHY_INTCS); |
418 | |
419 | return (rc < 0) ? rc : 0; |
420 | } |
421 | |
422 | static int kszphy_config_intr(struct phy_device *phydev) |
423 | { |
424 | const struct kszphy_type *type = phydev->drv->driver_data; |
425 | int temp, err; |
426 | u16 mask; |
427 | |
428 | if (type && type->interrupt_level_mask) |
429 | mask = type->interrupt_level_mask; |
430 | else |
431 | mask = KSZPHY_CTRL_INT_ACTIVE_HIGH; |
432 | |
433 | /* set the interrupt pin active low */ |
434 | temp = phy_read(phydev, MII_KSZPHY_CTRL); |
435 | if (temp < 0) |
436 | return temp; |
437 | temp &= ~mask; |
438 | phy_write(phydev, MII_KSZPHY_CTRL, val: temp); |
439 | |
440 | /* enable / disable interrupts */ |
441 | if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { |
442 | err = kszphy_ack_interrupt(phydev); |
443 | if (err) |
444 | return err; |
445 | |
446 | err = phy_write(phydev, MII_KSZPHY_INTCS, KSZPHY_INTCS_ALL); |
447 | } else { |
448 | err = phy_write(phydev, MII_KSZPHY_INTCS, val: 0); |
449 | if (err) |
450 | return err; |
451 | |
452 | err = kszphy_ack_interrupt(phydev); |
453 | } |
454 | |
455 | return err; |
456 | } |
457 | |
458 | static irqreturn_t kszphy_handle_interrupt(struct phy_device *phydev) |
459 | { |
460 | int irq_status; |
461 | |
462 | irq_status = phy_read(phydev, MII_KSZPHY_INTCS); |
463 | if (irq_status < 0) { |
464 | phy_error(phydev); |
465 | return IRQ_NONE; |
466 | } |
467 | |
468 | if (!(irq_status & KSZPHY_INTCS_STATUS)) |
469 | return IRQ_NONE; |
470 | |
471 | phy_trigger_machine(phydev); |
472 | |
473 | return IRQ_HANDLED; |
474 | } |
475 | |
476 | static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val) |
477 | { |
478 | int ctrl; |
479 | |
480 | ctrl = phy_read(phydev, MII_KSZPHY_CTRL); |
481 | if (ctrl < 0) |
482 | return ctrl; |
483 | |
484 | if (val) |
485 | ctrl |= KSZPHY_RMII_REF_CLK_SEL; |
486 | else |
487 | ctrl &= ~KSZPHY_RMII_REF_CLK_SEL; |
488 | |
489 | return phy_write(phydev, MII_KSZPHY_CTRL, val: ctrl); |
490 | } |
491 | |
492 | static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val) |
493 | { |
494 | int rc, temp, shift; |
495 | |
496 | switch (reg) { |
497 | case MII_KSZPHY_CTRL_1: |
498 | shift = 14; |
499 | break; |
500 | case MII_KSZPHY_CTRL_2: |
501 | shift = 4; |
502 | break; |
503 | default: |
504 | return -EINVAL; |
505 | } |
506 | |
507 | temp = phy_read(phydev, regnum: reg); |
508 | if (temp < 0) { |
509 | rc = temp; |
510 | goto out; |
511 | } |
512 | |
513 | temp &= ~(3 << shift); |
514 | temp |= val << shift; |
515 | rc = phy_write(phydev, regnum: reg, val: temp); |
516 | out: |
517 | if (rc < 0) |
518 | phydev_err(phydev, "failed to set led mode\n" ); |
519 | |
520 | return rc; |
521 | } |
522 | |
523 | /* Disable PHY address 0 as the broadcast address, so that it can be used as a |
524 | * unique (non-broadcast) address on a shared bus. |
525 | */ |
526 | static int kszphy_broadcast_disable(struct phy_device *phydev) |
527 | { |
528 | int ret; |
529 | |
530 | ret = phy_read(phydev, MII_KSZPHY_OMSO); |
531 | if (ret < 0) |
532 | goto out; |
533 | |
534 | ret = phy_write(phydev, MII_KSZPHY_OMSO, val: ret | KSZPHY_OMSO_B_CAST_OFF); |
535 | out: |
536 | if (ret) |
537 | phydev_err(phydev, "failed to disable broadcast address\n" ); |
538 | |
539 | return ret; |
540 | } |
541 | |
542 | static int kszphy_nand_tree_disable(struct phy_device *phydev) |
543 | { |
544 | int ret; |
545 | |
546 | ret = phy_read(phydev, MII_KSZPHY_OMSO); |
547 | if (ret < 0) |
548 | goto out; |
549 | |
550 | if (!(ret & KSZPHY_OMSO_NAND_TREE_ON)) |
551 | return 0; |
552 | |
553 | ret = phy_write(phydev, MII_KSZPHY_OMSO, |
554 | val: ret & ~KSZPHY_OMSO_NAND_TREE_ON); |
555 | out: |
556 | if (ret) |
557 | phydev_err(phydev, "failed to disable NAND tree mode\n" ); |
558 | |
559 | return ret; |
560 | } |
561 | |
562 | /* Some config bits need to be set again on resume, handle them here. */ |
563 | static int kszphy_config_reset(struct phy_device *phydev) |
564 | { |
565 | struct kszphy_priv *priv = phydev->priv; |
566 | int ret; |
567 | |
568 | if (priv->rmii_ref_clk_sel) { |
569 | ret = kszphy_rmii_clk_sel(phydev, val: priv->rmii_ref_clk_sel_val); |
570 | if (ret) { |
571 | phydev_err(phydev, |
572 | "failed to set rmii reference clock\n" ); |
573 | return ret; |
574 | } |
575 | } |
576 | |
577 | if (priv->type && priv->led_mode >= 0) |
578 | kszphy_setup_led(phydev, reg: priv->type->led_mode_reg, val: priv->led_mode); |
579 | |
580 | return 0; |
581 | } |
582 | |
583 | static int kszphy_config_init(struct phy_device *phydev) |
584 | { |
585 | struct kszphy_priv *priv = phydev->priv; |
586 | const struct kszphy_type *type; |
587 | |
588 | if (!priv) |
589 | return 0; |
590 | |
591 | type = priv->type; |
592 | |
593 | if (type && type->has_broadcast_disable) |
594 | kszphy_broadcast_disable(phydev); |
595 | |
596 | if (type && type->has_nand_tree_disable) |
597 | kszphy_nand_tree_disable(phydev); |
598 | |
599 | return kszphy_config_reset(phydev); |
600 | } |
601 | |
602 | static int ksz8041_fiber_mode(struct phy_device *phydev) |
603 | { |
604 | struct device_node *of_node = phydev->mdio.dev.of_node; |
605 | |
606 | return of_property_read_bool(np: of_node, propname: "micrel,fiber-mode" ); |
607 | } |
608 | |
609 | static int ksz8041_config_init(struct phy_device *phydev) |
610 | { |
611 | __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; |
612 | |
613 | /* Limit supported and advertised modes in fiber mode */ |
614 | if (ksz8041_fiber_mode(phydev)) { |
615 | phydev->dev_flags |= MICREL_PHY_FXEN; |
616 | linkmode_set_bit(nr: ETHTOOL_LINK_MODE_100baseT_Full_BIT, addr: mask); |
617 | linkmode_set_bit(nr: ETHTOOL_LINK_MODE_100baseT_Half_BIT, addr: mask); |
618 | |
619 | linkmode_and(dst: phydev->supported, a: phydev->supported, b: mask); |
620 | linkmode_set_bit(nr: ETHTOOL_LINK_MODE_FIBRE_BIT, |
621 | addr: phydev->supported); |
622 | linkmode_and(dst: phydev->advertising, a: phydev->advertising, b: mask); |
623 | linkmode_set_bit(nr: ETHTOOL_LINK_MODE_FIBRE_BIT, |
624 | addr: phydev->advertising); |
625 | phydev->autoneg = AUTONEG_DISABLE; |
626 | } |
627 | |
628 | return kszphy_config_init(phydev); |
629 | } |
630 | |
631 | static int ksz8041_config_aneg(struct phy_device *phydev) |
632 | { |
633 | /* Skip auto-negotiation in fiber mode */ |
634 | if (phydev->dev_flags & MICREL_PHY_FXEN) { |
635 | phydev->speed = SPEED_100; |
636 | return 0; |
637 | } |
638 | |
639 | return genphy_config_aneg(phydev); |
640 | } |
641 | |
642 | static int ksz8051_ksz8795_match_phy_device(struct phy_device *phydev, |
643 | const bool ksz_8051) |
644 | { |
645 | int ret; |
646 | |
647 | if (!phy_id_compare(id1: phydev->phy_id, PHY_ID_KSZ8051, MICREL_PHY_ID_MASK)) |
648 | return 0; |
649 | |
650 | ret = phy_read(phydev, MII_BMSR); |
651 | if (ret < 0) |
652 | return ret; |
653 | |
654 | /* KSZ8051 PHY and KSZ8794/KSZ8795/KSZ8765 switch share the same |
655 | * exact PHY ID. However, they can be told apart by the extended |
656 | * capability registers presence. The KSZ8051 PHY has them while |
657 | * the switch does not. |
658 | */ |
659 | ret &= BMSR_ERCAP; |
660 | if (ksz_8051) |
661 | return ret; |
662 | else |
663 | return !ret; |
664 | } |
665 | |
666 | static int ksz8051_match_phy_device(struct phy_device *phydev) |
667 | { |
668 | return ksz8051_ksz8795_match_phy_device(phydev, ksz_8051: true); |
669 | } |
670 | |
671 | static int ksz8081_config_init(struct phy_device *phydev) |
672 | { |
673 | /* KSZPHY_OMSO_FACTORY_TEST is set at de-assertion of the reset line |
674 | * based on the RXER (KSZ8081RNA/RND) or TXC (KSZ8081MNX/RNB) pin. If a |
675 | * pull-down is missing, the factory test mode should be cleared by |
676 | * manually writing a 0. |
677 | */ |
678 | phy_clear_bits(phydev, MII_KSZPHY_OMSO, KSZPHY_OMSO_FACTORY_TEST); |
679 | |
680 | return kszphy_config_init(phydev); |
681 | } |
682 | |
683 | static int ksz8081_config_mdix(struct phy_device *phydev, u8 ctrl) |
684 | { |
685 | u16 val; |
686 | |
687 | switch (ctrl) { |
688 | case ETH_TP_MDI: |
689 | val = KSZ8081_CTRL2_DISABLE_AUTO_MDIX; |
690 | break; |
691 | case ETH_TP_MDI_X: |
692 | val = KSZ8081_CTRL2_DISABLE_AUTO_MDIX | |
693 | KSZ8081_CTRL2_MDI_MDI_X_SELECT; |
694 | break; |
695 | case ETH_TP_MDI_AUTO: |
696 | val = 0; |
697 | break; |
698 | default: |
699 | return 0; |
700 | } |
701 | |
702 | return phy_modify(phydev, MII_KSZPHY_CTRL_2, |
703 | KSZ8081_CTRL2_HP_MDIX | |
704 | KSZ8081_CTRL2_MDI_MDI_X_SELECT | |
705 | KSZ8081_CTRL2_DISABLE_AUTO_MDIX, |
706 | KSZ8081_CTRL2_HP_MDIX | val); |
707 | } |
708 | |
709 | static int ksz8081_config_aneg(struct phy_device *phydev) |
710 | { |
711 | int ret; |
712 | |
713 | ret = genphy_config_aneg(phydev); |
714 | if (ret) |
715 | return ret; |
716 | |
717 | /* The MDI-X configuration is automatically changed by the PHY after |
718 | * switching from autoneg off to on. So, take MDI-X configuration under |
719 | * own control and set it after autoneg configuration was done. |
720 | */ |
721 | return ksz8081_config_mdix(phydev, ctrl: phydev->mdix_ctrl); |
722 | } |
723 | |
724 | static int ksz8081_mdix_update(struct phy_device *phydev) |
725 | { |
726 | int ret; |
727 | |
728 | ret = phy_read(phydev, MII_KSZPHY_CTRL_2); |
729 | if (ret < 0) |
730 | return ret; |
731 | |
732 | if (ret & KSZ8081_CTRL2_DISABLE_AUTO_MDIX) { |
733 | if (ret & KSZ8081_CTRL2_MDI_MDI_X_SELECT) |
734 | phydev->mdix_ctrl = ETH_TP_MDI_X; |
735 | else |
736 | phydev->mdix_ctrl = ETH_TP_MDI; |
737 | } else { |
738 | phydev->mdix_ctrl = ETH_TP_MDI_AUTO; |
739 | } |
740 | |
741 | ret = phy_read(phydev, MII_KSZPHY_CTRL_1); |
742 | if (ret < 0) |
743 | return ret; |
744 | |
745 | if (ret & KSZ8081_CTRL1_MDIX_STAT) |
746 | phydev->mdix = ETH_TP_MDI; |
747 | else |
748 | phydev->mdix = ETH_TP_MDI_X; |
749 | |
750 | return 0; |
751 | } |
752 | |
753 | static int ksz8081_read_status(struct phy_device *phydev) |
754 | { |
755 | int ret; |
756 | |
757 | ret = ksz8081_mdix_update(phydev); |
758 | if (ret < 0) |
759 | return ret; |
760 | |
761 | return genphy_read_status(phydev); |
762 | } |
763 | |
764 | static int ksz8061_config_init(struct phy_device *phydev) |
765 | { |
766 | int ret; |
767 | |
768 | ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, val: 0xB61A); |
769 | if (ret) |
770 | return ret; |
771 | |
772 | return kszphy_config_init(phydev); |
773 | } |
774 | |
775 | static int ksz8795_match_phy_device(struct phy_device *phydev) |
776 | { |
777 | return ksz8051_ksz8795_match_phy_device(phydev, ksz_8051: false); |
778 | } |
779 | |
780 | static int ksz9021_load_values_from_of(struct phy_device *phydev, |
781 | const struct device_node *of_node, |
782 | u16 reg, |
783 | const char *field1, const char *field2, |
784 | const char *field3, const char *field4) |
785 | { |
786 | int val1 = -1; |
787 | int val2 = -2; |
788 | int val3 = -3; |
789 | int val4 = -4; |
790 | int newval; |
791 | int matches = 0; |
792 | |
793 | if (!of_property_read_u32(np: of_node, propname: field1, out_value: &val1)) |
794 | matches++; |
795 | |
796 | if (!of_property_read_u32(np: of_node, propname: field2, out_value: &val2)) |
797 | matches++; |
798 | |
799 | if (!of_property_read_u32(np: of_node, propname: field3, out_value: &val3)) |
800 | matches++; |
801 | |
802 | if (!of_property_read_u32(np: of_node, propname: field4, out_value: &val4)) |
803 | matches++; |
804 | |
805 | if (!matches) |
806 | return 0; |
807 | |
808 | if (matches < 4) |
809 | newval = kszphy_extended_read(phydev, regnum: reg); |
810 | else |
811 | newval = 0; |
812 | |
813 | if (val1 != -1) |
814 | newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0); |
815 | |
816 | if (val2 != -2) |
817 | newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4); |
818 | |
819 | if (val3 != -3) |
820 | newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8); |
821 | |
822 | if (val4 != -4) |
823 | newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12); |
824 | |
825 | return kszphy_extended_write(phydev, regnum: reg, val: newval); |
826 | } |
827 | |
828 | static int ksz9021_config_init(struct phy_device *phydev) |
829 | { |
830 | const struct device_node *of_node; |
831 | const struct device *dev_walker; |
832 | |
833 | /* The Micrel driver has a deprecated option to place phy OF |
834 | * properties in the MAC node. Walk up the tree of devices to |
835 | * find a device with an OF node. |
836 | */ |
837 | dev_walker = &phydev->mdio.dev; |
838 | do { |
839 | of_node = dev_walker->of_node; |
840 | dev_walker = dev_walker->parent; |
841 | |
842 | } while (!of_node && dev_walker); |
843 | |
844 | if (of_node) { |
845 | ksz9021_load_values_from_of(phydev, of_node, |
846 | MII_KSZPHY_CLK_CONTROL_PAD_SKEW, |
847 | field1: "txen-skew-ps" , field2: "txc-skew-ps" , |
848 | field3: "rxdv-skew-ps" , field4: "rxc-skew-ps" ); |
849 | ksz9021_load_values_from_of(phydev, of_node, |
850 | MII_KSZPHY_RX_DATA_PAD_SKEW, |
851 | field1: "rxd0-skew-ps" , field2: "rxd1-skew-ps" , |
852 | field3: "rxd2-skew-ps" , field4: "rxd3-skew-ps" ); |
853 | ksz9021_load_values_from_of(phydev, of_node, |
854 | MII_KSZPHY_TX_DATA_PAD_SKEW, |
855 | field1: "txd0-skew-ps" , field2: "txd1-skew-ps" , |
856 | field3: "txd2-skew-ps" , field4: "txd3-skew-ps" ); |
857 | } |
858 | return 0; |
859 | } |
860 | |
861 | #define KSZ9031_PS_TO_REG 60 |
862 | |
863 | /* Extended registers */ |
864 | /* MMD Address 0x0 */ |
865 | #define MII_KSZ9031RN_FLP_BURST_TX_LO 3 |
866 | #define MII_KSZ9031RN_FLP_BURST_TX_HI 4 |
867 | |
868 | /* MMD Address 0x2 */ |
869 | #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4 |
870 | #define MII_KSZ9031RN_RX_CTL_M GENMASK(7, 4) |
871 | #define MII_KSZ9031RN_TX_CTL_M GENMASK(3, 0) |
872 | |
873 | #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5 |
874 | #define MII_KSZ9031RN_RXD3 GENMASK(15, 12) |
875 | #define MII_KSZ9031RN_RXD2 GENMASK(11, 8) |
876 | #define MII_KSZ9031RN_RXD1 GENMASK(7, 4) |
877 | #define MII_KSZ9031RN_RXD0 GENMASK(3, 0) |
878 | |
879 | #define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6 |
880 | #define MII_KSZ9031RN_TXD3 GENMASK(15, 12) |
881 | #define MII_KSZ9031RN_TXD2 GENMASK(11, 8) |
882 | #define MII_KSZ9031RN_TXD1 GENMASK(7, 4) |
883 | #define MII_KSZ9031RN_TXD0 GENMASK(3, 0) |
884 | |
885 | #define MII_KSZ9031RN_CLK_PAD_SKEW 8 |
886 | #define MII_KSZ9031RN_GTX_CLK GENMASK(9, 5) |
887 | #define MII_KSZ9031RN_RX_CLK GENMASK(4, 0) |
888 | |
889 | /* KSZ9031 has internal RGMII_IDRX = 1.2ns and RGMII_IDTX = 0ns. To |
890 | * provide different RGMII options we need to configure delay offset |
891 | * for each pad relative to build in delay. |
892 | */ |
893 | /* keep rx as "No delay adjustment" and set rx_clk to +0.60ns to get delays of |
894 | * 1.80ns |
895 | */ |
896 | #define RX_ID 0x7 |
897 | #define RX_CLK_ID 0x19 |
898 | |
899 | /* set rx to +0.30ns and rx_clk to -0.90ns to compensate the |
900 | * internal 1.2ns delay. |
901 | */ |
902 | #define RX_ND 0xc |
903 | #define RX_CLK_ND 0x0 |
904 | |
905 | /* set tx to -0.42ns and tx_clk to +0.96ns to get 1.38ns delay */ |
906 | #define TX_ID 0x0 |
907 | #define TX_CLK_ID 0x1f |
908 | |
909 | /* set tx and tx_clk to "No delay adjustment" to keep 0ns |
910 | * dealy |
911 | */ |
912 | #define TX_ND 0x7 |
913 | #define TX_CLK_ND 0xf |
914 | |
915 | /* MMD Address 0x1C */ |
916 | #define MII_KSZ9031RN_EDPD 0x23 |
917 | #define MII_KSZ9031RN_EDPD_ENABLE BIT(0) |
918 | |
919 | static int ksz9031_of_load_skew_values(struct phy_device *phydev, |
920 | const struct device_node *of_node, |
921 | u16 reg, size_t field_sz, |
922 | const char *field[], u8 numfields, |
923 | bool *update) |
924 | { |
925 | int val[4] = {-1, -2, -3, -4}; |
926 | int matches = 0; |
927 | u16 mask; |
928 | u16 maxval; |
929 | u16 newval; |
930 | int i; |
931 | |
932 | for (i = 0; i < numfields; i++) |
933 | if (!of_property_read_u32(np: of_node, propname: field[i], out_value: val + i)) |
934 | matches++; |
935 | |
936 | if (!matches) |
937 | return 0; |
938 | |
939 | *update |= true; |
940 | |
941 | if (matches < numfields) |
942 | newval = phy_read_mmd(phydev, devad: 2, regnum: reg); |
943 | else |
944 | newval = 0; |
945 | |
946 | maxval = (field_sz == 4) ? 0xf : 0x1f; |
947 | for (i = 0; i < numfields; i++) |
948 | if (val[i] != -(i + 1)) { |
949 | mask = 0xffff; |
950 | mask ^= maxval << (field_sz * i); |
951 | newval = (newval & mask) | |
952 | (((val[i] / KSZ9031_PS_TO_REG) & maxval) |
953 | << (field_sz * i)); |
954 | } |
955 | |
956 | return phy_write_mmd(phydev, devad: 2, regnum: reg, val: newval); |
957 | } |
958 | |
959 | /* Center KSZ9031RNX FLP timing at 16ms. */ |
960 | static int ksz9031_center_flp_timing(struct phy_device *phydev) |
961 | { |
962 | int result; |
963 | |
964 | result = phy_write_mmd(phydev, devad: 0, MII_KSZ9031RN_FLP_BURST_TX_HI, |
965 | val: 0x0006); |
966 | if (result) |
967 | return result; |
968 | |
969 | result = phy_write_mmd(phydev, devad: 0, MII_KSZ9031RN_FLP_BURST_TX_LO, |
970 | val: 0x1A80); |
971 | if (result) |
972 | return result; |
973 | |
974 | return genphy_restart_aneg(phydev); |
975 | } |
976 | |
977 | /* Enable energy-detect power-down mode */ |
978 | static int ksz9031_enable_edpd(struct phy_device *phydev) |
979 | { |
980 | int reg; |
981 | |
982 | reg = phy_read_mmd(phydev, devad: 0x1C, MII_KSZ9031RN_EDPD); |
983 | if (reg < 0) |
984 | return reg; |
985 | return phy_write_mmd(phydev, devad: 0x1C, MII_KSZ9031RN_EDPD, |
986 | val: reg | MII_KSZ9031RN_EDPD_ENABLE); |
987 | } |
988 | |
989 | static int ksz9031_config_rgmii_delay(struct phy_device *phydev) |
990 | { |
991 | u16 rx, tx, rx_clk, tx_clk; |
992 | int ret; |
993 | |
994 | switch (phydev->interface) { |
995 | case PHY_INTERFACE_MODE_RGMII: |
996 | tx = TX_ND; |
997 | tx_clk = TX_CLK_ND; |
998 | rx = RX_ND; |
999 | rx_clk = RX_CLK_ND; |
1000 | break; |
1001 | case PHY_INTERFACE_MODE_RGMII_ID: |
1002 | tx = TX_ID; |
1003 | tx_clk = TX_CLK_ID; |
1004 | rx = RX_ID; |
1005 | rx_clk = RX_CLK_ID; |
1006 | break; |
1007 | case PHY_INTERFACE_MODE_RGMII_RXID: |
1008 | tx = TX_ND; |
1009 | tx_clk = TX_CLK_ND; |
1010 | rx = RX_ID; |
1011 | rx_clk = RX_CLK_ID; |
1012 | break; |
1013 | case PHY_INTERFACE_MODE_RGMII_TXID: |
1014 | tx = TX_ID; |
1015 | tx_clk = TX_CLK_ID; |
1016 | rx = RX_ND; |
1017 | rx_clk = RX_CLK_ND; |
1018 | break; |
1019 | default: |
1020 | return 0; |
1021 | } |
1022 | |
1023 | ret = phy_write_mmd(phydev, devad: 2, MII_KSZ9031RN_CONTROL_PAD_SKEW, |
1024 | FIELD_PREP(MII_KSZ9031RN_RX_CTL_M, rx) | |
1025 | FIELD_PREP(MII_KSZ9031RN_TX_CTL_M, tx)); |
1026 | if (ret < 0) |
1027 | return ret; |
1028 | |
1029 | ret = phy_write_mmd(phydev, devad: 2, MII_KSZ9031RN_RX_DATA_PAD_SKEW, |
1030 | FIELD_PREP(MII_KSZ9031RN_RXD3, rx) | |
1031 | FIELD_PREP(MII_KSZ9031RN_RXD2, rx) | |
1032 | FIELD_PREP(MII_KSZ9031RN_RXD1, rx) | |
1033 | FIELD_PREP(MII_KSZ9031RN_RXD0, rx)); |
1034 | if (ret < 0) |
1035 | return ret; |
1036 | |
1037 | ret = phy_write_mmd(phydev, devad: 2, MII_KSZ9031RN_TX_DATA_PAD_SKEW, |
1038 | FIELD_PREP(MII_KSZ9031RN_TXD3, tx) | |
1039 | FIELD_PREP(MII_KSZ9031RN_TXD2, tx) | |
1040 | FIELD_PREP(MII_KSZ9031RN_TXD1, tx) | |
1041 | FIELD_PREP(MII_KSZ9031RN_TXD0, tx)); |
1042 | if (ret < 0) |
1043 | return ret; |
1044 | |
1045 | return phy_write_mmd(phydev, devad: 2, MII_KSZ9031RN_CLK_PAD_SKEW, |
1046 | FIELD_PREP(MII_KSZ9031RN_GTX_CLK, tx_clk) | |
1047 | FIELD_PREP(MII_KSZ9031RN_RX_CLK, rx_clk)); |
1048 | } |
1049 | |
1050 | static int ksz9031_config_init(struct phy_device *phydev) |
1051 | { |
1052 | const struct device_node *of_node; |
1053 | static const char *clk_skews[2] = {"rxc-skew-ps" , "txc-skew-ps" }; |
1054 | static const char *rx_data_skews[4] = { |
1055 | "rxd0-skew-ps" , "rxd1-skew-ps" , |
1056 | "rxd2-skew-ps" , "rxd3-skew-ps" |
1057 | }; |
1058 | static const char *tx_data_skews[4] = { |
1059 | "txd0-skew-ps" , "txd1-skew-ps" , |
1060 | "txd2-skew-ps" , "txd3-skew-ps" |
1061 | }; |
1062 | static const char *control_skews[2] = {"txen-skew-ps" , "rxdv-skew-ps" }; |
1063 | const struct device *dev_walker; |
1064 | int result; |
1065 | |
1066 | result = ksz9031_enable_edpd(phydev); |
1067 | if (result < 0) |
1068 | return result; |
1069 | |
1070 | /* The Micrel driver has a deprecated option to place phy OF |
1071 | * properties in the MAC node. Walk up the tree of devices to |
1072 | * find a device with an OF node. |
1073 | */ |
1074 | dev_walker = &phydev->mdio.dev; |
1075 | do { |
1076 | of_node = dev_walker->of_node; |
1077 | dev_walker = dev_walker->parent; |
1078 | } while (!of_node && dev_walker); |
1079 | |
1080 | if (of_node) { |
1081 | bool update = false; |
1082 | |
1083 | if (phy_interface_is_rgmii(phydev)) { |
1084 | result = ksz9031_config_rgmii_delay(phydev); |
1085 | if (result < 0) |
1086 | return result; |
1087 | } |
1088 | |
1089 | ksz9031_of_load_skew_values(phydev, of_node, |
1090 | MII_KSZ9031RN_CLK_PAD_SKEW, field_sz: 5, |
1091 | field: clk_skews, numfields: 2, update: &update); |
1092 | |
1093 | ksz9031_of_load_skew_values(phydev, of_node, |
1094 | MII_KSZ9031RN_CONTROL_PAD_SKEW, field_sz: 4, |
1095 | field: control_skews, numfields: 2, update: &update); |
1096 | |
1097 | ksz9031_of_load_skew_values(phydev, of_node, |
1098 | MII_KSZ9031RN_RX_DATA_PAD_SKEW, field_sz: 4, |
1099 | field: rx_data_skews, numfields: 4, update: &update); |
1100 | |
1101 | ksz9031_of_load_skew_values(phydev, of_node, |
1102 | MII_KSZ9031RN_TX_DATA_PAD_SKEW, field_sz: 4, |
1103 | field: tx_data_skews, numfields: 4, update: &update); |
1104 | |
1105 | if (update && !phy_interface_is_rgmii(phydev)) |
1106 | phydev_warn(phydev, |
1107 | "*-skew-ps values should be used only with RGMII PHY modes\n" ); |
1108 | |
1109 | /* Silicon Errata Sheet (DS80000691D or DS80000692D): |
1110 | * When the device links in the 1000BASE-T slave mode only, |
1111 | * the optional 125MHz reference output clock (CLK125_NDO) |
1112 | * has wide duty cycle variation. |
1113 | * |
1114 | * The optional CLK125_NDO clock does not meet the RGMII |
1115 | * 45/55 percent (min/max) duty cycle requirement and therefore |
1116 | * cannot be used directly by the MAC side for clocking |
1117 | * applications that have setup/hold time requirements on |
1118 | * rising and falling clock edges. |
1119 | * |
1120 | * Workaround: |
1121 | * Force the phy to be the master to receive a stable clock |
1122 | * which meets the duty cycle requirement. |
1123 | */ |
1124 | if (of_property_read_bool(np: of_node, propname: "micrel,force-master" )) { |
1125 | result = phy_read(phydev, MII_CTRL1000); |
1126 | if (result < 0) |
1127 | goto err_force_master; |
1128 | |
1129 | /* enable master mode, config & prefer master */ |
1130 | result |= CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER; |
1131 | result = phy_write(phydev, MII_CTRL1000, val: result); |
1132 | if (result < 0) |
1133 | goto err_force_master; |
1134 | } |
1135 | } |
1136 | |
1137 | return ksz9031_center_flp_timing(phydev); |
1138 | |
1139 | err_force_master: |
1140 | phydev_err(phydev, "failed to force the phy to master mode\n" ); |
1141 | return result; |
1142 | } |
1143 | |
1144 | #define KSZ9131_SKEW_5BIT_MAX 2400 |
1145 | #define KSZ9131_SKEW_4BIT_MAX 800 |
1146 | #define KSZ9131_OFFSET 700 |
1147 | #define KSZ9131_STEP 100 |
1148 | |
1149 | static int ksz9131_of_load_skew_values(struct phy_device *phydev, |
1150 | struct device_node *of_node, |
1151 | u16 reg, size_t field_sz, |
1152 | char *field[], u8 numfields) |
1153 | { |
1154 | int val[4] = {-(1 + KSZ9131_OFFSET), -(2 + KSZ9131_OFFSET), |
1155 | -(3 + KSZ9131_OFFSET), -(4 + KSZ9131_OFFSET)}; |
1156 | int skewval, skewmax = 0; |
1157 | int matches = 0; |
1158 | u16 maxval; |
1159 | u16 newval; |
1160 | u16 mask; |
1161 | int i; |
1162 | |
1163 | /* psec properties in dts should mean x pico seconds */ |
1164 | if (field_sz == 5) |
1165 | skewmax = KSZ9131_SKEW_5BIT_MAX; |
1166 | else |
1167 | skewmax = KSZ9131_SKEW_4BIT_MAX; |
1168 | |
1169 | for (i = 0; i < numfields; i++) |
1170 | if (!of_property_read_s32(np: of_node, propname: field[i], out_value: &skewval)) { |
1171 | if (skewval < -KSZ9131_OFFSET) |
1172 | skewval = -KSZ9131_OFFSET; |
1173 | else if (skewval > skewmax) |
1174 | skewval = skewmax; |
1175 | |
1176 | val[i] = skewval + KSZ9131_OFFSET; |
1177 | matches++; |
1178 | } |
1179 | |
1180 | if (!matches) |
1181 | return 0; |
1182 | |
1183 | if (matches < numfields) |
1184 | newval = phy_read_mmd(phydev, devad: 2, regnum: reg); |
1185 | else |
1186 | newval = 0; |
1187 | |
1188 | maxval = (field_sz == 4) ? 0xf : 0x1f; |
1189 | for (i = 0; i < numfields; i++) |
1190 | if (val[i] != -(i + 1 + KSZ9131_OFFSET)) { |
1191 | mask = 0xffff; |
1192 | mask ^= maxval << (field_sz * i); |
1193 | newval = (newval & mask) | |
1194 | (((val[i] / KSZ9131_STEP) & maxval) |
1195 | << (field_sz * i)); |
1196 | } |
1197 | |
1198 | return phy_write_mmd(phydev, devad: 2, regnum: reg, val: newval); |
1199 | } |
1200 | |
1201 | #define KSZ9131RN_MMD_COMMON_CTRL_REG 2 |
1202 | #define KSZ9131RN_RXC_DLL_CTRL 76 |
1203 | #define KSZ9131RN_TXC_DLL_CTRL 77 |
1204 | #define KSZ9131RN_DLL_ENABLE_DELAY 0 |
1205 | |
1206 | static int ksz9131_config_rgmii_delay(struct phy_device *phydev) |
1207 | { |
1208 | const struct kszphy_type *type = phydev->drv->driver_data; |
1209 | u16 rxcdll_val, txcdll_val; |
1210 | int ret; |
1211 | |
1212 | switch (phydev->interface) { |
1213 | case PHY_INTERFACE_MODE_RGMII: |
1214 | rxcdll_val = type->disable_dll_rx_bit; |
1215 | txcdll_val = type->disable_dll_tx_bit; |
1216 | break; |
1217 | case PHY_INTERFACE_MODE_RGMII_ID: |
1218 | rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY; |
1219 | txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY; |
1220 | break; |
1221 | case PHY_INTERFACE_MODE_RGMII_RXID: |
1222 | rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY; |
1223 | txcdll_val = type->disable_dll_tx_bit; |
1224 | break; |
1225 | case PHY_INTERFACE_MODE_RGMII_TXID: |
1226 | rxcdll_val = type->disable_dll_rx_bit; |
1227 | txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY; |
1228 | break; |
1229 | default: |
1230 | return 0; |
1231 | } |
1232 | |
1233 | ret = phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG, |
1234 | KSZ9131RN_RXC_DLL_CTRL, mask: type->disable_dll_mask, |
1235 | set: rxcdll_val); |
1236 | if (ret < 0) |
1237 | return ret; |
1238 | |
1239 | return phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG, |
1240 | KSZ9131RN_TXC_DLL_CTRL, mask: type->disable_dll_mask, |
1241 | set: txcdll_val); |
1242 | } |
1243 | |
1244 | /* Silicon Errata DS80000693B |
1245 | * |
1246 | * When LEDs are configured in Individual Mode, LED1 is ON in a no-link |
1247 | * condition. Workaround is to set register 0x1e, bit 9, this way LED1 behaves |
1248 | * according to the datasheet (off if there is no link). |
1249 | */ |
1250 | static int ksz9131_led_errata(struct phy_device *phydev) |
1251 | { |
1252 | int reg; |
1253 | |
1254 | reg = phy_read_mmd(phydev, devad: 2, regnum: 0); |
1255 | if (reg < 0) |
1256 | return reg; |
1257 | |
1258 | if (!(reg & BIT(4))) |
1259 | return 0; |
1260 | |
1261 | return phy_set_bits(phydev, regnum: 0x1e, BIT(9)); |
1262 | } |
1263 | |
1264 | static int ksz9131_config_init(struct phy_device *phydev) |
1265 | { |
1266 | struct device_node *of_node; |
1267 | char *clk_skews[2] = {"rxc-skew-psec" , "txc-skew-psec" }; |
1268 | char *rx_data_skews[4] = { |
1269 | "rxd0-skew-psec" , "rxd1-skew-psec" , |
1270 | "rxd2-skew-psec" , "rxd3-skew-psec" |
1271 | }; |
1272 | char *tx_data_skews[4] = { |
1273 | "txd0-skew-psec" , "txd1-skew-psec" , |
1274 | "txd2-skew-psec" , "txd3-skew-psec" |
1275 | }; |
1276 | char *control_skews[2] = {"txen-skew-psec" , "rxdv-skew-psec" }; |
1277 | const struct device *dev_walker; |
1278 | int ret; |
1279 | |
1280 | dev_walker = &phydev->mdio.dev; |
1281 | do { |
1282 | of_node = dev_walker->of_node; |
1283 | dev_walker = dev_walker->parent; |
1284 | } while (!of_node && dev_walker); |
1285 | |
1286 | if (!of_node) |
1287 | return 0; |
1288 | |
1289 | if (phy_interface_is_rgmii(phydev)) { |
1290 | ret = ksz9131_config_rgmii_delay(phydev); |
1291 | if (ret < 0) |
1292 | return ret; |
1293 | } |
1294 | |
1295 | ret = ksz9131_of_load_skew_values(phydev, of_node, |
1296 | MII_KSZ9031RN_CLK_PAD_SKEW, field_sz: 5, |
1297 | field: clk_skews, numfields: 2); |
1298 | if (ret < 0) |
1299 | return ret; |
1300 | |
1301 | ret = ksz9131_of_load_skew_values(phydev, of_node, |
1302 | MII_KSZ9031RN_CONTROL_PAD_SKEW, field_sz: 4, |
1303 | field: control_skews, numfields: 2); |
1304 | if (ret < 0) |
1305 | return ret; |
1306 | |
1307 | ret = ksz9131_of_load_skew_values(phydev, of_node, |
1308 | MII_KSZ9031RN_RX_DATA_PAD_SKEW, field_sz: 4, |
1309 | field: rx_data_skews, numfields: 4); |
1310 | if (ret < 0) |
1311 | return ret; |
1312 | |
1313 | ret = ksz9131_of_load_skew_values(phydev, of_node, |
1314 | MII_KSZ9031RN_TX_DATA_PAD_SKEW, field_sz: 4, |
1315 | field: tx_data_skews, numfields: 4); |
1316 | if (ret < 0) |
1317 | return ret; |
1318 | |
1319 | ret = ksz9131_led_errata(phydev); |
1320 | if (ret < 0) |
1321 | return ret; |
1322 | |
1323 | return 0; |
1324 | } |
1325 | |
1326 | #define MII_KSZ9131_AUTO_MDIX 0x1C |
1327 | #define MII_KSZ9131_AUTO_MDI_SET BIT(7) |
1328 | #define MII_KSZ9131_AUTO_MDIX_SWAP_OFF BIT(6) |
1329 | |
1330 | static int ksz9131_mdix_update(struct phy_device *phydev) |
1331 | { |
1332 | int ret; |
1333 | |
1334 | ret = phy_read(phydev, MII_KSZ9131_AUTO_MDIX); |
1335 | if (ret < 0) |
1336 | return ret; |
1337 | |
1338 | if (ret & MII_KSZ9131_AUTO_MDIX_SWAP_OFF) { |
1339 | if (ret & MII_KSZ9131_AUTO_MDI_SET) |
1340 | phydev->mdix_ctrl = ETH_TP_MDI; |
1341 | else |
1342 | phydev->mdix_ctrl = ETH_TP_MDI_X; |
1343 | } else { |
1344 | phydev->mdix_ctrl = ETH_TP_MDI_AUTO; |
1345 | } |
1346 | |
1347 | if (ret & MII_KSZ9131_AUTO_MDI_SET) |
1348 | phydev->mdix = ETH_TP_MDI; |
1349 | else |
1350 | phydev->mdix = ETH_TP_MDI_X; |
1351 | |
1352 | return 0; |
1353 | } |
1354 | |
1355 | static int ksz9131_config_mdix(struct phy_device *phydev, u8 ctrl) |
1356 | { |
1357 | u16 val; |
1358 | |
1359 | switch (ctrl) { |
1360 | case ETH_TP_MDI: |
1361 | val = MII_KSZ9131_AUTO_MDIX_SWAP_OFF | |
1362 | MII_KSZ9131_AUTO_MDI_SET; |
1363 | break; |
1364 | case ETH_TP_MDI_X: |
1365 | val = MII_KSZ9131_AUTO_MDIX_SWAP_OFF; |
1366 | break; |
1367 | case ETH_TP_MDI_AUTO: |
1368 | val = 0; |
1369 | break; |
1370 | default: |
1371 | return 0; |
1372 | } |
1373 | |
1374 | return phy_modify(phydev, MII_KSZ9131_AUTO_MDIX, |
1375 | MII_KSZ9131_AUTO_MDIX_SWAP_OFF | |
1376 | MII_KSZ9131_AUTO_MDI_SET, set: val); |
1377 | } |
1378 | |
1379 | static int ksz9131_read_status(struct phy_device *phydev) |
1380 | { |
1381 | int ret; |
1382 | |
1383 | ret = ksz9131_mdix_update(phydev); |
1384 | if (ret < 0) |
1385 | return ret; |
1386 | |
1387 | return genphy_read_status(phydev); |
1388 | } |
1389 | |
1390 | static int ksz9131_config_aneg(struct phy_device *phydev) |
1391 | { |
1392 | int ret; |
1393 | |
1394 | ret = ksz9131_config_mdix(phydev, ctrl: phydev->mdix_ctrl); |
1395 | if (ret) |
1396 | return ret; |
1397 | |
1398 | return genphy_config_aneg(phydev); |
1399 | } |
1400 | |
1401 | static int ksz9477_get_features(struct phy_device *phydev) |
1402 | { |
1403 | int ret; |
1404 | |
1405 | ret = genphy_read_abilities(phydev); |
1406 | if (ret) |
1407 | return ret; |
1408 | |
1409 | /* The "EEE control and capability 1" (Register 3.20) seems to be |
1410 | * influenced by the "EEE advertisement 1" (Register 7.60). Changes |
1411 | * on the 7.60 will affect 3.20. So, we need to construct our own list |
1412 | * of caps. |
1413 | * KSZ8563R should have 100BaseTX/Full only. |
1414 | */ |
1415 | linkmode_and(dst: phydev->supported_eee, a: phydev->supported, |
1416 | PHY_EEE_CAP1_FEATURES); |
1417 | |
1418 | return 0; |
1419 | } |
1420 | |
1421 | #define KSZ8873MLL_GLOBAL_CONTROL_4 0x06 |
1422 | #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6) |
1423 | #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4) |
1424 | static int ksz8873mll_read_status(struct phy_device *phydev) |
1425 | { |
1426 | int regval; |
1427 | |
1428 | /* dummy read */ |
1429 | regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4); |
1430 | |
1431 | regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4); |
1432 | |
1433 | if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX) |
1434 | phydev->duplex = DUPLEX_HALF; |
1435 | else |
1436 | phydev->duplex = DUPLEX_FULL; |
1437 | |
1438 | if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED) |
1439 | phydev->speed = SPEED_10; |
1440 | else |
1441 | phydev->speed = SPEED_100; |
1442 | |
1443 | phydev->link = 1; |
1444 | phydev->pause = phydev->asym_pause = 0; |
1445 | |
1446 | return 0; |
1447 | } |
1448 | |
1449 | static int ksz9031_get_features(struct phy_device *phydev) |
1450 | { |
1451 | int ret; |
1452 | |
1453 | ret = genphy_read_abilities(phydev); |
1454 | if (ret < 0) |
1455 | return ret; |
1456 | |
1457 | /* Silicon Errata Sheet (DS80000691D or DS80000692D): |
1458 | * Whenever the device's Asymmetric Pause capability is set to 1, |
1459 | * link-up may fail after a link-up to link-down transition. |
1460 | * |
1461 | * The Errata Sheet is for ksz9031, but ksz9021 has the same issue |
1462 | * |
1463 | * Workaround: |
1464 | * Do not enable the Asymmetric Pause capability bit. |
1465 | */ |
1466 | linkmode_clear_bit(nr: ETHTOOL_LINK_MODE_Asym_Pause_BIT, addr: phydev->supported); |
1467 | |
1468 | /* We force setting the Pause capability as the core will force the |
1469 | * Asymmetric Pause capability to 1 otherwise. |
1470 | */ |
1471 | linkmode_set_bit(nr: ETHTOOL_LINK_MODE_Pause_BIT, addr: phydev->supported); |
1472 | |
1473 | return 0; |
1474 | } |
1475 | |
1476 | static int ksz9031_read_status(struct phy_device *phydev) |
1477 | { |
1478 | int err; |
1479 | int regval; |
1480 | |
1481 | err = genphy_read_status(phydev); |
1482 | if (err) |
1483 | return err; |
1484 | |
1485 | /* Make sure the PHY is not broken. Read idle error count, |
1486 | * and reset the PHY if it is maxed out. |
1487 | */ |
1488 | regval = phy_read(phydev, MII_STAT1000); |
1489 | if ((regval & 0xFF) == 0xFF) { |
1490 | phy_init_hw(phydev); |
1491 | phydev->link = 0; |
1492 | if (phydev->drv->config_intr && phy_interrupt_is_valid(phydev)) |
1493 | phydev->drv->config_intr(phydev); |
1494 | return genphy_config_aneg(phydev); |
1495 | } |
1496 | |
1497 | return 0; |
1498 | } |
1499 | |
1500 | static int ksz9x31_cable_test_start(struct phy_device *phydev) |
1501 | { |
1502 | struct kszphy_priv *priv = phydev->priv; |
1503 | int ret; |
1504 | |
1505 | /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic |
1506 | * Prior to running the cable diagnostics, Auto-negotiation should |
1507 | * be disabled, full duplex set and the link speed set to 1000Mbps |
1508 | * via the Basic Control Register. |
1509 | */ |
1510 | ret = phy_modify(phydev, MII_BMCR, |
1511 | BMCR_SPEED1000 | BMCR_FULLDPLX | |
1512 | BMCR_ANENABLE | BMCR_SPEED100, |
1513 | BMCR_SPEED1000 | BMCR_FULLDPLX); |
1514 | if (ret) |
1515 | return ret; |
1516 | |
1517 | /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic |
1518 | * The Master-Slave configuration should be set to Slave by writing |
1519 | * a value of 0x1000 to the Auto-Negotiation Master Slave Control |
1520 | * Register. |
1521 | */ |
1522 | ret = phy_read(phydev, MII_CTRL1000); |
1523 | if (ret < 0) |
1524 | return ret; |
1525 | |
1526 | /* Cache these bits, they need to be restored once LinkMD finishes. */ |
1527 | priv->vct_ctrl1000 = ret & (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER); |
1528 | ret &= ~(CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER); |
1529 | ret |= CTL1000_ENABLE_MASTER; |
1530 | |
1531 | return phy_write(phydev, MII_CTRL1000, val: ret); |
1532 | } |
1533 | |
1534 | static int ksz9x31_cable_test_result_trans(u16 status) |
1535 | { |
1536 | switch (FIELD_GET(KSZ9x31_LMD_VCT_ST_MASK, status)) { |
1537 | case KSZ9x31_LMD_VCT_ST_NORMAL: |
1538 | return ETHTOOL_A_CABLE_RESULT_CODE_OK; |
1539 | case KSZ9x31_LMD_VCT_ST_OPEN: |
1540 | return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; |
1541 | case KSZ9x31_LMD_VCT_ST_SHORT: |
1542 | return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; |
1543 | case KSZ9x31_LMD_VCT_ST_FAIL: |
1544 | fallthrough; |
1545 | default: |
1546 | return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; |
1547 | } |
1548 | } |
1549 | |
1550 | static bool ksz9x31_cable_test_failed(u16 status) |
1551 | { |
1552 | int stat = FIELD_GET(KSZ9x31_LMD_VCT_ST_MASK, status); |
1553 | |
1554 | return stat == KSZ9x31_LMD_VCT_ST_FAIL; |
1555 | } |
1556 | |
1557 | static bool ksz9x31_cable_test_fault_length_valid(u16 status) |
1558 | { |
1559 | switch (FIELD_GET(KSZ9x31_LMD_VCT_ST_MASK, status)) { |
1560 | case KSZ9x31_LMD_VCT_ST_OPEN: |
1561 | fallthrough; |
1562 | case KSZ9x31_LMD_VCT_ST_SHORT: |
1563 | return true; |
1564 | } |
1565 | return false; |
1566 | } |
1567 | |
1568 | static int ksz9x31_cable_test_fault_length(struct phy_device *phydev, u16 stat) |
1569 | { |
1570 | int dt = FIELD_GET(KSZ9x31_LMD_VCT_DATA_MASK, stat); |
1571 | |
1572 | /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic |
1573 | * |
1574 | * distance to fault = (VCT_DATA - 22) * 4 / cable propagation velocity |
1575 | */ |
1576 | if (phydev_id_compare(phydev, PHY_ID_KSZ9131)) |
1577 | dt = clamp(dt - 22, 0, 255); |
1578 | |
1579 | return (dt * 400) / 10; |
1580 | } |
1581 | |
1582 | static int ksz9x31_cable_test_wait_for_completion(struct phy_device *phydev) |
1583 | { |
1584 | int val, ret; |
1585 | |
1586 | ret = phy_read_poll_timeout(phydev, KSZ9x31_LMD, val, |
1587 | !(val & KSZ9x31_LMD_VCT_EN), |
1588 | 30000, 100000, true); |
1589 | |
1590 | return ret < 0 ? ret : 0; |
1591 | } |
1592 | |
1593 | static int ksz9x31_cable_test_get_pair(int pair) |
1594 | { |
1595 | static const int ethtool_pair[] = { |
1596 | ETHTOOL_A_CABLE_PAIR_A, |
1597 | ETHTOOL_A_CABLE_PAIR_B, |
1598 | ETHTOOL_A_CABLE_PAIR_C, |
1599 | ETHTOOL_A_CABLE_PAIR_D, |
1600 | }; |
1601 | |
1602 | return ethtool_pair[pair]; |
1603 | } |
1604 | |
1605 | static int ksz9x31_cable_test_one_pair(struct phy_device *phydev, int pair) |
1606 | { |
1607 | int ret, val; |
1608 | |
1609 | /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic |
1610 | * To test each individual cable pair, set the cable pair in the Cable |
1611 | * Diagnostics Test Pair (VCT_PAIR[1:0]) field of the LinkMD Cable |
1612 | * Diagnostic Register, along with setting the Cable Diagnostics Test |
1613 | * Enable (VCT_EN) bit. The Cable Diagnostics Test Enable (VCT_EN) bit |
1614 | * will self clear when the test is concluded. |
1615 | */ |
1616 | ret = phy_write(phydev, KSZ9x31_LMD, |
1617 | KSZ9x31_LMD_VCT_EN | KSZ9x31_LMD_VCT_PAIR(pair)); |
1618 | if (ret) |
1619 | return ret; |
1620 | |
1621 | ret = ksz9x31_cable_test_wait_for_completion(phydev); |
1622 | if (ret) |
1623 | return ret; |
1624 | |
1625 | val = phy_read(phydev, KSZ9x31_LMD); |
1626 | if (val < 0) |
1627 | return val; |
1628 | |
1629 | if (ksz9x31_cable_test_failed(status: val)) |
1630 | return -EAGAIN; |
1631 | |
1632 | ret = ethnl_cable_test_result(phydev, |
1633 | pair: ksz9x31_cable_test_get_pair(pair), |
1634 | result: ksz9x31_cable_test_result_trans(status: val)); |
1635 | if (ret) |
1636 | return ret; |
1637 | |
1638 | if (!ksz9x31_cable_test_fault_length_valid(status: val)) |
1639 | return 0; |
1640 | |
1641 | return ethnl_cable_test_fault_length(phydev, |
1642 | pair: ksz9x31_cable_test_get_pair(pair), |
1643 | cm: ksz9x31_cable_test_fault_length(phydev, stat: val)); |
1644 | } |
1645 | |
1646 | static int ksz9x31_cable_test_get_status(struct phy_device *phydev, |
1647 | bool *finished) |
1648 | { |
1649 | struct kszphy_priv *priv = phydev->priv; |
1650 | unsigned long pair_mask = 0xf; |
1651 | int retries = 20; |
1652 | int pair, ret, rv; |
1653 | |
1654 | *finished = false; |
1655 | |
1656 | /* Try harder if link partner is active */ |
1657 | while (pair_mask && retries--) { |
1658 | for_each_set_bit(pair, &pair_mask, 4) { |
1659 | ret = ksz9x31_cable_test_one_pair(phydev, pair); |
1660 | if (ret == -EAGAIN) |
1661 | continue; |
1662 | if (ret < 0) |
1663 | return ret; |
1664 | clear_bit(nr: pair, addr: &pair_mask); |
1665 | } |
1666 | /* If link partner is in autonegotiation mode it will send 2ms |
1667 | * of FLPs with at least 6ms of silence. |
1668 | * Add 2ms sleep to have better chances to hit this silence. |
1669 | */ |
1670 | if (pair_mask) |
1671 | usleep_range(min: 2000, max: 3000); |
1672 | } |
1673 | |
1674 | /* Report remaining unfinished pair result as unknown. */ |
1675 | for_each_set_bit(pair, &pair_mask, 4) { |
1676 | ret = ethnl_cable_test_result(phydev, |
1677 | pair: ksz9x31_cable_test_get_pair(pair), |
1678 | result: ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC); |
1679 | } |
1680 | |
1681 | *finished = true; |
1682 | |
1683 | /* Restore cached bits from before LinkMD got started. */ |
1684 | rv = phy_modify(phydev, MII_CTRL1000, |
1685 | CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER, |
1686 | set: priv->vct_ctrl1000); |
1687 | if (rv) |
1688 | return rv; |
1689 | |
1690 | return ret; |
1691 | } |
1692 | |
1693 | static int ksz8873mll_config_aneg(struct phy_device *phydev) |
1694 | { |
1695 | return 0; |
1696 | } |
1697 | |
1698 | static int ksz886x_config_mdix(struct phy_device *phydev, u8 ctrl) |
1699 | { |
1700 | u16 val; |
1701 | |
1702 | switch (ctrl) { |
1703 | case ETH_TP_MDI: |
1704 | val = KSZ886X_BMCR_DISABLE_AUTO_MDIX; |
1705 | break; |
1706 | case ETH_TP_MDI_X: |
1707 | /* Note: The naming of the bit KSZ886X_BMCR_FORCE_MDI is bit |
1708 | * counter intuitive, the "-X" in "1 = Force MDI" in the data |
1709 | * sheet seems to be missing: |
1710 | * 1 = Force MDI (sic!) (transmit on RX+/RX- pins) |
1711 | * 0 = Normal operation (transmit on TX+/TX- pins) |
1712 | */ |
1713 | val = KSZ886X_BMCR_DISABLE_AUTO_MDIX | KSZ886X_BMCR_FORCE_MDI; |
1714 | break; |
1715 | case ETH_TP_MDI_AUTO: |
1716 | val = 0; |
1717 | break; |
1718 | default: |
1719 | return 0; |
1720 | } |
1721 | |
1722 | return phy_modify(phydev, MII_BMCR, |
1723 | KSZ886X_BMCR_HP_MDIX | KSZ886X_BMCR_FORCE_MDI | |
1724 | KSZ886X_BMCR_DISABLE_AUTO_MDIX, |
1725 | KSZ886X_BMCR_HP_MDIX | val); |
1726 | } |
1727 | |
1728 | static int ksz886x_config_aneg(struct phy_device *phydev) |
1729 | { |
1730 | int ret; |
1731 | |
1732 | ret = genphy_config_aneg(phydev); |
1733 | if (ret) |
1734 | return ret; |
1735 | |
1736 | if (phydev->autoneg != AUTONEG_ENABLE) { |
1737 | /* When autonegotation is disabled, we need to manually force |
1738 | * the link state. If we don't do this, the PHY will keep |
1739 | * sending Fast Link Pulses (FLPs) which are part of the |
1740 | * autonegotiation process. This is not desired when |
1741 | * autonegotiation is off. |
1742 | */ |
1743 | ret = phy_set_bits(phydev, MII_KSZPHY_CTRL, |
1744 | KSZ886X_CTRL_FORCE_LINK); |
1745 | if (ret) |
1746 | return ret; |
1747 | } else { |
1748 | /* If we had previously forced the link state, we need to |
1749 | * clear KSZ886X_CTRL_FORCE_LINK bit now. Otherwise, the PHY |
1750 | * will not perform autonegotiation. |
1751 | */ |
1752 | ret = phy_clear_bits(phydev, MII_KSZPHY_CTRL, |
1753 | KSZ886X_CTRL_FORCE_LINK); |
1754 | if (ret) |
1755 | return ret; |
1756 | } |
1757 | |
1758 | /* The MDI-X configuration is automatically changed by the PHY after |
1759 | * switching from autoneg off to on. So, take MDI-X configuration under |
1760 | * own control and set it after autoneg configuration was done. |
1761 | */ |
1762 | return ksz886x_config_mdix(phydev, ctrl: phydev->mdix_ctrl); |
1763 | } |
1764 | |
1765 | static int ksz886x_mdix_update(struct phy_device *phydev) |
1766 | { |
1767 | int ret; |
1768 | |
1769 | ret = phy_read(phydev, MII_BMCR); |
1770 | if (ret < 0) |
1771 | return ret; |
1772 | |
1773 | if (ret & KSZ886X_BMCR_DISABLE_AUTO_MDIX) { |
1774 | if (ret & KSZ886X_BMCR_FORCE_MDI) |
1775 | phydev->mdix_ctrl = ETH_TP_MDI_X; |
1776 | else |
1777 | phydev->mdix_ctrl = ETH_TP_MDI; |
1778 | } else { |
1779 | phydev->mdix_ctrl = ETH_TP_MDI_AUTO; |
1780 | } |
1781 | |
1782 | ret = phy_read(phydev, MII_KSZPHY_CTRL); |
1783 | if (ret < 0) |
1784 | return ret; |
1785 | |
1786 | /* Same reverse logic as KSZ886X_BMCR_FORCE_MDI */ |
1787 | if (ret & KSZ886X_CTRL_MDIX_STAT) |
1788 | phydev->mdix = ETH_TP_MDI_X; |
1789 | else |
1790 | phydev->mdix = ETH_TP_MDI; |
1791 | |
1792 | return 0; |
1793 | } |
1794 | |
1795 | static int ksz886x_read_status(struct phy_device *phydev) |
1796 | { |
1797 | int ret; |
1798 | |
1799 | ret = ksz886x_mdix_update(phydev); |
1800 | if (ret < 0) |
1801 | return ret; |
1802 | |
1803 | return genphy_read_status(phydev); |
1804 | } |
1805 | |
1806 | struct ksz9477_errata_write { |
1807 | u8 dev_addr; |
1808 | u8 reg_addr; |
1809 | u16 val; |
1810 | }; |
1811 | |
1812 | static const struct ksz9477_errata_write ksz9477_errata_writes[] = { |
1813 | /* Register settings are needed to improve PHY receive performance */ |
1814 | {0x01, 0x6f, 0xdd0b}, |
1815 | {0x01, 0x8f, 0x6032}, |
1816 | {0x01, 0x9d, 0x248c}, |
1817 | {0x01, 0x75, 0x0060}, |
1818 | {0x01, 0xd3, 0x7777}, |
1819 | {0x1c, 0x06, 0x3008}, |
1820 | {0x1c, 0x08, 0x2000}, |
1821 | |
1822 | /* Transmit waveform amplitude can be improved (1000BASE-T, 100BASE-TX, 10BASE-Te) */ |
1823 | {0x1c, 0x04, 0x00d0}, |
1824 | |
1825 | /* Register settings are required to meet data sheet supply current specifications */ |
1826 | {0x1c, 0x13, 0x6eff}, |
1827 | {0x1c, 0x14, 0xe6ff}, |
1828 | {0x1c, 0x15, 0x6eff}, |
1829 | {0x1c, 0x16, 0xe6ff}, |
1830 | {0x1c, 0x17, 0x00ff}, |
1831 | {0x1c, 0x18, 0x43ff}, |
1832 | {0x1c, 0x19, 0xc3ff}, |
1833 | {0x1c, 0x1a, 0x6fff}, |
1834 | {0x1c, 0x1b, 0x07ff}, |
1835 | {0x1c, 0x1c, 0x0fff}, |
1836 | {0x1c, 0x1d, 0xe7ff}, |
1837 | {0x1c, 0x1e, 0xefff}, |
1838 | {0x1c, 0x20, 0xeeee}, |
1839 | }; |
1840 | |
1841 | static int ksz9477_config_init(struct phy_device *phydev) |
1842 | { |
1843 | int err; |
1844 | int i; |
1845 | |
1846 | /* Apply PHY settings to address errata listed in |
1847 | * KSZ9477, KSZ9897, KSZ9896, KSZ9567, KSZ8565 |
1848 | * Silicon Errata and Data Sheet Clarification documents. |
1849 | * |
1850 | * Document notes: Before configuring the PHY MMD registers, it is |
1851 | * necessary to set the PHY to 100 Mbps speed with auto-negotiation |
1852 | * disabled by writing to register 0xN100-0xN101. After writing the |
1853 | * MMD registers, and after all errata workarounds that involve PHY |
1854 | * register settings, write register 0xN100-0xN101 again to enable |
1855 | * and restart auto-negotiation. |
1856 | */ |
1857 | err = phy_write(phydev, MII_BMCR, BMCR_SPEED100 | BMCR_FULLDPLX); |
1858 | if (err) |
1859 | return err; |
1860 | |
1861 | for (i = 0; i < ARRAY_SIZE(ksz9477_errata_writes); ++i) { |
1862 | const struct ksz9477_errata_write *errata = &ksz9477_errata_writes[i]; |
1863 | |
1864 | err = phy_write_mmd(phydev, devad: errata->dev_addr, regnum: errata->reg_addr, val: errata->val); |
1865 | if (err) |
1866 | return err; |
1867 | } |
1868 | |
1869 | /* According to KSZ9477 Errata DS80000754C (Module 4) all EEE modes |
1870 | * in this switch shall be regarded as broken. |
1871 | */ |
1872 | if (phydev->dev_flags & MICREL_NO_EEE) |
1873 | phydev->eee_broken_modes = -1; |
1874 | |
1875 | err = genphy_restart_aneg(phydev); |
1876 | if (err) |
1877 | return err; |
1878 | |
1879 | return kszphy_config_init(phydev); |
1880 | } |
1881 | |
1882 | static int kszphy_get_sset_count(struct phy_device *phydev) |
1883 | { |
1884 | return ARRAY_SIZE(kszphy_hw_stats); |
1885 | } |
1886 | |
1887 | static void kszphy_get_strings(struct phy_device *phydev, u8 *data) |
1888 | { |
1889 | int i; |
1890 | |
1891 | for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) { |
1892 | strscpy(p: data + i * ETH_GSTRING_LEN, |
1893 | q: kszphy_hw_stats[i].string, ETH_GSTRING_LEN); |
1894 | } |
1895 | } |
1896 | |
1897 | static u64 kszphy_get_stat(struct phy_device *phydev, int i) |
1898 | { |
1899 | struct kszphy_hw_stat stat = kszphy_hw_stats[i]; |
1900 | struct kszphy_priv *priv = phydev->priv; |
1901 | int val; |
1902 | u64 ret; |
1903 | |
1904 | val = phy_read(phydev, regnum: stat.reg); |
1905 | if (val < 0) { |
1906 | ret = U64_MAX; |
1907 | } else { |
1908 | val = val & ((1 << stat.bits) - 1); |
1909 | priv->stats[i] += val; |
1910 | ret = priv->stats[i]; |
1911 | } |
1912 | |
1913 | return ret; |
1914 | } |
1915 | |
1916 | static void kszphy_get_stats(struct phy_device *phydev, |
1917 | struct ethtool_stats *stats, u64 *data) |
1918 | { |
1919 | int i; |
1920 | |
1921 | for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) |
1922 | data[i] = kszphy_get_stat(phydev, i); |
1923 | } |
1924 | |
1925 | static int kszphy_suspend(struct phy_device *phydev) |
1926 | { |
1927 | /* Disable PHY Interrupts */ |
1928 | if (phy_interrupt_is_valid(phydev)) { |
1929 | phydev->interrupts = PHY_INTERRUPT_DISABLED; |
1930 | if (phydev->drv->config_intr) |
1931 | phydev->drv->config_intr(phydev); |
1932 | } |
1933 | |
1934 | return genphy_suspend(phydev); |
1935 | } |
1936 | |
1937 | static void kszphy_parse_led_mode(struct phy_device *phydev) |
1938 | { |
1939 | const struct kszphy_type *type = phydev->drv->driver_data; |
1940 | const struct device_node *np = phydev->mdio.dev.of_node; |
1941 | struct kszphy_priv *priv = phydev->priv; |
1942 | int ret; |
1943 | |
1944 | if (type && type->led_mode_reg) { |
1945 | ret = of_property_read_u32(np, propname: "micrel,led-mode" , |
1946 | out_value: &priv->led_mode); |
1947 | |
1948 | if (ret) |
1949 | priv->led_mode = -1; |
1950 | |
1951 | if (priv->led_mode > 3) { |
1952 | phydev_err(phydev, "invalid led mode: 0x%02x\n" , |
1953 | priv->led_mode); |
1954 | priv->led_mode = -1; |
1955 | } |
1956 | } else { |
1957 | priv->led_mode = -1; |
1958 | } |
1959 | } |
1960 | |
1961 | static int kszphy_resume(struct phy_device *phydev) |
1962 | { |
1963 | int ret; |
1964 | |
1965 | genphy_resume(phydev); |
1966 | |
1967 | /* After switching from power-down to normal mode, an internal global |
1968 | * reset is automatically generated. Wait a minimum of 1 ms before |
1969 | * read/write access to the PHY registers. |
1970 | */ |
1971 | usleep_range(min: 1000, max: 2000); |
1972 | |
1973 | ret = kszphy_config_reset(phydev); |
1974 | if (ret) |
1975 | return ret; |
1976 | |
1977 | /* Enable PHY Interrupts */ |
1978 | if (phy_interrupt_is_valid(phydev)) { |
1979 | phydev->interrupts = PHY_INTERRUPT_ENABLED; |
1980 | if (phydev->drv->config_intr) |
1981 | phydev->drv->config_intr(phydev); |
1982 | } |
1983 | |
1984 | return 0; |
1985 | } |
1986 | |
1987 | static int kszphy_probe(struct phy_device *phydev) |
1988 | { |
1989 | const struct kszphy_type *type = phydev->drv->driver_data; |
1990 | const struct device_node *np = phydev->mdio.dev.of_node; |
1991 | struct kszphy_priv *priv; |
1992 | struct clk *clk; |
1993 | |
1994 | priv = devm_kzalloc(dev: &phydev->mdio.dev, size: sizeof(*priv), GFP_KERNEL); |
1995 | if (!priv) |
1996 | return -ENOMEM; |
1997 | |
1998 | phydev->priv = priv; |
1999 | |
2000 | priv->type = type; |
2001 | |
2002 | kszphy_parse_led_mode(phydev); |
2003 | |
2004 | clk = devm_clk_get(dev: &phydev->mdio.dev, id: "rmii-ref" ); |
2005 | /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */ |
2006 | if (!IS_ERR_OR_NULL(ptr: clk)) { |
2007 | unsigned long rate = clk_get_rate(clk); |
2008 | bool rmii_ref_clk_sel_25_mhz; |
2009 | |
2010 | if (type) |
2011 | priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel; |
2012 | rmii_ref_clk_sel_25_mhz = of_property_read_bool(np, |
2013 | propname: "micrel,rmii-reference-clock-select-25-mhz" ); |
2014 | |
2015 | if (rate > 24500000 && rate < 25500000) { |
2016 | priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz; |
2017 | } else if (rate > 49500000 && rate < 50500000) { |
2018 | priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz; |
2019 | } else { |
2020 | phydev_err(phydev, "Clock rate out of range: %ld\n" , |
2021 | rate); |
2022 | return -EINVAL; |
2023 | } |
2024 | } |
2025 | |
2026 | if (ksz8041_fiber_mode(phydev)) |
2027 | phydev->port = PORT_FIBRE; |
2028 | |
2029 | /* Support legacy board-file configuration */ |
2030 | if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) { |
2031 | priv->rmii_ref_clk_sel = true; |
2032 | priv->rmii_ref_clk_sel_val = true; |
2033 | } |
2034 | |
2035 | return 0; |
2036 | } |
2037 | |
2038 | static int lan8814_cable_test_start(struct phy_device *phydev) |
2039 | { |
2040 | /* If autoneg is enabled, we won't be able to test cross pair |
2041 | * short. In this case, the PHY will "detect" a link and |
2042 | * confuse the internal state machine - disable auto neg here. |
2043 | * Set the speed to 1000mbit and full duplex. |
2044 | */ |
2045 | return phy_modify(phydev, MII_BMCR, BMCR_ANENABLE | BMCR_SPEED100, |
2046 | BMCR_SPEED1000 | BMCR_FULLDPLX); |
2047 | } |
2048 | |
2049 | static int ksz886x_cable_test_start(struct phy_device *phydev) |
2050 | { |
2051 | if (phydev->dev_flags & MICREL_KSZ8_P1_ERRATA) |
2052 | return -EOPNOTSUPP; |
2053 | |
2054 | /* If autoneg is enabled, we won't be able to test cross pair |
2055 | * short. In this case, the PHY will "detect" a link and |
2056 | * confuse the internal state machine - disable auto neg here. |
2057 | * If autoneg is disabled, we should set the speed to 10mbit. |
2058 | */ |
2059 | return phy_clear_bits(phydev, MII_BMCR, BMCR_ANENABLE | BMCR_SPEED100); |
2060 | } |
2061 | |
2062 | static __always_inline int ksz886x_cable_test_result_trans(u16 status, u16 mask) |
2063 | { |
2064 | switch (FIELD_GET(mask, status)) { |
2065 | case KSZ8081_LMD_STAT_NORMAL: |
2066 | return ETHTOOL_A_CABLE_RESULT_CODE_OK; |
2067 | case KSZ8081_LMD_STAT_SHORT: |
2068 | return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; |
2069 | case KSZ8081_LMD_STAT_OPEN: |
2070 | return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; |
2071 | case KSZ8081_LMD_STAT_FAIL: |
2072 | fallthrough; |
2073 | default: |
2074 | return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; |
2075 | } |
2076 | } |
2077 | |
2078 | static __always_inline bool ksz886x_cable_test_failed(u16 status, u16 mask) |
2079 | { |
2080 | return FIELD_GET(mask, status) == |
2081 | KSZ8081_LMD_STAT_FAIL; |
2082 | } |
2083 | |
2084 | static __always_inline bool ksz886x_cable_test_fault_length_valid(u16 status, u16 mask) |
2085 | { |
2086 | switch (FIELD_GET(mask, status)) { |
2087 | case KSZ8081_LMD_STAT_OPEN: |
2088 | fallthrough; |
2089 | case KSZ8081_LMD_STAT_SHORT: |
2090 | return true; |
2091 | } |
2092 | return false; |
2093 | } |
2094 | |
2095 | static __always_inline int ksz886x_cable_test_fault_length(struct phy_device *phydev, |
2096 | u16 status, u16 data_mask) |
2097 | { |
2098 | int dt; |
2099 | |
2100 | /* According to the data sheet the distance to the fault is |
2101 | * DELTA_TIME * 0.4 meters for ksz phys. |
2102 | * (DELTA_TIME - 22) * 0.8 for lan8814 phy. |
2103 | */ |
2104 | dt = FIELD_GET(data_mask, status); |
2105 | |
2106 | if (phydev_id_compare(phydev, PHY_ID_LAN8814)) |
2107 | return ((dt - 22) * 800) / 10; |
2108 | else |
2109 | return (dt * 400) / 10; |
2110 | } |
2111 | |
2112 | static int ksz886x_cable_test_wait_for_completion(struct phy_device *phydev) |
2113 | { |
2114 | const struct kszphy_type *type = phydev->drv->driver_data; |
2115 | int val, ret; |
2116 | |
2117 | ret = phy_read_poll_timeout(phydev, type->cable_diag_reg, val, |
2118 | !(val & KSZ8081_LMD_ENABLE_TEST), |
2119 | 30000, 100000, true); |
2120 | |
2121 | return ret < 0 ? ret : 0; |
2122 | } |
2123 | |
2124 | static int lan8814_cable_test_one_pair(struct phy_device *phydev, int pair) |
2125 | { |
2126 | static const int ethtool_pair[] = { ETHTOOL_A_CABLE_PAIR_A, |
2127 | ETHTOOL_A_CABLE_PAIR_B, |
2128 | ETHTOOL_A_CABLE_PAIR_C, |
2129 | ETHTOOL_A_CABLE_PAIR_D, |
2130 | }; |
2131 | u32 fault_length; |
2132 | int ret; |
2133 | int val; |
2134 | |
2135 | val = KSZ8081_LMD_ENABLE_TEST; |
2136 | val = val | (pair << LAN8814_PAIR_BIT_SHIFT); |
2137 | |
2138 | ret = phy_write(phydev, LAN8814_CABLE_DIAG, val); |
2139 | if (ret < 0) |
2140 | return ret; |
2141 | |
2142 | ret = ksz886x_cable_test_wait_for_completion(phydev); |
2143 | if (ret) |
2144 | return ret; |
2145 | |
2146 | val = phy_read(phydev, LAN8814_CABLE_DIAG); |
2147 | if (val < 0) |
2148 | return val; |
2149 | |
2150 | if (ksz886x_cable_test_failed(status: val, LAN8814_CABLE_DIAG_STAT_MASK)) |
2151 | return -EAGAIN; |
2152 | |
2153 | ret = ethnl_cable_test_result(phydev, pair: ethtool_pair[pair], |
2154 | result: ksz886x_cable_test_result_trans(status: val, |
2155 | LAN8814_CABLE_DIAG_STAT_MASK |
2156 | )); |
2157 | if (ret) |
2158 | return ret; |
2159 | |
2160 | if (!ksz886x_cable_test_fault_length_valid(status: val, LAN8814_CABLE_DIAG_STAT_MASK)) |
2161 | return 0; |
2162 | |
2163 | fault_length = ksz886x_cable_test_fault_length(phydev, status: val, |
2164 | LAN8814_CABLE_DIAG_VCT_DATA_MASK); |
2165 | |
2166 | return ethnl_cable_test_fault_length(phydev, pair: ethtool_pair[pair], cm: fault_length); |
2167 | } |
2168 | |
2169 | static int ksz886x_cable_test_one_pair(struct phy_device *phydev, int pair) |
2170 | { |
2171 | static const int ethtool_pair[] = { |
2172 | ETHTOOL_A_CABLE_PAIR_A, |
2173 | ETHTOOL_A_CABLE_PAIR_B, |
2174 | }; |
2175 | int ret, val, mdix; |
2176 | u32 fault_length; |
2177 | |
2178 | /* There is no way to choice the pair, like we do one ksz9031. |
2179 | * We can workaround this limitation by using the MDI-X functionality. |
2180 | */ |
2181 | if (pair == 0) |
2182 | mdix = ETH_TP_MDI; |
2183 | else |
2184 | mdix = ETH_TP_MDI_X; |
2185 | |
2186 | switch (phydev->phy_id & MICREL_PHY_ID_MASK) { |
2187 | case PHY_ID_KSZ8081: |
2188 | ret = ksz8081_config_mdix(phydev, ctrl: mdix); |
2189 | break; |
2190 | case PHY_ID_KSZ886X: |
2191 | ret = ksz886x_config_mdix(phydev, ctrl: mdix); |
2192 | break; |
2193 | default: |
2194 | ret = -ENODEV; |
2195 | } |
2196 | |
2197 | if (ret) |
2198 | return ret; |
2199 | |
2200 | /* Now we are ready to fire. This command will send a 100ns pulse |
2201 | * to the pair. |
2202 | */ |
2203 | ret = phy_write(phydev, KSZ8081_LMD, KSZ8081_LMD_ENABLE_TEST); |
2204 | if (ret) |
2205 | return ret; |
2206 | |
2207 | ret = ksz886x_cable_test_wait_for_completion(phydev); |
2208 | if (ret) |
2209 | return ret; |
2210 | |
2211 | val = phy_read(phydev, KSZ8081_LMD); |
2212 | if (val < 0) |
2213 | return val; |
2214 | |
2215 | if (ksz886x_cable_test_failed(status: val, KSZ8081_LMD_STAT_MASK)) |
2216 | return -EAGAIN; |
2217 | |
2218 | ret = ethnl_cable_test_result(phydev, pair: ethtool_pair[pair], |
2219 | result: ksz886x_cable_test_result_trans(status: val, KSZ8081_LMD_STAT_MASK)); |
2220 | if (ret) |
2221 | return ret; |
2222 | |
2223 | if (!ksz886x_cable_test_fault_length_valid(status: val, KSZ8081_LMD_STAT_MASK)) |
2224 | return 0; |
2225 | |
2226 | fault_length = ksz886x_cable_test_fault_length(phydev, status: val, KSZ8081_LMD_DELTA_TIME_MASK); |
2227 | |
2228 | return ethnl_cable_test_fault_length(phydev, pair: ethtool_pair[pair], cm: fault_length); |
2229 | } |
2230 | |
2231 | static int ksz886x_cable_test_get_status(struct phy_device *phydev, |
2232 | bool *finished) |
2233 | { |
2234 | const struct kszphy_type *type = phydev->drv->driver_data; |
2235 | unsigned long pair_mask = type->pair_mask; |
2236 | int retries = 20; |
2237 | int ret = 0; |
2238 | int pair; |
2239 | |
2240 | *finished = false; |
2241 | |
2242 | /* Try harder if link partner is active */ |
2243 | while (pair_mask && retries--) { |
2244 | for_each_set_bit(pair, &pair_mask, 4) { |
2245 | if (type->cable_diag_reg == LAN8814_CABLE_DIAG) |
2246 | ret = lan8814_cable_test_one_pair(phydev, pair); |
2247 | else |
2248 | ret = ksz886x_cable_test_one_pair(phydev, pair); |
2249 | if (ret == -EAGAIN) |
2250 | continue; |
2251 | if (ret < 0) |
2252 | return ret; |
2253 | clear_bit(nr: pair, addr: &pair_mask); |
2254 | } |
2255 | /* If link partner is in autonegotiation mode it will send 2ms |
2256 | * of FLPs with at least 6ms of silence. |
2257 | * Add 2ms sleep to have better chances to hit this silence. |
2258 | */ |
2259 | if (pair_mask) |
2260 | msleep(msecs: 2); |
2261 | } |
2262 | |
2263 | *finished = true; |
2264 | |
2265 | return ret; |
2266 | } |
2267 | |
2268 | #define LAN_EXT_PAGE_ACCESS_CONTROL 0x16 |
2269 | #define LAN_EXT_PAGE_ACCESS_ADDRESS_DATA 0x17 |
2270 | #define LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC 0x4000 |
2271 | |
2272 | #define LAN8814_QSGMII_SOFT_RESET 0x43 |
2273 | #define LAN8814_QSGMII_SOFT_RESET_BIT BIT(0) |
2274 | #define LAN8814_QSGMII_PCS1G_ANEG_CONFIG 0x13 |
2275 | #define LAN8814_QSGMII_PCS1G_ANEG_CONFIG_ANEG_ENA BIT(3) |
2276 | #define LAN8814_ALIGN_SWAP 0x4a |
2277 | #define LAN8814_ALIGN_TX_A_B_SWAP 0x1 |
2278 | #define LAN8814_ALIGN_TX_A_B_SWAP_MASK GENMASK(2, 0) |
2279 | |
2280 | #define LAN8804_ALIGN_SWAP 0x4a |
2281 | #define LAN8804_ALIGN_TX_A_B_SWAP 0x1 |
2282 | #define LAN8804_ALIGN_TX_A_B_SWAP_MASK GENMASK(2, 0) |
2283 | #define LAN8814_CLOCK_MANAGEMENT 0xd |
2284 | #define LAN8814_LINK_QUALITY 0x8e |
2285 | |
2286 | static int lanphy_read_page_reg(struct phy_device *phydev, int page, u32 addr) |
2287 | { |
2288 | int data; |
2289 | |
2290 | phy_lock_mdio_bus(phydev); |
2291 | __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL, val: page); |
2292 | __phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, val: addr); |
2293 | __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL, |
2294 | val: (page | LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC)); |
2295 | data = __phy_read(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA); |
2296 | phy_unlock_mdio_bus(phydev); |
2297 | |
2298 | return data; |
2299 | } |
2300 | |
2301 | static int lanphy_write_page_reg(struct phy_device *phydev, int page, u16 addr, |
2302 | u16 val) |
2303 | { |
2304 | phy_lock_mdio_bus(phydev); |
2305 | __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL, val: page); |
2306 | __phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, val: addr); |
2307 | __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL, |
2308 | val: page | LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC); |
2309 | |
2310 | val = __phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, val); |
2311 | if (val != 0) |
2312 | phydev_err(phydev, "Error: phy_write has returned error %d\n" , |
2313 | val); |
2314 | phy_unlock_mdio_bus(phydev); |
2315 | return val; |
2316 | } |
2317 | |
2318 | static int lan8814_config_ts_intr(struct phy_device *phydev, bool enable) |
2319 | { |
2320 | u16 val = 0; |
2321 | |
2322 | if (enable) |
2323 | val = PTP_TSU_INT_EN_PTP_TX_TS_EN_ | |
2324 | PTP_TSU_INT_EN_PTP_TX_TS_OVRFL_EN_ | |
2325 | PTP_TSU_INT_EN_PTP_RX_TS_EN_ | |
2326 | PTP_TSU_INT_EN_PTP_RX_TS_OVRFL_EN_; |
2327 | |
2328 | return lanphy_write_page_reg(phydev, page: 5, PTP_TSU_INT_EN, val); |
2329 | } |
2330 | |
2331 | static void lan8814_ptp_rx_ts_get(struct phy_device *phydev, |
2332 | u32 *seconds, u32 *nano_seconds, u16 *seq_id) |
2333 | { |
2334 | *seconds = lanphy_read_page_reg(phydev, page: 5, PTP_RX_INGRESS_SEC_HI); |
2335 | *seconds = (*seconds << 16) | |
2336 | lanphy_read_page_reg(phydev, page: 5, PTP_RX_INGRESS_SEC_LO); |
2337 | |
2338 | *nano_seconds = lanphy_read_page_reg(phydev, page: 5, PTP_RX_INGRESS_NS_HI); |
2339 | *nano_seconds = ((*nano_seconds & 0x3fff) << 16) | |
2340 | lanphy_read_page_reg(phydev, page: 5, PTP_RX_INGRESS_NS_LO); |
2341 | |
2342 | *seq_id = lanphy_read_page_reg(phydev, page: 5, PTP_RX_MSG_HEADER2); |
2343 | } |
2344 | |
2345 | static void lan8814_ptp_tx_ts_get(struct phy_device *phydev, |
2346 | u32 *seconds, u32 *nano_seconds, u16 *seq_id) |
2347 | { |
2348 | *seconds = lanphy_read_page_reg(phydev, page: 5, PTP_TX_EGRESS_SEC_HI); |
2349 | *seconds = *seconds << 16 | |
2350 | lanphy_read_page_reg(phydev, page: 5, PTP_TX_EGRESS_SEC_LO); |
2351 | |
2352 | *nano_seconds = lanphy_read_page_reg(phydev, page: 5, PTP_TX_EGRESS_NS_HI); |
2353 | *nano_seconds = ((*nano_seconds & 0x3fff) << 16) | |
2354 | lanphy_read_page_reg(phydev, page: 5, PTP_TX_EGRESS_NS_LO); |
2355 | |
2356 | *seq_id = lanphy_read_page_reg(phydev, page: 5, PTP_TX_MSG_HEADER2); |
2357 | } |
2358 | |
2359 | static int lan8814_ts_info(struct mii_timestamper *mii_ts, struct ethtool_ts_info *info) |
2360 | { |
2361 | struct kszphy_ptp_priv *ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts); |
2362 | struct phy_device *phydev = ptp_priv->phydev; |
2363 | struct lan8814_shared_priv *shared = phydev->shared->priv; |
2364 | |
2365 | info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE | |
2366 | SOF_TIMESTAMPING_RX_HARDWARE | |
2367 | SOF_TIMESTAMPING_RAW_HARDWARE; |
2368 | |
2369 | info->phc_index = ptp_clock_index(ptp: shared->ptp_clock); |
2370 | |
2371 | info->tx_types = |
2372 | (1 << HWTSTAMP_TX_OFF) | |
2373 | (1 << HWTSTAMP_TX_ON) | |
2374 | (1 << HWTSTAMP_TX_ONESTEP_SYNC); |
2375 | |
2376 | info->rx_filters = |
2377 | (1 << HWTSTAMP_FILTER_NONE) | |
2378 | (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) | |
2379 | (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) | |
2380 | (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | |
2381 | (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); |
2382 | |
2383 | return 0; |
2384 | } |
2385 | |
2386 | static void lan8814_flush_fifo(struct phy_device *phydev, bool egress) |
2387 | { |
2388 | int i; |
2389 | |
2390 | for (i = 0; i < FIFO_SIZE; ++i) |
2391 | lanphy_read_page_reg(phydev, page: 5, |
2392 | addr: egress ? PTP_TX_MSG_HEADER2 : PTP_RX_MSG_HEADER2); |
2393 | |
2394 | /* Read to clear overflow status bit */ |
2395 | lanphy_read_page_reg(phydev, page: 5, PTP_TSU_INT_STS); |
2396 | } |
2397 | |
2398 | static int lan8814_hwtstamp(struct mii_timestamper *mii_ts, struct ifreq *ifr) |
2399 | { |
2400 | struct kszphy_ptp_priv *ptp_priv = |
2401 | container_of(mii_ts, struct kszphy_ptp_priv, mii_ts); |
2402 | struct phy_device *phydev = ptp_priv->phydev; |
2403 | struct lan8814_shared_priv *shared = phydev->shared->priv; |
2404 | struct lan8814_ptp_rx_ts *rx_ts, *tmp; |
2405 | struct hwtstamp_config config; |
2406 | int txcfg = 0, rxcfg = 0; |
2407 | int pkt_ts_enable; |
2408 | |
2409 | if (copy_from_user(to: &config, from: ifr->ifr_data, n: sizeof(config))) |
2410 | return -EFAULT; |
2411 | |
2412 | ptp_priv->hwts_tx_type = config.tx_type; |
2413 | ptp_priv->rx_filter = config.rx_filter; |
2414 | |
2415 | switch (config.rx_filter) { |
2416 | case HWTSTAMP_FILTER_NONE: |
2417 | ptp_priv->layer = 0; |
2418 | ptp_priv->version = 0; |
2419 | break; |
2420 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: |
2421 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: |
2422 | case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: |
2423 | ptp_priv->layer = PTP_CLASS_L4; |
2424 | ptp_priv->version = PTP_CLASS_V2; |
2425 | break; |
2426 | case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: |
2427 | case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: |
2428 | case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: |
2429 | ptp_priv->layer = PTP_CLASS_L2; |
2430 | ptp_priv->version = PTP_CLASS_V2; |
2431 | break; |
2432 | case HWTSTAMP_FILTER_PTP_V2_EVENT: |
2433 | case HWTSTAMP_FILTER_PTP_V2_SYNC: |
2434 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: |
2435 | ptp_priv->layer = PTP_CLASS_L4 | PTP_CLASS_L2; |
2436 | ptp_priv->version = PTP_CLASS_V2; |
2437 | break; |
2438 | default: |
2439 | return -ERANGE; |
2440 | } |
2441 | |
2442 | if (ptp_priv->layer & PTP_CLASS_L2) { |
2443 | rxcfg = PTP_RX_PARSE_CONFIG_LAYER2_EN_; |
2444 | txcfg = PTP_TX_PARSE_CONFIG_LAYER2_EN_; |
2445 | } else if (ptp_priv->layer & PTP_CLASS_L4) { |
2446 | rxcfg |= PTP_RX_PARSE_CONFIG_IPV4_EN_ | PTP_RX_PARSE_CONFIG_IPV6_EN_; |
2447 | txcfg |= PTP_TX_PARSE_CONFIG_IPV4_EN_ | PTP_TX_PARSE_CONFIG_IPV6_EN_; |
2448 | } |
2449 | lanphy_write_page_reg(phydev: ptp_priv->phydev, page: 5, PTP_RX_PARSE_CONFIG, val: rxcfg); |
2450 | lanphy_write_page_reg(phydev: ptp_priv->phydev, page: 5, PTP_TX_PARSE_CONFIG, val: txcfg); |
2451 | |
2452 | pkt_ts_enable = PTP_TIMESTAMP_EN_SYNC_ | PTP_TIMESTAMP_EN_DREQ_ | |
2453 | PTP_TIMESTAMP_EN_PDREQ_ | PTP_TIMESTAMP_EN_PDRES_; |
2454 | lanphy_write_page_reg(phydev: ptp_priv->phydev, page: 5, PTP_RX_TIMESTAMP_EN, val: pkt_ts_enable); |
2455 | lanphy_write_page_reg(phydev: ptp_priv->phydev, page: 5, PTP_TX_TIMESTAMP_EN, val: pkt_ts_enable); |
2456 | |
2457 | if (ptp_priv->hwts_tx_type == HWTSTAMP_TX_ONESTEP_SYNC) |
2458 | lanphy_write_page_reg(phydev: ptp_priv->phydev, page: 5, PTP_TX_MOD, |
2459 | PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_); |
2460 | |
2461 | if (config.rx_filter != HWTSTAMP_FILTER_NONE) |
2462 | lan8814_config_ts_intr(phydev: ptp_priv->phydev, enable: true); |
2463 | else |
2464 | lan8814_config_ts_intr(phydev: ptp_priv->phydev, enable: false); |
2465 | |
2466 | mutex_lock(&shared->shared_lock); |
2467 | if (config.rx_filter != HWTSTAMP_FILTER_NONE) |
2468 | shared->ref++; |
2469 | else |
2470 | shared->ref--; |
2471 | |
2472 | if (shared->ref) |
2473 | lanphy_write_page_reg(phydev: ptp_priv->phydev, page: 4, PTP_CMD_CTL, |
2474 | PTP_CMD_CTL_PTP_ENABLE_); |
2475 | else |
2476 | lanphy_write_page_reg(phydev: ptp_priv->phydev, page: 4, PTP_CMD_CTL, |
2477 | PTP_CMD_CTL_PTP_DISABLE_); |
2478 | mutex_unlock(lock: &shared->shared_lock); |
2479 | |
2480 | /* In case of multiple starts and stops, these needs to be cleared */ |
2481 | list_for_each_entry_safe(rx_ts, tmp, &ptp_priv->rx_ts_list, list) { |
2482 | list_del(entry: &rx_ts->list); |
2483 | kfree(objp: rx_ts); |
2484 | } |
2485 | skb_queue_purge(list: &ptp_priv->rx_queue); |
2486 | skb_queue_purge(list: &ptp_priv->tx_queue); |
2487 | |
2488 | lan8814_flush_fifo(phydev: ptp_priv->phydev, egress: false); |
2489 | lan8814_flush_fifo(phydev: ptp_priv->phydev, egress: true); |
2490 | |
2491 | return copy_to_user(to: ifr->ifr_data, from: &config, n: sizeof(config)) ? -EFAULT : 0; |
2492 | } |
2493 | |
2494 | static void lan8814_txtstamp(struct mii_timestamper *mii_ts, |
2495 | struct sk_buff *skb, int type) |
2496 | { |
2497 | struct kszphy_ptp_priv *ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts); |
2498 | |
2499 | switch (ptp_priv->hwts_tx_type) { |
2500 | case HWTSTAMP_TX_ONESTEP_SYNC: |
2501 | if (ptp_msg_is_sync(skb, type)) { |
2502 | kfree_skb(skb); |
2503 | return; |
2504 | } |
2505 | fallthrough; |
2506 | case HWTSTAMP_TX_ON: |
2507 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; |
2508 | skb_queue_tail(list: &ptp_priv->tx_queue, newsk: skb); |
2509 | break; |
2510 | case HWTSTAMP_TX_OFF: |
2511 | default: |
2512 | kfree_skb(skb); |
2513 | break; |
2514 | } |
2515 | } |
2516 | |
2517 | static void lan8814_get_sig_rx(struct sk_buff *skb, u16 *sig) |
2518 | { |
2519 | struct ptp_header *; |
2520 | u32 type; |
2521 | |
2522 | skb_push(skb, ETH_HLEN); |
2523 | type = ptp_classify_raw(skb); |
2524 | ptp_header = ptp_parse_header(skb, type); |
2525 | skb_pull_inline(skb, ETH_HLEN); |
2526 | |
2527 | *sig = (__force u16)(ntohs(ptp_header->sequence_id)); |
2528 | } |
2529 | |
2530 | static bool lan8814_match_rx_skb(struct kszphy_ptp_priv *ptp_priv, |
2531 | struct sk_buff *skb) |
2532 | { |
2533 | struct skb_shared_hwtstamps *shhwtstamps; |
2534 | struct lan8814_ptp_rx_ts *rx_ts, *tmp; |
2535 | unsigned long flags; |
2536 | bool ret = false; |
2537 | u16 skb_sig; |
2538 | |
2539 | lan8814_get_sig_rx(skb, sig: &skb_sig); |
2540 | |
2541 | /* Iterate over all RX timestamps and match it with the received skbs */ |
2542 | spin_lock_irqsave(&ptp_priv->rx_ts_lock, flags); |
2543 | list_for_each_entry_safe(rx_ts, tmp, &ptp_priv->rx_ts_list, list) { |
2544 | /* Check if we found the signature we were looking for. */ |
2545 | if (memcmp(p: &skb_sig, q: &rx_ts->seq_id, size: sizeof(rx_ts->seq_id))) |
2546 | continue; |
2547 | |
2548 | shhwtstamps = skb_hwtstamps(skb); |
2549 | memset(shhwtstamps, 0, sizeof(*shhwtstamps)); |
2550 | shhwtstamps->hwtstamp = ktime_set(secs: rx_ts->seconds, |
2551 | nsecs: rx_ts->nsec); |
2552 | list_del(entry: &rx_ts->list); |
2553 | kfree(objp: rx_ts); |
2554 | |
2555 | ret = true; |
2556 | break; |
2557 | } |
2558 | spin_unlock_irqrestore(lock: &ptp_priv->rx_ts_lock, flags); |
2559 | |
2560 | if (ret) |
2561 | netif_rx(skb); |
2562 | return ret; |
2563 | } |
2564 | |
2565 | static bool lan8814_rxtstamp(struct mii_timestamper *mii_ts, struct sk_buff *skb, int type) |
2566 | { |
2567 | struct kszphy_ptp_priv *ptp_priv = |
2568 | container_of(mii_ts, struct kszphy_ptp_priv, mii_ts); |
2569 | |
2570 | if (ptp_priv->rx_filter == HWTSTAMP_FILTER_NONE || |
2571 | type == PTP_CLASS_NONE) |
2572 | return false; |
2573 | |
2574 | if ((type & ptp_priv->version) == 0 || (type & ptp_priv->layer) == 0) |
2575 | return false; |
2576 | |
2577 | /* If we failed to match then add it to the queue for when the timestamp |
2578 | * will come |
2579 | */ |
2580 | if (!lan8814_match_rx_skb(ptp_priv, skb)) |
2581 | skb_queue_tail(list: &ptp_priv->rx_queue, newsk: skb); |
2582 | |
2583 | return true; |
2584 | } |
2585 | |
2586 | static void lan8814_ptp_clock_set(struct phy_device *phydev, |
2587 | u32 seconds, u32 nano_seconds) |
2588 | { |
2589 | u32 sec_low, sec_high, nsec_low, nsec_high; |
2590 | |
2591 | sec_low = seconds & 0xffff; |
2592 | sec_high = (seconds >> 16) & 0xffff; |
2593 | nsec_low = nano_seconds & 0xffff; |
2594 | nsec_high = (nano_seconds >> 16) & 0x3fff; |
2595 | |
2596 | lanphy_write_page_reg(phydev, page: 4, PTP_CLOCK_SET_SEC_LO, val: sec_low); |
2597 | lanphy_write_page_reg(phydev, page: 4, PTP_CLOCK_SET_SEC_MID, val: sec_high); |
2598 | lanphy_write_page_reg(phydev, page: 4, PTP_CLOCK_SET_NS_LO, val: nsec_low); |
2599 | lanphy_write_page_reg(phydev, page: 4, PTP_CLOCK_SET_NS_HI, val: nsec_high); |
2600 | |
2601 | lanphy_write_page_reg(phydev, page: 4, PTP_CMD_CTL, PTP_CMD_CTL_PTP_CLOCK_LOAD_); |
2602 | } |
2603 | |
2604 | static void lan8814_ptp_clock_get(struct phy_device *phydev, |
2605 | u32 *seconds, u32 *nano_seconds) |
2606 | { |
2607 | lanphy_write_page_reg(phydev, page: 4, PTP_CMD_CTL, PTP_CMD_CTL_PTP_CLOCK_READ_); |
2608 | |
2609 | *seconds = lanphy_read_page_reg(phydev, page: 4, PTP_CLOCK_READ_SEC_MID); |
2610 | *seconds = (*seconds << 16) | |
2611 | lanphy_read_page_reg(phydev, page: 4, PTP_CLOCK_READ_SEC_LO); |
2612 | |
2613 | *nano_seconds = lanphy_read_page_reg(phydev, page: 4, PTP_CLOCK_READ_NS_HI); |
2614 | *nano_seconds = ((*nano_seconds & 0x3fff) << 16) | |
2615 | lanphy_read_page_reg(phydev, page: 4, PTP_CLOCK_READ_NS_LO); |
2616 | } |
2617 | |
2618 | static int lan8814_ptpci_gettime64(struct ptp_clock_info *ptpci, |
2619 | struct timespec64 *ts) |
2620 | { |
2621 | struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv, |
2622 | ptp_clock_info); |
2623 | struct phy_device *phydev = shared->phydev; |
2624 | u32 nano_seconds; |
2625 | u32 seconds; |
2626 | |
2627 | mutex_lock(&shared->shared_lock); |
2628 | lan8814_ptp_clock_get(phydev, seconds: &seconds, nano_seconds: &nano_seconds); |
2629 | mutex_unlock(lock: &shared->shared_lock); |
2630 | ts->tv_sec = seconds; |
2631 | ts->tv_nsec = nano_seconds; |
2632 | |
2633 | return 0; |
2634 | } |
2635 | |
2636 | static int lan8814_ptpci_settime64(struct ptp_clock_info *ptpci, |
2637 | const struct timespec64 *ts) |
2638 | { |
2639 | struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv, |
2640 | ptp_clock_info); |
2641 | struct phy_device *phydev = shared->phydev; |
2642 | |
2643 | mutex_lock(&shared->shared_lock); |
2644 | lan8814_ptp_clock_set(phydev, seconds: ts->tv_sec, nano_seconds: ts->tv_nsec); |
2645 | mutex_unlock(lock: &shared->shared_lock); |
2646 | |
2647 | return 0; |
2648 | } |
2649 | |
2650 | static void lan8814_ptp_clock_step(struct phy_device *phydev, |
2651 | s64 time_step_ns) |
2652 | { |
2653 | u32 nano_seconds_step; |
2654 | u64 abs_time_step_ns; |
2655 | u32 unsigned_seconds; |
2656 | u32 nano_seconds; |
2657 | u32 remainder; |
2658 | s32 seconds; |
2659 | |
2660 | if (time_step_ns > 15000000000LL) { |
2661 | /* convert to clock set */ |
2662 | lan8814_ptp_clock_get(phydev, seconds: &unsigned_seconds, nano_seconds: &nano_seconds); |
2663 | unsigned_seconds += div_u64_rem(dividend: time_step_ns, divisor: 1000000000LL, |
2664 | remainder: &remainder); |
2665 | nano_seconds += remainder; |
2666 | if (nano_seconds >= 1000000000) { |
2667 | unsigned_seconds++; |
2668 | nano_seconds -= 1000000000; |
2669 | } |
2670 | lan8814_ptp_clock_set(phydev, seconds: unsigned_seconds, nano_seconds); |
2671 | return; |
2672 | } else if (time_step_ns < -15000000000LL) { |
2673 | /* convert to clock set */ |
2674 | time_step_ns = -time_step_ns; |
2675 | |
2676 | lan8814_ptp_clock_get(phydev, seconds: &unsigned_seconds, nano_seconds: &nano_seconds); |
2677 | unsigned_seconds -= div_u64_rem(dividend: time_step_ns, divisor: 1000000000LL, |
2678 | remainder: &remainder); |
2679 | nano_seconds_step = remainder; |
2680 | if (nano_seconds < nano_seconds_step) { |
2681 | unsigned_seconds--; |
2682 | nano_seconds += 1000000000; |
2683 | } |
2684 | nano_seconds -= nano_seconds_step; |
2685 | lan8814_ptp_clock_set(phydev, seconds: unsigned_seconds, |
2686 | nano_seconds); |
2687 | return; |
2688 | } |
2689 | |
2690 | /* do clock step */ |
2691 | if (time_step_ns >= 0) { |
2692 | abs_time_step_ns = (u64)time_step_ns; |
2693 | seconds = (s32)div_u64_rem(dividend: abs_time_step_ns, divisor: 1000000000, |
2694 | remainder: &remainder); |
2695 | nano_seconds = remainder; |
2696 | } else { |
2697 | abs_time_step_ns = (u64)(-time_step_ns); |
2698 | seconds = -((s32)div_u64_rem(dividend: abs_time_step_ns, divisor: 1000000000, |
2699 | remainder: &remainder)); |
2700 | nano_seconds = remainder; |
2701 | if (nano_seconds > 0) { |
2702 | /* subtracting nano seconds is not allowed |
2703 | * convert to subtracting from seconds, |
2704 | * and adding to nanoseconds |
2705 | */ |
2706 | seconds--; |
2707 | nano_seconds = (1000000000 - nano_seconds); |
2708 | } |
2709 | } |
2710 | |
2711 | if (nano_seconds > 0) { |
2712 | /* add 8 ns to cover the likely normal increment */ |
2713 | nano_seconds += 8; |
2714 | } |
2715 | |
2716 | if (nano_seconds >= 1000000000) { |
2717 | /* carry into seconds */ |
2718 | seconds++; |
2719 | nano_seconds -= 1000000000; |
2720 | } |
2721 | |
2722 | while (seconds) { |
2723 | if (seconds > 0) { |
2724 | u32 adjustment_value = (u32)seconds; |
2725 | u16 adjustment_value_lo, adjustment_value_hi; |
2726 | |
2727 | if (adjustment_value > 0xF) |
2728 | adjustment_value = 0xF; |
2729 | |
2730 | adjustment_value_lo = adjustment_value & 0xffff; |
2731 | adjustment_value_hi = (adjustment_value >> 16) & 0x3fff; |
2732 | |
2733 | lanphy_write_page_reg(phydev, page: 4, PTP_LTC_STEP_ADJ_LO, |
2734 | val: adjustment_value_lo); |
2735 | lanphy_write_page_reg(phydev, page: 4, PTP_LTC_STEP_ADJ_HI, |
2736 | PTP_LTC_STEP_ADJ_DIR_ | |
2737 | adjustment_value_hi); |
2738 | seconds -= ((s32)adjustment_value); |
2739 | } else { |
2740 | u32 adjustment_value = (u32)(-seconds); |
2741 | u16 adjustment_value_lo, adjustment_value_hi; |
2742 | |
2743 | if (adjustment_value > 0xF) |
2744 | adjustment_value = 0xF; |
2745 | |
2746 | adjustment_value_lo = adjustment_value & 0xffff; |
2747 | adjustment_value_hi = (adjustment_value >> 16) & 0x3fff; |
2748 | |
2749 | lanphy_write_page_reg(phydev, page: 4, PTP_LTC_STEP_ADJ_LO, |
2750 | val: adjustment_value_lo); |
2751 | lanphy_write_page_reg(phydev, page: 4, PTP_LTC_STEP_ADJ_HI, |
2752 | val: adjustment_value_hi); |
2753 | seconds += ((s32)adjustment_value); |
2754 | } |
2755 | lanphy_write_page_reg(phydev, page: 4, PTP_CMD_CTL, |
2756 | PTP_CMD_CTL_PTP_LTC_STEP_SEC_); |
2757 | } |
2758 | if (nano_seconds) { |
2759 | u16 nano_seconds_lo; |
2760 | u16 nano_seconds_hi; |
2761 | |
2762 | nano_seconds_lo = nano_seconds & 0xffff; |
2763 | nano_seconds_hi = (nano_seconds >> 16) & 0x3fff; |
2764 | |
2765 | lanphy_write_page_reg(phydev, page: 4, PTP_LTC_STEP_ADJ_LO, |
2766 | val: nano_seconds_lo); |
2767 | lanphy_write_page_reg(phydev, page: 4, PTP_LTC_STEP_ADJ_HI, |
2768 | PTP_LTC_STEP_ADJ_DIR_ | |
2769 | nano_seconds_hi); |
2770 | lanphy_write_page_reg(phydev, page: 4, PTP_CMD_CTL, |
2771 | PTP_CMD_CTL_PTP_LTC_STEP_NSEC_); |
2772 | } |
2773 | } |
2774 | |
2775 | static int lan8814_ptpci_adjtime(struct ptp_clock_info *ptpci, s64 delta) |
2776 | { |
2777 | struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv, |
2778 | ptp_clock_info); |
2779 | struct phy_device *phydev = shared->phydev; |
2780 | |
2781 | mutex_lock(&shared->shared_lock); |
2782 | lan8814_ptp_clock_step(phydev, time_step_ns: delta); |
2783 | mutex_unlock(lock: &shared->shared_lock); |
2784 | |
2785 | return 0; |
2786 | } |
2787 | |
2788 | static int lan8814_ptpci_adjfine(struct ptp_clock_info *ptpci, long scaled_ppm) |
2789 | { |
2790 | struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv, |
2791 | ptp_clock_info); |
2792 | struct phy_device *phydev = shared->phydev; |
2793 | u16 kszphy_rate_adj_lo, kszphy_rate_adj_hi; |
2794 | bool positive = true; |
2795 | u32 kszphy_rate_adj; |
2796 | |
2797 | if (scaled_ppm < 0) { |
2798 | scaled_ppm = -scaled_ppm; |
2799 | positive = false; |
2800 | } |
2801 | |
2802 | kszphy_rate_adj = LAN8814_1PPM_FORMAT * (scaled_ppm >> 16); |
2803 | kszphy_rate_adj += (LAN8814_1PPM_FORMAT * (0xffff & scaled_ppm)) >> 16; |
2804 | |
2805 | kszphy_rate_adj_lo = kszphy_rate_adj & 0xffff; |
2806 | kszphy_rate_adj_hi = (kszphy_rate_adj >> 16) & 0x3fff; |
2807 | |
2808 | if (positive) |
2809 | kszphy_rate_adj_hi |= PTP_CLOCK_RATE_ADJ_DIR_; |
2810 | |
2811 | mutex_lock(&shared->shared_lock); |
2812 | lanphy_write_page_reg(phydev, page: 4, PTP_CLOCK_RATE_ADJ_HI, val: kszphy_rate_adj_hi); |
2813 | lanphy_write_page_reg(phydev, page: 4, PTP_CLOCK_RATE_ADJ_LO, val: kszphy_rate_adj_lo); |
2814 | mutex_unlock(lock: &shared->shared_lock); |
2815 | |
2816 | return 0; |
2817 | } |
2818 | |
2819 | static void lan8814_get_sig_tx(struct sk_buff *skb, u16 *sig) |
2820 | { |
2821 | struct ptp_header *; |
2822 | u32 type; |
2823 | |
2824 | type = ptp_classify_raw(skb); |
2825 | ptp_header = ptp_parse_header(skb, type); |
2826 | |
2827 | *sig = (__force u16)(ntohs(ptp_header->sequence_id)); |
2828 | } |
2829 | |
2830 | static void lan8814_match_tx_skb(struct kszphy_ptp_priv *ptp_priv, |
2831 | u32 seconds, u32 nsec, u16 seq_id) |
2832 | { |
2833 | struct skb_shared_hwtstamps shhwtstamps; |
2834 | struct sk_buff *skb, *skb_tmp; |
2835 | unsigned long flags; |
2836 | bool ret = false; |
2837 | u16 skb_sig; |
2838 | |
2839 | spin_lock_irqsave(&ptp_priv->tx_queue.lock, flags); |
2840 | skb_queue_walk_safe(&ptp_priv->tx_queue, skb, skb_tmp) { |
2841 | lan8814_get_sig_tx(skb, sig: &skb_sig); |
2842 | |
2843 | if (memcmp(p: &skb_sig, q: &seq_id, size: sizeof(seq_id))) |
2844 | continue; |
2845 | |
2846 | __skb_unlink(skb, list: &ptp_priv->tx_queue); |
2847 | ret = true; |
2848 | break; |
2849 | } |
2850 | spin_unlock_irqrestore(lock: &ptp_priv->tx_queue.lock, flags); |
2851 | |
2852 | if (ret) { |
2853 | memset(&shhwtstamps, 0, sizeof(shhwtstamps)); |
2854 | shhwtstamps.hwtstamp = ktime_set(secs: seconds, nsecs: nsec); |
2855 | skb_complete_tx_timestamp(skb, hwtstamps: &shhwtstamps); |
2856 | } |
2857 | } |
2858 | |
2859 | static void lan8814_dequeue_tx_skb(struct kszphy_ptp_priv *ptp_priv) |
2860 | { |
2861 | struct phy_device *phydev = ptp_priv->phydev; |
2862 | u32 seconds, nsec; |
2863 | u16 seq_id; |
2864 | |
2865 | lan8814_ptp_tx_ts_get(phydev, seconds: &seconds, nano_seconds: &nsec, seq_id: &seq_id); |
2866 | lan8814_match_tx_skb(ptp_priv, seconds, nsec, seq_id); |
2867 | } |
2868 | |
2869 | static void lan8814_get_tx_ts(struct kszphy_ptp_priv *ptp_priv) |
2870 | { |
2871 | struct phy_device *phydev = ptp_priv->phydev; |
2872 | u32 reg; |
2873 | |
2874 | do { |
2875 | lan8814_dequeue_tx_skb(ptp_priv); |
2876 | |
2877 | /* If other timestamps are available in the FIFO, |
2878 | * process them. |
2879 | */ |
2880 | reg = lanphy_read_page_reg(phydev, page: 5, PTP_CAP_INFO); |
2881 | } while (PTP_CAP_INFO_TX_TS_CNT_GET_(reg) > 0); |
2882 | } |
2883 | |
2884 | static bool lan8814_match_skb(struct kszphy_ptp_priv *ptp_priv, |
2885 | struct lan8814_ptp_rx_ts *rx_ts) |
2886 | { |
2887 | struct skb_shared_hwtstamps *shhwtstamps; |
2888 | struct sk_buff *skb, *skb_tmp; |
2889 | unsigned long flags; |
2890 | bool ret = false; |
2891 | u16 skb_sig; |
2892 | |
2893 | spin_lock_irqsave(&ptp_priv->rx_queue.lock, flags); |
2894 | skb_queue_walk_safe(&ptp_priv->rx_queue, skb, skb_tmp) { |
2895 | lan8814_get_sig_rx(skb, sig: &skb_sig); |
2896 | |
2897 | if (memcmp(p: &skb_sig, q: &rx_ts->seq_id, size: sizeof(rx_ts->seq_id))) |
2898 | continue; |
2899 | |
2900 | __skb_unlink(skb, list: &ptp_priv->rx_queue); |
2901 | |
2902 | ret = true; |
2903 | break; |
2904 | } |
2905 | spin_unlock_irqrestore(lock: &ptp_priv->rx_queue.lock, flags); |
2906 | |
2907 | if (ret) { |
2908 | shhwtstamps = skb_hwtstamps(skb); |
2909 | memset(shhwtstamps, 0, sizeof(*shhwtstamps)); |
2910 | shhwtstamps->hwtstamp = ktime_set(secs: rx_ts->seconds, nsecs: rx_ts->nsec); |
2911 | netif_rx(skb); |
2912 | } |
2913 | |
2914 | return ret; |
2915 | } |
2916 | |
2917 | static void lan8814_match_rx_ts(struct kszphy_ptp_priv *ptp_priv, |
2918 | struct lan8814_ptp_rx_ts *rx_ts) |
2919 | { |
2920 | unsigned long flags; |
2921 | |
2922 | /* If we failed to match the skb add it to the queue for when |
2923 | * the frame will come |
2924 | */ |
2925 | if (!lan8814_match_skb(ptp_priv, rx_ts)) { |
2926 | spin_lock_irqsave(&ptp_priv->rx_ts_lock, flags); |
2927 | list_add(new: &rx_ts->list, head: &ptp_priv->rx_ts_list); |
2928 | spin_unlock_irqrestore(lock: &ptp_priv->rx_ts_lock, flags); |
2929 | } else { |
2930 | kfree(objp: rx_ts); |
2931 | } |
2932 | } |
2933 | |
2934 | static void lan8814_get_rx_ts(struct kszphy_ptp_priv *ptp_priv) |
2935 | { |
2936 | struct phy_device *phydev = ptp_priv->phydev; |
2937 | struct lan8814_ptp_rx_ts *rx_ts; |
2938 | u32 reg; |
2939 | |
2940 | do { |
2941 | rx_ts = kzalloc(size: sizeof(*rx_ts), GFP_KERNEL); |
2942 | if (!rx_ts) |
2943 | return; |
2944 | |
2945 | lan8814_ptp_rx_ts_get(phydev, seconds: &rx_ts->seconds, nano_seconds: &rx_ts->nsec, |
2946 | seq_id: &rx_ts->seq_id); |
2947 | lan8814_match_rx_ts(ptp_priv, rx_ts); |
2948 | |
2949 | /* If other timestamps are available in the FIFO, |
2950 | * process them. |
2951 | */ |
2952 | reg = lanphy_read_page_reg(phydev, page: 5, PTP_CAP_INFO); |
2953 | } while (PTP_CAP_INFO_RX_TS_CNT_GET_(reg) > 0); |
2954 | } |
2955 | |
2956 | static void lan8814_handle_ptp_interrupt(struct phy_device *phydev, u16 status) |
2957 | { |
2958 | struct kszphy_priv *priv = phydev->priv; |
2959 | struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv; |
2960 | |
2961 | if (status & PTP_TSU_INT_STS_PTP_TX_TS_EN_) |
2962 | lan8814_get_tx_ts(ptp_priv); |
2963 | |
2964 | if (status & PTP_TSU_INT_STS_PTP_RX_TS_EN_) |
2965 | lan8814_get_rx_ts(ptp_priv); |
2966 | |
2967 | if (status & PTP_TSU_INT_STS_PTP_TX_TS_OVRFL_INT_) { |
2968 | lan8814_flush_fifo(phydev, egress: true); |
2969 | skb_queue_purge(list: &ptp_priv->tx_queue); |
2970 | } |
2971 | |
2972 | if (status & PTP_TSU_INT_STS_PTP_RX_TS_OVRFL_INT_) { |
2973 | lan8814_flush_fifo(phydev, egress: false); |
2974 | skb_queue_purge(list: &ptp_priv->rx_queue); |
2975 | } |
2976 | } |
2977 | |
2978 | static int lan8804_config_init(struct phy_device *phydev) |
2979 | { |
2980 | int val; |
2981 | |
2982 | /* MDI-X setting for swap A,B transmit */ |
2983 | val = lanphy_read_page_reg(phydev, page: 2, LAN8804_ALIGN_SWAP); |
2984 | val &= ~LAN8804_ALIGN_TX_A_B_SWAP_MASK; |
2985 | val |= LAN8804_ALIGN_TX_A_B_SWAP; |
2986 | lanphy_write_page_reg(phydev, page: 2, LAN8804_ALIGN_SWAP, val); |
2987 | |
2988 | /* Make sure that the PHY will not stop generating the clock when the |
2989 | * link partner goes down |
2990 | */ |
2991 | lanphy_write_page_reg(phydev, page: 31, LAN8814_CLOCK_MANAGEMENT, val: 0x27e); |
2992 | lanphy_read_page_reg(phydev, page: 1, LAN8814_LINK_QUALITY); |
2993 | |
2994 | return 0; |
2995 | } |
2996 | |
2997 | static irqreturn_t lan8804_handle_interrupt(struct phy_device *phydev) |
2998 | { |
2999 | int status; |
3000 | |
3001 | status = phy_read(phydev, LAN8814_INTS); |
3002 | if (status < 0) { |
3003 | phy_error(phydev); |
3004 | return IRQ_NONE; |
3005 | } |
3006 | |
3007 | if (status > 0) |
3008 | phy_trigger_machine(phydev); |
3009 | |
3010 | return IRQ_HANDLED; |
3011 | } |
3012 | |
3013 | #define LAN8804_OUTPUT_CONTROL 25 |
3014 | #define LAN8804_OUTPUT_CONTROL_INTR_BUFFER BIT(14) |
3015 | #define LAN8804_CONTROL 31 |
3016 | #define LAN8804_CONTROL_INTR_POLARITY BIT(14) |
3017 | |
3018 | static int lan8804_config_intr(struct phy_device *phydev) |
3019 | { |
3020 | int err; |
3021 | |
3022 | /* This is an internal PHY of lan966x and is not possible to change the |
3023 | * polarity on the GIC found in lan966x, therefore change the polarity |
3024 | * of the interrupt in the PHY from being active low instead of active |
3025 | * high. |
3026 | */ |
3027 | phy_write(phydev, LAN8804_CONTROL, LAN8804_CONTROL_INTR_POLARITY); |
3028 | |
3029 | /* By default interrupt buffer is open-drain in which case the interrupt |
3030 | * can be active only low. Therefore change the interrupt buffer to be |
3031 | * push-pull to be able to change interrupt polarity |
3032 | */ |
3033 | phy_write(phydev, LAN8804_OUTPUT_CONTROL, |
3034 | LAN8804_OUTPUT_CONTROL_INTR_BUFFER); |
3035 | |
3036 | if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { |
3037 | err = phy_read(phydev, LAN8814_INTS); |
3038 | if (err < 0) |
3039 | return err; |
3040 | |
3041 | err = phy_write(phydev, LAN8814_INTC, LAN8814_INT_LINK); |
3042 | if (err) |
3043 | return err; |
3044 | } else { |
3045 | err = phy_write(phydev, LAN8814_INTC, val: 0); |
3046 | if (err) |
3047 | return err; |
3048 | |
3049 | err = phy_read(phydev, LAN8814_INTS); |
3050 | if (err < 0) |
3051 | return err; |
3052 | } |
3053 | |
3054 | return 0; |
3055 | } |
3056 | |
3057 | static irqreturn_t lan8814_handle_interrupt(struct phy_device *phydev) |
3058 | { |
3059 | int ret = IRQ_NONE; |
3060 | int irq_status; |
3061 | |
3062 | irq_status = phy_read(phydev, LAN8814_INTS); |
3063 | if (irq_status < 0) { |
3064 | phy_error(phydev); |
3065 | return IRQ_NONE; |
3066 | } |
3067 | |
3068 | if (irq_status & LAN8814_INT_LINK) { |
3069 | phy_trigger_machine(phydev); |
3070 | ret = IRQ_HANDLED; |
3071 | } |
3072 | |
3073 | while (true) { |
3074 | irq_status = lanphy_read_page_reg(phydev, page: 5, PTP_TSU_INT_STS); |
3075 | if (!irq_status) |
3076 | break; |
3077 | |
3078 | lan8814_handle_ptp_interrupt(phydev, status: irq_status); |
3079 | ret = IRQ_HANDLED; |
3080 | } |
3081 | |
3082 | return ret; |
3083 | } |
3084 | |
3085 | static int lan8814_ack_interrupt(struct phy_device *phydev) |
3086 | { |
3087 | /* bit[12..0] int status, which is a read and clear register. */ |
3088 | int rc; |
3089 | |
3090 | rc = phy_read(phydev, LAN8814_INTS); |
3091 | |
3092 | return (rc < 0) ? rc : 0; |
3093 | } |
3094 | |
3095 | static int lan8814_config_intr(struct phy_device *phydev) |
3096 | { |
3097 | int err; |
3098 | |
3099 | lanphy_write_page_reg(phydev, page: 4, LAN8814_INTR_CTRL_REG, |
3100 | LAN8814_INTR_CTRL_REG_POLARITY | |
3101 | LAN8814_INTR_CTRL_REG_INTR_ENABLE); |
3102 | |
3103 | /* enable / disable interrupts */ |
3104 | if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { |
3105 | err = lan8814_ack_interrupt(phydev); |
3106 | if (err) |
3107 | return err; |
3108 | |
3109 | err = phy_write(phydev, LAN8814_INTC, LAN8814_INT_LINK); |
3110 | } else { |
3111 | err = phy_write(phydev, LAN8814_INTC, val: 0); |
3112 | if (err) |
3113 | return err; |
3114 | |
3115 | err = lan8814_ack_interrupt(phydev); |
3116 | } |
3117 | |
3118 | return err; |
3119 | } |
3120 | |
3121 | static void lan8814_ptp_init(struct phy_device *phydev) |
3122 | { |
3123 | struct kszphy_priv *priv = phydev->priv; |
3124 | struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv; |
3125 | u32 temp; |
3126 | |
3127 | if (!IS_ENABLED(CONFIG_PTP_1588_CLOCK) || |
3128 | !IS_ENABLED(CONFIG_NETWORK_PHY_TIMESTAMPING)) |
3129 | return; |
3130 | |
3131 | lanphy_write_page_reg(phydev, page: 5, TSU_HARD_RESET, TSU_HARD_RESET_); |
3132 | |
3133 | temp = lanphy_read_page_reg(phydev, page: 5, PTP_TX_MOD); |
3134 | temp |= PTP_TX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_; |
3135 | lanphy_write_page_reg(phydev, page: 5, PTP_TX_MOD, val: temp); |
3136 | |
3137 | temp = lanphy_read_page_reg(phydev, page: 5, PTP_RX_MOD); |
3138 | temp |= PTP_RX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_; |
3139 | lanphy_write_page_reg(phydev, page: 5, PTP_RX_MOD, val: temp); |
3140 | |
3141 | lanphy_write_page_reg(phydev, page: 5, PTP_RX_PARSE_CONFIG, val: 0); |
3142 | lanphy_write_page_reg(phydev, page: 5, PTP_TX_PARSE_CONFIG, val: 0); |
3143 | |
3144 | /* Removing default registers configs related to L2 and IP */ |
3145 | lanphy_write_page_reg(phydev, page: 5, PTP_TX_PARSE_L2_ADDR_EN, val: 0); |
3146 | lanphy_write_page_reg(phydev, page: 5, PTP_RX_PARSE_L2_ADDR_EN, val: 0); |
3147 | lanphy_write_page_reg(phydev, page: 5, PTP_TX_PARSE_IP_ADDR_EN, val: 0); |
3148 | lanphy_write_page_reg(phydev, page: 5, PTP_RX_PARSE_IP_ADDR_EN, val: 0); |
3149 | |
3150 | skb_queue_head_init(list: &ptp_priv->tx_queue); |
3151 | skb_queue_head_init(list: &ptp_priv->rx_queue); |
3152 | INIT_LIST_HEAD(list: &ptp_priv->rx_ts_list); |
3153 | spin_lock_init(&ptp_priv->rx_ts_lock); |
3154 | |
3155 | ptp_priv->phydev = phydev; |
3156 | |
3157 | ptp_priv->mii_ts.rxtstamp = lan8814_rxtstamp; |
3158 | ptp_priv->mii_ts.txtstamp = lan8814_txtstamp; |
3159 | ptp_priv->mii_ts.hwtstamp = lan8814_hwtstamp; |
3160 | ptp_priv->mii_ts.ts_info = lan8814_ts_info; |
3161 | |
3162 | phydev->mii_ts = &ptp_priv->mii_ts; |
3163 | } |
3164 | |
3165 | static int lan8814_ptp_probe_once(struct phy_device *phydev) |
3166 | { |
3167 | struct lan8814_shared_priv *shared = phydev->shared->priv; |
3168 | |
3169 | /* Initialise shared lock for clock*/ |
3170 | mutex_init(&shared->shared_lock); |
3171 | |
3172 | shared->ptp_clock_info.owner = THIS_MODULE; |
3173 | snprintf(buf: shared->ptp_clock_info.name, size: 30, fmt: "%s" , phydev->drv->name); |
3174 | shared->ptp_clock_info.max_adj = 31249999; |
3175 | shared->ptp_clock_info.n_alarm = 0; |
3176 | shared->ptp_clock_info.n_ext_ts = 0; |
3177 | shared->ptp_clock_info.n_pins = 0; |
3178 | shared->ptp_clock_info.pps = 0; |
3179 | shared->ptp_clock_info.pin_config = NULL; |
3180 | shared->ptp_clock_info.adjfine = lan8814_ptpci_adjfine; |
3181 | shared->ptp_clock_info.adjtime = lan8814_ptpci_adjtime; |
3182 | shared->ptp_clock_info.gettime64 = lan8814_ptpci_gettime64; |
3183 | shared->ptp_clock_info.settime64 = lan8814_ptpci_settime64; |
3184 | shared->ptp_clock_info.getcrosststamp = NULL; |
3185 | |
3186 | shared->ptp_clock = ptp_clock_register(info: &shared->ptp_clock_info, |
3187 | parent: &phydev->mdio.dev); |
3188 | if (IS_ERR(ptr: shared->ptp_clock)) { |
3189 | phydev_err(phydev, "ptp_clock_register failed %lu\n" , |
3190 | PTR_ERR(shared->ptp_clock)); |
3191 | return -EINVAL; |
3192 | } |
3193 | |
3194 | /* Check if PHC support is missing at the configuration level */ |
3195 | if (!shared->ptp_clock) |
3196 | return 0; |
3197 | |
3198 | phydev_dbg(phydev, "successfully registered ptp clock\n" ); |
3199 | |
3200 | shared->phydev = phydev; |
3201 | |
3202 | /* The EP.4 is shared between all the PHYs in the package and also it |
3203 | * can be accessed by any of the PHYs |
3204 | */ |
3205 | lanphy_write_page_reg(phydev, page: 4, LTC_HARD_RESET, LTC_HARD_RESET_); |
3206 | lanphy_write_page_reg(phydev, page: 4, PTP_OPERATING_MODE, |
3207 | PTP_OPERATING_MODE_STANDALONE_); |
3208 | |
3209 | return 0; |
3210 | } |
3211 | |
3212 | static void lan8814_setup_led(struct phy_device *phydev, int val) |
3213 | { |
3214 | int temp; |
3215 | |
3216 | temp = lanphy_read_page_reg(phydev, page: 5, LAN8814_LED_CTRL_1); |
3217 | |
3218 | if (val) |
3219 | temp |= LAN8814_LED_CTRL_1_KSZ9031_LED_MODE_; |
3220 | else |
3221 | temp &= ~LAN8814_LED_CTRL_1_KSZ9031_LED_MODE_; |
3222 | |
3223 | lanphy_write_page_reg(phydev, page: 5, LAN8814_LED_CTRL_1, val: temp); |
3224 | } |
3225 | |
3226 | static int lan8814_config_init(struct phy_device *phydev) |
3227 | { |
3228 | struct kszphy_priv *lan8814 = phydev->priv; |
3229 | int val; |
3230 | |
3231 | /* Reset the PHY */ |
3232 | val = lanphy_read_page_reg(phydev, page: 4, LAN8814_QSGMII_SOFT_RESET); |
3233 | val |= LAN8814_QSGMII_SOFT_RESET_BIT; |
3234 | lanphy_write_page_reg(phydev, page: 4, LAN8814_QSGMII_SOFT_RESET, val); |
3235 | |
3236 | /* Disable ANEG with QSGMII PCS Host side */ |
3237 | val = lanphy_read_page_reg(phydev, page: 5, LAN8814_QSGMII_PCS1G_ANEG_CONFIG); |
3238 | val &= ~LAN8814_QSGMII_PCS1G_ANEG_CONFIG_ANEG_ENA; |
3239 | lanphy_write_page_reg(phydev, page: 5, LAN8814_QSGMII_PCS1G_ANEG_CONFIG, val); |
3240 | |
3241 | /* MDI-X setting for swap A,B transmit */ |
3242 | val = lanphy_read_page_reg(phydev, page: 2, LAN8814_ALIGN_SWAP); |
3243 | val &= ~LAN8814_ALIGN_TX_A_B_SWAP_MASK; |
3244 | val |= LAN8814_ALIGN_TX_A_B_SWAP; |
3245 | lanphy_write_page_reg(phydev, page: 2, LAN8814_ALIGN_SWAP, val); |
3246 | |
3247 | if (lan8814->led_mode >= 0) |
3248 | lan8814_setup_led(phydev, val: lan8814->led_mode); |
3249 | |
3250 | return 0; |
3251 | } |
3252 | |
3253 | /* It is expected that there will not be any 'lan8814_take_coma_mode' |
3254 | * function called in suspend. Because the GPIO line can be shared, so if one of |
3255 | * the phys goes back in coma mode, then all the other PHYs will go, which is |
3256 | * wrong. |
3257 | */ |
3258 | static int lan8814_release_coma_mode(struct phy_device *phydev) |
3259 | { |
3260 | struct gpio_desc *gpiod; |
3261 | |
3262 | gpiod = devm_gpiod_get_optional(dev: &phydev->mdio.dev, con_id: "coma-mode" , |
3263 | flags: GPIOD_OUT_HIGH_OPEN_DRAIN | |
3264 | GPIOD_FLAGS_BIT_NONEXCLUSIVE); |
3265 | if (IS_ERR(ptr: gpiod)) |
3266 | return PTR_ERR(ptr: gpiod); |
3267 | |
3268 | gpiod_set_consumer_name(desc: gpiod, name: "LAN8814 coma mode" ); |
3269 | gpiod_set_value_cansleep(desc: gpiod, value: 0); |
3270 | |
3271 | return 0; |
3272 | } |
3273 | |
3274 | static int lan8814_probe(struct phy_device *phydev) |
3275 | { |
3276 | const struct kszphy_type *type = phydev->drv->driver_data; |
3277 | struct kszphy_priv *priv; |
3278 | u16 addr; |
3279 | int err; |
3280 | |
3281 | priv = devm_kzalloc(dev: &phydev->mdio.dev, size: sizeof(*priv), GFP_KERNEL); |
3282 | if (!priv) |
3283 | return -ENOMEM; |
3284 | |
3285 | phydev->priv = priv; |
3286 | |
3287 | priv->type = type; |
3288 | |
3289 | kszphy_parse_led_mode(phydev); |
3290 | |
3291 | /* Strap-in value for PHY address, below register read gives starting |
3292 | * phy address value |
3293 | */ |
3294 | addr = lanphy_read_page_reg(phydev, page: 4, addr: 0) & 0x1F; |
3295 | devm_phy_package_join(dev: &phydev->mdio.dev, phydev, |
3296 | addr, priv_size: sizeof(struct lan8814_shared_priv)); |
3297 | |
3298 | if (phy_package_init_once(phydev)) { |
3299 | err = lan8814_release_coma_mode(phydev); |
3300 | if (err) |
3301 | return err; |
3302 | |
3303 | err = lan8814_ptp_probe_once(phydev); |
3304 | if (err) |
3305 | return err; |
3306 | } |
3307 | |
3308 | lan8814_ptp_init(phydev); |
3309 | |
3310 | return 0; |
3311 | } |
3312 | |
3313 | #define LAN8841_MMD_TIMER_REG 0 |
3314 | #define LAN8841_MMD0_REGISTER_17 17 |
3315 | #define LAN8841_MMD0_REGISTER_17_DROP_OPT(x) ((x) & 0x3) |
3316 | #define LAN8841_MMD0_REGISTER_17_XMIT_TOG_TX_DIS BIT(3) |
3317 | #define LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG 2 |
3318 | #define LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG_MAGJACK BIT(14) |
3319 | #define LAN8841_MMD_ANALOG_REG 28 |
3320 | #define LAN8841_ANALOG_CONTROL_1 1 |
3321 | #define LAN8841_ANALOG_CONTROL_1_PLL_TRIM(x) (((x) & 0x3) << 5) |
3322 | #define LAN8841_ANALOG_CONTROL_10 13 |
3323 | #define LAN8841_ANALOG_CONTROL_10_PLL_DIV(x) ((x) & 0x3) |
3324 | #define LAN8841_ANALOG_CONTROL_11 14 |
3325 | #define LAN8841_ANALOG_CONTROL_11_LDO_REF(x) (((x) & 0x7) << 12) |
3326 | #define LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT 69 |
3327 | #define LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT_VAL 0xbffc |
3328 | #define LAN8841_BTRX_POWER_DOWN 70 |
3329 | #define LAN8841_BTRX_POWER_DOWN_QBIAS_CH_A BIT(0) |
3330 | #define LAN8841_BTRX_POWER_DOWN_BTRX_CH_A BIT(1) |
3331 | #define LAN8841_BTRX_POWER_DOWN_QBIAS_CH_B BIT(2) |
3332 | #define LAN8841_BTRX_POWER_DOWN_BTRX_CH_B BIT(3) |
3333 | #define LAN8841_BTRX_POWER_DOWN_BTRX_CH_C BIT(5) |
3334 | #define LAN8841_BTRX_POWER_DOWN_BTRX_CH_D BIT(7) |
3335 | #define LAN8841_ADC_CHANNEL_MASK 198 |
3336 | #define LAN8841_PTP_RX_PARSE_L2_ADDR_EN 370 |
3337 | #define LAN8841_PTP_RX_PARSE_IP_ADDR_EN 371 |
3338 | #define LAN8841_PTP_TX_PARSE_L2_ADDR_EN 434 |
3339 | #define LAN8841_PTP_TX_PARSE_IP_ADDR_EN 435 |
3340 | #define LAN8841_PTP_CMD_CTL 256 |
3341 | #define LAN8841_PTP_CMD_CTL_PTP_ENABLE BIT(2) |
3342 | #define LAN8841_PTP_CMD_CTL_PTP_DISABLE BIT(1) |
3343 | #define LAN8841_PTP_CMD_CTL_PTP_RESET BIT(0) |
3344 | #define LAN8841_PTP_RX_PARSE_CONFIG 368 |
3345 | #define LAN8841_PTP_TX_PARSE_CONFIG 432 |
3346 | #define LAN8841_PTP_RX_MODE 381 |
3347 | #define LAN8841_PTP_INSERT_TS_EN BIT(0) |
3348 | #define LAN8841_PTP_INSERT_TS_32BIT BIT(1) |
3349 | |
3350 | static int lan8841_config_init(struct phy_device *phydev) |
3351 | { |
3352 | int ret; |
3353 | |
3354 | ret = ksz9131_config_init(phydev); |
3355 | if (ret) |
3356 | return ret; |
3357 | |
3358 | /* Initialize the HW by resetting everything */ |
3359 | phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG, |
3360 | LAN8841_PTP_CMD_CTL, |
3361 | LAN8841_PTP_CMD_CTL_PTP_RESET, |
3362 | LAN8841_PTP_CMD_CTL_PTP_RESET); |
3363 | |
3364 | phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG, |
3365 | LAN8841_PTP_CMD_CTL, |
3366 | LAN8841_PTP_CMD_CTL_PTP_ENABLE, |
3367 | LAN8841_PTP_CMD_CTL_PTP_ENABLE); |
3368 | |
3369 | /* Don't process any frames */ |
3370 | phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG, |
3371 | LAN8841_PTP_RX_PARSE_CONFIG, val: 0); |
3372 | phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG, |
3373 | LAN8841_PTP_TX_PARSE_CONFIG, val: 0); |
3374 | phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG, |
3375 | LAN8841_PTP_TX_PARSE_L2_ADDR_EN, val: 0); |
3376 | phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG, |
3377 | LAN8841_PTP_RX_PARSE_L2_ADDR_EN, val: 0); |
3378 | phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG, |
3379 | LAN8841_PTP_TX_PARSE_IP_ADDR_EN, val: 0); |
3380 | phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG, |
3381 | LAN8841_PTP_RX_PARSE_IP_ADDR_EN, val: 0); |
3382 | |
3383 | /* 100BT Clause 40 improvenent errata */ |
3384 | phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG, |
3385 | LAN8841_ANALOG_CONTROL_1, |
3386 | LAN8841_ANALOG_CONTROL_1_PLL_TRIM(0x2)); |
3387 | phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG, |
3388 | LAN8841_ANALOG_CONTROL_10, |
3389 | LAN8841_ANALOG_CONTROL_10_PLL_DIV(0x1)); |
3390 | |
3391 | /* 10M/100M Ethernet Signal Tuning Errata for Shorted-Center Tap |
3392 | * Magnetics |
3393 | */ |
3394 | ret = phy_read_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG, |
3395 | LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG); |
3396 | if (ret & LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG_MAGJACK) { |
3397 | phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG, |
3398 | LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT, |
3399 | LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT_VAL); |
3400 | phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG, |
3401 | LAN8841_BTRX_POWER_DOWN, |
3402 | LAN8841_BTRX_POWER_DOWN_QBIAS_CH_A | |
3403 | LAN8841_BTRX_POWER_DOWN_BTRX_CH_A | |
3404 | LAN8841_BTRX_POWER_DOWN_QBIAS_CH_B | |
3405 | LAN8841_BTRX_POWER_DOWN_BTRX_CH_B | |
3406 | LAN8841_BTRX_POWER_DOWN_BTRX_CH_C | |
3407 | LAN8841_BTRX_POWER_DOWN_BTRX_CH_D); |
3408 | } |
3409 | |
3410 | /* LDO Adjustment errata */ |
3411 | phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG, |
3412 | LAN8841_ANALOG_CONTROL_11, |
3413 | LAN8841_ANALOG_CONTROL_11_LDO_REF(1)); |
3414 | |
3415 | /* 100BT RGMII latency tuning errata */ |
3416 | phy_write_mmd(phydev, MDIO_MMD_PMAPMD, |
3417 | LAN8841_ADC_CHANNEL_MASK, val: 0x0); |
3418 | phy_write_mmd(phydev, LAN8841_MMD_TIMER_REG, |
3419 | LAN8841_MMD0_REGISTER_17, |
3420 | LAN8841_MMD0_REGISTER_17_DROP_OPT(2) | |
3421 | LAN8841_MMD0_REGISTER_17_XMIT_TOG_TX_DIS); |
3422 | |
3423 | return 0; |
3424 | } |
3425 | |
3426 | #define LAN8841_OUTPUT_CTRL 25 |
3427 | #define LAN8841_OUTPUT_CTRL_INT_BUFFER BIT(14) |
3428 | #define LAN8841_INT_PTP BIT(9) |
3429 | |
3430 | static int lan8841_config_intr(struct phy_device *phydev) |
3431 | { |
3432 | int err; |
3433 | |
3434 | phy_modify(phydev, LAN8841_OUTPUT_CTRL, |
3435 | LAN8841_OUTPUT_CTRL_INT_BUFFER, set: 0); |
3436 | |
3437 | if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { |
3438 | err = phy_read(phydev, LAN8814_INTS); |
3439 | if (err) |
3440 | return err; |
3441 | |
3442 | /* Enable / disable interrupts. It is OK to enable PTP interrupt |
3443 | * even if it PTP is not enabled. Because the underneath blocks |
3444 | * will not enable the PTP so we will never get the PTP |
3445 | * interrupt. |
3446 | */ |
3447 | err = phy_write(phydev, LAN8814_INTC, |
3448 | LAN8814_INT_LINK | LAN8841_INT_PTP); |
3449 | } else { |
3450 | err = phy_write(phydev, LAN8814_INTC, val: 0); |
3451 | if (err) |
3452 | return err; |
3453 | |
3454 | err = phy_read(phydev, LAN8814_INTS); |
3455 | } |
3456 | |
3457 | return err; |
3458 | } |
3459 | |
3460 | #define LAN8841_PTP_TX_EGRESS_SEC_LO 453 |
3461 | #define LAN8841_PTP_TX_EGRESS_SEC_HI 452 |
3462 | #define LAN8841_PTP_TX_EGRESS_NS_LO 451 |
3463 | #define LAN8841_PTP_TX_EGRESS_NS_HI 450 |
3464 | #define LAN8841_PTP_TX_EGRESS_NSEC_HI_VALID BIT(15) |
3465 | #define 455 |
3466 | |
3467 | static bool lan8841_ptp_get_tx_ts(struct kszphy_ptp_priv *ptp_priv, |
3468 | u32 *sec, u32 *nsec, u16 *seq) |
3469 | { |
3470 | struct phy_device *phydev = ptp_priv->phydev; |
3471 | |
3472 | *nsec = phy_read_mmd(phydev, devad: 2, LAN8841_PTP_TX_EGRESS_NS_HI); |
3473 | if (!(*nsec & LAN8841_PTP_TX_EGRESS_NSEC_HI_VALID)) |
3474 | return false; |
3475 | |
3476 | *nsec = ((*nsec & 0x3fff) << 16); |
3477 | *nsec = *nsec | phy_read_mmd(phydev, devad: 2, LAN8841_PTP_TX_EGRESS_NS_LO); |
3478 | |
3479 | *sec = phy_read_mmd(phydev, devad: 2, LAN8841_PTP_TX_EGRESS_SEC_HI); |
3480 | *sec = *sec << 16; |
3481 | *sec = *sec | phy_read_mmd(phydev, devad: 2, LAN8841_PTP_TX_EGRESS_SEC_LO); |
3482 | |
3483 | *seq = phy_read_mmd(phydev, devad: 2, LAN8841_PTP_TX_MSG_HEADER2); |
3484 | |
3485 | return true; |
3486 | } |
3487 | |
3488 | static void lan8841_ptp_process_tx_ts(struct kszphy_ptp_priv *ptp_priv) |
3489 | { |
3490 | u32 sec, nsec; |
3491 | u16 seq; |
3492 | |
3493 | while (lan8841_ptp_get_tx_ts(ptp_priv, sec: &sec, nsec: &nsec, seq: &seq)) |
3494 | lan8814_match_tx_skb(ptp_priv, seconds: sec, nsec, seq_id: seq); |
3495 | } |
3496 | |
3497 | #define LAN8841_PTP_INT_STS 259 |
3498 | #define LAN8841_PTP_INT_STS_PTP_TX_TS_OVRFL_INT BIT(13) |
3499 | #define LAN8841_PTP_INT_STS_PTP_TX_TS_INT BIT(12) |
3500 | #define LAN8841_PTP_INT_STS_PTP_GPIO_CAP_INT BIT(2) |
3501 | |
3502 | static void lan8841_ptp_flush_fifo(struct kszphy_ptp_priv *ptp_priv) |
3503 | { |
3504 | struct phy_device *phydev = ptp_priv->phydev; |
3505 | int i; |
3506 | |
3507 | for (i = 0; i < FIFO_SIZE; ++i) |
3508 | phy_read_mmd(phydev, devad: 2, LAN8841_PTP_TX_MSG_HEADER2); |
3509 | |
3510 | phy_read_mmd(phydev, devad: 2, LAN8841_PTP_INT_STS); |
3511 | } |
3512 | |
3513 | #define LAN8841_PTP_GPIO_CAP_STS 506 |
3514 | #define LAN8841_PTP_GPIO_SEL 327 |
3515 | #define LAN8841_PTP_GPIO_SEL_GPIO_SEL(gpio) ((gpio) << 8) |
3516 | #define LAN8841_PTP_GPIO_RE_LTC_SEC_HI_CAP 498 |
3517 | #define LAN8841_PTP_GPIO_RE_LTC_SEC_LO_CAP 499 |
3518 | #define LAN8841_PTP_GPIO_RE_LTC_NS_HI_CAP 500 |
3519 | #define LAN8841_PTP_GPIO_RE_LTC_NS_LO_CAP 501 |
3520 | #define LAN8841_PTP_GPIO_FE_LTC_SEC_HI_CAP 502 |
3521 | #define LAN8841_PTP_GPIO_FE_LTC_SEC_LO_CAP 503 |
3522 | #define LAN8841_PTP_GPIO_FE_LTC_NS_HI_CAP 504 |
3523 | #define LAN8841_PTP_GPIO_FE_LTC_NS_LO_CAP 505 |
3524 | |
3525 | static void lan8841_gpio_process_cap(struct kszphy_ptp_priv *ptp_priv) |
3526 | { |
3527 | struct phy_device *phydev = ptp_priv->phydev; |
3528 | struct ptp_clock_event ptp_event = {0}; |
3529 | int pin, ret, tmp; |
3530 | s32 sec, nsec; |
3531 | |
3532 | pin = ptp_find_pin_unlocked(ptp: ptp_priv->ptp_clock, func: PTP_PF_EXTTS, chan: 0); |
3533 | if (pin == -1) |
3534 | return; |
3535 | |
3536 | tmp = phy_read_mmd(phydev, devad: 2, LAN8841_PTP_GPIO_CAP_STS); |
3537 | if (tmp < 0) |
3538 | return; |
3539 | |
3540 | ret = phy_write_mmd(phydev, devad: 2, LAN8841_PTP_GPIO_SEL, |
3541 | LAN8841_PTP_GPIO_SEL_GPIO_SEL(pin)); |
3542 | if (ret) |
3543 | return; |
3544 | |
3545 | mutex_lock(&ptp_priv->ptp_lock); |
3546 | if (tmp & BIT(pin)) { |
3547 | sec = phy_read_mmd(phydev, devad: 2, LAN8841_PTP_GPIO_RE_LTC_SEC_HI_CAP); |
3548 | sec <<= 16; |
3549 | sec |= phy_read_mmd(phydev, devad: 2, LAN8841_PTP_GPIO_RE_LTC_SEC_LO_CAP); |
3550 | |
3551 | nsec = phy_read_mmd(phydev, devad: 2, LAN8841_PTP_GPIO_RE_LTC_NS_HI_CAP) & 0x3fff; |
3552 | nsec <<= 16; |
3553 | nsec |= phy_read_mmd(phydev, devad: 2, LAN8841_PTP_GPIO_RE_LTC_NS_LO_CAP); |
3554 | } else { |
3555 | sec = phy_read_mmd(phydev, devad: 2, LAN8841_PTP_GPIO_FE_LTC_SEC_HI_CAP); |
3556 | sec <<= 16; |
3557 | sec |= phy_read_mmd(phydev, devad: 2, LAN8841_PTP_GPIO_FE_LTC_SEC_LO_CAP); |
3558 | |
3559 | nsec = phy_read_mmd(phydev, devad: 2, LAN8841_PTP_GPIO_FE_LTC_NS_HI_CAP) & 0x3fff; |
3560 | nsec <<= 16; |
3561 | nsec |= phy_read_mmd(phydev, devad: 2, LAN8841_PTP_GPIO_FE_LTC_NS_LO_CAP); |
3562 | } |
3563 | mutex_unlock(lock: &ptp_priv->ptp_lock); |
3564 | ret = phy_write_mmd(phydev, devad: 2, LAN8841_PTP_GPIO_SEL, val: 0); |
3565 | if (ret) |
3566 | return; |
3567 | |
3568 | ptp_event.index = 0; |
3569 | ptp_event.timestamp = ktime_set(secs: sec, nsecs: nsec); |
3570 | ptp_event.type = PTP_CLOCK_EXTTS; |
3571 | ptp_clock_event(ptp: ptp_priv->ptp_clock, event: &ptp_event); |
3572 | } |
3573 | |
3574 | static void lan8841_handle_ptp_interrupt(struct phy_device *phydev) |
3575 | { |
3576 | struct kszphy_priv *priv = phydev->priv; |
3577 | struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv; |
3578 | u16 status; |
3579 | |
3580 | do { |
3581 | status = phy_read_mmd(phydev, devad: 2, LAN8841_PTP_INT_STS); |
3582 | |
3583 | if (status & LAN8841_PTP_INT_STS_PTP_TX_TS_INT) |
3584 | lan8841_ptp_process_tx_ts(ptp_priv); |
3585 | |
3586 | if (status & LAN8841_PTP_INT_STS_PTP_GPIO_CAP_INT) |
3587 | lan8841_gpio_process_cap(ptp_priv); |
3588 | |
3589 | if (status & LAN8841_PTP_INT_STS_PTP_TX_TS_OVRFL_INT) { |
3590 | lan8841_ptp_flush_fifo(ptp_priv); |
3591 | skb_queue_purge(list: &ptp_priv->tx_queue); |
3592 | } |
3593 | |
3594 | } while (status & (LAN8841_PTP_INT_STS_PTP_TX_TS_INT | |
3595 | LAN8841_PTP_INT_STS_PTP_GPIO_CAP_INT | |
3596 | LAN8841_PTP_INT_STS_PTP_TX_TS_OVRFL_INT)); |
3597 | } |
3598 | |
3599 | #define LAN8841_INTS_PTP BIT(9) |
3600 | |
3601 | static irqreturn_t lan8841_handle_interrupt(struct phy_device *phydev) |
3602 | { |
3603 | irqreturn_t ret = IRQ_NONE; |
3604 | int irq_status; |
3605 | |
3606 | irq_status = phy_read(phydev, LAN8814_INTS); |
3607 | if (irq_status < 0) { |
3608 | phy_error(phydev); |
3609 | return IRQ_NONE; |
3610 | } |
3611 | |
3612 | if (irq_status & LAN8814_INT_LINK) { |
3613 | phy_trigger_machine(phydev); |
3614 | ret = IRQ_HANDLED; |
3615 | } |
3616 | |
3617 | if (irq_status & LAN8841_INTS_PTP) { |
3618 | lan8841_handle_ptp_interrupt(phydev); |
3619 | ret = IRQ_HANDLED; |
3620 | } |
3621 | |
3622 | return ret; |
3623 | } |
3624 | |
3625 | static int lan8841_ts_info(struct mii_timestamper *mii_ts, |
3626 | struct ethtool_ts_info *info) |
3627 | { |
3628 | struct kszphy_ptp_priv *ptp_priv; |
3629 | |
3630 | ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts); |
3631 | |
3632 | info->phc_index = ptp_priv->ptp_clock ? |
3633 | ptp_clock_index(ptp: ptp_priv->ptp_clock) : -1; |
3634 | if (info->phc_index == -1) { |
3635 | info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE | |
3636 | SOF_TIMESTAMPING_RX_SOFTWARE | |
3637 | SOF_TIMESTAMPING_SOFTWARE; |
3638 | return 0; |
3639 | } |
3640 | |
3641 | info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE | |
3642 | SOF_TIMESTAMPING_RX_HARDWARE | |
3643 | SOF_TIMESTAMPING_RAW_HARDWARE; |
3644 | |
3645 | info->tx_types = (1 << HWTSTAMP_TX_OFF) | |
3646 | (1 << HWTSTAMP_TX_ON) | |
3647 | (1 << HWTSTAMP_TX_ONESTEP_SYNC); |
3648 | |
3649 | info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | |
3650 | (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) | |
3651 | (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | |
3652 | (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); |
3653 | |
3654 | return 0; |
3655 | } |
3656 | |
3657 | #define LAN8841_PTP_INT_EN 260 |
3658 | #define LAN8841_PTP_INT_EN_PTP_TX_TS_OVRFL_EN BIT(13) |
3659 | #define LAN8841_PTP_INT_EN_PTP_TX_TS_EN BIT(12) |
3660 | |
3661 | static void lan8841_ptp_enable_processing(struct kszphy_ptp_priv *ptp_priv, |
3662 | bool enable) |
3663 | { |
3664 | struct phy_device *phydev = ptp_priv->phydev; |
3665 | |
3666 | if (enable) { |
3667 | /* Enable interrupts on the TX side */ |
3668 | phy_modify_mmd(phydev, devad: 2, LAN8841_PTP_INT_EN, |
3669 | LAN8841_PTP_INT_EN_PTP_TX_TS_OVRFL_EN | |
3670 | LAN8841_PTP_INT_EN_PTP_TX_TS_EN, |
3671 | LAN8841_PTP_INT_EN_PTP_TX_TS_OVRFL_EN | |
3672 | LAN8841_PTP_INT_EN_PTP_TX_TS_EN); |
3673 | |
3674 | /* Enable the modification of the frame on RX side, |
3675 | * this will add the ns and 2 bits of sec in the reserved field |
3676 | * of the PTP header |
3677 | */ |
3678 | phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG, |
3679 | LAN8841_PTP_RX_MODE, |
3680 | LAN8841_PTP_INSERT_TS_EN | |
3681 | LAN8841_PTP_INSERT_TS_32BIT, |
3682 | LAN8841_PTP_INSERT_TS_EN | |
3683 | LAN8841_PTP_INSERT_TS_32BIT); |
3684 | |
3685 | ptp_schedule_worker(ptp: ptp_priv->ptp_clock, delay: 0); |
3686 | } else { |
3687 | /* Disable interrupts on the TX side */ |
3688 | phy_modify_mmd(phydev, devad: 2, LAN8841_PTP_INT_EN, |
3689 | LAN8841_PTP_INT_EN_PTP_TX_TS_OVRFL_EN | |
3690 | LAN8841_PTP_INT_EN_PTP_TX_TS_EN, set: 0); |
3691 | |
3692 | /* Disable modification of the RX frames */ |
3693 | phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG, |
3694 | LAN8841_PTP_RX_MODE, |
3695 | LAN8841_PTP_INSERT_TS_EN | |
3696 | LAN8841_PTP_INSERT_TS_32BIT, set: 0); |
3697 | |
3698 | ptp_cancel_worker_sync(ptp: ptp_priv->ptp_clock); |
3699 | } |
3700 | } |
3701 | |
3702 | #define LAN8841_PTP_RX_TIMESTAMP_EN 379 |
3703 | #define LAN8841_PTP_TX_TIMESTAMP_EN 443 |
3704 | #define LAN8841_PTP_TX_MOD 445 |
3705 | |
3706 | static int lan8841_hwtstamp(struct mii_timestamper *mii_ts, struct ifreq *ifr) |
3707 | { |
3708 | struct kszphy_ptp_priv *ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts); |
3709 | struct phy_device *phydev = ptp_priv->phydev; |
3710 | struct hwtstamp_config config; |
3711 | int txcfg = 0, rxcfg = 0; |
3712 | int pkt_ts_enable; |
3713 | |
3714 | if (copy_from_user(to: &config, from: ifr->ifr_data, n: sizeof(config))) |
3715 | return -EFAULT; |
3716 | |
3717 | ptp_priv->hwts_tx_type = config.tx_type; |
3718 | ptp_priv->rx_filter = config.rx_filter; |
3719 | |
3720 | switch (config.rx_filter) { |
3721 | case HWTSTAMP_FILTER_NONE: |
3722 | ptp_priv->layer = 0; |
3723 | ptp_priv->version = 0; |
3724 | break; |
3725 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: |
3726 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: |
3727 | case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: |
3728 | ptp_priv->layer = PTP_CLASS_L4; |
3729 | ptp_priv->version = PTP_CLASS_V2; |
3730 | break; |
3731 | case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: |
3732 | case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: |
3733 | case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: |
3734 | ptp_priv->layer = PTP_CLASS_L2; |
3735 | ptp_priv->version = PTP_CLASS_V2; |
3736 | break; |
3737 | case HWTSTAMP_FILTER_PTP_V2_EVENT: |
3738 | case HWTSTAMP_FILTER_PTP_V2_SYNC: |
3739 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: |
3740 | ptp_priv->layer = PTP_CLASS_L4 | PTP_CLASS_L2; |
3741 | ptp_priv->version = PTP_CLASS_V2; |
3742 | break; |
3743 | default: |
3744 | return -ERANGE; |
3745 | } |
3746 | |
3747 | /* Setup parsing of the frames and enable the timestamping for ptp |
3748 | * frames |
3749 | */ |
3750 | if (ptp_priv->layer & PTP_CLASS_L2) { |
3751 | rxcfg |= PTP_RX_PARSE_CONFIG_LAYER2_EN_; |
3752 | txcfg |= PTP_TX_PARSE_CONFIG_LAYER2_EN_; |
3753 | } else if (ptp_priv->layer & PTP_CLASS_L4) { |
3754 | rxcfg |= PTP_RX_PARSE_CONFIG_IPV4_EN_ | PTP_RX_PARSE_CONFIG_IPV6_EN_; |
3755 | txcfg |= PTP_TX_PARSE_CONFIG_IPV4_EN_ | PTP_TX_PARSE_CONFIG_IPV6_EN_; |
3756 | } |
3757 | |
3758 | phy_write_mmd(phydev, devad: 2, LAN8841_PTP_RX_PARSE_CONFIG, val: rxcfg); |
3759 | phy_write_mmd(phydev, devad: 2, LAN8841_PTP_TX_PARSE_CONFIG, val: txcfg); |
3760 | |
3761 | pkt_ts_enable = PTP_TIMESTAMP_EN_SYNC_ | PTP_TIMESTAMP_EN_DREQ_ | |
3762 | PTP_TIMESTAMP_EN_PDREQ_ | PTP_TIMESTAMP_EN_PDRES_; |
3763 | phy_write_mmd(phydev, devad: 2, LAN8841_PTP_RX_TIMESTAMP_EN, val: pkt_ts_enable); |
3764 | phy_write_mmd(phydev, devad: 2, LAN8841_PTP_TX_TIMESTAMP_EN, val: pkt_ts_enable); |
3765 | |
3766 | /* Enable / disable of the TX timestamp in the SYNC frames */ |
3767 | phy_modify_mmd(phydev, devad: 2, LAN8841_PTP_TX_MOD, |
3768 | PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_, |
3769 | set: ptp_priv->hwts_tx_type == HWTSTAMP_TX_ONESTEP_SYNC ? |
3770 | PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_ : 0); |
3771 | |
3772 | /* Now enable/disable the timestamping */ |
3773 | lan8841_ptp_enable_processing(ptp_priv, |
3774 | enable: config.rx_filter != HWTSTAMP_FILTER_NONE); |
3775 | |
3776 | skb_queue_purge(list: &ptp_priv->tx_queue); |
3777 | |
3778 | lan8841_ptp_flush_fifo(ptp_priv); |
3779 | |
3780 | return copy_to_user(to: ifr->ifr_data, from: &config, n: sizeof(config)) ? -EFAULT : 0; |
3781 | } |
3782 | |
3783 | static bool lan8841_rxtstamp(struct mii_timestamper *mii_ts, |
3784 | struct sk_buff *skb, int type) |
3785 | { |
3786 | struct kszphy_ptp_priv *ptp_priv = |
3787 | container_of(mii_ts, struct kszphy_ptp_priv, mii_ts); |
3788 | struct ptp_header * = ptp_parse_header(skb, type); |
3789 | struct skb_shared_hwtstamps *shhwtstamps; |
3790 | struct timespec64 ts; |
3791 | unsigned long flags; |
3792 | u32 ; |
3793 | |
3794 | if (!header) |
3795 | return false; |
3796 | |
3797 | if (ptp_priv->rx_filter == HWTSTAMP_FILTER_NONE || |
3798 | type == PTP_CLASS_NONE) |
3799 | return false; |
3800 | |
3801 | if ((type & ptp_priv->version) == 0 || (type & ptp_priv->layer) == 0) |
3802 | return false; |
3803 | |
3804 | spin_lock_irqsave(&ptp_priv->seconds_lock, flags); |
3805 | ts.tv_sec = ptp_priv->seconds; |
3806 | spin_unlock_irqrestore(lock: &ptp_priv->seconds_lock, flags); |
3807 | ts_header = __be32_to_cpu(header->reserved2); |
3808 | |
3809 | shhwtstamps = skb_hwtstamps(skb); |
3810 | memset(shhwtstamps, 0, sizeof(*shhwtstamps)); |
3811 | |
3812 | /* Check for any wrap arounds for the second part */ |
3813 | if ((ts.tv_sec & GENMASK(1, 0)) == 0 && (ts_header >> 30) == 3) |
3814 | ts.tv_sec -= GENMASK(1, 0) + 1; |
3815 | else if ((ts.tv_sec & GENMASK(1, 0)) == 3 && (ts_header >> 30) == 0) |
3816 | ts.tv_sec += 1; |
3817 | |
3818 | shhwtstamps->hwtstamp = |
3819 | ktime_set(secs: (ts.tv_sec & ~(GENMASK(1, 0))) | ts_header >> 30, |
3820 | nsecs: ts_header & GENMASK(29, 0)); |
3821 | header->reserved2 = 0; |
3822 | |
3823 | netif_rx(skb); |
3824 | |
3825 | return true; |
3826 | } |
3827 | |
3828 | #define LAN8841_EVENT_A 0 |
3829 | #define LAN8841_EVENT_B 1 |
3830 | #define LAN8841_PTP_LTC_TARGET_SEC_HI(event) ((event) == LAN8841_EVENT_A ? 278 : 288) |
3831 | #define LAN8841_PTP_LTC_TARGET_SEC_LO(event) ((event) == LAN8841_EVENT_A ? 279 : 289) |
3832 | #define LAN8841_PTP_LTC_TARGET_NS_HI(event) ((event) == LAN8841_EVENT_A ? 280 : 290) |
3833 | #define LAN8841_PTP_LTC_TARGET_NS_LO(event) ((event) == LAN8841_EVENT_A ? 281 : 291) |
3834 | |
3835 | static int lan8841_ptp_set_target(struct kszphy_ptp_priv *ptp_priv, u8 event, |
3836 | s64 sec, u32 nsec) |
3837 | { |
3838 | struct phy_device *phydev = ptp_priv->phydev; |
3839 | int ret; |
3840 | |
3841 | ret = phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_TARGET_SEC_HI(event), |
3842 | upper_16_bits(sec)); |
3843 | if (ret) |
3844 | return ret; |
3845 | |
3846 | ret = phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_TARGET_SEC_LO(event), |
3847 | lower_16_bits(sec)); |
3848 | if (ret) |
3849 | return ret; |
3850 | |
3851 | ret = phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_TARGET_NS_HI(event) & 0x3fff, |
3852 | upper_16_bits(nsec)); |
3853 | if (ret) |
3854 | return ret; |
3855 | |
3856 | return phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_TARGET_NS_LO(event), |
3857 | lower_16_bits(nsec)); |
3858 | } |
3859 | |
3860 | #define LAN8841_BUFFER_TIME 2 |
3861 | |
3862 | static int lan8841_ptp_update_target(struct kszphy_ptp_priv *ptp_priv, |
3863 | const struct timespec64 *ts) |
3864 | { |
3865 | return lan8841_ptp_set_target(ptp_priv, LAN8841_EVENT_A, |
3866 | sec: ts->tv_sec + LAN8841_BUFFER_TIME, nsec: 0); |
3867 | } |
3868 | |
3869 | #define LAN8841_PTP_LTC_TARGET_RELOAD_SEC_HI(event) ((event) == LAN8841_EVENT_A ? 282 : 292) |
3870 | #define LAN8841_PTP_LTC_TARGET_RELOAD_SEC_LO(event) ((event) == LAN8841_EVENT_A ? 283 : 293) |
3871 | #define LAN8841_PTP_LTC_TARGET_RELOAD_NS_HI(event) ((event) == LAN8841_EVENT_A ? 284 : 294) |
3872 | #define LAN8841_PTP_LTC_TARGET_RELOAD_NS_LO(event) ((event) == LAN8841_EVENT_A ? 285 : 295) |
3873 | |
3874 | static int lan8841_ptp_set_reload(struct kszphy_ptp_priv *ptp_priv, u8 event, |
3875 | s64 sec, u32 nsec) |
3876 | { |
3877 | struct phy_device *phydev = ptp_priv->phydev; |
3878 | int ret; |
3879 | |
3880 | ret = phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_TARGET_RELOAD_SEC_HI(event), |
3881 | upper_16_bits(sec)); |
3882 | if (ret) |
3883 | return ret; |
3884 | |
3885 | ret = phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_TARGET_RELOAD_SEC_LO(event), |
3886 | lower_16_bits(sec)); |
3887 | if (ret) |
3888 | return ret; |
3889 | |
3890 | ret = phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_TARGET_RELOAD_NS_HI(event) & 0x3fff, |
3891 | upper_16_bits(nsec)); |
3892 | if (ret) |
3893 | return ret; |
3894 | |
3895 | return phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_TARGET_RELOAD_NS_LO(event), |
3896 | lower_16_bits(nsec)); |
3897 | } |
3898 | |
3899 | #define LAN8841_PTP_LTC_SET_SEC_HI 262 |
3900 | #define LAN8841_PTP_LTC_SET_SEC_MID 263 |
3901 | #define LAN8841_PTP_LTC_SET_SEC_LO 264 |
3902 | #define LAN8841_PTP_LTC_SET_NS_HI 265 |
3903 | #define LAN8841_PTP_LTC_SET_NS_LO 266 |
3904 | #define LAN8841_PTP_CMD_CTL_PTP_LTC_LOAD BIT(4) |
3905 | |
3906 | static int lan8841_ptp_settime64(struct ptp_clock_info *ptp, |
3907 | const struct timespec64 *ts) |
3908 | { |
3909 | struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv, |
3910 | ptp_clock_info); |
3911 | struct phy_device *phydev = ptp_priv->phydev; |
3912 | unsigned long flags; |
3913 | int ret; |
3914 | |
3915 | /* Set the value to be stored */ |
3916 | mutex_lock(&ptp_priv->ptp_lock); |
3917 | phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_SET_SEC_LO, lower_16_bits(ts->tv_sec)); |
3918 | phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_SET_SEC_MID, upper_16_bits(ts->tv_sec)); |
3919 | phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_SET_SEC_HI, upper_32_bits(ts->tv_sec) & 0xffff); |
3920 | phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_SET_NS_LO, lower_16_bits(ts->tv_nsec)); |
3921 | phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_SET_NS_HI, upper_16_bits(ts->tv_nsec) & 0x3fff); |
3922 | |
3923 | /* Set the command to load the LTC */ |
3924 | phy_write_mmd(phydev, devad: 2, LAN8841_PTP_CMD_CTL, |
3925 | LAN8841_PTP_CMD_CTL_PTP_LTC_LOAD); |
3926 | ret = lan8841_ptp_update_target(ptp_priv, ts); |
3927 | mutex_unlock(lock: &ptp_priv->ptp_lock); |
3928 | |
3929 | spin_lock_irqsave(&ptp_priv->seconds_lock, flags); |
3930 | ptp_priv->seconds = ts->tv_sec; |
3931 | spin_unlock_irqrestore(lock: &ptp_priv->seconds_lock, flags); |
3932 | |
3933 | return ret; |
3934 | } |
3935 | |
3936 | #define LAN8841_PTP_LTC_RD_SEC_HI 358 |
3937 | #define LAN8841_PTP_LTC_RD_SEC_MID 359 |
3938 | #define LAN8841_PTP_LTC_RD_SEC_LO 360 |
3939 | #define LAN8841_PTP_LTC_RD_NS_HI 361 |
3940 | #define LAN8841_PTP_LTC_RD_NS_LO 362 |
3941 | #define LAN8841_PTP_CMD_CTL_PTP_LTC_READ BIT(3) |
3942 | |
3943 | static int lan8841_ptp_gettime64(struct ptp_clock_info *ptp, |
3944 | struct timespec64 *ts) |
3945 | { |
3946 | struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv, |
3947 | ptp_clock_info); |
3948 | struct phy_device *phydev = ptp_priv->phydev; |
3949 | time64_t s; |
3950 | s64 ns; |
3951 | |
3952 | mutex_lock(&ptp_priv->ptp_lock); |
3953 | /* Issue the command to read the LTC */ |
3954 | phy_write_mmd(phydev, devad: 2, LAN8841_PTP_CMD_CTL, |
3955 | LAN8841_PTP_CMD_CTL_PTP_LTC_READ); |
3956 | |
3957 | /* Read the LTC */ |
3958 | s = phy_read_mmd(phydev, devad: 2, LAN8841_PTP_LTC_RD_SEC_HI); |
3959 | s <<= 16; |
3960 | s |= phy_read_mmd(phydev, devad: 2, LAN8841_PTP_LTC_RD_SEC_MID); |
3961 | s <<= 16; |
3962 | s |= phy_read_mmd(phydev, devad: 2, LAN8841_PTP_LTC_RD_SEC_LO); |
3963 | |
3964 | ns = phy_read_mmd(phydev, devad: 2, LAN8841_PTP_LTC_RD_NS_HI) & 0x3fff; |
3965 | ns <<= 16; |
3966 | ns |= phy_read_mmd(phydev, devad: 2, LAN8841_PTP_LTC_RD_NS_LO); |
3967 | mutex_unlock(lock: &ptp_priv->ptp_lock); |
3968 | |
3969 | set_normalized_timespec64(ts, sec: s, nsec: ns); |
3970 | return 0; |
3971 | } |
3972 | |
3973 | static void lan8841_ptp_getseconds(struct ptp_clock_info *ptp, |
3974 | struct timespec64 *ts) |
3975 | { |
3976 | struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv, |
3977 | ptp_clock_info); |
3978 | struct phy_device *phydev = ptp_priv->phydev; |
3979 | time64_t s; |
3980 | |
3981 | mutex_lock(&ptp_priv->ptp_lock); |
3982 | /* Issue the command to read the LTC */ |
3983 | phy_write_mmd(phydev, devad: 2, LAN8841_PTP_CMD_CTL, |
3984 | LAN8841_PTP_CMD_CTL_PTP_LTC_READ); |
3985 | |
3986 | /* Read the LTC */ |
3987 | s = phy_read_mmd(phydev, devad: 2, LAN8841_PTP_LTC_RD_SEC_HI); |
3988 | s <<= 16; |
3989 | s |= phy_read_mmd(phydev, devad: 2, LAN8841_PTP_LTC_RD_SEC_MID); |
3990 | s <<= 16; |
3991 | s |= phy_read_mmd(phydev, devad: 2, LAN8841_PTP_LTC_RD_SEC_LO); |
3992 | mutex_unlock(lock: &ptp_priv->ptp_lock); |
3993 | |
3994 | set_normalized_timespec64(ts, sec: s, nsec: 0); |
3995 | } |
3996 | |
3997 | #define LAN8841_PTP_LTC_STEP_ADJ_LO 276 |
3998 | #define LAN8841_PTP_LTC_STEP_ADJ_HI 275 |
3999 | #define LAN8841_PTP_LTC_STEP_ADJ_DIR BIT(15) |
4000 | #define LAN8841_PTP_CMD_CTL_PTP_LTC_STEP_SECONDS BIT(5) |
4001 | #define LAN8841_PTP_CMD_CTL_PTP_LTC_STEP_NANOSECONDS BIT(6) |
4002 | |
4003 | static int lan8841_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) |
4004 | { |
4005 | struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv, |
4006 | ptp_clock_info); |
4007 | struct phy_device *phydev = ptp_priv->phydev; |
4008 | struct timespec64 ts; |
4009 | bool add = true; |
4010 | u32 nsec; |
4011 | s32 sec; |
4012 | int ret; |
4013 | |
4014 | /* The HW allows up to 15 sec to adjust the time, but here we limit to |
4015 | * 10 sec the adjustment. The reason is, in case the adjustment is 14 |
4016 | * sec and 999999999 nsec, then we add 8ns to compansate the actual |
4017 | * increment so the value can be bigger than 15 sec. Therefore limit the |
4018 | * possible adjustments so we will not have these corner cases |
4019 | */ |
4020 | if (delta > 10000000000LL || delta < -10000000000LL) { |
4021 | /* The timeadjustment is too big, so fall back using set time */ |
4022 | u64 now; |
4023 | |
4024 | ptp->gettime64(ptp, &ts); |
4025 | |
4026 | now = ktime_to_ns(kt: timespec64_to_ktime(ts)); |
4027 | ts = ns_to_timespec64(nsec: now + delta); |
4028 | |
4029 | ptp->settime64(ptp, &ts); |
4030 | return 0; |
4031 | } |
4032 | |
4033 | sec = div_u64_rem(dividend: delta < 0 ? -delta : delta, NSEC_PER_SEC, remainder: &nsec); |
4034 | if (delta < 0 && nsec != 0) { |
4035 | /* It is not allowed to adjust low the nsec part, therefore |
4036 | * subtract more from second part and add to nanosecond such |
4037 | * that would roll over, so the second part will increase |
4038 | */ |
4039 | sec--; |
4040 | nsec = NSEC_PER_SEC - nsec; |
4041 | } |
4042 | |
4043 | /* Calculate the adjustments and the direction */ |
4044 | if (delta < 0) |
4045 | add = false; |
4046 | |
4047 | if (nsec > 0) |
4048 | /* add 8 ns to cover the likely normal increment */ |
4049 | nsec += 8; |
4050 | |
4051 | if (nsec >= NSEC_PER_SEC) { |
4052 | /* carry into seconds */ |
4053 | sec++; |
4054 | nsec -= NSEC_PER_SEC; |
4055 | } |
4056 | |
4057 | mutex_lock(&ptp_priv->ptp_lock); |
4058 | if (sec) { |
4059 | phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_STEP_ADJ_LO, val: sec); |
4060 | phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_STEP_ADJ_HI, |
4061 | val: add ? LAN8841_PTP_LTC_STEP_ADJ_DIR : 0); |
4062 | phy_write_mmd(phydev, devad: 2, LAN8841_PTP_CMD_CTL, |
4063 | LAN8841_PTP_CMD_CTL_PTP_LTC_STEP_SECONDS); |
4064 | } |
4065 | |
4066 | if (nsec) { |
4067 | phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_STEP_ADJ_LO, |
4068 | val: nsec & 0xffff); |
4069 | phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_STEP_ADJ_HI, |
4070 | val: (nsec >> 16) & 0x3fff); |
4071 | phy_write_mmd(phydev, devad: 2, LAN8841_PTP_CMD_CTL, |
4072 | LAN8841_PTP_CMD_CTL_PTP_LTC_STEP_NANOSECONDS); |
4073 | } |
4074 | mutex_unlock(lock: &ptp_priv->ptp_lock); |
4075 | |
4076 | /* Update the target clock */ |
4077 | ptp->gettime64(ptp, &ts); |
4078 | mutex_lock(&ptp_priv->ptp_lock); |
4079 | ret = lan8841_ptp_update_target(ptp_priv, ts: &ts); |
4080 | mutex_unlock(lock: &ptp_priv->ptp_lock); |
4081 | |
4082 | return ret; |
4083 | } |
4084 | |
4085 | #define LAN8841_PTP_LTC_RATE_ADJ_HI 269 |
4086 | #define LAN8841_PTP_LTC_RATE_ADJ_HI_DIR BIT(15) |
4087 | #define LAN8841_PTP_LTC_RATE_ADJ_LO 270 |
4088 | |
4089 | static int lan8841_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm) |
4090 | { |
4091 | struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv, |
4092 | ptp_clock_info); |
4093 | struct phy_device *phydev = ptp_priv->phydev; |
4094 | bool faster = true; |
4095 | u32 rate; |
4096 | |
4097 | if (!scaled_ppm) |
4098 | return 0; |
4099 | |
4100 | if (scaled_ppm < 0) { |
4101 | scaled_ppm = -scaled_ppm; |
4102 | faster = false; |
4103 | } |
4104 | |
4105 | rate = LAN8814_1PPM_FORMAT * (upper_16_bits(scaled_ppm)); |
4106 | rate += (LAN8814_1PPM_FORMAT * (lower_16_bits(scaled_ppm))) >> 16; |
4107 | |
4108 | mutex_lock(&ptp_priv->ptp_lock); |
4109 | phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_RATE_ADJ_HI, |
4110 | val: faster ? LAN8841_PTP_LTC_RATE_ADJ_HI_DIR | (upper_16_bits(rate) & 0x3fff) |
4111 | : upper_16_bits(rate) & 0x3fff); |
4112 | phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_RATE_ADJ_LO, lower_16_bits(rate)); |
4113 | mutex_unlock(lock: &ptp_priv->ptp_lock); |
4114 | |
4115 | return 0; |
4116 | } |
4117 | |
4118 | static int lan8841_ptp_verify(struct ptp_clock_info *ptp, unsigned int pin, |
4119 | enum ptp_pin_function func, unsigned int chan) |
4120 | { |
4121 | switch (func) { |
4122 | case PTP_PF_NONE: |
4123 | case PTP_PF_PEROUT: |
4124 | case PTP_PF_EXTTS: |
4125 | break; |
4126 | default: |
4127 | return -1; |
4128 | } |
4129 | |
4130 | return 0; |
4131 | } |
4132 | |
4133 | #define LAN8841_PTP_GPIO_NUM 10 |
4134 | #define LAN8841_GPIO_EN 128 |
4135 | #define LAN8841_GPIO_DIR 129 |
4136 | #define LAN8841_GPIO_BUF 130 |
4137 | |
4138 | static int lan8841_ptp_perout_off(struct kszphy_ptp_priv *ptp_priv, int pin) |
4139 | { |
4140 | struct phy_device *phydev = ptp_priv->phydev; |
4141 | int ret; |
4142 | |
4143 | ret = phy_clear_bits_mmd(phydev, devad: 2, LAN8841_GPIO_EN, BIT(pin)); |
4144 | if (ret) |
4145 | return ret; |
4146 | |
4147 | ret = phy_clear_bits_mmd(phydev, devad: 2, LAN8841_GPIO_DIR, BIT(pin)); |
4148 | if (ret) |
4149 | return ret; |
4150 | |
4151 | return phy_clear_bits_mmd(phydev, devad: 2, LAN8841_GPIO_BUF, BIT(pin)); |
4152 | } |
4153 | |
4154 | static int lan8841_ptp_perout_on(struct kszphy_ptp_priv *ptp_priv, int pin) |
4155 | { |
4156 | struct phy_device *phydev = ptp_priv->phydev; |
4157 | int ret; |
4158 | |
4159 | ret = phy_set_bits_mmd(phydev, devad: 2, LAN8841_GPIO_EN, BIT(pin)); |
4160 | if (ret) |
4161 | return ret; |
4162 | |
4163 | ret = phy_set_bits_mmd(phydev, devad: 2, LAN8841_GPIO_DIR, BIT(pin)); |
4164 | if (ret) |
4165 | return ret; |
4166 | |
4167 | return phy_set_bits_mmd(phydev, devad: 2, LAN8841_GPIO_BUF, BIT(pin)); |
4168 | } |
4169 | |
4170 | #define LAN8841_GPIO_DATA_SEL1 131 |
4171 | #define LAN8841_GPIO_DATA_SEL2 132 |
4172 | #define LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_MASK GENMASK(2, 0) |
4173 | #define LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_A 1 |
4174 | #define LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_B 2 |
4175 | #define LAN8841_PTP_GENERAL_CONFIG 257 |
4176 | #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_A BIT(1) |
4177 | #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_B BIT(3) |
4178 | #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A_MASK GENMASK(7, 4) |
4179 | #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B_MASK GENMASK(11, 8) |
4180 | #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A 4 |
4181 | #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B 7 |
4182 | |
4183 | static int lan8841_ptp_remove_event(struct kszphy_ptp_priv *ptp_priv, int pin, |
4184 | u8 event) |
4185 | { |
4186 | struct phy_device *phydev = ptp_priv->phydev; |
4187 | u16 tmp; |
4188 | int ret; |
4189 | |
4190 | /* Now remove pin from the event. GPIO_DATA_SEL1 contains the GPIO |
4191 | * pins 0-4 while GPIO_DATA_SEL2 contains GPIO pins 5-9, therefore |
4192 | * depending on the pin, it requires to read a different register |
4193 | */ |
4194 | if (pin < 5) { |
4195 | tmp = LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_MASK << (3 * pin); |
4196 | ret = phy_clear_bits_mmd(phydev, devad: 2, LAN8841_GPIO_DATA_SEL1, val: tmp); |
4197 | } else { |
4198 | tmp = LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_MASK << (3 * (pin - 5)); |
4199 | ret = phy_clear_bits_mmd(phydev, devad: 2, LAN8841_GPIO_DATA_SEL2, val: tmp); |
4200 | } |
4201 | if (ret) |
4202 | return ret; |
4203 | |
4204 | /* Disable the event */ |
4205 | if (event == LAN8841_EVENT_A) |
4206 | tmp = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_A | |
4207 | LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A_MASK; |
4208 | else |
4209 | tmp = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_B | |
4210 | LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B_MASK; |
4211 | return phy_clear_bits_mmd(phydev, devad: 2, LAN8841_GPIO_EN, val: tmp); |
4212 | } |
4213 | |
4214 | static int lan8841_ptp_enable_event(struct kszphy_ptp_priv *ptp_priv, int pin, |
4215 | u8 event, int pulse_width) |
4216 | { |
4217 | struct phy_device *phydev = ptp_priv->phydev; |
4218 | u16 tmp; |
4219 | int ret; |
4220 | |
4221 | /* Enable the event */ |
4222 | if (event == LAN8841_EVENT_A) |
4223 | ret = phy_modify_mmd(phydev, devad: 2, LAN8841_PTP_GENERAL_CONFIG, |
4224 | LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_A | |
4225 | LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A_MASK, |
4226 | LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_A | |
4227 | pulse_width << LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A); |
4228 | else |
4229 | ret = phy_modify_mmd(phydev, devad: 2, LAN8841_PTP_GENERAL_CONFIG, |
4230 | LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_B | |
4231 | LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B_MASK, |
4232 | LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_B | |
4233 | pulse_width << LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B); |
4234 | if (ret) |
4235 | return ret; |
4236 | |
4237 | /* Now connect the pin to the event. GPIO_DATA_SEL1 contains the GPIO |
4238 | * pins 0-4 while GPIO_DATA_SEL2 contains GPIO pins 5-9, therefore |
4239 | * depending on the pin, it requires to read a different register |
4240 | */ |
4241 | if (event == LAN8841_EVENT_A) |
4242 | tmp = LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_A; |
4243 | else |
4244 | tmp = LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_B; |
4245 | |
4246 | if (pin < 5) |
4247 | ret = phy_set_bits_mmd(phydev, devad: 2, LAN8841_GPIO_DATA_SEL1, |
4248 | val: tmp << (3 * pin)); |
4249 | else |
4250 | ret = phy_set_bits_mmd(phydev, devad: 2, LAN8841_GPIO_DATA_SEL2, |
4251 | val: tmp << (3 * (pin - 5))); |
4252 | |
4253 | return ret; |
4254 | } |
4255 | |
4256 | #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_200MS 13 |
4257 | #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100MS 12 |
4258 | #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50MS 11 |
4259 | #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10MS 10 |
4260 | #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5MS 9 |
4261 | #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1MS 8 |
4262 | #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500US 7 |
4263 | #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100US 6 |
4264 | #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50US 5 |
4265 | #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10US 4 |
4266 | #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5US 3 |
4267 | #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1US 2 |
4268 | #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500NS 1 |
4269 | #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100NS 0 |
4270 | |
4271 | static int lan8841_ptp_perout(struct ptp_clock_info *ptp, |
4272 | struct ptp_clock_request *rq, int on) |
4273 | { |
4274 | struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv, |
4275 | ptp_clock_info); |
4276 | struct phy_device *phydev = ptp_priv->phydev; |
4277 | struct timespec64 ts_on, ts_period; |
4278 | s64 on_nsec, period_nsec; |
4279 | int pulse_width; |
4280 | int pin; |
4281 | int ret; |
4282 | |
4283 | if (rq->perout.flags & ~PTP_PEROUT_DUTY_CYCLE) |
4284 | return -EOPNOTSUPP; |
4285 | |
4286 | pin = ptp_find_pin(ptp: ptp_priv->ptp_clock, func: PTP_PF_PEROUT, chan: rq->perout.index); |
4287 | if (pin == -1 || pin >= LAN8841_PTP_GPIO_NUM) |
4288 | return -EINVAL; |
4289 | |
4290 | if (!on) { |
4291 | ret = lan8841_ptp_perout_off(ptp_priv, pin); |
4292 | if (ret) |
4293 | return ret; |
4294 | |
4295 | return lan8841_ptp_remove_event(ptp_priv, LAN8841_EVENT_A, event: pin); |
4296 | } |
4297 | |
4298 | ts_on.tv_sec = rq->perout.on.sec; |
4299 | ts_on.tv_nsec = rq->perout.on.nsec; |
4300 | on_nsec = timespec64_to_ns(ts: &ts_on); |
4301 | |
4302 | ts_period.tv_sec = rq->perout.period.sec; |
4303 | ts_period.tv_nsec = rq->perout.period.nsec; |
4304 | period_nsec = timespec64_to_ns(ts: &ts_period); |
4305 | |
4306 | if (period_nsec < 200) { |
4307 | pr_warn_ratelimited("%s: perout period too small, minimum is 200 nsec\n" , |
4308 | phydev_name(phydev)); |
4309 | return -EOPNOTSUPP; |
4310 | } |
4311 | |
4312 | if (on_nsec >= period_nsec) { |
4313 | pr_warn_ratelimited("%s: pulse width must be smaller than period\n" , |
4314 | phydev_name(phydev)); |
4315 | return -EINVAL; |
4316 | } |
4317 | |
4318 | switch (on_nsec) { |
4319 | case 200000000: |
4320 | pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_200MS; |
4321 | break; |
4322 | case 100000000: |
4323 | pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100MS; |
4324 | break; |
4325 | case 50000000: |
4326 | pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50MS; |
4327 | break; |
4328 | case 10000000: |
4329 | pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10MS; |
4330 | break; |
4331 | case 5000000: |
4332 | pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5MS; |
4333 | break; |
4334 | case 1000000: |
4335 | pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1MS; |
4336 | break; |
4337 | case 500000: |
4338 | pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500US; |
4339 | break; |
4340 | case 100000: |
4341 | pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100US; |
4342 | break; |
4343 | case 50000: |
4344 | pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50US; |
4345 | break; |
4346 | case 10000: |
4347 | pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10US; |
4348 | break; |
4349 | case 5000: |
4350 | pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5US; |
4351 | break; |
4352 | case 1000: |
4353 | pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1US; |
4354 | break; |
4355 | case 500: |
4356 | pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500NS; |
4357 | break; |
4358 | case 100: |
4359 | pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100NS; |
4360 | break; |
4361 | default: |
4362 | pr_warn_ratelimited("%s: Use default duty cycle of 100ns\n" , |
4363 | phydev_name(phydev)); |
4364 | pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100NS; |
4365 | break; |
4366 | } |
4367 | |
4368 | mutex_lock(&ptp_priv->ptp_lock); |
4369 | ret = lan8841_ptp_set_target(ptp_priv, LAN8841_EVENT_A, sec: rq->perout.start.sec, |
4370 | nsec: rq->perout.start.nsec); |
4371 | mutex_unlock(lock: &ptp_priv->ptp_lock); |
4372 | if (ret) |
4373 | return ret; |
4374 | |
4375 | ret = lan8841_ptp_set_reload(ptp_priv, LAN8841_EVENT_A, sec: rq->perout.period.sec, |
4376 | nsec: rq->perout.period.nsec); |
4377 | if (ret) |
4378 | return ret; |
4379 | |
4380 | ret = lan8841_ptp_enable_event(ptp_priv, pin, LAN8841_EVENT_A, |
4381 | pulse_width); |
4382 | if (ret) |
4383 | return ret; |
4384 | |
4385 | ret = lan8841_ptp_perout_on(ptp_priv, pin); |
4386 | if (ret) |
4387 | lan8841_ptp_remove_event(ptp_priv, pin, LAN8841_EVENT_A); |
4388 | |
4389 | return ret; |
4390 | } |
4391 | |
4392 | #define LAN8841_PTP_GPIO_CAP_EN 496 |
4393 | #define LAN8841_PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(gpio) (BIT(gpio)) |
4394 | #define LAN8841_PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(gpio) (BIT(gpio) << 8) |
4395 | #define LAN8841_PTP_INT_EN_PTP_GPIO_CAP_EN BIT(2) |
4396 | |
4397 | static int lan8841_ptp_extts_on(struct kszphy_ptp_priv *ptp_priv, int pin, |
4398 | u32 flags) |
4399 | { |
4400 | struct phy_device *phydev = ptp_priv->phydev; |
4401 | u16 tmp = 0; |
4402 | int ret; |
4403 | |
4404 | /* Set GPIO to be intput */ |
4405 | ret = phy_set_bits_mmd(phydev, devad: 2, LAN8841_GPIO_EN, BIT(pin)); |
4406 | if (ret) |
4407 | return ret; |
4408 | |
4409 | ret = phy_clear_bits_mmd(phydev, devad: 2, LAN8841_GPIO_BUF, BIT(pin)); |
4410 | if (ret) |
4411 | return ret; |
4412 | |
4413 | /* Enable capture on the edges of the pin */ |
4414 | if (flags & PTP_RISING_EDGE) |
4415 | tmp |= LAN8841_PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(pin); |
4416 | if (flags & PTP_FALLING_EDGE) |
4417 | tmp |= LAN8841_PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(pin); |
4418 | ret = phy_write_mmd(phydev, devad: 2, LAN8841_PTP_GPIO_CAP_EN, val: tmp); |
4419 | if (ret) |
4420 | return ret; |
4421 | |
4422 | /* Enable interrupt */ |
4423 | return phy_modify_mmd(phydev, devad: 2, LAN8841_PTP_INT_EN, |
4424 | LAN8841_PTP_INT_EN_PTP_GPIO_CAP_EN, |
4425 | LAN8841_PTP_INT_EN_PTP_GPIO_CAP_EN); |
4426 | } |
4427 | |
4428 | static int lan8841_ptp_extts_off(struct kszphy_ptp_priv *ptp_priv, int pin) |
4429 | { |
4430 | struct phy_device *phydev = ptp_priv->phydev; |
4431 | int ret; |
4432 | |
4433 | /* Set GPIO to be output */ |
4434 | ret = phy_clear_bits_mmd(phydev, devad: 2, LAN8841_GPIO_EN, BIT(pin)); |
4435 | if (ret) |
4436 | return ret; |
4437 | |
4438 | ret = phy_clear_bits_mmd(phydev, devad: 2, LAN8841_GPIO_BUF, BIT(pin)); |
4439 | if (ret) |
4440 | return ret; |
4441 | |
4442 | /* Disable capture on both of the edges */ |
4443 | ret = phy_modify_mmd(phydev, devad: 2, LAN8841_PTP_GPIO_CAP_EN, |
4444 | LAN8841_PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(pin) | |
4445 | LAN8841_PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(pin), |
4446 | set: 0); |
4447 | if (ret) |
4448 | return ret; |
4449 | |
4450 | /* Disable interrupt */ |
4451 | return phy_modify_mmd(phydev, devad: 2, LAN8841_PTP_INT_EN, |
4452 | LAN8841_PTP_INT_EN_PTP_GPIO_CAP_EN, |
4453 | set: 0); |
4454 | } |
4455 | |
4456 | static int lan8841_ptp_extts(struct ptp_clock_info *ptp, |
4457 | struct ptp_clock_request *rq, int on) |
4458 | { |
4459 | struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv, |
4460 | ptp_clock_info); |
4461 | int pin; |
4462 | int ret; |
4463 | |
4464 | /* Reject requests with unsupported flags */ |
4465 | if (rq->extts.flags & ~(PTP_ENABLE_FEATURE | |
4466 | PTP_EXTTS_EDGES | |
4467 | PTP_STRICT_FLAGS)) |
4468 | return -EOPNOTSUPP; |
4469 | |
4470 | pin = ptp_find_pin(ptp: ptp_priv->ptp_clock, func: PTP_PF_EXTTS, chan: rq->extts.index); |
4471 | if (pin == -1 || pin >= LAN8841_PTP_GPIO_NUM) |
4472 | return -EINVAL; |
4473 | |
4474 | mutex_lock(&ptp_priv->ptp_lock); |
4475 | if (on) |
4476 | ret = lan8841_ptp_extts_on(ptp_priv, pin, flags: rq->extts.flags); |
4477 | else |
4478 | ret = lan8841_ptp_extts_off(ptp_priv, pin); |
4479 | mutex_unlock(lock: &ptp_priv->ptp_lock); |
4480 | |
4481 | return ret; |
4482 | } |
4483 | |
4484 | static int lan8841_ptp_enable(struct ptp_clock_info *ptp, |
4485 | struct ptp_clock_request *rq, int on) |
4486 | { |
4487 | switch (rq->type) { |
4488 | case PTP_CLK_REQ_EXTTS: |
4489 | return lan8841_ptp_extts(ptp, rq, on); |
4490 | case PTP_CLK_REQ_PEROUT: |
4491 | return lan8841_ptp_perout(ptp, rq, on); |
4492 | default: |
4493 | return -EOPNOTSUPP; |
4494 | } |
4495 | |
4496 | return 0; |
4497 | } |
4498 | |
4499 | static long lan8841_ptp_do_aux_work(struct ptp_clock_info *ptp) |
4500 | { |
4501 | struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv, |
4502 | ptp_clock_info); |
4503 | struct timespec64 ts; |
4504 | unsigned long flags; |
4505 | |
4506 | lan8841_ptp_getseconds(ptp: &ptp_priv->ptp_clock_info, ts: &ts); |
4507 | |
4508 | spin_lock_irqsave(&ptp_priv->seconds_lock, flags); |
4509 | ptp_priv->seconds = ts.tv_sec; |
4510 | spin_unlock_irqrestore(lock: &ptp_priv->seconds_lock, flags); |
4511 | |
4512 | return nsecs_to_jiffies(LAN8841_GET_SEC_LTC_DELAY); |
4513 | } |
4514 | |
4515 | static struct ptp_clock_info lan8841_ptp_clock_info = { |
4516 | .owner = THIS_MODULE, |
4517 | .name = "lan8841 ptp" , |
4518 | .max_adj = 31249999, |
4519 | .gettime64 = lan8841_ptp_gettime64, |
4520 | .settime64 = lan8841_ptp_settime64, |
4521 | .adjtime = lan8841_ptp_adjtime, |
4522 | .adjfine = lan8841_ptp_adjfine, |
4523 | .verify = lan8841_ptp_verify, |
4524 | .enable = lan8841_ptp_enable, |
4525 | .do_aux_work = lan8841_ptp_do_aux_work, |
4526 | .n_per_out = LAN8841_PTP_GPIO_NUM, |
4527 | .n_ext_ts = LAN8841_PTP_GPIO_NUM, |
4528 | .n_pins = LAN8841_PTP_GPIO_NUM, |
4529 | }; |
4530 | |
4531 | #define LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER 3 |
4532 | #define LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER_STRAP_RGMII_EN BIT(0) |
4533 | |
4534 | static int lan8841_probe(struct phy_device *phydev) |
4535 | { |
4536 | struct kszphy_ptp_priv *ptp_priv; |
4537 | struct kszphy_priv *priv; |
4538 | int err; |
4539 | |
4540 | err = kszphy_probe(phydev); |
4541 | if (err) |
4542 | return err; |
4543 | |
4544 | if (phy_read_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG, |
4545 | LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER) & |
4546 | LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER_STRAP_RGMII_EN) |
4547 | phydev->interface = PHY_INTERFACE_MODE_RGMII_RXID; |
4548 | |
4549 | /* Register the clock */ |
4550 | if (!IS_ENABLED(CONFIG_NETWORK_PHY_TIMESTAMPING)) |
4551 | return 0; |
4552 | |
4553 | priv = phydev->priv; |
4554 | ptp_priv = &priv->ptp_priv; |
4555 | |
4556 | ptp_priv->pin_config = devm_kcalloc(dev: &phydev->mdio.dev, |
4557 | LAN8841_PTP_GPIO_NUM, |
4558 | size: sizeof(*ptp_priv->pin_config), |
4559 | GFP_KERNEL); |
4560 | if (!ptp_priv->pin_config) |
4561 | return -ENOMEM; |
4562 | |
4563 | for (int i = 0; i < LAN8841_PTP_GPIO_NUM; ++i) { |
4564 | struct ptp_pin_desc *p = &ptp_priv->pin_config[i]; |
4565 | |
4566 | snprintf(buf: p->name, size: sizeof(p->name), fmt: "pin%d" , i); |
4567 | p->index = i; |
4568 | p->func = PTP_PF_NONE; |
4569 | } |
4570 | |
4571 | ptp_priv->ptp_clock_info = lan8841_ptp_clock_info; |
4572 | ptp_priv->ptp_clock_info.pin_config = ptp_priv->pin_config; |
4573 | ptp_priv->ptp_clock = ptp_clock_register(info: &ptp_priv->ptp_clock_info, |
4574 | parent: &phydev->mdio.dev); |
4575 | if (IS_ERR(ptr: ptp_priv->ptp_clock)) { |
4576 | phydev_err(phydev, "ptp_clock_register failed: %lu\n" , |
4577 | PTR_ERR(ptp_priv->ptp_clock)); |
4578 | return -EINVAL; |
4579 | } |
4580 | |
4581 | if (!ptp_priv->ptp_clock) |
4582 | return 0; |
4583 | |
4584 | /* Initialize the SW */ |
4585 | skb_queue_head_init(list: &ptp_priv->tx_queue); |
4586 | ptp_priv->phydev = phydev; |
4587 | mutex_init(&ptp_priv->ptp_lock); |
4588 | spin_lock_init(&ptp_priv->seconds_lock); |
4589 | |
4590 | ptp_priv->mii_ts.rxtstamp = lan8841_rxtstamp; |
4591 | ptp_priv->mii_ts.txtstamp = lan8814_txtstamp; |
4592 | ptp_priv->mii_ts.hwtstamp = lan8841_hwtstamp; |
4593 | ptp_priv->mii_ts.ts_info = lan8841_ts_info; |
4594 | |
4595 | phydev->mii_ts = &ptp_priv->mii_ts; |
4596 | |
4597 | return 0; |
4598 | } |
4599 | |
4600 | static int lan8841_suspend(struct phy_device *phydev) |
4601 | { |
4602 | struct kszphy_priv *priv = phydev->priv; |
4603 | struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv; |
4604 | |
4605 | ptp_cancel_worker_sync(ptp: ptp_priv->ptp_clock); |
4606 | |
4607 | return genphy_suspend(phydev); |
4608 | } |
4609 | |
4610 | static struct phy_driver ksphy_driver[] = { |
4611 | { |
4612 | .phy_id = PHY_ID_KS8737, |
4613 | .phy_id_mask = MICREL_PHY_ID_MASK, |
4614 | .name = "Micrel KS8737" , |
4615 | /* PHY_BASIC_FEATURES */ |
4616 | .driver_data = &ks8737_type, |
4617 | .probe = kszphy_probe, |
4618 | .config_init = kszphy_config_init, |
4619 | .config_intr = kszphy_config_intr, |
4620 | .handle_interrupt = kszphy_handle_interrupt, |
4621 | .suspend = kszphy_suspend, |
4622 | .resume = kszphy_resume, |
4623 | }, { |
4624 | .phy_id = PHY_ID_KSZ8021, |
4625 | .phy_id_mask = 0x00ffffff, |
4626 | .name = "Micrel KSZ8021 or KSZ8031" , |
4627 | /* PHY_BASIC_FEATURES */ |
4628 | .driver_data = &ksz8021_type, |
4629 | .probe = kszphy_probe, |
4630 | .config_init = kszphy_config_init, |
4631 | .config_intr = kszphy_config_intr, |
4632 | .handle_interrupt = kszphy_handle_interrupt, |
4633 | .get_sset_count = kszphy_get_sset_count, |
4634 | .get_strings = kszphy_get_strings, |
4635 | .get_stats = kszphy_get_stats, |
4636 | .suspend = kszphy_suspend, |
4637 | .resume = kszphy_resume, |
4638 | }, { |
4639 | .phy_id = PHY_ID_KSZ8031, |
4640 | .phy_id_mask = 0x00ffffff, |
4641 | .name = "Micrel KSZ8031" , |
4642 | /* PHY_BASIC_FEATURES */ |
4643 | .driver_data = &ksz8021_type, |
4644 | .probe = kszphy_probe, |
4645 | .config_init = kszphy_config_init, |
4646 | .config_intr = kszphy_config_intr, |
4647 | .handle_interrupt = kszphy_handle_interrupt, |
4648 | .get_sset_count = kszphy_get_sset_count, |
4649 | .get_strings = kszphy_get_strings, |
4650 | .get_stats = kszphy_get_stats, |
4651 | .suspend = kszphy_suspend, |
4652 | .resume = kszphy_resume, |
4653 | }, { |
4654 | .phy_id = PHY_ID_KSZ8041, |
4655 | .phy_id_mask = MICREL_PHY_ID_MASK, |
4656 | .name = "Micrel KSZ8041" , |
4657 | /* PHY_BASIC_FEATURES */ |
4658 | .driver_data = &ksz8041_type, |
4659 | .probe = kszphy_probe, |
4660 | .config_init = ksz8041_config_init, |
4661 | .config_aneg = ksz8041_config_aneg, |
4662 | .config_intr = kszphy_config_intr, |
4663 | .handle_interrupt = kszphy_handle_interrupt, |
4664 | .get_sset_count = kszphy_get_sset_count, |
4665 | .get_strings = kszphy_get_strings, |
4666 | .get_stats = kszphy_get_stats, |
4667 | /* No suspend/resume callbacks because of errata DS80000700A, |
4668 | * receiver error following software power down. |
4669 | */ |
4670 | }, { |
4671 | .phy_id = PHY_ID_KSZ8041RNLI, |
4672 | .phy_id_mask = MICREL_PHY_ID_MASK, |
4673 | .name = "Micrel KSZ8041RNLI" , |
4674 | /* PHY_BASIC_FEATURES */ |
4675 | .driver_data = &ksz8041_type, |
4676 | .probe = kszphy_probe, |
4677 | .config_init = kszphy_config_init, |
4678 | .config_intr = kszphy_config_intr, |
4679 | .handle_interrupt = kszphy_handle_interrupt, |
4680 | .get_sset_count = kszphy_get_sset_count, |
4681 | .get_strings = kszphy_get_strings, |
4682 | .get_stats = kszphy_get_stats, |
4683 | .suspend = kszphy_suspend, |
4684 | .resume = kszphy_resume, |
4685 | }, { |
4686 | .name = "Micrel KSZ8051" , |
4687 | /* PHY_BASIC_FEATURES */ |
4688 | .driver_data = &ksz8051_type, |
4689 | .probe = kszphy_probe, |
4690 | .config_init = kszphy_config_init, |
4691 | .config_intr = kszphy_config_intr, |
4692 | .handle_interrupt = kszphy_handle_interrupt, |
4693 | .get_sset_count = kszphy_get_sset_count, |
4694 | .get_strings = kszphy_get_strings, |
4695 | .get_stats = kszphy_get_stats, |
4696 | .match_phy_device = ksz8051_match_phy_device, |
4697 | .suspend = kszphy_suspend, |
4698 | .resume = kszphy_resume, |
4699 | }, { |
4700 | .phy_id = PHY_ID_KSZ8001, |
4701 | .name = "Micrel KSZ8001 or KS8721" , |
4702 | .phy_id_mask = 0x00fffffc, |
4703 | /* PHY_BASIC_FEATURES */ |
4704 | .driver_data = &ksz8041_type, |
4705 | .probe = kszphy_probe, |
4706 | .config_init = kszphy_config_init, |
4707 | .config_intr = kszphy_config_intr, |
4708 | .handle_interrupt = kszphy_handle_interrupt, |
4709 | .get_sset_count = kszphy_get_sset_count, |
4710 | .get_strings = kszphy_get_strings, |
4711 | .get_stats = kszphy_get_stats, |
4712 | .suspend = kszphy_suspend, |
4713 | .resume = kszphy_resume, |
4714 | }, { |
4715 | .phy_id = PHY_ID_KSZ8081, |
4716 | .name = "Micrel KSZ8081 or KSZ8091" , |
4717 | .phy_id_mask = MICREL_PHY_ID_MASK, |
4718 | .flags = PHY_POLL_CABLE_TEST, |
4719 | /* PHY_BASIC_FEATURES */ |
4720 | .driver_data = &ksz8081_type, |
4721 | .probe = kszphy_probe, |
4722 | .config_init = ksz8081_config_init, |
4723 | .soft_reset = genphy_soft_reset, |
4724 | .config_aneg = ksz8081_config_aneg, |
4725 | .read_status = ksz8081_read_status, |
4726 | .config_intr = kszphy_config_intr, |
4727 | .handle_interrupt = kszphy_handle_interrupt, |
4728 | .get_sset_count = kszphy_get_sset_count, |
4729 | .get_strings = kszphy_get_strings, |
4730 | .get_stats = kszphy_get_stats, |
4731 | .suspend = kszphy_suspend, |
4732 | .resume = kszphy_resume, |
4733 | .cable_test_start = ksz886x_cable_test_start, |
4734 | .cable_test_get_status = ksz886x_cable_test_get_status, |
4735 | }, { |
4736 | .phy_id = PHY_ID_KSZ8061, |
4737 | .name = "Micrel KSZ8061" , |
4738 | .phy_id_mask = MICREL_PHY_ID_MASK, |
4739 | /* PHY_BASIC_FEATURES */ |
4740 | .probe = kszphy_probe, |
4741 | .config_init = ksz8061_config_init, |
4742 | .config_intr = kszphy_config_intr, |
4743 | .handle_interrupt = kszphy_handle_interrupt, |
4744 | .suspend = kszphy_suspend, |
4745 | .resume = kszphy_resume, |
4746 | }, { |
4747 | .phy_id = PHY_ID_KSZ9021, |
4748 | .phy_id_mask = 0x000ffffe, |
4749 | .name = "Micrel KSZ9021 Gigabit PHY" , |
4750 | /* PHY_GBIT_FEATURES */ |
4751 | .driver_data = &ksz9021_type, |
4752 | .probe = kszphy_probe, |
4753 | .get_features = ksz9031_get_features, |
4754 | .config_init = ksz9021_config_init, |
4755 | .config_intr = kszphy_config_intr, |
4756 | .handle_interrupt = kszphy_handle_interrupt, |
4757 | .get_sset_count = kszphy_get_sset_count, |
4758 | .get_strings = kszphy_get_strings, |
4759 | .get_stats = kszphy_get_stats, |
4760 | .suspend = kszphy_suspend, |
4761 | .resume = kszphy_resume, |
4762 | .read_mmd = genphy_read_mmd_unsupported, |
4763 | .write_mmd = genphy_write_mmd_unsupported, |
4764 | }, { |
4765 | .phy_id = PHY_ID_KSZ9031, |
4766 | .phy_id_mask = MICREL_PHY_ID_MASK, |
4767 | .name = "Micrel KSZ9031 Gigabit PHY" , |
4768 | .flags = PHY_POLL_CABLE_TEST, |
4769 | .driver_data = &ksz9021_type, |
4770 | .probe = kszphy_probe, |
4771 | .get_features = ksz9031_get_features, |
4772 | .config_init = ksz9031_config_init, |
4773 | .soft_reset = genphy_soft_reset, |
4774 | .read_status = ksz9031_read_status, |
4775 | .config_intr = kszphy_config_intr, |
4776 | .handle_interrupt = kszphy_handle_interrupt, |
4777 | .get_sset_count = kszphy_get_sset_count, |
4778 | .get_strings = kszphy_get_strings, |
4779 | .get_stats = kszphy_get_stats, |
4780 | .suspend = kszphy_suspend, |
4781 | .resume = kszphy_resume, |
4782 | .cable_test_start = ksz9x31_cable_test_start, |
4783 | .cable_test_get_status = ksz9x31_cable_test_get_status, |
4784 | }, { |
4785 | .phy_id = PHY_ID_LAN8814, |
4786 | .phy_id_mask = MICREL_PHY_ID_MASK, |
4787 | .name = "Microchip INDY Gigabit Quad PHY" , |
4788 | .flags = PHY_POLL_CABLE_TEST, |
4789 | .config_init = lan8814_config_init, |
4790 | .driver_data = &lan8814_type, |
4791 | .probe = lan8814_probe, |
4792 | .soft_reset = genphy_soft_reset, |
4793 | .read_status = ksz9031_read_status, |
4794 | .get_sset_count = kszphy_get_sset_count, |
4795 | .get_strings = kszphy_get_strings, |
4796 | .get_stats = kszphy_get_stats, |
4797 | .suspend = genphy_suspend, |
4798 | .resume = kszphy_resume, |
4799 | .config_intr = lan8814_config_intr, |
4800 | .handle_interrupt = lan8814_handle_interrupt, |
4801 | .cable_test_start = lan8814_cable_test_start, |
4802 | .cable_test_get_status = ksz886x_cable_test_get_status, |
4803 | }, { |
4804 | .phy_id = PHY_ID_LAN8804, |
4805 | .phy_id_mask = MICREL_PHY_ID_MASK, |
4806 | .name = "Microchip LAN966X Gigabit PHY" , |
4807 | .config_init = lan8804_config_init, |
4808 | .driver_data = &ksz9021_type, |
4809 | .probe = kszphy_probe, |
4810 | .soft_reset = genphy_soft_reset, |
4811 | .read_status = ksz9031_read_status, |
4812 | .get_sset_count = kszphy_get_sset_count, |
4813 | .get_strings = kszphy_get_strings, |
4814 | .get_stats = kszphy_get_stats, |
4815 | .suspend = genphy_suspend, |
4816 | .resume = kszphy_resume, |
4817 | .config_intr = lan8804_config_intr, |
4818 | .handle_interrupt = lan8804_handle_interrupt, |
4819 | }, { |
4820 | .phy_id = PHY_ID_LAN8841, |
4821 | .phy_id_mask = MICREL_PHY_ID_MASK, |
4822 | .name = "Microchip LAN8841 Gigabit PHY" , |
4823 | .flags = PHY_POLL_CABLE_TEST, |
4824 | .driver_data = &lan8841_type, |
4825 | .config_init = lan8841_config_init, |
4826 | .probe = lan8841_probe, |
4827 | .soft_reset = genphy_soft_reset, |
4828 | .config_intr = lan8841_config_intr, |
4829 | .handle_interrupt = lan8841_handle_interrupt, |
4830 | .get_sset_count = kszphy_get_sset_count, |
4831 | .get_strings = kszphy_get_strings, |
4832 | .get_stats = kszphy_get_stats, |
4833 | .suspend = lan8841_suspend, |
4834 | .resume = genphy_resume, |
4835 | .cable_test_start = lan8814_cable_test_start, |
4836 | .cable_test_get_status = ksz886x_cable_test_get_status, |
4837 | }, { |
4838 | .phy_id = PHY_ID_KSZ9131, |
4839 | .phy_id_mask = MICREL_PHY_ID_MASK, |
4840 | .name = "Microchip KSZ9131 Gigabit PHY" , |
4841 | /* PHY_GBIT_FEATURES */ |
4842 | .flags = PHY_POLL_CABLE_TEST, |
4843 | .driver_data = &ksz9131_type, |
4844 | .probe = kszphy_probe, |
4845 | .config_init = ksz9131_config_init, |
4846 | .config_intr = kszphy_config_intr, |
4847 | .config_aneg = ksz9131_config_aneg, |
4848 | .read_status = ksz9131_read_status, |
4849 | .handle_interrupt = kszphy_handle_interrupt, |
4850 | .get_sset_count = kszphy_get_sset_count, |
4851 | .get_strings = kszphy_get_strings, |
4852 | .get_stats = kszphy_get_stats, |
4853 | .suspend = kszphy_suspend, |
4854 | .resume = kszphy_resume, |
4855 | .cable_test_start = ksz9x31_cable_test_start, |
4856 | .cable_test_get_status = ksz9x31_cable_test_get_status, |
4857 | .get_features = ksz9477_get_features, |
4858 | }, { |
4859 | .phy_id = PHY_ID_KSZ8873MLL, |
4860 | .phy_id_mask = MICREL_PHY_ID_MASK, |
4861 | .name = "Micrel KSZ8873MLL Switch" , |
4862 | /* PHY_BASIC_FEATURES */ |
4863 | .config_init = kszphy_config_init, |
4864 | .config_aneg = ksz8873mll_config_aneg, |
4865 | .read_status = ksz8873mll_read_status, |
4866 | .suspend = genphy_suspend, |
4867 | .resume = genphy_resume, |
4868 | }, { |
4869 | .phy_id = PHY_ID_KSZ886X, |
4870 | .phy_id_mask = MICREL_PHY_ID_MASK, |
4871 | .name = "Micrel KSZ8851 Ethernet MAC or KSZ886X Switch" , |
4872 | .driver_data = &ksz886x_type, |
4873 | /* PHY_BASIC_FEATURES */ |
4874 | .flags = PHY_POLL_CABLE_TEST, |
4875 | .config_init = kszphy_config_init, |
4876 | .config_aneg = ksz886x_config_aneg, |
4877 | .read_status = ksz886x_read_status, |
4878 | .suspend = genphy_suspend, |
4879 | .resume = genphy_resume, |
4880 | .cable_test_start = ksz886x_cable_test_start, |
4881 | .cable_test_get_status = ksz886x_cable_test_get_status, |
4882 | }, { |
4883 | .name = "Micrel KSZ87XX Switch" , |
4884 | /* PHY_BASIC_FEATURES */ |
4885 | .config_init = kszphy_config_init, |
4886 | .match_phy_device = ksz8795_match_phy_device, |
4887 | .suspend = genphy_suspend, |
4888 | .resume = genphy_resume, |
4889 | }, { |
4890 | .phy_id = PHY_ID_KSZ9477, |
4891 | .phy_id_mask = MICREL_PHY_ID_MASK, |
4892 | .name = "Microchip KSZ9477" , |
4893 | /* PHY_GBIT_FEATURES */ |
4894 | .config_init = ksz9477_config_init, |
4895 | .config_intr = kszphy_config_intr, |
4896 | .handle_interrupt = kszphy_handle_interrupt, |
4897 | .suspend = genphy_suspend, |
4898 | .resume = genphy_resume, |
4899 | .get_features = ksz9477_get_features, |
4900 | } }; |
4901 | |
4902 | module_phy_driver(ksphy_driver); |
4903 | |
4904 | MODULE_DESCRIPTION("Micrel PHY driver" ); |
4905 | MODULE_AUTHOR("David J. Choi" ); |
4906 | MODULE_LICENSE("GPL" ); |
4907 | |
4908 | static struct mdio_device_id __maybe_unused micrel_tbl[] = { |
4909 | { PHY_ID_KSZ9021, 0x000ffffe }, |
4910 | { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK }, |
4911 | { PHY_ID_KSZ9131, MICREL_PHY_ID_MASK }, |
4912 | { PHY_ID_KSZ8001, 0x00fffffc }, |
4913 | { PHY_ID_KS8737, MICREL_PHY_ID_MASK }, |
4914 | { PHY_ID_KSZ8021, 0x00ffffff }, |
4915 | { PHY_ID_KSZ8031, 0x00ffffff }, |
4916 | { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK }, |
4917 | { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK }, |
4918 | { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK }, |
4919 | { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK }, |
4920 | { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK }, |
4921 | { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK }, |
4922 | { PHY_ID_LAN8814, MICREL_PHY_ID_MASK }, |
4923 | { PHY_ID_LAN8804, MICREL_PHY_ID_MASK }, |
4924 | { PHY_ID_LAN8841, MICREL_PHY_ID_MASK }, |
4925 | { } |
4926 | }; |
4927 | |
4928 | MODULE_DEVICE_TABLE(mdio, micrel_tbl); |
4929 | |