1	// SPDX-License-Identifier: GPL-2.0-only
2	/*
3	* Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
4	*/
5
6	#include <linux/signal.h>
7	#include <linux/slab.h>
8	#include <linux/module.h>
9	#include <linux/netdevice.h>
10	#include <linux/etherdevice.h>
11	#include <linux/mii.h>
12	#include <linux/ethtool.h>
13	#include <linux/usb.h>
14	#include <linux/crc32.h>
15	#include <linux/if_vlan.h>
16	#include <linux/uaccess.h>
17	#include <linux/list.h>
18	#include <linux/ip.h>
19	#include <linux/ipv6.h>
20	#include <net/ip6_checksum.h>
21	#include <uapi/linux/mdio.h>
22	#include <linux/mdio.h>
23	#include <linux/usb/cdc.h>
24	#include <linux/suspend.h>
25	#include <linux/atomic.h>
26	#include <linux/acpi.h>
27	#include <linux/firmware.h>
28	#include <crypto/hash.h>
29	#include <linux/usb/r8152.h>
30	#include <net/gso.h>
31
32	/* Information for net-next */
33	#define NETNEXT_VERSION "12"
34
35	/* Information for net */
36	#define NET_VERSION "13"
37
38	#define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION
39	#define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
40	#define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
41	#define MODULENAME "r8152"
42
43	#define R8152_PHY_ID 32
44
45	#define PLA_IDR 0xc000
46	#define PLA_RCR 0xc010
47	#define PLA_RCR1 0xc012
48	#define PLA_RMS 0xc016
49	#define PLA_RXFIFO_CTRL0 0xc0a0
50	#define PLA_RXFIFO_FULL 0xc0a2
51	#define PLA_RXFIFO_CTRL1 0xc0a4
52	#define PLA_RX_FIFO_FULL 0xc0a6
53	#define PLA_RXFIFO_CTRL2 0xc0a8
54	#define PLA_RX_FIFO_EMPTY 0xc0aa
55	#define PLA_DMY_REG0 0xc0b0
56	#define PLA_FMC 0xc0b4
57	#define PLA_CFG_WOL 0xc0b6
58	#define PLA_TEREDO_CFG 0xc0bc
59	#define PLA_TEREDO_WAKE_BASE 0xc0c4
60	#define PLA_MAR 0xcd00
61	#define PLA_BACKUP 0xd000
62	#define PLA_BDC_CR 0xd1a0
63	#define PLA_TEREDO_TIMER 0xd2cc
64	#define PLA_REALWOW_TIMER 0xd2e8
65	#define PLA_UPHY_TIMER 0xd388
66	#define PLA_SUSPEND_FLAG 0xd38a
67	#define PLA_INDICATE_FALG 0xd38c
68	#define PLA_MACDBG_PRE 0xd38c /* RTL_VER_04 only */
69	#define PLA_MACDBG_POST 0xd38e /* RTL_VER_04 only */
70	#define PLA_EXTRA_STATUS 0xd398
71	#define PLA_GPHY_CTRL 0xd3ae
72	#define PLA_POL_GPIO_CTRL 0xdc6a
73	#define PLA_EFUSE_DATA 0xdd00
74	#define PLA_EFUSE_CMD 0xdd02
75	#define PLA_LEDSEL 0xdd90
76	#define PLA_LED_FEATURE 0xdd92
77	#define PLA_PHYAR 0xde00
78	#define PLA_BOOT_CTRL 0xe004
79	#define PLA_LWAKE_CTRL_REG 0xe007
80	#define PLA_GPHY_INTR_IMR 0xe022
81	#define PLA_EEE_CR 0xe040
82	#define PLA_EEE_TXTWSYS 0xe04c
83	#define PLA_EEE_TXTWSYS_2P5G 0xe058
84	#define PLA_EEEP_CR 0xe080
85	#define PLA_MAC_PWR_CTRL 0xe0c0
86	#define PLA_MAC_PWR_CTRL2 0xe0ca
87	#define PLA_MAC_PWR_CTRL3 0xe0cc
88	#define PLA_MAC_PWR_CTRL4 0xe0ce
89	#define PLA_WDT6_CTRL 0xe428
90	#define PLA_TCR0 0xe610
91	#define PLA_TCR1 0xe612
92	#define PLA_MTPS 0xe615
93	#define PLA_TXFIFO_CTRL 0xe618
94	#define PLA_TXFIFO_FULL 0xe61a
95	#define PLA_RSTTALLY 0xe800
96	#define PLA_CR 0xe813
97	#define PLA_CRWECR 0xe81c
98	#define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
99	#define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
100	#define PLA_CONFIG5 0xe822
101	#define PLA_PHY_PWR 0xe84c
102	#define PLA_OOB_CTRL 0xe84f
103	#define PLA_CPCR 0xe854
104	#define PLA_MISC_0 0xe858
105	#define PLA_MISC_1 0xe85a
106	#define PLA_OCP_GPHY_BASE 0xe86c
107	#define PLA_TALLYCNT 0xe890
108	#define PLA_SFF_STS_7 0xe8de
109	#define PLA_PHYSTATUS 0xe908
110	#define PLA_CONFIG6 0xe90a /* CONFIG6 */
111	#define PLA_USB_CFG 0xe952
112	#define PLA_BP_BA 0xfc26
113	#define PLA_BP_0 0xfc28
114	#define PLA_BP_1 0xfc2a
115	#define PLA_BP_2 0xfc2c
116	#define PLA_BP_3 0xfc2e
117	#define PLA_BP_4 0xfc30
118	#define PLA_BP_5 0xfc32
119	#define PLA_BP_6 0xfc34
120	#define PLA_BP_7 0xfc36
121	#define PLA_BP_EN 0xfc38
122
123	#define USB_USB2PHY 0xb41e
124	#define USB_SSPHYLINK1 0xb426
125	#define USB_SSPHYLINK2 0xb428
126	#define USB_L1_CTRL 0xb45e
127	#define USB_U2P3_CTRL 0xb460
128	#define USB_CSR_DUMMY1 0xb464
129	#define USB_CSR_DUMMY2 0xb466
130	#define USB_DEV_STAT 0xb808
131	#define USB_CONNECT_TIMER 0xcbf8
132	#define USB_MSC_TIMER 0xcbfc
133	#define USB_BURST_SIZE 0xcfc0
134	#define USB_FW_FIX_EN0 0xcfca
135	#define USB_FW_FIX_EN1 0xcfcc
136	#define USB_LPM_CONFIG 0xcfd8
137	#define USB_ECM_OPTION 0xcfee
138	#define USB_CSTMR 0xcfef /* RTL8153A */
139	#define USB_MISC_2 0xcfff
140	#define USB_ECM_OP 0xd26b
141	#define USB_GPHY_CTRL 0xd284
142	#define USB_SPEED_OPTION 0xd32a
143	#define USB_FW_CTRL 0xd334 /* RTL8153B */
144	#define USB_FC_TIMER 0xd340
145	#define USB_USB_CTRL 0xd406
146	#define USB_PHY_CTRL 0xd408
147	#define USB_TX_AGG 0xd40a
148	#define USB_RX_BUF_TH 0xd40c
149	#define USB_USB_TIMER 0xd428
150	#define USB_RX_EARLY_TIMEOUT 0xd42c
151	#define USB_RX_EARLY_SIZE 0xd42e
152	#define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */
153	#define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */
154	#define USB_TX_DMA 0xd434
155	#define USB_UPT_RXDMA_OWN 0xd437
156	#define USB_UPHY3_MDCMDIO 0xd480
157	#define USB_TOLERANCE 0xd490
158	#define USB_LPM_CTRL 0xd41a
159	#define USB_BMU_RESET 0xd4b0
160	#define USB_BMU_CONFIG 0xd4b4
161	#define USB_U1U2_TIMER 0xd4da
162	#define USB_FW_TASK 0xd4e8 /* RTL8153B */
163	#define USB_RX_AGGR_NUM 0xd4ee
164	#define USB_UPS_CTRL 0xd800
165	#define USB_POWER_CUT 0xd80a
166	#define USB_MISC_0 0xd81a
167	#define USB_MISC_1 0xd81f
168	#define USB_AFE_CTRL2 0xd824
169	#define USB_UPHY_XTAL 0xd826
170	#define USB_UPS_CFG 0xd842
171	#define USB_UPS_FLAGS 0xd848
172	#define USB_WDT1_CTRL 0xe404
173	#define USB_WDT11_CTRL 0xe43c
174	#define USB_BP_BA PLA_BP_BA
175	#define USB_BP_0 PLA_BP_0
176	#define USB_BP_1 PLA_BP_1
177	#define USB_BP_2 PLA_BP_2
178	#define USB_BP_3 PLA_BP_3
179	#define USB_BP_4 PLA_BP_4
180	#define USB_BP_5 PLA_BP_5
181	#define USB_BP_6 PLA_BP_6
182	#define USB_BP_7 PLA_BP_7
183	#define USB_BP_EN PLA_BP_EN /* RTL8153A */
184	#define USB_BP_8 0xfc38 /* RTL8153B */
185	#define USB_BP_9 0xfc3a
186	#define USB_BP_10 0xfc3c
187	#define USB_BP_11 0xfc3e
188	#define USB_BP_12 0xfc40
189	#define USB_BP_13 0xfc42
190	#define USB_BP_14 0xfc44
191	#define USB_BP_15 0xfc46
192	#define USB_BP2_EN 0xfc48
193
194	/* OCP Registers */
195	#define OCP_ALDPS_CONFIG 0x2010
196	#define OCP_EEE_CONFIG1 0x2080
197	#define OCP_EEE_CONFIG2 0x2092
198	#define OCP_EEE_CONFIG3 0x2094
199	#define OCP_BASE_MII 0xa400
200	#define OCP_EEE_AR 0xa41a
201	#define OCP_EEE_DATA 0xa41c
202	#define OCP_PHY_STATUS 0xa420
203	#define OCP_INTR_EN 0xa424
204	#define OCP_NCTL_CFG 0xa42c
205	#define OCP_POWER_CFG 0xa430
206	#define OCP_EEE_CFG 0xa432
207	#define OCP_SRAM_ADDR 0xa436
208	#define OCP_SRAM_DATA 0xa438
209	#define OCP_DOWN_SPEED 0xa442
210	#define OCP_EEE_ABLE 0xa5c4
211	#define OCP_EEE_ADV 0xa5d0
212	#define OCP_EEE_LPABLE 0xa5d2
213	#define OCP_10GBT_CTRL 0xa5d4
214	#define OCP_10GBT_STAT 0xa5d6
215	#define OCP_EEE_ADV2 0xa6d4
216	#define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
217	#define OCP_PHY_PATCH_STAT 0xb800
218	#define OCP_PHY_PATCH_CMD 0xb820
219	#define OCP_PHY_LOCK 0xb82e
220	#define OCP_ADC_IOFFSET 0xbcfc
221	#define OCP_ADC_CFG 0xbc06
222	#define OCP_SYSCLK_CFG 0xc416
223
224	/* SRAM Register */
225	#define SRAM_GREEN_CFG 0x8011
226	#define SRAM_LPF_CFG 0x8012
227	#define SRAM_GPHY_FW_VER 0x801e
228	#define SRAM_10M_AMP1 0x8080
229	#define SRAM_10M_AMP2 0x8082
230	#define SRAM_IMPEDANCE 0x8084
231	#define SRAM_PHY_LOCK 0xb82e
232
233	/* PLA_RCR */
234	#define RCR_AAP 0x00000001
235	#define RCR_APM 0x00000002
236	#define RCR_AM 0x00000004
237	#define RCR_AB 0x00000008
238	#define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
239	#define SLOT_EN BIT(11)
240
241	/* PLA_RCR1 */
242	#define OUTER_VLAN BIT(7)
243	#define INNER_VLAN BIT(6)
244
245	/* PLA_RXFIFO_CTRL0 */
246	#define RXFIFO_THR1_NORMAL 0x00080002
247	#define RXFIFO_THR1_OOB 0x01800003
248
249	/* PLA_RXFIFO_FULL */
250	#define RXFIFO_FULL_MASK 0xfff
251
252	/* PLA_RXFIFO_CTRL1 */
253	#define RXFIFO_THR2_FULL 0x00000060
254	#define RXFIFO_THR2_HIGH 0x00000038
255	#define RXFIFO_THR2_OOB 0x0000004a
256	#define RXFIFO_THR2_NORMAL 0x00a0
257
258	/* PLA_RXFIFO_CTRL2 */
259	#define RXFIFO_THR3_FULL 0x00000078
260	#define RXFIFO_THR3_HIGH 0x00000048
261	#define RXFIFO_THR3_OOB 0x0000005a
262	#define RXFIFO_THR3_NORMAL 0x0110
263
264	/* PLA_TXFIFO_CTRL */
265	#define TXFIFO_THR_NORMAL 0x00400008
266	#define TXFIFO_THR_NORMAL2 0x01000008
267
268	/* PLA_DMY_REG0 */
269	#define ECM_ALDPS 0x0002
270
271	/* PLA_FMC */
272	#define FMC_FCR_MCU_EN 0x0001
273
274	/* PLA_EEEP_CR */
275	#define EEEP_CR_EEEP_TX 0x0002
276
277	/* PLA_WDT6_CTRL */
278	#define WDT6_SET_MODE 0x0010
279
280	/* PLA_TCR0 */
281	#define TCR0_TX_EMPTY 0x0800
282	#define TCR0_AUTO_FIFO 0x0080
283
284	/* PLA_TCR1 */
285	#define VERSION_MASK 0x7cf0
286	#define IFG_MASK (BIT(3) | BIT(9) | BIT(8))
287	#define IFG_144NS BIT(9)
288	#define IFG_96NS (BIT(9) | BIT(8))
289
290	/* PLA_MTPS */
291	#define MTPS_JUMBO (12 * 1024 / 64)
292	#define MTPS_DEFAULT (6 * 1024 / 64)
293
294	/* PLA_RSTTALLY */
295	#define TALLY_RESET 0x0001
296
297	/* PLA_CR */
298	#define CR_RST 0x10
299	#define CR_RE 0x08
300	#define CR_TE 0x04
301
302	/* PLA_CRWECR */
303	#define CRWECR_NORAML 0x00
304	#define CRWECR_CONFIG 0xc0
305
306	/* PLA_OOB_CTRL */
307	#define NOW_IS_OOB 0x80
308	#define TXFIFO_EMPTY 0x20
309	#define RXFIFO_EMPTY 0x10
310	#define LINK_LIST_READY 0x02
311	#define DIS_MCU_CLROOB 0x01
312	#define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
313
314	/* PLA_MISC_1 */
315	#define RXDY_GATED_EN 0x0008
316
317	/* PLA_SFF_STS_7 */
318	#define RE_INIT_LL 0x8000
319	#define MCU_BORW_EN 0x4000
320
321	/* PLA_CPCR */
322	#define FLOW_CTRL_EN BIT(0)
323	#define CPCR_RX_VLAN 0x0040
324
325	/* PLA_CFG_WOL */
326	#define MAGIC_EN 0x0001
327
328	/* PLA_TEREDO_CFG */
329	#define TEREDO_SEL 0x8000
330	#define TEREDO_WAKE_MASK 0x7f00
331	#define TEREDO_RS_EVENT_MASK 0x00fe
332	#define OOB_TEREDO_EN 0x0001
333
334	/* PLA_BDC_CR */
335	#define ALDPS_PROXY_MODE 0x0001
336
337	/* PLA_EFUSE_CMD */
338	#define EFUSE_READ_CMD BIT(15)
339	#define EFUSE_DATA_BIT16 BIT(7)
340
341	/* PLA_CONFIG34 */
342	#define LINK_ON_WAKE_EN 0x0010
343	#define LINK_OFF_WAKE_EN 0x0008
344
345	/* PLA_CONFIG6 */
346	#define LANWAKE_CLR_EN BIT(0)
347
348	/* PLA_USB_CFG */
349	#define EN_XG_LIP BIT(1)
350	#define EN_G_LIP BIT(2)
351
352	/* PLA_CONFIG5 */
353	#define BWF_EN 0x0040
354	#define MWF_EN 0x0020
355	#define UWF_EN 0x0010
356	#define LAN_WAKE_EN 0x0002
357
358	/* PLA_LED_FEATURE */
359	#define LED_MODE_MASK 0x0700
360
361	/* PLA_PHY_PWR */
362	#define TX_10M_IDLE_EN 0x0080
363	#define PFM_PWM_SWITCH 0x0040
364	#define TEST_IO_OFF BIT(4)
365
366	/* PLA_MAC_PWR_CTRL */
367	#define D3_CLK_GATED_EN 0x00004000
368	#define MCU_CLK_RATIO 0x07010f07
369	#define MCU_CLK_RATIO_MASK 0x0f0f0f0f
370	#define ALDPS_SPDWN_RATIO 0x0f87
371
372	/* PLA_MAC_PWR_CTRL2 */
373	#define EEE_SPDWN_RATIO 0x8007
374	#define MAC_CLK_SPDWN_EN BIT(15)
375	#define EEE_SPDWN_RATIO_MASK 0xff
376
377	/* PLA_MAC_PWR_CTRL3 */
378	#define PLA_MCU_SPDWN_EN BIT(14)
379	#define PKT_AVAIL_SPDWN_EN 0x0100
380	#define SUSPEND_SPDWN_EN 0x0004
381	#define U1U2_SPDWN_EN 0x0002
382	#define L1_SPDWN_EN 0x0001
383
384	/* PLA_MAC_PWR_CTRL4 */
385	#define PWRSAVE_SPDWN_EN 0x1000
386	#define RXDV_SPDWN_EN 0x0800
387	#define TX10MIDLE_EN 0x0100
388	#define IDLE_SPDWN_EN BIT(6)
389	#define TP100_SPDWN_EN 0x0020
390	#define TP500_SPDWN_EN 0x0010
391	#define TP1000_SPDWN_EN 0x0008
392	#define EEE_SPDWN_EN 0x0001
393
394	/* PLA_GPHY_INTR_IMR */
395	#define GPHY_STS_MSK 0x0001
396	#define SPEED_DOWN_MSK 0x0002
397	#define SPDWN_RXDV_MSK 0x0004
398	#define SPDWN_LINKCHG_MSK 0x0008
399
400	/* PLA_PHYAR */
401	#define PHYAR_FLAG 0x80000000
402
403	/* PLA_EEE_CR */
404	#define EEE_RX_EN 0x0001
405	#define EEE_TX_EN 0x0002
406
407	/* PLA_BOOT_CTRL */
408	#define AUTOLOAD_DONE 0x0002
409
410	/* PLA_LWAKE_CTRL_REG */
411	#define LANWAKE_PIN BIT(7)
412
413	/* PLA_SUSPEND_FLAG */
414	#define LINK_CHG_EVENT BIT(0)
415
416	/* PLA_INDICATE_FALG */
417	#define UPCOMING_RUNTIME_D3 BIT(0)
418
419	/* PLA_MACDBG_PRE and PLA_MACDBG_POST */
420	#define DEBUG_OE BIT(0)
421	#define DEBUG_LTSSM 0x0082
422
423	/* PLA_EXTRA_STATUS */
424	#define CUR_LINK_OK BIT(15)
425	#define U3P3_CHECK_EN BIT(7) /* RTL_VER_05 only */
426	#define LINK_CHANGE_FLAG BIT(8)
427	#define POLL_LINK_CHG BIT(0)
428
429	/* PLA_GPHY_CTRL */
430	#define GPHY_FLASH BIT(1)
431
432	/* PLA_POL_GPIO_CTRL */
433	#define DACK_DET_EN BIT(15)
434	#define POL_GPHY_PATCH BIT(4)
435
436	/* USB_USB2PHY */
437	#define USB2PHY_SUSPEND 0x0001
438	#define USB2PHY_L1 0x0002
439
440	/* USB_SSPHYLINK1 */
441	#define DELAY_PHY_PWR_CHG BIT(1)
442
443	/* USB_SSPHYLINK2 */
444	#define pwd_dn_scale_mask 0x3ffe
445	#define pwd_dn_scale(x) ((x) << 1)
446
447	/* USB_CSR_DUMMY1 */
448	#define DYNAMIC_BURST 0x0001
449
450	/* USB_CSR_DUMMY2 */
451	#define EP4_FULL_FC 0x0001
452
453	/* USB_DEV_STAT */
454	#define STAT_SPEED_MASK 0x0006
455	#define STAT_SPEED_HIGH 0x0000
456	#define STAT_SPEED_FULL 0x0002
457
458	/* USB_FW_FIX_EN0 */
459	#define FW_FIX_SUSPEND BIT(14)
460
461	/* USB_FW_FIX_EN1 */
462	#define FW_IP_RESET_EN BIT(9)
463
464	/* USB_LPM_CONFIG */
465	#define LPM_U1U2_EN BIT(0)
466
467	/* USB_TX_AGG */
468	#define TX_AGG_MAX_THRESHOLD 0x03
469
470	/* USB_RX_BUF_TH */
471	#define RX_THR_SUPPER 0x0c350180
472	#define RX_THR_HIGH 0x7a120180
473	#define RX_THR_SLOW 0xffff0180
474	#define RX_THR_B 0x00010001
475
476	/* USB_TX_DMA */
477	#define TEST_MODE_DISABLE 0x00000001
478	#define TX_SIZE_ADJUST1 0x00000100
479
480	/* USB_BMU_RESET */
481	#define BMU_RESET_EP_IN 0x01
482	#define BMU_RESET_EP_OUT 0x02
483
484	/* USB_BMU_CONFIG */
485	#define ACT_ODMA BIT(1)
486
487	/* USB_UPT_RXDMA_OWN */
488	#define OWN_UPDATE BIT(0)
489	#define OWN_CLEAR BIT(1)
490
491	/* USB_FW_TASK */
492	#define FC_PATCH_TASK BIT(1)
493
494	/* USB_RX_AGGR_NUM */
495	#define RX_AGGR_NUM_MASK 0x1ff
496
497	/* USB_UPS_CTRL */
498	#define POWER_CUT 0x0100
499
500	/* USB_PM_CTRL_STATUS */
501	#define RESUME_INDICATE 0x0001
502
503	/* USB_ECM_OPTION */
504	#define BYPASS_MAC_RESET BIT(5)
505
506	/* USB_CSTMR */
507	#define FORCE_SUPER BIT(0)
508
509	/* USB_MISC_2 */
510	#define UPS_FORCE_PWR_DOWN BIT(0)
511
512	/* USB_ECM_OP */
513	#define EN_ALL_SPEED BIT(0)
514
515	/* USB_GPHY_CTRL */
516	#define GPHY_PATCH_DONE BIT(2)
517	#define BYPASS_FLASH BIT(5)
518	#define BACKUP_RESTRORE BIT(6)
519
520	/* USB_SPEED_OPTION */
521	#define RG_PWRDN_EN BIT(8)
522	#define ALL_SPEED_OFF BIT(9)
523
524	/* USB_FW_CTRL */
525	#define FLOW_CTRL_PATCH_OPT BIT(1)
526	#define AUTO_SPEEDUP BIT(3)
527	#define FLOW_CTRL_PATCH_2 BIT(8)
528
529	/* USB_FC_TIMER */
530	#define CTRL_TIMER_EN BIT(15)
531
532	/* USB_USB_CTRL */
533	#define CDC_ECM_EN BIT(3)
534	#define RX_AGG_DISABLE 0x0010
535	#define RX_ZERO_EN 0x0080
536
537	/* USB_U2P3_CTRL */
538	#define U2P3_ENABLE 0x0001
539	#define RX_DETECT8 BIT(3)
540
541	/* USB_POWER_CUT */
542	#define PWR_EN 0x0001
543	#define PHASE2_EN 0x0008
544	#define UPS_EN BIT(4)
545	#define USP_PREWAKE BIT(5)
546
547	/* USB_MISC_0 */
548	#define PCUT_STATUS 0x0001
549
550	/* USB_RX_EARLY_TIMEOUT */
551	#define COALESCE_SUPER 85000U
552	#define COALESCE_HIGH 250000U
553	#define COALESCE_SLOW 524280U
554
555	/* USB_WDT1_CTRL */
556	#define WTD1_EN BIT(0)
557
558	/* USB_WDT11_CTRL */
559	#define TIMER11_EN 0x0001
560
561	/* USB_LPM_CTRL */
562	/* bit 4 ~ 5: fifo empty boundary */
563	#define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
564	/* bit 2 ~ 3: LMP timer */
565	#define LPM_TIMER_MASK 0x0c
566	#define LPM_TIMER_500MS 0x04 /* 500 ms */
567	#define LPM_TIMER_500US 0x0c /* 500 us */
568	#define ROK_EXIT_LPM 0x02
569
570	/* USB_AFE_CTRL2 */
571	#define SEN_VAL_MASK 0xf800
572	#define SEN_VAL_NORMAL 0xa000
573	#define SEL_RXIDLE 0x0100
574
575	/* USB_UPHY_XTAL */
576	#define OOBS_POLLING BIT(8)
577
578	/* USB_UPS_CFG */
579	#define SAW_CNT_1MS_MASK 0x0fff
580	#define MID_REVERSE BIT(5) /* RTL8156A */
581
582	/* USB_UPS_FLAGS */
583	#define UPS_FLAGS_R_TUNE BIT(0)
584	#define UPS_FLAGS_EN_10M_CKDIV BIT(1)
585	#define UPS_FLAGS_250M_CKDIV BIT(2)
586	#define UPS_FLAGS_EN_ALDPS BIT(3)
587	#define UPS_FLAGS_CTAP_SHORT_DIS BIT(4)
588	#define UPS_FLAGS_SPEED_MASK (0xf << 16)
589	#define ups_flags_speed(x) ((x) << 16)
590	#define UPS_FLAGS_EN_EEE BIT(20)
591	#define UPS_FLAGS_EN_500M_EEE BIT(21)
592	#define UPS_FLAGS_EN_EEE_CKDIV BIT(22)
593	#define UPS_FLAGS_EEE_PLLOFF_100 BIT(23)
594	#define UPS_FLAGS_EEE_PLLOFF_GIGA BIT(24)
595	#define UPS_FLAGS_EEE_CMOD_LV_EN BIT(25)
596	#define UPS_FLAGS_EN_GREEN BIT(26)
597	#define UPS_FLAGS_EN_FLOW_CTR BIT(27)
598
599	enum spd_duplex {
600	NWAY_10M_HALF,
601	NWAY_10M_FULL,
602	NWAY_100M_HALF,
603	NWAY_100M_FULL,
604	NWAY_1000M_FULL,
605	FORCE_10M_HALF,
606	FORCE_10M_FULL,
607	FORCE_100M_HALF,
608	FORCE_100M_FULL,
609	FORCE_1000M_FULL,
610	NWAY_2500M_FULL,
611	};
612
613	/* OCP_ALDPS_CONFIG */
614	#define ENPWRSAVE 0x8000
615	#define ENPDNPS 0x0200
616	#define LINKENA 0x0100
617	#define DIS_SDSAVE 0x0010
618
619	/* OCP_PHY_STATUS */
620	#define PHY_STAT_MASK 0x0007
621	#define PHY_STAT_EXT_INIT 2
622	#define PHY_STAT_LAN_ON 3
623	#define PHY_STAT_PWRDN 5
624
625	/* OCP_INTR_EN */
626	#define INTR_SPEED_FORCE BIT(3)
627
628	/* OCP_NCTL_CFG */
629	#define PGA_RETURN_EN BIT(1)
630
631	/* OCP_POWER_CFG */
632	#define EEE_CLKDIV_EN 0x8000
633	#define EN_ALDPS 0x0004
634	#define EN_10M_PLLOFF 0x0001
635
636	/* OCP_EEE_CONFIG1 */
637	#define RG_TXLPI_MSK_HFDUP 0x8000
638	#define RG_MATCLR_EN 0x4000
639	#define EEE_10_CAP 0x2000
640	#define EEE_NWAY_EN 0x1000
641	#define TX_QUIET_EN 0x0200
642	#define RX_QUIET_EN 0x0100
643	#define sd_rise_time_mask 0x0070
644	#define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
645	#define RG_RXLPI_MSK_HFDUP 0x0008
646	#define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
647
648	/* OCP_EEE_CONFIG2 */
649	#define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
650	#define RG_DACQUIET_EN 0x0400
651	#define RG_LDVQUIET_EN 0x0200
652	#define RG_CKRSEL 0x0020
653	#define RG_EEEPRG_EN 0x0010
654
655	/* OCP_EEE_CONFIG3 */
656	#define fast_snr_mask 0xff80
657	#define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
658	#define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
659	#define MSK_PH 0x0006 /* bit 0 ~ 3 */
660
661	/* OCP_EEE_AR */
662	/* bit[15:14] function */
663	#define FUN_ADDR 0x0000
664	#define FUN_DATA 0x4000
665	/* bit[4:0] device addr */
666
667	/* OCP_EEE_CFG */
668	#define CTAP_SHORT_EN 0x0040
669	#define EEE10_EN 0x0010
670
671	/* OCP_DOWN_SPEED */
672	#define EN_EEE_CMODE BIT(14)
673	#define EN_EEE_1000 BIT(13)
674	#define EN_EEE_100 BIT(12)
675	#define EN_10M_CLKDIV BIT(11)
676	#define EN_10M_BGOFF 0x0080
677
678	/* OCP_10GBT_CTRL */
679	#define RTL_ADV2_5G_F_R BIT(5) /* Advertise 2.5GBASE-T fast-retrain */
680
681	/* OCP_PHY_STATE */
682	#define TXDIS_STATE 0x01
683	#define ABD_STATE 0x02
684
685	/* OCP_PHY_PATCH_STAT */
686	#define PATCH_READY BIT(6)
687
688	/* OCP_PHY_PATCH_CMD */
689	#define PATCH_REQUEST BIT(4)
690
691	/* OCP_PHY_LOCK */
692	#define PATCH_LOCK BIT(0)
693
694	/* OCP_ADC_CFG */
695	#define CKADSEL_L 0x0100
696	#define ADC_EN 0x0080
697	#define EN_EMI_L 0x0040
698
699	/* OCP_SYSCLK_CFG */
700	#define sysclk_div_expo(x) (min(x, 5) << 8)
701	#define clk_div_expo(x) (min(x, 5) << 4)
702
703	/* SRAM_GREEN_CFG */
704	#define GREEN_ETH_EN BIT(15)
705	#define R_TUNE_EN BIT(11)
706
707	/* SRAM_LPF_CFG */
708	#define LPF_AUTO_TUNE 0x8000
709
710	/* SRAM_10M_AMP1 */
711	#define GDAC_IB_UPALL 0x0008
712
713	/* SRAM_10M_AMP2 */
714	#define AMP_DN 0x0200
715
716	/* SRAM_IMPEDANCE */
717	#define RX_DRIVING_MASK 0x6000
718
719	/* SRAM_PHY_LOCK */
720	#define PHY_PATCH_LOCK 0x0001
721
722	/* MAC PASSTHRU */
723	#define AD_MASK 0xfee0
724	#define BND_MASK 0x0004
725	#define BD_MASK 0x0001
726	#define EFUSE 0xcfdb
727	#define PASS_THRU_MASK 0x1
728
729	#define BP4_SUPER_ONLY 0x1578 /* RTL_VER_04 only */
730
731	enum rtl_register_content {
732	_2500bps = BIT(10),
733	_1250bps = BIT(9),
734	_500bps = BIT(8),
735	_tx_flow = BIT(6),
736	_rx_flow = BIT(5),
737	_1000bps = 0x10,
738	_100bps = 0x08,
739	_10bps = 0x04,
740	LINK_STATUS = 0x02,
741	FULL_DUP = 0x01,
742	};
743
744	#define is_speed_2500(_speed) (((_speed) & (_2500bps | LINK_STATUS)) == (_2500bps | LINK_STATUS))
745	#define is_flow_control(_speed) (((_speed) & (_tx_flow | _rx_flow)) == (_tx_flow | _rx_flow))
746
747	#define RTL8152_MAX_TX 4
748	#define RTL8152_MAX_RX 10
749	#define INTBUFSIZE 2
750	#define TX_ALIGN 4
751	#define RX_ALIGN 8
752
753	#define RTL8152_RX_MAX_PENDING 4096
754	#define RTL8152_RXFG_HEADSZ 256
755
756	#define INTR_LINK 0x0004
757
758	#define RTL8152_RMS (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
759	#define RTL8153_RMS RTL8153_MAX_PACKET
760	#define RTL8152_TX_TIMEOUT (5 * HZ)
761	#define mtu_to_size(m) ((m) + VLAN_ETH_HLEN + ETH_FCS_LEN)
762	#define size_to_mtu(s) ((s) - VLAN_ETH_HLEN - ETH_FCS_LEN)
763	#define rx_reserved_size(x) (mtu_to_size(x) + sizeof(struct rx_desc) + RX_ALIGN)
764
765	/* rtl8152 flags */
766	enum rtl8152_flags {
767	RTL8152_INACCESSIBLE = 0,
768	RTL8152_SET_RX_MODE,
769	WORK_ENABLE,
770	RTL8152_LINK_CHG,
771	SELECTIVE_SUSPEND,
772	PHY_RESET,
773	SCHEDULE_TASKLET,
774	GREEN_ETHERNET,
775	RX_EPROTO,
776	IN_PRE_RESET,
777	PROBED_WITH_NO_ERRORS,
778	PROBE_SHOULD_RETRY,
779	};
780
781	#define DEVICE_ID_LENOVO_USB_C_TRAVEL_HUB 0x721e
782	#define DEVICE_ID_THINKPAD_ONELINK_PLUS_DOCK 0x3054
783	#define DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2 0x3082
784	#define DEVICE_ID_THINKPAD_USB_C_DONGLE 0x720c
785	#define DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2 0xa387
786	#define DEVICE_ID_THINKPAD_USB_C_DOCK_GEN3 0x3062
787
788	struct tally_counter {
789	__le64 tx_packets;
790	__le64 rx_packets;
791	__le64 tx_errors;
792	__le32 rx_errors;
793	__le16 rx_missed;
794	__le16 align_errors;
795	__le32 tx_one_collision;
796	__le32 tx_multi_collision;
797	__le64 rx_unicast;
798	__le64 rx_broadcast;
799	__le32 rx_multicast;
800	__le16 tx_aborted;
801	__le16 tx_underrun;
802	};
803
804	struct rx_desc {
805	__le32 opts1;
806	#define RX_LEN_MASK 0x7fff
807
808	__le32 opts2;
809	#define RD_UDP_CS BIT(23)
810	#define RD_TCP_CS BIT(22)
811	#define RD_IPV6_CS BIT(20)
812	#define RD_IPV4_CS BIT(19)
813
814	__le32 opts3;
815	#define IPF BIT(23) /* IP checksum fail */
816	#define UDPF BIT(22) /* UDP checksum fail */
817	#define TCPF BIT(21) /* TCP checksum fail */
818	#define RX_VLAN_TAG BIT(16)
819
820	__le32 opts4;
821	__le32 opts5;
822	__le32 opts6;
823	};
824
825	struct tx_desc {
826	__le32 opts1;
827	#define TX_FS BIT(31) /* First segment of a packet */
828	#define TX_LS BIT(30) /* Final segment of a packet */
829	#define GTSENDV4 BIT(28)
830	#define GTSENDV6 BIT(27)
831	#define GTTCPHO_SHIFT 18
832	#define GTTCPHO_MAX 0x7fU
833	#define TX_LEN_MAX 0x3ffffU
834
835	__le32 opts2;
836	#define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
837	#define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
838	#define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
839	#define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
840	#define MSS_SHIFT 17
841	#define MSS_MAX 0x7ffU
842	#define TCPHO_SHIFT 17
843	#define TCPHO_MAX 0x7ffU
844	#define TX_VLAN_TAG BIT(16)
845	};
846
847	struct r8152;
848
849	struct rx_agg {
850	struct list_head list, info_list;
851	struct urb *urb;
852	struct r8152 *context;
853	struct page *page;
854	void *buffer;
855	};
856
857	struct tx_agg {
858	struct list_head list;
859	struct urb *urb;
860	struct r8152 *context;
861	void *buffer;
862	void *head;
863	u32 skb_num;
864	u32 skb_len;
865	};
866
867	struct r8152 {
868	unsigned long flags;
869	struct usb_device *udev;
870	struct napi_struct napi;
871	struct usb_interface *intf;
872	struct net_device *netdev;
873	struct urb *intr_urb;
874	struct tx_agg tx_info[RTL8152_MAX_TX];
875	struct list_head rx_info, rx_used;
876	struct list_head rx_done, tx_free;
877	struct sk_buff_head tx_queue, rx_queue;
878	spinlock_t rx_lock, tx_lock;
879	struct delayed_work schedule, hw_phy_work;
880	struct mii_if_info mii;
881	struct mutex control; /* use for hw setting */
882	#ifdef CONFIG_PM_SLEEP
883	struct notifier_block pm_notifier;
884	#endif
885	struct tasklet_struct tx_tl;
886
887	struct rtl_ops {
888	void (*init)(struct r8152 *tp);
889	int (*enable)(struct r8152 *tp);
890	void (*disable)(struct r8152 *tp);
891	void (*up)(struct r8152 *tp);
892	void (*down)(struct r8152 *tp);
893	void (*unload)(struct r8152 *tp);
894	int (*eee_get)(struct r8152 *tp, struct ethtool_eee *eee);
895	int (*eee_set)(struct r8152 *tp, struct ethtool_eee *eee);
896	bool (*in_nway)(struct r8152 *tp);
897	void (*hw_phy_cfg)(struct r8152 *tp);
898	void (*autosuspend_en)(struct r8152 *tp, bool enable);
899	void (*change_mtu)(struct r8152 *tp);
900	} rtl_ops;
901
902	struct ups_info {
903	u32 r_tune:1;
904	u32 _10m_ckdiv:1;
905	u32 _250m_ckdiv:1;
906	u32 aldps:1;
907	u32 lite_mode:2;
908	u32 speed_duplex:4;
909	u32 eee:1;
910	u32 eee_lite:1;
911	u32 eee_ckdiv:1;
912	u32 eee_plloff_100:1;
913	u32 eee_plloff_giga:1;
914	u32 eee_cmod_lv:1;
915	u32 green:1;
916	u32 flow_control:1;
917	u32 ctap_short_off:1;
918	} ups_info;
919
920	#define RTL_VER_SIZE 32
921
922	struct rtl_fw {
923	const char *fw_name;
924	const struct firmware *fw;
925
926	char version[RTL_VER_SIZE];
927	int (*pre_fw)(struct r8152 *tp);
928	int (*post_fw)(struct r8152 *tp);
929
930	bool retry;
931	} rtl_fw;
932
933	atomic_t rx_count;
934
935	bool eee_en;
936	int intr_interval;
937	u32 saved_wolopts;
938	u32 msg_enable;
939	u32 tx_qlen;
940	u32 coalesce;
941	u32 advertising;
942	u32 rx_buf_sz;
943	u32 rx_copybreak;
944	u32 rx_pending;
945	u32 fc_pause_on, fc_pause_off;
946
947	unsigned int pipe_in, pipe_out, pipe_intr, pipe_ctrl_in, pipe_ctrl_out;
948
949	u32 support_2500full:1;
950	u32 lenovo_macpassthru:1;
951	u32 dell_tb_rx_agg_bug:1;
952	u16 ocp_base;
953	u16 speed;
954	u16 eee_adv;
955	u8 *intr_buff;
956	u8 version;
957	u8 duplex;
958	u8 autoneg;
959
960	unsigned int reg_access_reset_count;
961	};
962
963	/**
964	* struct fw_block - block type and total length
965	* @type: type of the current block, such as RTL_FW_END, RTL_FW_PLA,
966	* RTL_FW_USB and so on.
967	* @length: total length of the current block.
968	*/
969	struct fw_block {
970	__le32 type;
971	__le32 length;
972	} __packed;
973
974	/**
975	* struct fw_header - header of the firmware file
976	* @checksum: checksum of sha256 which is calculated from the whole file
977	* except the checksum field of the file. That is, calculate sha256
978	* from the version field to the end of the file.
979	* @version: version of this firmware.
980	* @blocks: the first firmware block of the file
981	*/
982	struct fw_header {
983	u8 checksum[32];
984	char version[RTL_VER_SIZE];
985	struct fw_block blocks[];
986	} __packed;
987
988	enum rtl8152_fw_flags {
989	FW_FLAGS_USB = 0,
990	FW_FLAGS_PLA,
991	FW_FLAGS_START,
992	FW_FLAGS_STOP,
993	FW_FLAGS_NC,
994	FW_FLAGS_NC1,
995	FW_FLAGS_NC2,
996	FW_FLAGS_UC2,
997	FW_FLAGS_UC,
998	FW_FLAGS_SPEED_UP,
999	FW_FLAGS_VER,
1000	};
1001
1002	enum rtl8152_fw_fixup_cmd {
1003	FW_FIXUP_AND = 0,
1004	FW_FIXUP_OR,
1005	FW_FIXUP_NOT,
1006	FW_FIXUP_XOR,
1007	};
1008
1009	struct fw_phy_set {
1010	__le16 addr;
1011	__le16 data;
1012	} __packed;
1013
1014	struct fw_phy_speed_up {
1015	struct fw_block blk_hdr;
1016	__le16 fw_offset;
1017	__le16 version;
1018	__le16 fw_reg;
1019	__le16 reserved;
1020	char info[];
1021	} __packed;
1022
1023	struct fw_phy_ver {
1024	struct fw_block blk_hdr;
1025	struct fw_phy_set ver;
1026	__le32 reserved;
1027	} __packed;
1028
1029	struct fw_phy_fixup {
1030	struct fw_block blk_hdr;
1031	struct fw_phy_set setting;
1032	__le16 bit_cmd;
1033	__le16 reserved;
1034	} __packed;
1035
1036	struct fw_phy_union {
1037	struct fw_block blk_hdr;
1038	__le16 fw_offset;
1039	__le16 fw_reg;
1040	struct fw_phy_set pre_set[2];
1041	struct fw_phy_set bp[8];
1042	struct fw_phy_set bp_en;
1043	u8 pre_num;
1044	u8 bp_num;
1045	char info[];
1046	} __packed;
1047
1048	/**
1049	* struct fw_mac - a firmware block used by RTL_FW_PLA and RTL_FW_USB.
1050	* The layout of the firmware block is:
1051	* <struct fw_mac> + <info> + <firmware data>.
1052	* @blk_hdr: firmware descriptor (type, length)
1053	* @fw_offset: offset of the firmware binary data. The start address of
1054	* the data would be the address of struct fw_mac + @fw_offset.
1055	* @fw_reg: the register to load the firmware. Depends on chip.
1056	* @bp_ba_addr: the register to write break point base address. Depends on
1057	* chip.
1058	* @bp_ba_value: break point base address. Depends on chip.
1059	* @bp_en_addr: the register to write break point enabled mask. Depends
1060	* on chip.
1061	* @bp_en_value: break point enabled mask. Depends on the firmware.
1062	* @bp_start: the start register of break points. Depends on chip.
1063	* @bp_num: the break point number which needs to be set for this firmware.
1064	* Depends on the firmware.
1065	* @bp: break points. Depends on firmware.
1066	* @reserved: reserved space (unused)
1067	* @fw_ver_reg: the register to store the fw version.
1068	* @fw_ver_data: the firmware version of the current type.
1069	* @info: additional information for debugging, and is followed by the
1070	* binary data of firmware.
1071	*/
1072	struct fw_mac {
1073	struct fw_block blk_hdr;
1074	__le16 fw_offset;
1075	__le16 fw_reg;
1076	__le16 bp_ba_addr;
1077	__le16 bp_ba_value;
1078	__le16 bp_en_addr;
1079	__le16 bp_en_value;
1080	__le16 bp_start;
1081	__le16 bp_num;
1082	__le16 bp[16]; /* any value determined by firmware */
1083	__le32 reserved;
1084	__le16 fw_ver_reg;
1085	u8 fw_ver_data;
1086	char info[];
1087	} __packed;
1088
1089	/**
1090	* struct fw_phy_patch_key - a firmware block used by RTL_FW_PHY_START.
1091	* This is used to set patch key when loading the firmware of PHY.
1092	* @blk_hdr: firmware descriptor (type, length)
1093	* @key_reg: the register to write the patch key.
1094	* @key_data: patch key.
1095	* @reserved: reserved space (unused)
1096	*/
1097	struct fw_phy_patch_key {
1098	struct fw_block blk_hdr;
1099	__le16 key_reg;
1100	__le16 key_data;
1101	__le32 reserved;
1102	} __packed;
1103
1104	/**
1105	* struct fw_phy_nc - a firmware block used by RTL_FW_PHY_NC.
1106	* The layout of the firmware block is:
1107	* <struct fw_phy_nc> + <info> + <firmware data>.
1108	* @blk_hdr: firmware descriptor (type, length)
1109	* @fw_offset: offset of the firmware binary data. The start address of
1110	* the data would be the address of struct fw_phy_nc + @fw_offset.
1111	* @fw_reg: the register to load the firmware. Depends on chip.
1112	* @ba_reg: the register to write the base address. Depends on chip.
1113	* @ba_data: base address. Depends on chip.
1114	* @patch_en_addr: the register of enabling patch mode. Depends on chip.
1115	* @patch_en_value: patch mode enabled mask. Depends on the firmware.
1116	* @mode_reg: the regitster of switching the mode.
1117	* @mode_pre: the mode needing to be set before loading the firmware.
1118	* @mode_post: the mode to be set when finishing to load the firmware.
1119	* @reserved: reserved space (unused)
1120	* @bp_start: the start register of break points. Depends on chip.
1121	* @bp_num: the break point number which needs to be set for this firmware.
1122	* Depends on the firmware.
1123	* @bp: break points. Depends on firmware.
1124	* @info: additional information for debugging, and is followed by the
1125	* binary data of firmware.
1126	*/
1127	struct fw_phy_nc {
1128	struct fw_block blk_hdr;
1129	__le16 fw_offset;
1130	__le16 fw_reg;
1131	__le16 ba_reg;
1132	__le16 ba_data;
1133	__le16 patch_en_addr;
1134	__le16 patch_en_value;
1135	__le16 mode_reg;
1136	__le16 mode_pre;
1137	__le16 mode_post;
1138	__le16 reserved;
1139	__le16 bp_start;
1140	__le16 bp_num;
1141	__le16 bp[4];
1142	char info[];
1143	} __packed;
1144
1145	enum rtl_fw_type {
1146	RTL_FW_END = 0,
1147	RTL_FW_PLA,
1148	RTL_FW_USB,
1149	RTL_FW_PHY_START,
1150	RTL_FW_PHY_STOP,
1151	RTL_FW_PHY_NC,
1152	RTL_FW_PHY_FIXUP,
1153	RTL_FW_PHY_UNION_NC,
1154	RTL_FW_PHY_UNION_NC1,
1155	RTL_FW_PHY_UNION_NC2,
1156	RTL_FW_PHY_UNION_UC2,
1157	RTL_FW_PHY_UNION_UC,
1158	RTL_FW_PHY_UNION_MISC,
1159	RTL_FW_PHY_SPEED_UP,
1160	RTL_FW_PHY_VER,
1161	};
1162
1163	enum rtl_version {
1164	RTL_VER_UNKNOWN = 0,
1165	RTL_VER_01,
1166	RTL_VER_02,
1167	RTL_VER_03,
1168	RTL_VER_04,
1169	RTL_VER_05,
1170	RTL_VER_06,
1171	RTL_VER_07,
1172	RTL_VER_08,
1173	RTL_VER_09,
1174
1175	RTL_TEST_01,
1176	RTL_VER_10,
1177	RTL_VER_11,
1178	RTL_VER_12,
1179	RTL_VER_13,
1180	RTL_VER_14,
1181	RTL_VER_15,
1182
1183	RTL_VER_MAX
1184	};
1185
1186	enum tx_csum_stat {
1187	TX_CSUM_SUCCESS = 0,
1188	TX_CSUM_TSO,
1189	TX_CSUM_NONE
1190	};
1191
1192	#define RTL_ADVERTISED_10_HALF BIT(0)
1193	#define RTL_ADVERTISED_10_FULL BIT(1)
1194	#define RTL_ADVERTISED_100_HALF BIT(2)
1195	#define RTL_ADVERTISED_100_FULL BIT(3)
1196	#define RTL_ADVERTISED_1000_HALF BIT(4)
1197	#define RTL_ADVERTISED_1000_FULL BIT(5)
1198	#define RTL_ADVERTISED_2500_FULL BIT(6)
1199
1200	/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
1201	* The RTL chips use a 64 element hash table based on the Ethernet CRC.
1202	*/
1203	static const int multicast_filter_limit = 32;
1204	static unsigned int agg_buf_sz = 16384;
1205
1206	#define RTL_LIMITED_TSO_SIZE (size_to_mtu(agg_buf_sz) - sizeof(struct tx_desc))
1207
1208	/* If register access fails then we block access and issue a reset. If this
1209	* happens too many times in a row without a successful access then we stop
1210	* trying to reset and just leave access blocked.
1211	*/
1212	#define REGISTER_ACCESS_MAX_RESETS 3
1213
1214	static void rtl_set_inaccessible(struct r8152 *tp)
1215	{
1216	set_bit(nr: RTL8152_INACCESSIBLE, addr: &tp->flags);
1217	smp_mb__after_atomic();
1218	}
1219
1220	static void rtl_set_accessible(struct r8152 *tp)
1221	{
1222	clear_bit(nr: RTL8152_INACCESSIBLE, addr: &tp->flags);
1223	smp_mb__after_atomic();
1224	}
1225
1226	static
1227	int r8152_control_msg(struct r8152 *tp, unsigned int pipe, __u8 request,
1228	__u8 requesttype, __u16 value, __u16 index, void *data,
1229	__u16 size, const char *msg_tag)
1230	{
1231	struct usb_device *udev = tp->udev;
1232	int ret;
1233
1234	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
1235	return -ENODEV;
1236
1237	ret = usb_control_msg(dev: udev, pipe, request, requesttype,
1238	value, index, data, size,
1239	USB_CTRL_GET_TIMEOUT);
1240
1241	/* No need to issue a reset to report an error if the USB device got
1242	* unplugged; just return immediately.
1243	*/
1244	if (ret == -ENODEV)
1245	return ret;
1246
1247	/* If the write was successful then we're done */
1248	if (ret >= 0) {
1249	tp->reg_access_reset_count = 0;
1250	return ret;
1251	}
1252
1253	dev_err(&udev->dev,
1254	"Failed to %s %d bytes at %#06x/%#06x (%d)\n",
1255	msg_tag, size, value, index, ret);
1256
1257	/* Block all future register access until we reset. Much of the code
1258	* in the driver doesn't check for errors. Notably, many parts of the
1259	* driver do a read/modify/write of a register value without
1260	* confirming that the read succeeded. Writing back modified garbage
1261	* like this can fully wedge the adapter, requiring a power cycle.
1262	*/
1263	rtl_set_inaccessible(tp);
1264
1265	/* If probe hasn't yet finished, then we'll request a retry of the
1266	* whole probe routine if we get any control transfer errors. We
1267	* never have to clear this bit since we free/reallocate the whole "tp"
1268	* structure if we retry probe.
1269	*/
1270	if (!test_bit(PROBED_WITH_NO_ERRORS, &tp->flags)) {
1271	set_bit(nr: PROBE_SHOULD_RETRY, addr: &tp->flags);
1272	return ret;
1273	}
1274
1275	/* Failing to access registers in pre-reset is not surprising since we
1276	* wouldn't be resetting if things were behaving normally. The register
1277	* access we do in pre-reset isn't truly mandatory--we're just reusing
1278	* the disable() function and trying to be nice by powering the
1279	* adapter down before resetting it. Thus, if we're in pre-reset,
1280	* we'll return right away and not try to queue up yet another reset.
1281	* We know the post-reset is already coming.
1282	*/
1283	if (test_bit(IN_PRE_RESET, &tp->flags))
1284	return ret;
1285
1286	if (tp->reg_access_reset_count < REGISTER_ACCESS_MAX_RESETS) {
1287	usb_queue_reset_device(dev: tp->intf);
1288	tp->reg_access_reset_count++;
1289	} else if (tp->reg_access_reset_count == REGISTER_ACCESS_MAX_RESETS) {
1290	dev_err(&udev->dev,
1291	"Tried to reset %d times; giving up.\n",
1292	REGISTER_ACCESS_MAX_RESETS);
1293	}
1294
1295	return ret;
1296	}
1297
1298	static
1299	int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
1300	{
1301	int ret;
1302	void *tmp;
1303
1304	tmp = kmalloc(size, GFP_KERNEL);
1305	if (!tmp)
1306	return -ENOMEM;
1307
1308	ret = r8152_control_msg(tp, pipe: tp->pipe_ctrl_in,
1309	RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
1310	value, index, data: tmp, size, msg_tag: "read");
1311
1312	if (ret < 0)
1313	memset(data, 0xff, size);
1314	else
1315	memcpy(data, tmp, size);
1316
1317	kfree(objp: tmp);
1318
1319	return ret;
1320	}
1321
1322	static
1323	int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
1324	{
1325	int ret;
1326	void *tmp;
1327
1328	tmp = kmemdup(p: data, size, GFP_KERNEL);
1329	if (!tmp)
1330	return -ENOMEM;
1331
1332	ret = r8152_control_msg(tp, pipe: tp->pipe_ctrl_out,
1333	RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
1334	value, index, data: tmp, size, msg_tag: "write");
1335
1336	kfree(objp: tmp);
1337
1338	return ret;
1339	}
1340
1341	static void rtl_set_unplug(struct r8152 *tp)
1342	{
1343	if (tp->udev->state == USB_STATE_NOTATTACHED)
1344	rtl_set_inaccessible(tp);
1345	}
1346
1347	static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
1348	void *data, u16 type)
1349	{
1350	u16 limit = 64;
1351	int ret = 0;
1352
1353	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
1354	return -ENODEV;
1355
1356	/* both size and indix must be 4 bytes align */
1357	if ((size & 3) || !size || (index & 3) || !data)
1358	return -EPERM;
1359
1360	if ((u32)index + (u32)size > 0xffff)
1361	return -EPERM;
1362
1363	while (size) {
1364	if (size > limit) {
1365	ret = get_registers(tp, value: index, index: type, size: limit, data);
1366	if (ret < 0)
1367	break;
1368
1369	index += limit;
1370	data += limit;
1371	size -= limit;
1372	} else {
1373	ret = get_registers(tp, value: index, index: type, size, data);
1374	if (ret < 0)
1375	break;
1376
1377	index += size;
1378	data += size;
1379	size = 0;
1380	break;
1381	}
1382	}
1383
1384	if (ret == -ENODEV)
1385	rtl_set_unplug(tp);
1386
1387	return ret;
1388	}
1389
1390	static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
1391	u16 size, void *data, u16 type)
1392	{
1393	int ret;
1394	u16 byteen_start, byteen_end, byen;
1395	u16 limit = 512;
1396
1397	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
1398	return -ENODEV;
1399
1400	/* both size and indix must be 4 bytes align */
1401	if ((size & 3) || !size || (index & 3) || !data)
1402	return -EPERM;
1403
1404	if ((u32)index + (u32)size > 0xffff)
1405	return -EPERM;
1406
1407	byteen_start = byteen & BYTE_EN_START_MASK;
1408	byteen_end = byteen & BYTE_EN_END_MASK;
1409
1410	byen = byteen_start | (byteen_start << 4);
1411
1412	/* Split the first DWORD if the byte_en is not 0xff */
1413	if (byen != BYTE_EN_DWORD) {
1414	ret = set_registers(tp, value: index, index: type | byen, size: 4, data);
1415	if (ret < 0)
1416	goto error1;
1417
1418	index += 4;
1419	data += 4;
1420	size -= 4;
1421	}
1422
1423	if (size) {
1424	byen = byteen_end | (byteen_end >> 4);
1425
1426	/* Split the last DWORD if the byte_en is not 0xff */
1427	if (byen != BYTE_EN_DWORD)
1428	size -= 4;
1429
1430	while (size) {
1431	if (size > limit) {
1432	ret = set_registers(tp, value: index,
1433	index: type | BYTE_EN_DWORD,
1434	size: limit, data);
1435	if (ret < 0)
1436	goto error1;
1437
1438	index += limit;
1439	data += limit;
1440	size -= limit;
1441	} else {
1442	ret = set_registers(tp, value: index,
1443	index: type | BYTE_EN_DWORD,
1444	size, data);
1445	if (ret < 0)
1446	goto error1;
1447
1448	index += size;
1449	data += size;
1450	size = 0;
1451	break;
1452	}
1453	}
1454
1455	/* Set the last DWORD */
1456	if (byen != BYTE_EN_DWORD)
1457	ret = set_registers(tp, value: index, index: type | byen, size: 4, data);
1458	}
1459
1460	error1:
1461	if (ret == -ENODEV)
1462	rtl_set_unplug(tp);
1463
1464	return ret;
1465	}
1466
1467	static inline
1468	int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
1469	{
1470	return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
1471	}
1472
1473	static inline
1474	int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1475	{
1476	return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
1477	}
1478
1479	static inline
1480	int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1481	{
1482	return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
1483	}
1484
1485	static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
1486	{
1487	__le32 data;
1488
1489	generic_ocp_read(tp, index, size: sizeof(data), data: &data, type);
1490
1491	return __le32_to_cpu(data);
1492	}
1493
1494	static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
1495	{
1496	__le32 tmp = __cpu_to_le32(data);
1497
1498	generic_ocp_write(tp, index, BYTE_EN_DWORD, size: sizeof(tmp), data: &tmp, type);
1499	}
1500
1501	static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
1502	{
1503	u32 data;
1504	__le32 tmp;
1505	u16 byen = BYTE_EN_WORD;
1506	u8 shift = index & 2;
1507
1508	index &= ~3;
1509	byen <<= shift;
1510
1511	generic_ocp_read(tp, index, size: sizeof(tmp), data: &tmp, type: type | byen);
1512
1513	data = __le32_to_cpu(tmp);
1514	data >>= (shift * 8);
1515	data &= 0xffff;
1516
1517	return (u16)data;
1518	}
1519
1520	static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
1521	{
1522	u32 mask = 0xffff;
1523	__le32 tmp;
1524	u16 byen = BYTE_EN_WORD;
1525	u8 shift = index & 2;
1526
1527	data &= mask;
1528
1529	if (index & 2) {
1530	byen <<= shift;
1531	mask <<= (shift * 8);
1532	data <<= (shift * 8);
1533	index &= ~3;
1534	}
1535
1536	tmp = __cpu_to_le32(data);
1537
1538	generic_ocp_write(tp, index, byteen: byen, size: sizeof(tmp), data: &tmp, type);
1539	}
1540
1541	static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
1542	{
1543	u32 data;
1544	__le32 tmp;
1545	u8 shift = index & 3;
1546
1547	index &= ~3;
1548
1549	generic_ocp_read(tp, index, size: sizeof(tmp), data: &tmp, type);
1550
1551	data = __le32_to_cpu(tmp);
1552	data >>= (shift * 8);
1553	data &= 0xff;
1554
1555	return (u8)data;
1556	}
1557
1558	static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
1559	{
1560	u32 mask = 0xff;
1561	__le32 tmp;
1562	u16 byen = BYTE_EN_BYTE;
1563	u8 shift = index & 3;
1564
1565	data &= mask;
1566
1567	if (index & 3) {
1568	byen <<= shift;
1569	mask <<= (shift * 8);
1570	data <<= (shift * 8);
1571	index &= ~3;
1572	}
1573
1574	tmp = __cpu_to_le32(data);
1575
1576	generic_ocp_write(tp, index, byteen: byen, size: sizeof(tmp), data: &tmp, type);
1577	}
1578
1579	static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
1580	{
1581	u16 ocp_base, ocp_index;
1582
1583	ocp_base = addr & 0xf000;
1584	if (ocp_base != tp->ocp_base) {
1585	ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, data: ocp_base);
1586	tp->ocp_base = ocp_base;
1587	}
1588
1589	ocp_index = (addr & 0x0fff) | 0xb000;
1590	return ocp_read_word(tp, MCU_TYPE_PLA, index: ocp_index);
1591	}
1592
1593	static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
1594	{
1595	u16 ocp_base, ocp_index;
1596
1597	ocp_base = addr & 0xf000;
1598	if (ocp_base != tp->ocp_base) {
1599	ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, data: ocp_base);
1600	tp->ocp_base = ocp_base;
1601	}
1602
1603	ocp_index = (addr & 0x0fff) | 0xb000;
1604	ocp_write_word(tp, MCU_TYPE_PLA, index: ocp_index, data);
1605	}
1606
1607	static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
1608	{
1609	ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, data: value);
1610	}
1611
1612	static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
1613	{
1614	return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
1615	}
1616
1617	static void sram_write(struct r8152 *tp, u16 addr, u16 data)
1618	{
1619	ocp_reg_write(tp, OCP_SRAM_ADDR, data: addr);
1620	ocp_reg_write(tp, OCP_SRAM_DATA, data);
1621	}
1622
1623	static u16 sram_read(struct r8152 *tp, u16 addr)
1624	{
1625	ocp_reg_write(tp, OCP_SRAM_ADDR, data: addr);
1626	return ocp_reg_read(tp, OCP_SRAM_DATA);
1627	}
1628
1629	static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
1630	{
1631	struct r8152 *tp = netdev_priv(dev: netdev);
1632	int ret;
1633
1634	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
1635	return -ENODEV;
1636
1637	if (phy_id != R8152_PHY_ID)
1638	return -EINVAL;
1639
1640	ret = r8152_mdio_read(tp, reg_addr: reg);
1641
1642	return ret;
1643	}
1644
1645	static
1646	void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
1647	{
1648	struct r8152 *tp = netdev_priv(dev: netdev);
1649
1650	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
1651	return;
1652
1653	if (phy_id != R8152_PHY_ID)
1654	return;
1655
1656	r8152_mdio_write(tp, reg_addr: reg, value: val);
1657	}
1658
1659	static int
1660	r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
1661
1662	static int
1663	rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,
1664	u32 advertising);
1665
1666	static int __rtl8152_set_mac_address(struct net_device *netdev, void *p,
1667	bool in_resume)
1668	{
1669	struct r8152 *tp = netdev_priv(dev: netdev);
1670	struct sockaddr *addr = p;
1671	int ret = -EADDRNOTAVAIL;
1672
1673	if (!is_valid_ether_addr(addr: addr->sa_data))
1674	goto out1;
1675
1676	if (!in_resume) {
1677	ret = usb_autopm_get_interface(intf: tp->intf);
1678	if (ret < 0)
1679	goto out1;
1680	}
1681
1682	mutex_lock(&tp->control);
1683
1684	eth_hw_addr_set(dev: netdev, addr: addr->sa_data);
1685
1686	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1687	pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, size: 8, data: addr->sa_data);
1688	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1689
1690	mutex_unlock(lock: &tp->control);
1691
1692	if (!in_resume)
1693	usb_autopm_put_interface(intf: tp->intf);
1694	out1:
1695	return ret;
1696	}
1697
1698	static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
1699	{
1700	return __rtl8152_set_mac_address(netdev, p, in_resume: false);
1701	}
1702
1703	/* Devices containing proper chips can support a persistent
1704	* host system provided MAC address.
1705	* Examples of this are Dell TB15 and Dell WD15 docks
1706	*/
1707	static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa)
1708	{
1709	acpi_status status;
1710	struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
1711	union acpi_object *obj;
1712	int ret = -EINVAL;
1713	u32 ocp_data;
1714	unsigned char buf[6];
1715	char *mac_obj_name;
1716	acpi_object_type mac_obj_type;
1717	int mac_strlen;
1718
1719	if (tp->lenovo_macpassthru) {
1720	mac_obj_name = "\\MACA";
1721	mac_obj_type = ACPI_TYPE_STRING;
1722	mac_strlen = 0x16;
1723	} else {
1724	/* test for -AD variant of RTL8153 */
1725	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
1726	if ((ocp_data & AD_MASK) == 0x1000) {
1727	/* test for MAC address pass-through bit */
1728	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE);
1729	if ((ocp_data & PASS_THRU_MASK) != 1) {
1730	netif_dbg(tp, probe, tp->netdev,
1731	"No efuse for RTL8153-AD MAC pass through\n");
1732	return -ENODEV;
1733	}
1734	} else {
1735	/* test for RTL8153-BND and RTL8153-BD */
1736	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
1737	if ((ocp_data & BND_MASK) == 0 && (ocp_data & BD_MASK) == 0) {
1738	netif_dbg(tp, probe, tp->netdev,
1739	"Invalid variant for MAC pass through\n");
1740	return -ENODEV;
1741	}
1742	}
1743
1744	mac_obj_name = "\\_SB.AMAC";
1745	mac_obj_type = ACPI_TYPE_BUFFER;
1746	mac_strlen = 0x17;
1747	}
1748
1749	/* returns _AUXMAC_#AABBCCDDEEFF# */
1750	status = acpi_evaluate_object(NULL, pathname: mac_obj_name, NULL, return_object_buffer: &buffer);
1751	obj = (union acpi_object *)buffer.pointer;
1752	if (!ACPI_SUCCESS(status))
1753	return -ENODEV;
1754	if (obj->type != mac_obj_type || obj->string.length != mac_strlen) {
1755	netif_warn(tp, probe, tp->netdev,
1756	"Invalid buffer for pass-thru MAC addr: (%d, %d)\n",
1757	obj->type, obj->string.length);
1758	goto amacout;
1759	}
1760
1761	if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 ||
1762	strncmp(obj->string.pointer + 0x15, "#", 1) != 0) {
1763	netif_warn(tp, probe, tp->netdev,
1764	"Invalid header when reading pass-thru MAC addr\n");
1765	goto amacout;
1766	}
1767	ret = hex2bin(dst: buf, src: obj->string.pointer + 9, count: 6);
1768	if (!(ret == 0 && is_valid_ether_addr(addr: buf))) {
1769	netif_warn(tp, probe, tp->netdev,
1770	"Invalid MAC for pass-thru MAC addr: %d, %pM\n",
1771	ret, buf);
1772	ret = -EINVAL;
1773	goto amacout;
1774	}
1775	memcpy(sa->sa_data, buf, 6);
1776	netif_info(tp, probe, tp->netdev,
1777	"Using pass-thru MAC addr %pM\n", sa->sa_data);
1778
1779	amacout:
1780	kfree(objp: obj);
1781	return ret;
1782	}
1783
1784	static int determine_ethernet_addr(struct r8152 *tp, struct sockaddr *sa)
1785	{
1786	struct net_device *dev = tp->netdev;
1787	int ret;
1788
1789	sa->sa_family = dev->type;
1790
1791	ret = eth_platform_get_mac_address(dev: &tp->udev->dev, mac_addr: sa->sa_data);
1792	if (ret < 0) {
1793	if (tp->version == RTL_VER_01) {
1794	ret = pla_ocp_read(tp, PLA_IDR, size: 8, data: sa->sa_data);
1795	} else {
1796	/* if device doesn't support MAC pass through this will
1797	* be expected to be non-zero
1798	*/
1799	ret = vendor_mac_passthru_addr_read(tp, sa);
1800	if (ret < 0)
1801	ret = pla_ocp_read(tp, PLA_BACKUP, size: 8,
1802	data: sa->sa_data);
1803	}
1804	}
1805
1806	if (ret < 0) {
1807	netif_err(tp, probe, dev, "Get ether addr fail\n");
1808	} else if (!is_valid_ether_addr(addr: sa->sa_data)) {
1809	netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1810	sa->sa_data);
1811	eth_hw_addr_random(dev);
1812	ether_addr_copy(dst: sa->sa_data, src: dev->dev_addr);
1813	netif_info(tp, probe, dev, "Random ether addr %pM\n",
1814	sa->sa_data);
1815	return 0;
1816	}
1817
1818	return ret;
1819	}
1820
1821	static int set_ethernet_addr(struct r8152 *tp, bool in_resume)
1822	{
1823	struct net_device *dev = tp->netdev;
1824	struct sockaddr sa;
1825	int ret;
1826
1827	ret = determine_ethernet_addr(tp, sa: &sa);
1828	if (ret < 0)
1829	return ret;
1830
1831	if (tp->version == RTL_VER_01)
1832	eth_hw_addr_set(dev, addr: sa.sa_data);
1833	else
1834	ret = __rtl8152_set_mac_address(netdev: dev, p: &sa, in_resume);
1835
1836	return ret;
1837	}
1838
1839	static void read_bulk_callback(struct urb *urb)
1840	{
1841	struct net_device *netdev;
1842	int status = urb->status;
1843	struct rx_agg *agg;
1844	struct r8152 *tp;
1845	unsigned long flags;
1846
1847	agg = urb->context;
1848	if (!agg)
1849	return;
1850
1851	tp = agg->context;
1852	if (!tp)
1853	return;
1854
1855	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
1856	return;
1857
1858	if (!test_bit(WORK_ENABLE, &tp->flags))
1859	return;
1860
1861	netdev = tp->netdev;
1862
1863	/* When link down, the driver would cancel all bulks. */
1864	/* This avoid the re-submitting bulk */
1865	if (!netif_carrier_ok(dev: netdev))
1866	return;
1867
1868	usb_mark_last_busy(udev: tp->udev);
1869
1870	switch (status) {
1871	case 0:
1872	if (urb->actual_length < ETH_ZLEN)
1873	break;
1874
1875	spin_lock_irqsave(&tp->rx_lock, flags);
1876	list_add_tail(new: &agg->list, head: &tp->rx_done);
1877	spin_unlock_irqrestore(lock: &tp->rx_lock, flags);
1878	napi_schedule(n: &tp->napi);
1879	return;
1880	case -ESHUTDOWN:
1881	rtl_set_unplug(tp);
1882	netif_device_detach(dev: tp->netdev);
1883	return;
1884	case -EPROTO:
1885	urb->actual_length = 0;
1886	spin_lock_irqsave(&tp->rx_lock, flags);
1887	list_add_tail(new: &agg->list, head: &tp->rx_done);
1888	spin_unlock_irqrestore(lock: &tp->rx_lock, flags);
1889	set_bit(nr: RX_EPROTO, addr: &tp->flags);
1890	schedule_delayed_work(dwork: &tp->schedule, delay: 1);
1891	return;
1892	case -ENOENT:
1893	return; /* the urb is in unlink state */
1894	case -ETIME:
1895	if (net_ratelimit())
1896	netdev_warn(dev: netdev, format: "maybe reset is needed?\n");
1897	break;
1898	default:
1899	if (net_ratelimit())
1900	netdev_warn(dev: netdev, format: "Rx status %d\n", status);
1901	break;
1902	}
1903
1904	r8152_submit_rx(tp, agg, GFP_ATOMIC);
1905	}
1906
1907	static void write_bulk_callback(struct urb *urb)
1908	{
1909	struct net_device_stats *stats;
1910	struct net_device *netdev;
1911	struct tx_agg *agg;
1912	struct r8152 *tp;
1913	unsigned long flags;
1914	int status = urb->status;
1915
1916	agg = urb->context;
1917	if (!agg)
1918	return;
1919
1920	tp = agg->context;
1921	if (!tp)
1922	return;
1923
1924	netdev = tp->netdev;
1925	stats = &netdev->stats;
1926	if (status) {
1927	if (net_ratelimit())
1928	netdev_warn(dev: netdev, format: "Tx status %d\n", status);
1929	stats->tx_errors += agg->skb_num;
1930	} else {
1931	stats->tx_packets += agg->skb_num;
1932	stats->tx_bytes += agg->skb_len;
1933	}
1934
1935	spin_lock_irqsave(&tp->tx_lock, flags);
1936	list_add_tail(new: &agg->list, head: &tp->tx_free);
1937	spin_unlock_irqrestore(lock: &tp->tx_lock, flags);
1938
1939	usb_autopm_put_interface_async(intf: tp->intf);
1940
1941	if (!netif_carrier_ok(dev: netdev))
1942	return;
1943
1944	if (!test_bit(WORK_ENABLE, &tp->flags))
1945	return;
1946
1947	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
1948	return;
1949
1950	if (!skb_queue_empty(list: &tp->tx_queue))
1951	tasklet_schedule(t: &tp->tx_tl);
1952	}
1953
1954	static void intr_callback(struct urb *urb)
1955	{
1956	struct r8152 *tp;
1957	__le16 *d;
1958	int status = urb->status;
1959	int res;
1960
1961	tp = urb->context;
1962	if (!tp)
1963	return;
1964
1965	if (!test_bit(WORK_ENABLE, &tp->flags))
1966	return;
1967
1968	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
1969	return;
1970
1971	switch (status) {
1972	case 0: /* success */
1973	break;
1974	case -ECONNRESET: /* unlink */
1975	case -ESHUTDOWN:
1976	netif_device_detach(dev: tp->netdev);
1977	fallthrough;
1978	case -ENOENT:
1979	case -EPROTO:
1980	netif_info(tp, intr, tp->netdev,
1981	"Stop submitting intr, status %d\n", status);
1982	return;
1983	case -EOVERFLOW:
1984	if (net_ratelimit())
1985	netif_info(tp, intr, tp->netdev,
1986	"intr status -EOVERFLOW\n");
1987	goto resubmit;
1988	/* -EPIPE: should clear the halt */
1989	default:
1990	netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1991	goto resubmit;
1992	}
1993
1994	d = urb->transfer_buffer;
1995	if (INTR_LINK & __le16_to_cpu(d[0])) {
1996	if (!netif_carrier_ok(dev: tp->netdev)) {
1997	set_bit(nr: RTL8152_LINK_CHG, addr: &tp->flags);
1998	schedule_delayed_work(dwork: &tp->schedule, delay: 0);
1999	}
2000	} else {
2001	if (netif_carrier_ok(dev: tp->netdev)) {
2002	netif_stop_queue(dev: tp->netdev);
2003	set_bit(nr: RTL8152_LINK_CHG, addr: &tp->flags);
2004	schedule_delayed_work(dwork: &tp->schedule, delay: 0);
2005	}
2006	}
2007
2008	resubmit:
2009	res = usb_submit_urb(urb, GFP_ATOMIC);
2010	if (res == -ENODEV) {
2011	rtl_set_unplug(tp);
2012	netif_device_detach(dev: tp->netdev);
2013	} else if (res) {
2014	netif_err(tp, intr, tp->netdev,
2015	"can't resubmit intr, status %d\n", res);
2016	}
2017	}
2018
2019	static inline void *rx_agg_align(void *data)
2020	{
2021	return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
2022	}
2023
2024	static inline void *tx_agg_align(void *data)
2025	{
2026	return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
2027	}
2028
2029	static void free_rx_agg(struct r8152 *tp, struct rx_agg *agg)
2030	{
2031	list_del(entry: &agg->info_list);
2032
2033	usb_free_urb(urb: agg->urb);
2034	put_page(page: agg->page);
2035	kfree(objp: agg);
2036
2037	atomic_dec(v: &tp->rx_count);
2038	}
2039
2040	static struct rx_agg *alloc_rx_agg(struct r8152 *tp, gfp_t mflags)
2041	{
2042	struct net_device *netdev = tp->netdev;
2043	int node = netdev->dev.parent ? dev_to_node(dev: netdev->dev.parent) : -1;
2044	unsigned int order = get_order(size: tp->rx_buf_sz);
2045	struct rx_agg *rx_agg;
2046	unsigned long flags;
2047
2048	rx_agg = kmalloc_node(size: sizeof(*rx_agg), flags: mflags, node);
2049	if (!rx_agg)
2050	return NULL;
2051
2052	rx_agg->page = alloc_pages(gfp: mflags | __GFP_COMP | __GFP_NOWARN, order);
2053	if (!rx_agg->page)
2054	goto free_rx;
2055
2056	rx_agg->buffer = page_address(rx_agg->page);
2057
2058	rx_agg->urb = usb_alloc_urb(iso_packets: 0, mem_flags: mflags);
2059	if (!rx_agg->urb)
2060	goto free_buf;
2061
2062	rx_agg->context = tp;
2063
2064	INIT_LIST_HEAD(list: &rx_agg->list);
2065	INIT_LIST_HEAD(list: &rx_agg->info_list);
2066	spin_lock_irqsave(&tp->rx_lock, flags);
2067	list_add_tail(new: &rx_agg->info_list, head: &tp->rx_info);
2068	spin_unlock_irqrestore(lock: &tp->rx_lock, flags);
2069
2070	atomic_inc(v: &tp->rx_count);
2071
2072	return rx_agg;
2073
2074	free_buf:
2075	__free_pages(page: rx_agg->page, order);
2076	free_rx:
2077	kfree(objp: rx_agg);
2078	return NULL;
2079	}
2080
2081	static void free_all_mem(struct r8152 *tp)
2082	{
2083	struct rx_agg *agg, *agg_next;
2084	unsigned long flags;
2085	int i;
2086
2087	spin_lock_irqsave(&tp->rx_lock, flags);
2088
2089	list_for_each_entry_safe(agg, agg_next, &tp->rx_info, info_list)
2090	free_rx_agg(tp, agg);
2091
2092	spin_unlock_irqrestore(lock: &tp->rx_lock, flags);
2093
2094	WARN_ON(atomic_read(&tp->rx_count));
2095
2096	for (i = 0; i < RTL8152_MAX_TX; i++) {
2097	usb_free_urb(urb: tp->tx_info[i].urb);
2098	tp->tx_info[i].urb = NULL;
2099
2100	kfree(objp: tp->tx_info[i].buffer);
2101	tp->tx_info[i].buffer = NULL;
2102	tp->tx_info[i].head = NULL;
2103	}
2104
2105	usb_free_urb(urb: tp->intr_urb);
2106	tp->intr_urb = NULL;
2107
2108	kfree(objp: tp->intr_buff);
2109	tp->intr_buff = NULL;
2110	}
2111
2112	static int alloc_all_mem(struct r8152 *tp)
2113	{
2114	struct net_device *netdev = tp->netdev;
2115	struct usb_interface *intf = tp->intf;
2116	struct usb_host_interface *alt = intf->cur_altsetting;
2117	struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
2118	int node, i;
2119
2120	node = netdev->dev.parent ? dev_to_node(dev: netdev->dev.parent) : -1;
2121
2122	spin_lock_init(&tp->rx_lock);
2123	spin_lock_init(&tp->tx_lock);
2124	INIT_LIST_HEAD(list: &tp->rx_info);
2125	INIT_LIST_HEAD(list: &tp->tx_free);
2126	INIT_LIST_HEAD(list: &tp->rx_done);
2127	skb_queue_head_init(list: &tp->tx_queue);
2128	skb_queue_head_init(list: &tp->rx_queue);
2129	atomic_set(v: &tp->rx_count, i: 0);
2130
2131	for (i = 0; i < RTL8152_MAX_RX; i++) {
2132	if (!alloc_rx_agg(tp, GFP_KERNEL))
2133	goto err1;
2134	}
2135
2136	for (i = 0; i < RTL8152_MAX_TX; i++) {
2137	struct urb *urb;
2138	u8 *buf;
2139
2140	buf = kmalloc_node(size: agg_buf_sz, GFP_KERNEL, node);
2141	if (!buf)
2142	goto err1;
2143
2144	if (buf != tx_agg_align(data: buf)) {
2145	kfree(objp: buf);
2146	buf = kmalloc_node(size: agg_buf_sz + TX_ALIGN, GFP_KERNEL,
2147	node);
2148	if (!buf)
2149	goto err1;
2150	}
2151
2152	urb = usb_alloc_urb(iso_packets: 0, GFP_KERNEL);
2153	if (!urb) {
2154	kfree(objp: buf);
2155	goto err1;
2156	}
2157
2158	INIT_LIST_HEAD(list: &tp->tx_info[i].list);
2159	tp->tx_info[i].context = tp;
2160	tp->tx_info[i].urb = urb;
2161	tp->tx_info[i].buffer = buf;
2162	tp->tx_info[i].head = tx_agg_align(data: buf);
2163
2164	list_add_tail(new: &tp->tx_info[i].list, head: &tp->tx_free);
2165	}
2166
2167	tp->intr_urb = usb_alloc_urb(iso_packets: 0, GFP_KERNEL);
2168	if (!tp->intr_urb)
2169	goto err1;
2170
2171	tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
2172	if (!tp->intr_buff)
2173	goto err1;
2174
2175	tp->intr_interval = (int)ep_intr->desc.bInterval;
2176	usb_fill_int_urb(urb: tp->intr_urb, dev: tp->udev, pipe: tp->pipe_intr,
2177	transfer_buffer: tp->intr_buff, INTBUFSIZE, complete_fn: intr_callback,
2178	context: tp, interval: tp->intr_interval);
2179
2180	return 0;
2181
2182	err1:
2183	free_all_mem(tp);
2184	return -ENOMEM;
2185	}
2186
2187	static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
2188	{
2189	struct tx_agg *agg = NULL;
2190	unsigned long flags;
2191
2192	if (list_empty(head: &tp->tx_free))
2193	return NULL;
2194
2195	spin_lock_irqsave(&tp->tx_lock, flags);
2196	if (!list_empty(head: &tp->tx_free)) {
2197	struct list_head *cursor;
2198
2199	cursor = tp->tx_free.next;
2200	list_del_init(entry: cursor);
2201	agg = list_entry(cursor, struct tx_agg, list);
2202	}
2203	spin_unlock_irqrestore(lock: &tp->tx_lock, flags);
2204
2205	return agg;
2206	}
2207
2208	/* r8152_csum_workaround()
2209	* The hw limits the value of the transport offset. When the offset is out of
2210	* range, calculate the checksum by sw.
2211	*/
2212	static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
2213	struct sk_buff_head *list)
2214	{
2215	if (skb_shinfo(skb)->gso_size) {
2216	netdev_features_t features = tp->netdev->features;
2217	struct sk_buff *segs, *seg, *next;
2218	struct sk_buff_head seg_list;
2219
2220	features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
2221	segs = skb_gso_segment(skb, features);
2222	if (IS_ERR(ptr: segs) || !segs)
2223	goto drop;
2224
2225	__skb_queue_head_init(list: &seg_list);
2226
2227	skb_list_walk_safe(segs, seg, next) {
2228	skb_mark_not_on_list(skb: seg);
2229	__skb_queue_tail(list: &seg_list, newsk: seg);
2230	}
2231
2232	skb_queue_splice(list: &seg_list, head: list);
2233	dev_kfree_skb(skb);
2234	} else if (skb->ip_summed == CHECKSUM_PARTIAL) {
2235	if (skb_checksum_help(skb) < 0)
2236	goto drop;
2237
2238	__skb_queue_head(list, newsk: skb);
2239	} else {
2240	struct net_device_stats *stats;
2241
2242	drop:
2243	stats = &tp->netdev->stats;
2244	stats->tx_dropped++;
2245	dev_kfree_skb(skb);
2246	}
2247	}
2248
2249	static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
2250	{
2251	if (skb_vlan_tag_present(skb)) {
2252	u32 opts2;
2253
2254	opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
2255	desc->opts2 |= cpu_to_le32(opts2);
2256	}
2257	}
2258
2259	static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
2260	{
2261	u32 opts2 = le32_to_cpu(desc->opts2);
2262
2263	if (opts2 & RX_VLAN_TAG)
2264	__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
2265	swab16(opts2 & 0xffff));
2266	}
2267
2268	static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
2269	struct sk_buff *skb, u32 len)
2270	{
2271	u32 mss = skb_shinfo(skb)->gso_size;
2272	u32 opts1, opts2 = 0;
2273	int ret = TX_CSUM_SUCCESS;
2274
2275	WARN_ON_ONCE(len > TX_LEN_MAX);
2276
2277	opts1 = len | TX_FS | TX_LS;
2278
2279	if (mss) {
2280	u32 transport_offset = (u32)skb_transport_offset(skb);
2281
2282	if (transport_offset > GTTCPHO_MAX) {
2283	netif_warn(tp, tx_err, tp->netdev,
2284	"Invalid transport offset 0x%x for TSO\n",
2285	transport_offset);
2286	ret = TX_CSUM_TSO;
2287	goto unavailable;
2288	}
2289
2290	switch (vlan_get_protocol(skb)) {
2291	case htons(ETH_P_IP):
2292	opts1 |= GTSENDV4;
2293	break;
2294
2295	case htons(ETH_P_IPV6):
2296	if (skb_cow_head(skb, headroom: 0)) {
2297	ret = TX_CSUM_TSO;
2298	goto unavailable;
2299	}
2300	tcp_v6_gso_csum_prep(skb);
2301	opts1 |= GTSENDV6;
2302	break;
2303
2304	default:
2305	WARN_ON_ONCE(1);
2306	break;
2307	}
2308
2309	opts1 |= transport_offset << GTTCPHO_SHIFT;
2310	opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
2311	} else if (skb->ip_summed == CHECKSUM_PARTIAL) {
2312	u32 transport_offset = (u32)skb_transport_offset(skb);
2313	u8 ip_protocol;
2314
2315	if (transport_offset > TCPHO_MAX) {
2316	netif_warn(tp, tx_err, tp->netdev,
2317	"Invalid transport offset 0x%x\n",
2318	transport_offset);
2319	ret = TX_CSUM_NONE;
2320	goto unavailable;
2321	}
2322
2323	switch (vlan_get_protocol(skb)) {
2324	case htons(ETH_P_IP):
2325	opts2 |= IPV4_CS;
2326	ip_protocol = ip_hdr(skb)->protocol;
2327	break;
2328
2329	case htons(ETH_P_IPV6):
2330	opts2 |= IPV6_CS;
2331	ip_protocol = ipv6_hdr(skb)->nexthdr;
2332	break;
2333
2334	default:
2335	ip_protocol = IPPROTO_RAW;
2336	break;
2337	}
2338
2339	if (ip_protocol == IPPROTO_TCP)
2340	opts2 |= TCP_CS;
2341	else if (ip_protocol == IPPROTO_UDP)
2342	opts2 |= UDP_CS;
2343	else
2344	WARN_ON_ONCE(1);
2345
2346	opts2 |= transport_offset << TCPHO_SHIFT;
2347	}
2348
2349	desc->opts2 = cpu_to_le32(opts2);
2350	desc->opts1 = cpu_to_le32(opts1);
2351
2352	unavailable:
2353	return ret;
2354	}
2355
2356	static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
2357	{
2358	struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2359	int remain, ret;
2360	u8 *tx_data;
2361
2362	__skb_queue_head_init(list: &skb_head);
2363	spin_lock(lock: &tx_queue->lock);
2364	skb_queue_splice_init(list: tx_queue, head: &skb_head);
2365	spin_unlock(lock: &tx_queue->lock);
2366
2367	tx_data = agg->head;
2368	agg->skb_num = 0;
2369	agg->skb_len = 0;
2370	remain = agg_buf_sz;
2371
2372	while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
2373	struct tx_desc *tx_desc;
2374	struct sk_buff *skb;
2375	unsigned int len;
2376
2377	skb = __skb_dequeue(list: &skb_head);
2378	if (!skb)
2379	break;
2380
2381	len = skb->len + sizeof(*tx_desc);
2382
2383	if (len > remain) {
2384	__skb_queue_head(list: &skb_head, newsk: skb);
2385	break;
2386	}
2387
2388	tx_data = tx_agg_align(data: tx_data);
2389	tx_desc = (struct tx_desc *)tx_data;
2390
2391	if (r8152_tx_csum(tp, desc: tx_desc, skb, len: skb->len)) {
2392	r8152_csum_workaround(tp, skb, list: &skb_head);
2393	continue;
2394	}
2395
2396	rtl_tx_vlan_tag(desc: tx_desc, skb);
2397
2398	tx_data += sizeof(*tx_desc);
2399
2400	len = skb->len;
2401	if (skb_copy_bits(skb, offset: 0, to: tx_data, len) < 0) {
2402	struct net_device_stats *stats = &tp->netdev->stats;
2403
2404	stats->tx_dropped++;
2405	dev_kfree_skb_any(skb);
2406	tx_data -= sizeof(*tx_desc);
2407	continue;
2408	}
2409
2410	tx_data += len;
2411	agg->skb_len += len;
2412	agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1;
2413
2414	dev_kfree_skb_any(skb);
2415
2416	remain = agg_buf_sz - (int)(tx_agg_align(data: tx_data) - agg->head);
2417
2418	if (tp->dell_tb_rx_agg_bug)
2419	break;
2420	}
2421
2422	if (!skb_queue_empty(list: &skb_head)) {
2423	spin_lock(lock: &tx_queue->lock);
2424	skb_queue_splice(list: &skb_head, head: tx_queue);
2425	spin_unlock(lock: &tx_queue->lock);
2426	}
2427
2428	netif_tx_lock(dev: tp->netdev);
2429
2430	if (netif_queue_stopped(dev: tp->netdev) &&
2431	skb_queue_len(list_: &tp->tx_queue) < tp->tx_qlen)
2432	netif_wake_queue(dev: tp->netdev);
2433
2434	netif_tx_unlock(dev: tp->netdev);
2435
2436	ret = usb_autopm_get_interface_async(intf: tp->intf);
2437	if (ret < 0)
2438	goto out_tx_fill;
2439
2440	usb_fill_bulk_urb(urb: agg->urb, dev: tp->udev, pipe: tp->pipe_out,
2441	transfer_buffer: agg->head, buffer_length: (int)(tx_data - (u8 *)agg->head),
2442	complete_fn: (usb_complete_t)write_bulk_callback, context: agg);
2443
2444	ret = usb_submit_urb(urb: agg->urb, GFP_ATOMIC);
2445	if (ret < 0)
2446	usb_autopm_put_interface_async(intf: tp->intf);
2447
2448	out_tx_fill:
2449	return ret;
2450	}
2451
2452	static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
2453	{
2454	u8 checksum = CHECKSUM_NONE;
2455	u32 opts2, opts3;
2456
2457	if (!(tp->netdev->features & NETIF_F_RXCSUM))
2458	goto return_result;
2459
2460	opts2 = le32_to_cpu(rx_desc->opts2);
2461	opts3 = le32_to_cpu(rx_desc->opts3);
2462
2463	if (opts2 & RD_IPV4_CS) {
2464	if (opts3 & IPF)
2465	checksum = CHECKSUM_NONE;
2466	else if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
2467	checksum = CHECKSUM_UNNECESSARY;
2468	else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
2469	checksum = CHECKSUM_UNNECESSARY;
2470	} else if (opts2 & RD_IPV6_CS) {
2471	if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
2472	checksum = CHECKSUM_UNNECESSARY;
2473	else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
2474	checksum = CHECKSUM_UNNECESSARY;
2475	}
2476
2477	return_result:
2478	return checksum;
2479	}
2480
2481	static inline bool rx_count_exceed(struct r8152 *tp)
2482	{
2483	return atomic_read(v: &tp->rx_count) > RTL8152_MAX_RX;
2484	}
2485
2486	static inline int agg_offset(struct rx_agg *agg, void *addr)
2487	{
2488	return (int)(addr - agg->buffer);
2489	}
2490
2491	static struct rx_agg *rtl_get_free_rx(struct r8152 *tp, gfp_t mflags)
2492	{
2493	struct rx_agg *agg, *agg_next, *agg_free = NULL;
2494	unsigned long flags;
2495
2496	spin_lock_irqsave(&tp->rx_lock, flags);
2497
2498	list_for_each_entry_safe(agg, agg_next, &tp->rx_used, list) {
2499	if (page_count(page: agg->page) == 1) {
2500	if (!agg_free) {
2501	list_del_init(entry: &agg->list);
2502	agg_free = agg;
2503	continue;
2504	}
2505	if (rx_count_exceed(tp)) {
2506	list_del_init(entry: &agg->list);
2507	free_rx_agg(tp, agg);
2508	}
2509	break;
2510	}
2511	}
2512
2513	spin_unlock_irqrestore(lock: &tp->rx_lock, flags);
2514
2515	if (!agg_free && atomic_read(v: &tp->rx_count) < tp->rx_pending)
2516	agg_free = alloc_rx_agg(tp, mflags);
2517
2518	return agg_free;
2519	}
2520
2521	static int rx_bottom(struct r8152 *tp, int budget)
2522	{
2523	unsigned long flags;
2524	struct list_head *cursor, *next, rx_queue;
2525	int ret = 0, work_done = 0;
2526	struct napi_struct *napi = &tp->napi;
2527
2528	if (!skb_queue_empty(list: &tp->rx_queue)) {
2529	while (work_done < budget) {
2530	struct sk_buff *skb = __skb_dequeue(list: &tp->rx_queue);
2531	struct net_device *netdev = tp->netdev;
2532	struct net_device_stats *stats = &netdev->stats;
2533	unsigned int pkt_len;
2534
2535	if (!skb)
2536	break;
2537
2538	pkt_len = skb->len;
2539	napi_gro_receive(napi, skb);
2540	work_done++;
2541	stats->rx_packets++;
2542	stats->rx_bytes += pkt_len;
2543	}
2544	}
2545
2546	if (list_empty(head: &tp->rx_done) || work_done >= budget)
2547	goto out1;
2548
2549	clear_bit(nr: RX_EPROTO, addr: &tp->flags);
2550	INIT_LIST_HEAD(list: &rx_queue);
2551	spin_lock_irqsave(&tp->rx_lock, flags);
2552	list_splice_init(list: &tp->rx_done, head: &rx_queue);
2553	spin_unlock_irqrestore(lock: &tp->rx_lock, flags);
2554
2555	list_for_each_safe(cursor, next, &rx_queue) {
2556	struct rx_desc *rx_desc;
2557	struct rx_agg *agg, *agg_free;
2558	int len_used = 0;
2559	struct urb *urb;
2560	u8 *rx_data;
2561
2562	/* A bulk transfer of USB may contain may packets, so the
2563	* total packets may more than the budget. Deal with all
2564	* packets in current bulk transfer, and stop to handle the
2565	* next bulk transfer until next schedule, if budget is
2566	* exhausted.
2567	*/
2568	if (work_done >= budget)
2569	break;
2570
2571	list_del_init(entry: cursor);
2572
2573	agg = list_entry(cursor, struct rx_agg, list);
2574	urb = agg->urb;
2575	if (urb->status != 0 || urb->actual_length < ETH_ZLEN)
2576	goto submit;
2577
2578	agg_free = rtl_get_free_rx(tp, GFP_ATOMIC);
2579
2580	rx_desc = agg->buffer;
2581	rx_data = agg->buffer;
2582	len_used += sizeof(struct rx_desc);
2583
2584	while (urb->actual_length > len_used) {
2585	struct net_device *netdev = tp->netdev;
2586	struct net_device_stats *stats = &netdev->stats;
2587	unsigned int pkt_len, rx_frag_head_sz, len;
2588	struct sk_buff *skb;
2589	bool use_frags;
2590
2591	WARN_ON_ONCE(skb_queue_len(&tp->rx_queue) >= 1000);
2592
2593	pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
2594	if (pkt_len < ETH_ZLEN)
2595	break;
2596
2597	len_used += pkt_len;
2598	if (urb->actual_length < len_used)
2599	break;
2600
2601	pkt_len -= ETH_FCS_LEN;
2602	len = pkt_len;
2603	rx_data += sizeof(struct rx_desc);
2604
2605	if (!agg_free || tp->rx_copybreak > len)
2606	use_frags = false;
2607	else
2608	use_frags = true;
2609
2610	if (use_frags) {
2611	/* If the budget is exhausted, the packet
2612	* would be queued in the driver. That is,
2613	* napi_gro_frags() wouldn't be called, so
2614	* we couldn't use napi_get_frags().
2615	*/
2616	if (work_done >= budget) {
2617	rx_frag_head_sz = tp->rx_copybreak;
2618	skb = napi_alloc_skb(napi,
2619	length: rx_frag_head_sz);
2620	} else {
2621	rx_frag_head_sz = 0;
2622	skb = napi_get_frags(napi);
2623	}
2624	} else {
2625	rx_frag_head_sz = 0;
2626	skb = napi_alloc_skb(napi, length: len);
2627	}
2628
2629	if (!skb) {
2630	stats->rx_dropped++;
2631	goto find_next_rx;
2632	}
2633
2634	skb->ip_summed = r8152_rx_csum(tp, rx_desc);
2635	rtl_rx_vlan_tag(desc: rx_desc, skb);
2636
2637	if (use_frags) {
2638	if (rx_frag_head_sz) {
2639	memcpy(skb->data, rx_data,
2640	rx_frag_head_sz);
2641	skb_put(skb, len: rx_frag_head_sz);
2642	len -= rx_frag_head_sz;
2643	rx_data += rx_frag_head_sz;
2644	skb->protocol = eth_type_trans(skb,
2645	dev: netdev);
2646	}
2647
2648	skb_add_rx_frag(skb, i: 0, page: agg->page,
2649	off: agg_offset(agg, addr: rx_data),
2650	size: len, SKB_DATA_ALIGN(len));
2651	get_page(page: agg->page);
2652	} else {
2653	memcpy(skb->data, rx_data, len);
2654	skb_put(skb, len);
2655	skb->protocol = eth_type_trans(skb, dev: netdev);
2656	}
2657
2658	if (work_done < budget) {
2659	if (use_frags)
2660	napi_gro_frags(napi);
2661	else
2662	napi_gro_receive(napi, skb);
2663
2664	work_done++;
2665	stats->rx_packets++;
2666	stats->rx_bytes += pkt_len;
2667	} else {
2668	__skb_queue_tail(list: &tp->rx_queue, newsk: skb);
2669	}
2670
2671	find_next_rx:
2672	rx_data = rx_agg_align(data: rx_data + len + ETH_FCS_LEN);
2673	rx_desc = (struct rx_desc *)rx_data;
2674	len_used = agg_offset(agg, addr: rx_data);
2675	len_used += sizeof(struct rx_desc);
2676	}
2677
2678	WARN_ON(!agg_free && page_count(agg->page) > 1);
2679
2680	if (agg_free) {
2681	spin_lock_irqsave(&tp->rx_lock, flags);
2682	if (page_count(page: agg->page) == 1) {
2683	list_add(new: &agg_free->list, head: &tp->rx_used);
2684	} else {
2685	list_add_tail(new: &agg->list, head: &tp->rx_used);
2686	agg = agg_free;
2687	urb = agg->urb;
2688	}
2689	spin_unlock_irqrestore(lock: &tp->rx_lock, flags);
2690	}
2691
2692	submit:
2693	if (!ret) {
2694	ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
2695	} else {
2696	urb->actual_length = 0;
2697	list_add_tail(new: &agg->list, head: next);
2698	}
2699	}
2700
2701	/* Splice the remained list back to rx_done for next schedule */
2702	if (!list_empty(head: &rx_queue)) {
2703	spin_lock_irqsave(&tp->rx_lock, flags);
2704	list_splice(list: &rx_queue, head: &tp->rx_done);
2705	spin_unlock_irqrestore(lock: &tp->rx_lock, flags);
2706	}
2707
2708	out1:
2709	return work_done;
2710	}
2711
2712	static void tx_bottom(struct r8152 *tp)
2713	{
2714	int res;
2715
2716	do {
2717	struct net_device *netdev = tp->netdev;
2718	struct tx_agg *agg;
2719
2720	if (skb_queue_empty(list: &tp->tx_queue))
2721	break;
2722
2723	agg = r8152_get_tx_agg(tp);
2724	if (!agg)
2725	break;
2726
2727	res = r8152_tx_agg_fill(tp, agg);
2728	if (!res)
2729	continue;
2730
2731	if (res == -ENODEV) {
2732	rtl_set_unplug(tp);
2733	netif_device_detach(dev: netdev);
2734	} else {
2735	struct net_device_stats *stats = &netdev->stats;
2736	unsigned long flags;
2737
2738	netif_warn(tp, tx_err, netdev,
2739	"failed tx_urb %d\n", res);
2740	stats->tx_dropped += agg->skb_num;
2741
2742	spin_lock_irqsave(&tp->tx_lock, flags);
2743	list_add_tail(new: &agg->list, head: &tp->tx_free);
2744	spin_unlock_irqrestore(lock: &tp->tx_lock, flags);
2745	}
2746	} while (res == 0);
2747	}
2748
2749	static void bottom_half(struct tasklet_struct *t)
2750	{
2751	struct r8152 *tp = from_tasklet(tp, t, tx_tl);
2752
2753	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
2754	return;
2755
2756	if (!test_bit(WORK_ENABLE, &tp->flags))
2757	return;
2758
2759	/* When link down, the driver would cancel all bulks. */
2760	/* This avoid the re-submitting bulk */
2761	if (!netif_carrier_ok(dev: tp->netdev))
2762	return;
2763
2764	clear_bit(nr: SCHEDULE_TASKLET, addr: &tp->flags);
2765
2766	tx_bottom(tp);
2767	}
2768
2769	static int r8152_poll(struct napi_struct *napi, int budget)
2770	{
2771	struct r8152 *tp = container_of(napi, struct r8152, napi);
2772	int work_done;
2773
2774	if (!budget)
2775	return 0;
2776
2777	work_done = rx_bottom(tp, budget);
2778
2779	if (work_done < budget) {
2780	if (!napi_complete_done(n: napi, work_done))
2781	goto out;
2782	if (!list_empty(head: &tp->rx_done))
2783	napi_schedule(n: napi);
2784	}
2785
2786	out:
2787	return work_done;
2788	}
2789
2790	static
2791	int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
2792	{
2793	int ret;
2794
2795	/* The rx would be stopped, so skip submitting */
2796	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags) ||
2797	!test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(dev: tp->netdev))
2798	return 0;
2799
2800	usb_fill_bulk_urb(urb: agg->urb, dev: tp->udev, pipe: tp->pipe_in,
2801	transfer_buffer: agg->buffer, buffer_length: tp->rx_buf_sz,
2802	complete_fn: (usb_complete_t)read_bulk_callback, context: agg);
2803
2804	ret = usb_submit_urb(urb: agg->urb, mem_flags);
2805	if (ret == -ENODEV) {
2806	rtl_set_unplug(tp);
2807	netif_device_detach(dev: tp->netdev);
2808	} else if (ret) {
2809	struct urb *urb = agg->urb;
2810	unsigned long flags;
2811
2812	urb->actual_length = 0;
2813	spin_lock_irqsave(&tp->rx_lock, flags);
2814	list_add_tail(new: &agg->list, head: &tp->rx_done);
2815	spin_unlock_irqrestore(lock: &tp->rx_lock, flags);
2816
2817	netif_err(tp, rx_err, tp->netdev,
2818	"Couldn't submit rx[%p], ret = %d\n", agg, ret);
2819
2820	napi_schedule(n: &tp->napi);
2821	}
2822
2823	return ret;
2824	}
2825
2826	static void rtl_drop_queued_tx(struct r8152 *tp)
2827	{
2828	struct net_device_stats *stats = &tp->netdev->stats;
2829	struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2830	struct sk_buff *skb;
2831
2832	if (skb_queue_empty(list: tx_queue))
2833	return;
2834
2835	__skb_queue_head_init(list: &skb_head);
2836	spin_lock_bh(lock: &tx_queue->lock);
2837	skb_queue_splice_init(list: tx_queue, head: &skb_head);
2838	spin_unlock_bh(lock: &tx_queue->lock);
2839
2840	while ((skb = __skb_dequeue(list: &skb_head))) {
2841	dev_kfree_skb(skb);
2842	stats->tx_dropped++;
2843	}
2844	}
2845
2846	static void rtl8152_tx_timeout(struct net_device *netdev, unsigned int txqueue)
2847	{
2848	struct r8152 *tp = netdev_priv(dev: netdev);
2849
2850	netif_warn(tp, tx_err, netdev, "Tx timeout\n");
2851
2852	usb_queue_reset_device(dev: tp->intf);
2853	}
2854
2855	static void rtl8152_set_rx_mode(struct net_device *netdev)
2856	{
2857	struct r8152 *tp = netdev_priv(dev: netdev);
2858
2859	if (netif_carrier_ok(dev: netdev)) {
2860	set_bit(nr: RTL8152_SET_RX_MODE, addr: &tp->flags);
2861	schedule_delayed_work(dwork: &tp->schedule, delay: 0);
2862	}
2863	}
2864
2865	static void _rtl8152_set_rx_mode(struct net_device *netdev)
2866	{
2867	struct r8152 *tp = netdev_priv(dev: netdev);
2868	u32 mc_filter[2]; /* Multicast hash filter */
2869	__le32 tmp[2];
2870	u32 ocp_data;
2871
2872	netif_stop_queue(dev: netdev);
2873	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2874	ocp_data &= ~RCR_ACPT_ALL;
2875	ocp_data |= RCR_AB | RCR_APM;
2876
2877	if (netdev->flags & IFF_PROMISC) {
2878	/* Unconditionally log net taps. */
2879	netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
2880	ocp_data |= RCR_AM | RCR_AAP;
2881	mc_filter[1] = 0xffffffff;
2882	mc_filter[0] = 0xffffffff;
2883	} else if ((netdev->flags & IFF_MULTICAST &&
2884	netdev_mc_count(netdev) > multicast_filter_limit) ||
2885	(netdev->flags & IFF_ALLMULTI)) {
2886	/* Too many to filter perfectly -- accept all multicasts. */
2887	ocp_data |= RCR_AM;
2888	mc_filter[1] = 0xffffffff;
2889	mc_filter[0] = 0xffffffff;
2890	} else {
2891	mc_filter[1] = 0;
2892	mc_filter[0] = 0;
2893
2894	if (netdev->flags & IFF_MULTICAST) {
2895	struct netdev_hw_addr *ha;
2896
2897	netdev_for_each_mc_addr(ha, netdev) {
2898	int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2899
2900	mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2901	ocp_data |= RCR_AM;
2902	}
2903	}
2904	}
2905
2906	tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
2907	tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
2908
2909	pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, size: sizeof(tmp), data: tmp);
2910	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, data: ocp_data);
2911	netif_wake_queue(dev: netdev);
2912	}
2913
2914	static netdev_features_t
2915	rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
2916	netdev_features_t features)
2917	{
2918	u32 mss = skb_shinfo(skb)->gso_size;
2919	int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
2920
2921	if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) &&
2922	skb_transport_offset(skb) > max_offset)
2923	features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2924	else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
2925	features &= ~NETIF_F_GSO_MASK;
2926
2927	return features;
2928	}
2929
2930	static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
2931	struct net_device *netdev)
2932	{
2933	struct r8152 *tp = netdev_priv(dev: netdev);
2934
2935	skb_tx_timestamp(skb);
2936
2937	skb_queue_tail(list: &tp->tx_queue, newsk: skb);
2938
2939	if (!list_empty(head: &tp->tx_free)) {
2940	if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2941	set_bit(nr: SCHEDULE_TASKLET, addr: &tp->flags);
2942	schedule_delayed_work(dwork: &tp->schedule, delay: 0);
2943	} else {
2944	usb_mark_last_busy(udev: tp->udev);
2945	tasklet_schedule(t: &tp->tx_tl);
2946	}
2947	} else if (skb_queue_len(list_: &tp->tx_queue) > tp->tx_qlen) {
2948	netif_stop_queue(dev: netdev);
2949	}
2950
2951	return NETDEV_TX_OK;
2952	}
2953
2954	static void r8152b_reset_packet_filter(struct r8152 *tp)
2955	{
2956	u32 ocp_data;
2957
2958	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
2959	ocp_data &= ~FMC_FCR_MCU_EN;
2960	ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, data: ocp_data);
2961	ocp_data |= FMC_FCR_MCU_EN;
2962	ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, data: ocp_data);
2963	}
2964
2965	static void rtl8152_nic_reset(struct r8152 *tp)
2966	{
2967	u32 ocp_data;
2968	int i;
2969
2970	switch (tp->version) {
2971	case RTL_TEST_01:
2972	case RTL_VER_10:
2973	case RTL_VER_11:
2974	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2975	ocp_data &= ~CR_TE;
2976	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, data: ocp_data);
2977
2978	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET);
2979	ocp_data &= ~BMU_RESET_EP_IN;
2980	ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, data: ocp_data);
2981
2982	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2983	ocp_data |= CDC_ECM_EN;
2984	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, data: ocp_data);
2985
2986	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2987	ocp_data &= ~CR_RE;
2988	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, data: ocp_data);
2989
2990	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET);
2991	ocp_data |= BMU_RESET_EP_IN;
2992	ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, data: ocp_data);
2993
2994	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2995	ocp_data &= ~CDC_ECM_EN;
2996	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, data: ocp_data);
2997	break;
2998
2999	default:
3000	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
3001
3002	for (i = 0; i < 1000; i++) {
3003	if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
3004	break;
3005	usleep_range(min: 100, max: 400);
3006	}
3007	break;
3008	}
3009	}
3010
3011	static void set_tx_qlen(struct r8152 *tp)
3012	{
3013	tp->tx_qlen = agg_buf_sz / (mtu_to_size(tp->netdev->mtu) + sizeof(struct tx_desc));
3014	}
3015
3016	static inline u16 rtl8152_get_speed(struct r8152 *tp)
3017	{
3018	return ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
3019	}
3020
3021	static void rtl_eee_plus_en(struct r8152 *tp, bool enable)
3022	{
3023	u32 ocp_data;
3024
3025	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
3026	if (enable)
3027	ocp_data |= EEEP_CR_EEEP_TX;
3028	else
3029	ocp_data &= ~EEEP_CR_EEEP_TX;
3030	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, data: ocp_data);
3031	}
3032
3033	static void rtl_set_eee_plus(struct r8152 *tp)
3034	{
3035	if (rtl8152_get_speed(tp) & _10bps)
3036	rtl_eee_plus_en(tp, enable: true);
3037	else
3038	rtl_eee_plus_en(tp, enable: false);
3039	}
3040
3041	static void rxdy_gated_en(struct r8152 *tp, bool enable)
3042	{
3043	u32 ocp_data;
3044
3045	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
3046	if (enable)
3047	ocp_data |= RXDY_GATED_EN;
3048	else
3049	ocp_data &= ~RXDY_GATED_EN;
3050	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, data: ocp_data);
3051	}
3052
3053	static int rtl_start_rx(struct r8152 *tp)
3054	{
3055	struct rx_agg *agg, *agg_next;
3056	struct list_head tmp_list;
3057	unsigned long flags;
3058	int ret = 0, i = 0;
3059
3060	INIT_LIST_HEAD(list: &tmp_list);
3061
3062	spin_lock_irqsave(&tp->rx_lock, flags);
3063
3064	INIT_LIST_HEAD(list: &tp->rx_done);
3065	INIT_LIST_HEAD(list: &tp->rx_used);
3066
3067	list_splice_init(list: &tp->rx_info, head: &tmp_list);
3068
3069	spin_unlock_irqrestore(lock: &tp->rx_lock, flags);
3070
3071	list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
3072	INIT_LIST_HEAD(list: &agg->list);
3073
3074	/* Only RTL8152_MAX_RX rx_agg need to be submitted. */
3075	if (++i > RTL8152_MAX_RX) {
3076	spin_lock_irqsave(&tp->rx_lock, flags);
3077	list_add_tail(new: &agg->list, head: &tp->rx_used);
3078	spin_unlock_irqrestore(lock: &tp->rx_lock, flags);
3079	} else if (unlikely(ret < 0)) {
3080	spin_lock_irqsave(&tp->rx_lock, flags);
3081	list_add_tail(new: &agg->list, head: &tp->rx_done);
3082	spin_unlock_irqrestore(lock: &tp->rx_lock, flags);
3083	} else {
3084	ret = r8152_submit_rx(tp, agg, GFP_KERNEL);
3085	}
3086	}
3087
3088	spin_lock_irqsave(&tp->rx_lock, flags);
3089	WARN_ON(!list_empty(&tp->rx_info));
3090	list_splice(list: &tmp_list, head: &tp->rx_info);
3091	spin_unlock_irqrestore(lock: &tp->rx_lock, flags);
3092
3093	return ret;
3094	}
3095
3096	static int rtl_stop_rx(struct r8152 *tp)
3097	{
3098	struct rx_agg *agg, *agg_next;
3099	struct list_head tmp_list;
3100	unsigned long flags;
3101
3102	INIT_LIST_HEAD(list: &tmp_list);
3103
3104	/* The usb_kill_urb() couldn't be used in atomic.
3105	* Therefore, move the list of rx_info to a tmp one.
3106	* Then, list_for_each_entry_safe could be used without
3107	* spin lock.
3108	*/
3109
3110	spin_lock_irqsave(&tp->rx_lock, flags);
3111	list_splice_init(list: &tp->rx_info, head: &tmp_list);
3112	spin_unlock_irqrestore(lock: &tp->rx_lock, flags);
3113
3114	list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
3115	/* At least RTL8152_MAX_RX rx_agg have the page_count being
3116	* equal to 1, so the other ones could be freed safely.
3117	*/
3118	if (page_count(page: agg->page) > 1)
3119	free_rx_agg(tp, agg);
3120	else
3121	usb_kill_urb(urb: agg->urb);
3122	}
3123
3124	/* Move back the list of temp to the rx_info */
3125	spin_lock_irqsave(&tp->rx_lock, flags);
3126	WARN_ON(!list_empty(&tp->rx_info));
3127	list_splice(list: &tmp_list, head: &tp->rx_info);
3128	spin_unlock_irqrestore(lock: &tp->rx_lock, flags);
3129
3130	while (!skb_queue_empty(list: &tp->rx_queue))
3131	dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
3132
3133	return 0;
3134	}
3135
3136	static void rtl_set_ifg(struct r8152 *tp, u16 speed)
3137	{
3138	u32 ocp_data;
3139
3140	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
3141	ocp_data &= ~IFG_MASK;
3142	if ((speed & (_10bps | _100bps)) && !(speed & FULL_DUP)) {
3143	ocp_data |= IFG_144NS;
3144	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR1, data: ocp_data);
3145
3146	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
3147	ocp_data &= ~TX10MIDLE_EN;
3148	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, data: ocp_data);
3149	} else {
3150	ocp_data |= IFG_96NS;
3151	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR1, data: ocp_data);
3152
3153	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
3154	ocp_data |= TX10MIDLE_EN;
3155	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, data: ocp_data);
3156	}
3157	}
3158
3159	static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp)
3160	{
3161	ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN,
3162	OWN_UPDATE | OWN_CLEAR);
3163	}
3164
3165	static int rtl_enable(struct r8152 *tp)
3166	{
3167	u32 ocp_data;
3168
3169	r8152b_reset_packet_filter(tp);
3170
3171	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
3172	ocp_data |= CR_RE | CR_TE;
3173	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, data: ocp_data);
3174
3175	switch (tp->version) {
3176	case RTL_VER_01:
3177	case RTL_VER_02:
3178	case RTL_VER_03:
3179	case RTL_VER_04:
3180	case RTL_VER_05:
3181	case RTL_VER_06:
3182	case RTL_VER_07:
3183	break;
3184	default:
3185	r8153b_rx_agg_chg_indicate(tp);
3186	break;
3187	}
3188
3189	rxdy_gated_en(tp, enable: false);
3190
3191	return 0;
3192	}
3193
3194	static int rtl8152_enable(struct r8152 *tp)
3195	{
3196	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
3197	return -ENODEV;
3198
3199	set_tx_qlen(tp);
3200	rtl_set_eee_plus(tp);
3201
3202	return rtl_enable(tp);
3203	}
3204
3205	static void r8153_set_rx_early_timeout(struct r8152 *tp)
3206	{
3207	u32 ocp_data = tp->coalesce / 8;
3208
3209	switch (tp->version) {
3210	case RTL_VER_03:
3211	case RTL_VER_04:
3212	case RTL_VER_05:
3213	case RTL_VER_06:
3214	ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
3215	data: ocp_data);
3216	break;
3217
3218	case RTL_VER_08:
3219	case RTL_VER_09:
3220	case RTL_VER_14:
3221	/* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout
3222	* primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns.
3223	*/
3224	ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
3225	data: 128 / 8);
3226	ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
3227	data: ocp_data);
3228	break;
3229
3230	case RTL_VER_10:
3231	case RTL_VER_11:
3232	case RTL_VER_12:
3233	case RTL_VER_13:
3234	case RTL_VER_15:
3235	ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
3236	data: 640 / 8);
3237	ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
3238	data: ocp_data);
3239	break;
3240
3241	default:
3242	break;
3243	}
3244	}
3245
3246	static void r8153_set_rx_early_size(struct r8152 *tp)
3247	{
3248	u32 ocp_data = tp->rx_buf_sz - rx_reserved_size(tp->netdev->mtu);
3249
3250	switch (tp->version) {
3251	case RTL_VER_03:
3252	case RTL_VER_04:
3253	case RTL_VER_05:
3254	case RTL_VER_06:
3255	ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
3256	data: ocp_data / 4);
3257	break;
3258	case RTL_VER_08:
3259	case RTL_VER_09:
3260	case RTL_VER_14:
3261	ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
3262	data: ocp_data / 8);
3263	break;
3264	case RTL_TEST_01:
3265	case RTL_VER_10:
3266	case RTL_VER_11:
3267	case RTL_VER_12:
3268	case RTL_VER_13:
3269	case RTL_VER_15:
3270	ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
3271	data: ocp_data / 8);
3272	break;
3273	default:
3274	WARN_ON_ONCE(1);
3275	break;
3276	}
3277	}
3278
3279	static int rtl8153_enable(struct r8152 *tp)
3280	{
3281	u32 ocp_data;
3282
3283	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
3284	return -ENODEV;
3285
3286	set_tx_qlen(tp);
3287	rtl_set_eee_plus(tp);
3288	r8153_set_rx_early_timeout(tp);
3289	r8153_set_rx_early_size(tp);
3290
3291	rtl_set_ifg(tp, speed: rtl8152_get_speed(tp));
3292
3293	switch (tp->version) {
3294	case RTL_VER_09:
3295	case RTL_VER_14:
3296	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
3297	ocp_data &= ~FC_PATCH_TASK;
3298	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, data: ocp_data);
3299	usleep_range(min: 1000, max: 2000);
3300	ocp_data |= FC_PATCH_TASK;
3301	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, data: ocp_data);
3302	break;
3303	default:
3304	break;
3305	}
3306
3307	return rtl_enable(tp);
3308	}
3309
3310	static void rtl_disable(struct r8152 *tp)
3311	{
3312	u32 ocp_data;
3313	int i;
3314
3315	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
3316	rtl_drop_queued_tx(tp);
3317	return;
3318	}
3319
3320	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3321	ocp_data &= ~RCR_ACPT_ALL;
3322	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, data: ocp_data);
3323
3324	rtl_drop_queued_tx(tp);
3325
3326	for (i = 0; i < RTL8152_MAX_TX; i++)
3327	usb_kill_urb(urb: tp->tx_info[i].urb);
3328
3329	rxdy_gated_en(tp, enable: true);
3330
3331	for (i = 0; i < 1000; i++) {
3332	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3333	if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
3334	break;
3335	usleep_range(min: 1000, max: 2000);
3336	}
3337
3338	for (i = 0; i < 1000; i++) {
3339	if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
3340	break;
3341	usleep_range(min: 1000, max: 2000);
3342	}
3343
3344	rtl_stop_rx(tp);
3345
3346	rtl8152_nic_reset(tp);
3347	}
3348
3349	static void r8152_power_cut_en(struct r8152 *tp, bool enable)
3350	{
3351	u32 ocp_data;
3352
3353	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
3354	if (enable)
3355	ocp_data |= POWER_CUT;
3356	else
3357	ocp_data &= ~POWER_CUT;
3358	ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, data: ocp_data);
3359
3360	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
3361	ocp_data &= ~RESUME_INDICATE;
3362	ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, data: ocp_data);
3363	}
3364
3365	static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
3366	{
3367	u32 ocp_data;
3368
3369	switch (tp->version) {
3370	case RTL_VER_01:
3371	case RTL_VER_02:
3372	case RTL_VER_03:
3373	case RTL_VER_04:
3374	case RTL_VER_05:
3375	case RTL_VER_06:
3376	case RTL_VER_07:
3377	case RTL_VER_08:
3378	case RTL_VER_09:
3379	case RTL_VER_14:
3380	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
3381	if (enable)
3382	ocp_data |= CPCR_RX_VLAN;
3383	else
3384	ocp_data &= ~CPCR_RX_VLAN;
3385	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, data: ocp_data);
3386	break;
3387
3388	case RTL_TEST_01:
3389	case RTL_VER_10:
3390	case RTL_VER_11:
3391	case RTL_VER_12:
3392	case RTL_VER_13:
3393	case RTL_VER_15:
3394	default:
3395	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR1);
3396	if (enable)
3397	ocp_data |= OUTER_VLAN | INNER_VLAN;
3398	else
3399	ocp_data &= ~(OUTER_VLAN | INNER_VLAN);
3400	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR1, data: ocp_data);
3401	break;
3402	}
3403	}
3404
3405	static int rtl8152_set_features(struct net_device *dev,
3406	netdev_features_t features)
3407	{
3408	netdev_features_t changed = features ^ dev->features;
3409	struct r8152 *tp = netdev_priv(dev);
3410	int ret;
3411
3412	ret = usb_autopm_get_interface(intf: tp->intf);
3413	if (ret < 0)
3414	goto out;
3415
3416	mutex_lock(&tp->control);
3417
3418	if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
3419	if (features & NETIF_F_HW_VLAN_CTAG_RX)
3420	rtl_rx_vlan_en(tp, enable: true);
3421	else
3422	rtl_rx_vlan_en(tp, enable: false);
3423	}
3424
3425	mutex_unlock(lock: &tp->control);
3426
3427	usb_autopm_put_interface(intf: tp->intf);
3428
3429	out:
3430	return ret;
3431	}
3432
3433	#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
3434
3435	static u32 __rtl_get_wol(struct r8152 *tp)
3436	{
3437	u32 ocp_data;
3438	u32 wolopts = 0;
3439
3440	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3441	if (ocp_data & LINK_ON_WAKE_EN)
3442	wolopts |= WAKE_PHY;
3443
3444	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
3445	if (ocp_data & UWF_EN)
3446	wolopts |= WAKE_UCAST;
3447	if (ocp_data & BWF_EN)
3448	wolopts |= WAKE_BCAST;
3449	if (ocp_data & MWF_EN)
3450	wolopts |= WAKE_MCAST;
3451
3452	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
3453	if (ocp_data & MAGIC_EN)
3454	wolopts |= WAKE_MAGIC;
3455
3456	return wolopts;
3457	}
3458
3459	static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
3460	{
3461	u32 ocp_data;
3462
3463	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3464
3465	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3466	ocp_data &= ~LINK_ON_WAKE_EN;
3467	if (wolopts & WAKE_PHY)
3468	ocp_data |= LINK_ON_WAKE_EN;
3469	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, data: ocp_data);
3470
3471	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
3472	ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN);
3473	if (wolopts & WAKE_UCAST)
3474	ocp_data |= UWF_EN;
3475	if (wolopts & WAKE_BCAST)
3476	ocp_data |= BWF_EN;
3477	if (wolopts & WAKE_MCAST)
3478	ocp_data |= MWF_EN;
3479	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, data: ocp_data);
3480
3481	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3482
3483	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
3484	ocp_data &= ~MAGIC_EN;
3485	if (wolopts & WAKE_MAGIC)
3486	ocp_data |= MAGIC_EN;
3487	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, data: ocp_data);
3488
3489	if (wolopts & WAKE_ANY)
3490	device_set_wakeup_enable(dev: &tp->udev->dev, enable: true);
3491	else
3492	device_set_wakeup_enable(dev: &tp->udev->dev, enable: false);
3493	}
3494
3495	static void r8153_mac_clk_speed_down(struct r8152 *tp, bool enable)
3496	{
3497	u32 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
3498
3499	/* MAC clock speed down */
3500	if (enable)
3501	ocp_data |= MAC_CLK_SPDWN_EN;
3502	else
3503	ocp_data &= ~MAC_CLK_SPDWN_EN;
3504
3505	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, data: ocp_data);
3506	}
3507
3508	static void r8156_mac_clk_spd(struct r8152 *tp, bool enable)
3509	{
3510	u32 ocp_data;
3511
3512	/* MAC clock speed down */
3513	if (enable) {
3514	/* aldps_spdwn_ratio, tp10_spdwn_ratio */
3515	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL,
3516	data: 0x0403);
3517
3518	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
3519	ocp_data &= ~EEE_SPDWN_RATIO_MASK;
3520	ocp_data |= MAC_CLK_SPDWN_EN | 0x03; /* eee_spdwn_ratio */
3521	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, data: ocp_data);
3522	} else {
3523	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
3524	ocp_data &= ~MAC_CLK_SPDWN_EN;
3525	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, data: ocp_data);
3526	}
3527	}
3528
3529	static void r8153_u1u2en(struct r8152 *tp, bool enable)
3530	{
3531	u8 u1u2[8];
3532
3533	if (enable)
3534	memset(u1u2, 0xff, sizeof(u1u2));
3535	else
3536	memset(u1u2, 0x00, sizeof(u1u2));
3537
3538	usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, size: sizeof(u1u2), data: u1u2);
3539	}
3540
3541	static void r8153b_u1u2en(struct r8152 *tp, bool enable)
3542	{
3543	u32 ocp_data;
3544
3545	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG);
3546	if (enable)
3547	ocp_data |= LPM_U1U2_EN;
3548	else
3549	ocp_data &= ~LPM_U1U2_EN;
3550
3551	ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, data: ocp_data);
3552	}
3553
3554	static void r8153_u2p3en(struct r8152 *tp, bool enable)
3555	{
3556	u32 ocp_data;
3557
3558	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
3559	if (enable)
3560	ocp_data |= U2P3_ENABLE;
3561	else
3562	ocp_data &= ~U2P3_ENABLE;
3563	ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, data: ocp_data);
3564	}
3565
3566	static void r8153b_ups_flags(struct r8152 *tp)
3567	{
3568	u32 ups_flags = 0;
3569
3570	if (tp->ups_info.green)
3571	ups_flags |= UPS_FLAGS_EN_GREEN;
3572
3573	if (tp->ups_info.aldps)
3574	ups_flags |= UPS_FLAGS_EN_ALDPS;
3575
3576	if (tp->ups_info.eee)
3577	ups_flags |= UPS_FLAGS_EN_EEE;
3578
3579	if (tp->ups_info.flow_control)
3580	ups_flags |= UPS_FLAGS_EN_FLOW_CTR;
3581
3582	if (tp->ups_info.eee_ckdiv)
3583	ups_flags |= UPS_FLAGS_EN_EEE_CKDIV;
3584
3585	if (tp->ups_info.eee_cmod_lv)
3586	ups_flags |= UPS_FLAGS_EEE_CMOD_LV_EN;
3587
3588	if (tp->ups_info.r_tune)
3589	ups_flags |= UPS_FLAGS_R_TUNE;
3590
3591	if (tp->ups_info._10m_ckdiv)
3592	ups_flags |= UPS_FLAGS_EN_10M_CKDIV;
3593
3594	if (tp->ups_info.eee_plloff_100)
3595	ups_flags |= UPS_FLAGS_EEE_PLLOFF_100;
3596
3597	if (tp->ups_info.eee_plloff_giga)
3598	ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA;
3599
3600	if (tp->ups_info._250m_ckdiv)
3601	ups_flags |= UPS_FLAGS_250M_CKDIV;
3602
3603	if (tp->ups_info.ctap_short_off)
3604	ups_flags |= UPS_FLAGS_CTAP_SHORT_DIS;
3605
3606	switch (tp->ups_info.speed_duplex) {
3607	case NWAY_10M_HALF:
3608	ups_flags |= ups_flags_speed(1);
3609	break;
3610	case NWAY_10M_FULL:
3611	ups_flags |= ups_flags_speed(2);
3612	break;
3613	case NWAY_100M_HALF:
3614	ups_flags |= ups_flags_speed(3);
3615	break;
3616	case NWAY_100M_FULL:
3617	ups_flags |= ups_flags_speed(4);
3618	break;
3619	case NWAY_1000M_FULL:
3620	ups_flags |= ups_flags_speed(5);
3621	break;
3622	case FORCE_10M_HALF:
3623	ups_flags |= ups_flags_speed(6);
3624	break;
3625	case FORCE_10M_FULL:
3626	ups_flags |= ups_flags_speed(7);
3627	break;
3628	case FORCE_100M_HALF:
3629	ups_flags |= ups_flags_speed(8);
3630	break;
3631	case FORCE_100M_FULL:
3632	ups_flags |= ups_flags_speed(9);
3633	break;
3634	default:
3635	break;
3636	}
3637
3638	ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, data: ups_flags);
3639	}
3640
3641	static void r8156_ups_flags(struct r8152 *tp)
3642	{
3643	u32 ups_flags = 0;
3644
3645	if (tp->ups_info.green)
3646	ups_flags |= UPS_FLAGS_EN_GREEN;
3647
3648	if (tp->ups_info.aldps)
3649	ups_flags |= UPS_FLAGS_EN_ALDPS;
3650
3651	if (tp->ups_info.eee)
3652	ups_flags |= UPS_FLAGS_EN_EEE;
3653
3654	if (tp->ups_info.flow_control)
3655	ups_flags |= UPS_FLAGS_EN_FLOW_CTR;
3656
3657	if (tp->ups_info.eee_ckdiv)
3658	ups_flags |= UPS_FLAGS_EN_EEE_CKDIV;
3659
3660	if (tp->ups_info._10m_ckdiv)
3661	ups_flags |= UPS_FLAGS_EN_10M_CKDIV;
3662
3663	if (tp->ups_info.eee_plloff_100)
3664	ups_flags |= UPS_FLAGS_EEE_PLLOFF_100;
3665
3666	if (tp->ups_info.eee_plloff_giga)
3667	ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA;
3668
3669	if (tp->ups_info._250m_ckdiv)
3670	ups_flags |= UPS_FLAGS_250M_CKDIV;
3671
3672	switch (tp->ups_info.speed_duplex) {
3673	case FORCE_10M_HALF:
3674	ups_flags |= ups_flags_speed(0);
3675	break;
3676	case FORCE_10M_FULL:
3677	ups_flags |= ups_flags_speed(1);
3678	break;
3679	case FORCE_100M_HALF:
3680	ups_flags |= ups_flags_speed(2);
3681	break;
3682	case FORCE_100M_FULL:
3683	ups_flags |= ups_flags_speed(3);
3684	break;
3685	case NWAY_10M_HALF:
3686	ups_flags |= ups_flags_speed(4);
3687	break;
3688	case NWAY_10M_FULL:
3689	ups_flags |= ups_flags_speed(5);
3690	break;
3691	case NWAY_100M_HALF:
3692	ups_flags |= ups_flags_speed(6);
3693	break;
3694	case NWAY_100M_FULL:
3695	ups_flags |= ups_flags_speed(7);
3696	break;
3697	case NWAY_1000M_FULL:
3698	ups_flags |= ups_flags_speed(8);
3699	break;
3700	case NWAY_2500M_FULL:
3701	ups_flags |= ups_flags_speed(9);
3702	break;
3703	default:
3704	break;
3705	}
3706
3707	switch (tp->ups_info.lite_mode) {
3708	case 1:
3709	ups_flags |= 0 << 5;
3710	break;
3711	case 2:
3712	ups_flags |= 2 << 5;
3713	break;
3714	case 0:
3715	default:
3716	ups_flags |= 1 << 5;
3717	break;
3718	}
3719
3720	ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, data: ups_flags);
3721	}
3722
3723	static void rtl_green_en(struct r8152 *tp, bool enable)
3724	{
3725	u16 data;
3726
3727	data = sram_read(tp, SRAM_GREEN_CFG);
3728	if (enable)
3729	data |= GREEN_ETH_EN;
3730	else
3731	data &= ~GREEN_ETH_EN;
3732	sram_write(tp, SRAM_GREEN_CFG, data);
3733
3734	tp->ups_info.green = enable;
3735	}
3736
3737	static void r8153b_green_en(struct r8152 *tp, bool enable)
3738	{
3739	if (enable) {
3740	sram_write(tp, addr: 0x8045, data: 0); /* 10M abiq&ldvbias */
3741	sram_write(tp, addr: 0x804d, data: 0x1222); /* 100M short abiq&ldvbias */
3742	sram_write(tp, addr: 0x805d, data: 0x0022); /* 1000M short abiq&ldvbias */
3743	} else {
3744	sram_write(tp, addr: 0x8045, data: 0x2444); /* 10M abiq&ldvbias */
3745	sram_write(tp, addr: 0x804d, data: 0x2444); /* 100M short abiq&ldvbias */
3746	sram_write(tp, addr: 0x805d, data: 0x2444); /* 1000M short abiq&ldvbias */
3747	}
3748
3749	rtl_green_en(tp, enable: true);
3750	}
3751
3752	static u16 r8153_phy_status(struct r8152 *tp, u16 desired)
3753	{
3754	u16 data;
3755	int i;
3756
3757	for (i = 0; i < 500; i++) {
3758	data = ocp_reg_read(tp, OCP_PHY_STATUS);
3759	data &= PHY_STAT_MASK;
3760	if (desired) {
3761	if (data == desired)
3762	break;
3763	} else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN ||
3764	data == PHY_STAT_EXT_INIT) {
3765	break;
3766	}
3767
3768	msleep(msecs: 20);
3769	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
3770	break;
3771	}
3772
3773	return data;
3774	}
3775
3776	static void r8153b_ups_en(struct r8152 *tp, bool enable)
3777	{
3778	u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3779
3780	if (enable) {
3781	r8153b_ups_flags(tp);
3782
3783	ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3784	ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, data: ocp_data);
3785
3786	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3787	ocp_data |= UPS_FORCE_PWR_DOWN;
3788	ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, data: ocp_data);
3789	} else {
3790	ocp_data &= ~(UPS_EN | USP_PREWAKE);
3791	ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, data: ocp_data);
3792
3793	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3794	ocp_data &= ~UPS_FORCE_PWR_DOWN;
3795	ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, data: ocp_data);
3796
3797	if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
3798	int i;
3799
3800	for (i = 0; i < 500; i++) {
3801	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
3802	return;
3803	if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
3804	AUTOLOAD_DONE)
3805	break;
3806	msleep(msecs: 20);
3807	}
3808
3809	tp->rtl_ops.hw_phy_cfg(tp);
3810
3811	rtl8152_set_speed(tp, autoneg: tp->autoneg, speed: tp->speed,
3812	duplex: tp->duplex, advertising: tp->advertising);
3813	}
3814	}
3815	}
3816
3817	static void r8153c_ups_en(struct r8152 *tp, bool enable)
3818	{
3819	u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3820
3821	if (enable) {
3822	r8153b_ups_flags(tp);
3823
3824	ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3825	ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, data: ocp_data);
3826
3827	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3828	ocp_data |= UPS_FORCE_PWR_DOWN;
3829	ocp_data &= ~BIT(7);
3830	ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, data: ocp_data);
3831	} else {
3832	ocp_data &= ~(UPS_EN | USP_PREWAKE);
3833	ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, data: ocp_data);
3834
3835	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3836	ocp_data &= ~UPS_FORCE_PWR_DOWN;
3837	ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, data: ocp_data);
3838
3839	if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
3840	int i;
3841
3842	for (i = 0; i < 500; i++) {
3843	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
3844	return;
3845	if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
3846	AUTOLOAD_DONE)
3847	break;
3848	msleep(msecs: 20);
3849	}
3850
3851	tp->rtl_ops.hw_phy_cfg(tp);
3852
3853	rtl8152_set_speed(tp, autoneg: tp->autoneg, speed: tp->speed,
3854	duplex: tp->duplex, advertising: tp->advertising);
3855	}
3856
3857	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3858
3859	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3860	ocp_data |= BIT(8);
3861	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, data: ocp_data);
3862
3863	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3864	}
3865	}
3866
3867	static void r8156_ups_en(struct r8152 *tp, bool enable)
3868	{
3869	u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3870
3871	if (enable) {
3872	r8156_ups_flags(tp);
3873
3874	ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3875	ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, data: ocp_data);
3876
3877	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3878	ocp_data |= UPS_FORCE_PWR_DOWN;
3879	ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, data: ocp_data);
3880
3881	switch (tp->version) {
3882	case RTL_VER_13:
3883	case RTL_VER_15:
3884	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPHY_XTAL);
3885	ocp_data &= ~OOBS_POLLING;
3886	ocp_write_byte(tp, MCU_TYPE_USB, USB_UPHY_XTAL, data: ocp_data);
3887	break;
3888	default:
3889	break;
3890	}
3891	} else {
3892	ocp_data &= ~(UPS_EN | USP_PREWAKE);
3893	ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, data: ocp_data);
3894
3895	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3896	ocp_data &= ~UPS_FORCE_PWR_DOWN;
3897	ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, data: ocp_data);
3898
3899	if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
3900	tp->rtl_ops.hw_phy_cfg(tp);
3901
3902	rtl8152_set_speed(tp, autoneg: tp->autoneg, speed: tp->speed,
3903	duplex: tp->duplex, advertising: tp->advertising);
3904	}
3905	}
3906	}
3907
3908	static void r8153_power_cut_en(struct r8152 *tp, bool enable)
3909	{
3910	u32 ocp_data;
3911
3912	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3913	if (enable)
3914	ocp_data |= PWR_EN | PHASE2_EN;
3915	else
3916	ocp_data &= ~(PWR_EN | PHASE2_EN);
3917	ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, data: ocp_data);
3918
3919	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3920	ocp_data &= ~PCUT_STATUS;
3921	ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, data: ocp_data);
3922	}
3923
3924	static void r8153b_power_cut_en(struct r8152 *tp, bool enable)
3925	{
3926	u32 ocp_data;
3927
3928	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3929	if (enable)
3930	ocp_data |= PWR_EN | PHASE2_EN;
3931	else
3932	ocp_data &= ~PWR_EN;
3933	ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, data: ocp_data);
3934
3935	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3936	ocp_data &= ~PCUT_STATUS;
3937	ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, data: ocp_data);
3938	}
3939
3940	static void r8153_queue_wake(struct r8152 *tp, bool enable)
3941	{
3942	u32 ocp_data;
3943
3944	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG);
3945	if (enable)
3946	ocp_data |= UPCOMING_RUNTIME_D3;
3947	else
3948	ocp_data &= ~UPCOMING_RUNTIME_D3;
3949	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG, data: ocp_data);
3950
3951	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG);
3952	ocp_data &= ~LINK_CHG_EVENT;
3953	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG, data: ocp_data);
3954
3955	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
3956	ocp_data &= ~LINK_CHANGE_FLAG;
3957	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, data: ocp_data);
3958	}
3959
3960	static bool rtl_can_wakeup(struct r8152 *tp)
3961	{
3962	struct usb_device *udev = tp->udev;
3963
3964	return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
3965	}
3966
3967	static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
3968	{
3969	if (enable) {
3970	u32 ocp_data;
3971
3972	__rtl_set_wol(tp, WAKE_ANY);
3973
3974	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3975
3976	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3977	ocp_data |= LINK_OFF_WAKE_EN;
3978	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, data: ocp_data);
3979
3980	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3981	} else {
3982	u32 ocp_data;
3983
3984	__rtl_set_wol(tp, wolopts: tp->saved_wolopts);
3985
3986	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3987
3988	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3989	ocp_data &= ~LINK_OFF_WAKE_EN;
3990	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, data: ocp_data);
3991
3992	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3993	}
3994	}
3995
3996	static void rtl8153_runtime_enable(struct r8152 *tp, bool enable)
3997	{
3998	if (enable) {
3999	r8153_u1u2en(tp, enable: false);
4000	r8153_u2p3en(tp, enable: false);
4001	rtl_runtime_suspend_enable(tp, enable: true);
4002	} else {
4003	rtl_runtime_suspend_enable(tp, enable: false);
4004
4005	switch (tp->version) {
4006	case RTL_VER_03:
4007	case RTL_VER_04:
4008	break;
4009	case RTL_VER_05:
4010	case RTL_VER_06:
4011	default:
4012	r8153_u2p3en(tp, enable: true);
4013	break;
4014	}
4015
4016	r8153_u1u2en(tp, enable: true);
4017	}
4018	}
4019
4020	static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable)
4021	{
4022	if (enable) {
4023	r8153_queue_wake(tp, enable: true);
4024	r8153b_u1u2en(tp, enable: false);
4025	r8153_u2p3en(tp, enable: false);
4026	rtl_runtime_suspend_enable(tp, enable: true);
4027	r8153b_ups_en(tp, enable: true);
4028	} else {
4029	r8153b_ups_en(tp, enable: false);
4030	r8153_queue_wake(tp, enable: false);
4031	rtl_runtime_suspend_enable(tp, enable: false);
4032	if (tp->udev->speed >= USB_SPEED_SUPER)
4033	r8153b_u1u2en(tp, enable: true);
4034	}
4035	}
4036
4037	static void rtl8153c_runtime_enable(struct r8152 *tp, bool enable)
4038	{
4039	if (enable) {
4040	r8153_queue_wake(tp, enable: true);
4041	r8153b_u1u2en(tp, enable: false);
4042	r8153_u2p3en(tp, enable: false);
4043	rtl_runtime_suspend_enable(tp, enable: true);
4044	r8153c_ups_en(tp, enable: true);
4045	} else {
4046	r8153c_ups_en(tp, enable: false);
4047	r8153_queue_wake(tp, enable: false);
4048	rtl_runtime_suspend_enable(tp, enable: false);
4049	r8153b_u1u2en(tp, enable: true);
4050	}
4051	}
4052
4053	static void rtl8156_runtime_enable(struct r8152 *tp, bool enable)
4054	{
4055	if (enable) {
4056	r8153_queue_wake(tp, enable: true);
4057	r8153b_u1u2en(tp, enable: false);
4058	r8153_u2p3en(tp, enable: false);
4059	rtl_runtime_suspend_enable(tp, enable: true);
4060	} else {
4061	r8153_queue_wake(tp, enable: false);
4062	rtl_runtime_suspend_enable(tp, enable: false);
4063	r8153_u2p3en(tp, enable: true);
4064	if (tp->udev->speed >= USB_SPEED_SUPER)
4065	r8153b_u1u2en(tp, enable: true);
4066	}
4067	}
4068
4069	static void r8153_teredo_off(struct r8152 *tp)
4070	{
4071	u32 ocp_data;
4072
4073	switch (tp->version) {
4074	case RTL_VER_01:
4075	case RTL_VER_02:
4076	case RTL_VER_03:
4077	case RTL_VER_04:
4078	case RTL_VER_05:
4079	case RTL_VER_06:
4080	case RTL_VER_07:
4081	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
4082	ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK |
4083	OOB_TEREDO_EN);
4084	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, data: ocp_data);
4085	break;
4086
4087	case RTL_VER_08:
4088	case RTL_VER_09:
4089	case RTL_TEST_01:
4090	case RTL_VER_10:
4091	case RTL_VER_11:
4092	case RTL_VER_12:
4093	case RTL_VER_13:
4094	case RTL_VER_14:
4095	case RTL_VER_15:
4096	default:
4097	/* The bit 0 ~ 7 are relative with teredo settings. They are
4098	* W1C (write 1 to clear), so set all 1 to disable it.
4099	*/
4100	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, data: 0xff);
4101	break;
4102	}
4103
4104	ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
4105	ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, data: 0);
4106	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, data: 0);
4107	}
4108
4109	static void rtl_reset_bmu(struct r8152 *tp)
4110	{
4111	u32 ocp_data;
4112
4113	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
4114	ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
4115	ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, data: ocp_data);
4116	ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
4117	ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, data: ocp_data);
4118	}
4119
4120	/* Clear the bp to stop the firmware before loading a new one */
4121	static void rtl_clear_bp(struct r8152 *tp, u16 type)
4122	{
4123	u16 bp[16] = {0};
4124	u16 bp_num;
4125
4126	switch (tp->version) {
4127	case RTL_VER_08:
4128	case RTL_VER_09:
4129	case RTL_VER_10:
4130	case RTL_VER_11:
4131	case RTL_VER_12:
4132	case RTL_VER_13:
4133	case RTL_VER_15:
4134	if (type == MCU_TYPE_USB) {
4135	ocp_write_word(tp, MCU_TYPE_USB, USB_BP2_EN, data: 0);
4136	bp_num = 16;
4137	break;
4138	}
4139	fallthrough;
4140	case RTL_VER_03:
4141	case RTL_VER_04:
4142	case RTL_VER_05:
4143	case RTL_VER_06:
4144	ocp_write_byte(tp, type, PLA_BP_EN, data: 0);
4145	fallthrough;
4146	case RTL_VER_01:
4147	case RTL_VER_02:
4148	case RTL_VER_07:
4149	bp_num = 8;
4150	break;
4151	case RTL_VER_14:
4152	default:
4153	ocp_write_word(tp, type, USB_BP2_EN, data: 0);
4154	bp_num = 16;
4155	break;
4156	}
4157
4158	generic_ocp_write(tp, PLA_BP_0, BYTE_EN_DWORD, size: bp_num << 1, data: bp, type);
4159
4160	/* wait 3 ms to make sure the firmware is stopped */
4161	usleep_range(min: 3000, max: 6000);
4162	ocp_write_word(tp, type, PLA_BP_BA, data: 0);
4163	}
4164
4165	static inline void rtl_reset_ocp_base(struct r8152 *tp)
4166	{
4167	tp->ocp_base = -1;
4168	}
4169
4170	static int rtl_phy_patch_request(struct r8152 *tp, bool request, bool wait)
4171	{
4172	u16 data, check;
4173	int i;
4174
4175	data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD);
4176	if (request) {
4177	data |= PATCH_REQUEST;
4178	check = 0;
4179	} else {
4180	data &= ~PATCH_REQUEST;
4181	check = PATCH_READY;
4182	}
4183	ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data);
4184
4185	for (i = 0; wait && i < 5000; i++) {
4186	u32 ocp_data;
4187
4188	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
4189	return -ENODEV;
4190
4191	usleep_range(min: 1000, max: 2000);
4192	ocp_data = ocp_reg_read(tp, OCP_PHY_PATCH_STAT);
4193	if ((ocp_data & PATCH_READY) ^ check)
4194	break;
4195	}
4196
4197	if (request && wait &&
4198	!(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) {
4199	dev_err(&tp->intf->dev, "PHY patch request fail\n");
4200	rtl_phy_patch_request(tp, request: false, wait: false);
4201	return -ETIME;
4202	} else {
4203	return 0;
4204	}
4205	}
4206
4207	static void rtl_patch_key_set(struct r8152 *tp, u16 key_addr, u16 patch_key)
4208	{
4209	if (patch_key && key_addr) {
4210	sram_write(tp, addr: key_addr, data: patch_key);
4211	sram_write(tp, SRAM_PHY_LOCK, PHY_PATCH_LOCK);
4212	} else if (key_addr) {
4213	u16 data;
4214
4215	sram_write(tp, addr: 0x0000, data: 0x0000);
4216
4217	data = ocp_reg_read(tp, OCP_PHY_LOCK);
4218	data &= ~PATCH_LOCK;
4219	ocp_reg_write(tp, OCP_PHY_LOCK, data);
4220
4221	sram_write(tp, addr: key_addr, data: 0x0000);
4222	} else {
4223	WARN_ON_ONCE(1);
4224	}
4225	}
4226
4227	static int
4228	rtl_pre_ram_code(struct r8152 *tp, u16 key_addr, u16 patch_key, bool wait)
4229	{
4230	if (rtl_phy_patch_request(tp, request: true, wait))
4231	return -ETIME;
4232
4233	rtl_patch_key_set(tp, key_addr, patch_key);
4234
4235	return 0;
4236	}
4237
4238	static int rtl_post_ram_code(struct r8152 *tp, u16 key_addr, bool wait)
4239	{
4240	rtl_patch_key_set(tp, key_addr, patch_key: 0);
4241
4242	rtl_phy_patch_request(tp, request: false, wait);
4243
4244	return 0;
4245	}
4246
4247	static bool rtl8152_is_fw_phy_speed_up_ok(struct r8152 *tp, struct fw_phy_speed_up *phy)
4248	{
4249	u16 fw_offset;
4250	u32 length;
4251	bool rc = false;
4252
4253	switch (tp->version) {
4254	case RTL_VER_01:
4255	case RTL_VER_02:
4256	case RTL_VER_03:
4257	case RTL_VER_04:
4258	case RTL_VER_05:
4259	case RTL_VER_06:
4260	case RTL_VER_07:
4261	case RTL_VER_08:
4262	case RTL_VER_09:
4263	case RTL_VER_10:
4264	case RTL_VER_11:
4265	case RTL_VER_12:
4266	case RTL_VER_14:
4267	goto out;
4268	case RTL_VER_13:
4269	case RTL_VER_15:
4270	default:
4271	break;
4272	}
4273
4274	fw_offset = __le16_to_cpu(phy->fw_offset);
4275	length = __le32_to_cpu(phy->blk_hdr.length);
4276	if (fw_offset < sizeof(*phy) || length <= fw_offset) {
4277	dev_err(&tp->intf->dev, "invalid fw_offset\n");
4278	goto out;
4279	}
4280
4281	length -= fw_offset;
4282	if (length & 3) {
4283	dev_err(&tp->intf->dev, "invalid block length\n");
4284	goto out;
4285	}
4286
4287	if (__le16_to_cpu(phy->fw_reg) != 0x9A00) {
4288	dev_err(&tp->intf->dev, "invalid register to load firmware\n");
4289	goto out;
4290	}
4291
4292	rc = true;
4293	out:
4294	return rc;
4295	}
4296
4297	static bool rtl8152_is_fw_phy_ver_ok(struct r8152 *tp, struct fw_phy_ver *ver)
4298	{
4299	bool rc = false;
4300
4301	switch (tp->version) {
4302	case RTL_VER_10:
4303	case RTL_VER_11:
4304	case RTL_VER_12:
4305	case RTL_VER_13:
4306	case RTL_VER_15:
4307	break;
4308	default:
4309	goto out;
4310	}
4311
4312	if (__le32_to_cpu(ver->blk_hdr.length) != sizeof(*ver)) {
4313	dev_err(&tp->intf->dev, "invalid block length\n");
4314	goto out;
4315	}
4316
4317	if (__le16_to_cpu(ver->ver.addr) != SRAM_GPHY_FW_VER) {
4318	dev_err(&tp->intf->dev, "invalid phy ver addr\n");
4319	goto out;
4320	}
4321
4322	rc = true;
4323	out:
4324	return rc;
4325	}
4326
4327	static bool rtl8152_is_fw_phy_fixup_ok(struct r8152 *tp, struct fw_phy_fixup *fix)
4328	{
4329	bool rc = false;
4330
4331	switch (tp->version) {
4332	case RTL_VER_10:
4333	case RTL_VER_11:
4334	case RTL_VER_12:
4335	case RTL_VER_13:
4336	case RTL_VER_15:
4337	break;
4338	default:
4339	goto out;
4340	}
4341
4342	if (__le32_to_cpu(fix->blk_hdr.length) != sizeof(*fix)) {
4343	dev_err(&tp->intf->dev, "invalid block length\n");
4344	goto out;
4345	}
4346
4347	if (__le16_to_cpu(fix->setting.addr) != OCP_PHY_PATCH_CMD ||
4348	__le16_to_cpu(fix->setting.data) != BIT(7)) {
4349	dev_err(&tp->intf->dev, "invalid phy fixup\n");
4350	goto out;
4351	}
4352
4353	rc = true;
4354	out:
4355	return rc;
4356	}
4357
4358	static bool rtl8152_is_fw_phy_union_ok(struct r8152 *tp, struct fw_phy_union *phy)
4359	{
4360	u16 fw_offset;
4361	u32 length;
4362	bool rc = false;
4363
4364	switch (tp->version) {
4365	case RTL_VER_10:
4366	case RTL_VER_11:
4367	case RTL_VER_12:
4368	case RTL_VER_13:
4369	case RTL_VER_15:
4370	break;
4371	default:
4372	goto out;
4373	}
4374
4375	fw_offset = __le16_to_cpu(phy->fw_offset);
4376	length = __le32_to_cpu(phy->blk_hdr.length);
4377	if (fw_offset < sizeof(*phy) || length <= fw_offset) {
4378	dev_err(&tp->intf->dev, "invalid fw_offset\n");
4379	goto out;
4380	}
4381
4382	length -= fw_offset;
4383	if (length & 1) {
4384	dev_err(&tp->intf->dev, "invalid block length\n");
4385	goto out;
4386	}
4387
4388	if (phy->pre_num > 2) {
4389	dev_err(&tp->intf->dev, "invalid pre_num %d\n", phy->pre_num);
4390	goto out;
4391	}
4392
4393	if (phy->bp_num > 8) {
4394	dev_err(&tp->intf->dev, "invalid bp_num %d\n", phy->bp_num);
4395	goto out;
4396	}
4397
4398	rc = true;
4399	out:
4400	return rc;
4401	}
4402
4403	static bool rtl8152_is_fw_phy_nc_ok(struct r8152 *tp, struct fw_phy_nc *phy)
4404	{
4405	u32 length;
4406	u16 fw_offset, fw_reg, ba_reg, patch_en_addr, mode_reg, bp_start;
4407	bool rc = false;
4408
4409	switch (tp->version) {
4410	case RTL_VER_04:
4411	case RTL_VER_05:
4412	case RTL_VER_06:
4413	fw_reg = 0xa014;
4414	ba_reg = 0xa012;
4415	patch_en_addr = 0xa01a;
4416	mode_reg = 0xb820;
4417	bp_start = 0xa000;
4418	break;
4419	default:
4420	goto out;
4421	}
4422
4423	fw_offset = __le16_to_cpu(phy->fw_offset);
4424	if (fw_offset < sizeof(*phy)) {
4425	dev_err(&tp->intf->dev, "fw_offset too small\n");
4426	goto out;
4427	}
4428
4429	length = __le32_to_cpu(phy->blk_hdr.length);
4430	if (length < fw_offset) {
4431	dev_err(&tp->intf->dev, "invalid fw_offset\n");
4432	goto out;
4433	}
4434
4435	length -= __le16_to_cpu(phy->fw_offset);
4436	if (!length || (length & 1)) {
4437	dev_err(&tp->intf->dev, "invalid block length\n");
4438	goto out;
4439	}
4440
4441	if (__le16_to_cpu(phy->fw_reg) != fw_reg) {
4442	dev_err(&tp->intf->dev, "invalid register to load firmware\n");
4443	goto out;
4444	}
4445
4446	if (__le16_to_cpu(phy->ba_reg) != ba_reg) {
4447	dev_err(&tp->intf->dev, "invalid base address register\n");
4448	goto out;
4449	}
4450
4451	if (__le16_to_cpu(phy->patch_en_addr) != patch_en_addr) {
4452	dev_err(&tp->intf->dev,
4453	"invalid patch mode enabled register\n");
4454	goto out;
4455	}
4456
4457	if (__le16_to_cpu(phy->mode_reg) != mode_reg) {
4458	dev_err(&tp->intf->dev,
4459	"invalid register to switch the mode\n");
4460	goto out;
4461	}
4462
4463	if (__le16_to_cpu(phy->bp_start) != bp_start) {
4464	dev_err(&tp->intf->dev,
4465	"invalid start register of break point\n");
4466	goto out;
4467	}
4468
4469	if (__le16_to_cpu(phy->bp_num) > 4) {
4470	dev_err(&tp->intf->dev, "invalid break point number\n");
4471	goto out;
4472	}
4473
4474	rc = true;
4475	out:
4476	return rc;
4477	}
4478
4479	static bool rtl8152_is_fw_mac_ok(struct r8152 *tp, struct fw_mac *mac)
4480	{
4481	u16 fw_reg, bp_ba_addr, bp_en_addr, bp_start, fw_offset;
4482	bool rc = false;
4483	u32 length, type;
4484	int i, max_bp;
4485
4486	type = __le32_to_cpu(mac->blk_hdr.type);
4487	if (type == RTL_FW_PLA) {
4488	switch (tp->version) {
4489	case RTL_VER_01:
4490	case RTL_VER_02:
4491	case RTL_VER_07:
4492	fw_reg = 0xf800;
4493	bp_ba_addr = PLA_BP_BA;
4494	bp_en_addr = 0;
4495	bp_start = PLA_BP_0;
4496	max_bp = 8;
4497	break;
4498	case RTL_VER_03:
4499	case RTL_VER_04:
4500	case RTL_VER_05:
4501	case RTL_VER_06:
4502	case RTL_VER_08:
4503	case RTL_VER_09:
4504	case RTL_VER_11:
4505	case RTL_VER_12:
4506	case RTL_VER_13:
4507	case RTL_VER_15:
4508	fw_reg = 0xf800;
4509	bp_ba_addr = PLA_BP_BA;
4510	bp_en_addr = PLA_BP_EN;
4511	bp_start = PLA_BP_0;
4512	max_bp = 8;
4513	break;
4514	case RTL_VER_14:
4515	fw_reg = 0xf800;
4516	bp_ba_addr = PLA_BP_BA;
4517	bp_en_addr = USB_BP2_EN;
4518	bp_start = PLA_BP_0;
4519	max_bp = 16;
4520	break;
4521	default:
4522	goto out;
4523	}
4524	} else if (type == RTL_FW_USB) {
4525	switch (tp->version) {
4526	case RTL_VER_03:
4527	case RTL_VER_04:
4528	case RTL_VER_05:
4529	case RTL_VER_06:
4530	fw_reg = 0xf800;
4531	bp_ba_addr = USB_BP_BA;
4532	bp_en_addr = USB_BP_EN;
4533	bp_start = USB_BP_0;
4534	max_bp = 8;
4535	break;
4536	case RTL_VER_08:
4537	case RTL_VER_09:
4538	case RTL_VER_11:
4539	case RTL_VER_12:
4540	case RTL_VER_13:
4541	case RTL_VER_14:
4542	case RTL_VER_15:
4543	fw_reg = 0xe600;
4544	bp_ba_addr = USB_BP_BA;
4545	bp_en_addr = USB_BP2_EN;
4546	bp_start = USB_BP_0;
4547	max_bp = 16;
4548	break;
4549	case RTL_VER_01:
4550	case RTL_VER_02:
4551	case RTL_VER_07:
4552	default:
4553	goto out;
4554	}
4555	} else {
4556	goto out;
4557	}
4558
4559	fw_offset = __le16_to_cpu(mac->fw_offset);
4560	if (fw_offset < sizeof(*mac)) {
4561	dev_err(&tp->intf->dev, "fw_offset too small\n");
4562	goto out;
4563	}
4564
4565	length = __le32_to_cpu(mac->blk_hdr.length);
4566	if (length < fw_offset) {
4567	dev_err(&tp->intf->dev, "invalid fw_offset\n");
4568	goto out;
4569	}
4570
4571	length -= fw_offset;
4572	if (length < 4 || (length & 3)) {
4573	dev_err(&tp->intf->dev, "invalid block length\n");
4574	goto out;
4575	}
4576
4577	if (__le16_to_cpu(mac->fw_reg) != fw_reg) {
4578	dev_err(&tp->intf->dev, "invalid register to load firmware\n");
4579	goto out;
4580	}
4581
4582	if (__le16_to_cpu(mac->bp_ba_addr) != bp_ba_addr) {
4583	dev_err(&tp->intf->dev, "invalid base address register\n");
4584	goto out;
4585	}
4586
4587	if (__le16_to_cpu(mac->bp_en_addr) != bp_en_addr) {
4588	dev_err(&tp->intf->dev, "invalid enabled mask register\n");
4589	goto out;
4590	}
4591
4592	if (__le16_to_cpu(mac->bp_start) != bp_start) {
4593	dev_err(&tp->intf->dev,
4594	"invalid start register of break point\n");
4595	goto out;
4596	}
4597
4598	if (__le16_to_cpu(mac->bp_num) > max_bp) {
4599	dev_err(&tp->intf->dev, "invalid break point number\n");
4600	goto out;
4601	}
4602
4603	for (i = __le16_to_cpu(mac->bp_num); i < max_bp; i++) {
4604	if (mac->bp[i]) {
4605	dev_err(&tp->intf->dev, "unused bp%u is not zero\n", i);
4606	goto out;
4607	}
4608	}
4609
4610	rc = true;
4611	out:
4612	return rc;
4613	}
4614
4615	/* Verify the checksum for the firmware file. It is calculated from the version
4616	* field to the end of the file. Compare the result with the checksum field to
4617	* make sure the file is correct.
4618	*/
4619	static long rtl8152_fw_verify_checksum(struct r8152 *tp,
4620	struct fw_header *fw_hdr, size_t size)
4621	{
4622	unsigned char checksum[sizeof(fw_hdr->checksum)];
4623	struct crypto_shash *alg;
4624	struct shash_desc *sdesc;
4625	size_t len;
4626	long rc;
4627
4628	alg = crypto_alloc_shash(alg_name: "sha256", type: 0, mask: 0);
4629	if (IS_ERR(ptr: alg)) {
4630	rc = PTR_ERR(ptr: alg);
4631	goto out;
4632	}
4633
4634	if (crypto_shash_digestsize(tfm: alg) != sizeof(fw_hdr->checksum)) {
4635	rc = -EFAULT;
4636	dev_err(&tp->intf->dev, "digestsize incorrect (%u)\n",
4637	crypto_shash_digestsize(alg));
4638	goto free_shash;
4639	}
4640
4641	len = sizeof(*sdesc) + crypto_shash_descsize(tfm: alg);
4642	sdesc = kmalloc(size: len, GFP_KERNEL);
4643	if (!sdesc) {
4644	rc = -ENOMEM;
4645	goto free_shash;
4646	}
4647	sdesc->tfm = alg;
4648
4649	len = size - sizeof(fw_hdr->checksum);
4650	rc = crypto_shash_digest(desc: sdesc, data: fw_hdr->version, len, out: checksum);
4651	kfree(objp: sdesc);
4652	if (rc)
4653	goto free_shash;
4654
4655	if (memcmp(p: fw_hdr->checksum, q: checksum, size: sizeof(fw_hdr->checksum))) {
4656	dev_err(&tp->intf->dev, "checksum fail\n");
4657	rc = -EFAULT;
4658	}
4659
4660	free_shash:
4661	crypto_free_shash(tfm: alg);
4662	out:
4663	return rc;
4664	}
4665
4666	static long rtl8152_check_firmware(struct r8152 *tp, struct rtl_fw *rtl_fw)
4667	{
4668	const struct firmware *fw = rtl_fw->fw;
4669	struct fw_header *fw_hdr = (struct fw_header *)fw->data;
4670	unsigned long fw_flags = 0;
4671	long ret = -EFAULT;
4672	int i;
4673
4674	if (fw->size < sizeof(*fw_hdr)) {
4675	dev_err(&tp->intf->dev, "file too small\n");
4676	goto fail;
4677	}
4678
4679	ret = rtl8152_fw_verify_checksum(tp, fw_hdr, size: fw->size);
4680	if (ret)
4681	goto fail;
4682
4683	ret = -EFAULT;
4684
4685	for (i = sizeof(*fw_hdr); i < fw->size;) {
4686	struct fw_block *block = (struct fw_block *)&fw->data[i];
4687	u32 type;
4688
4689	if ((i + sizeof(*block)) > fw->size)
4690	goto fail;
4691
4692	type = __le32_to_cpu(block->type);
4693	switch (type) {
4694	case RTL_FW_END:
4695	if (__le32_to_cpu(block->length) != sizeof(*block))
4696	goto fail;
4697	goto fw_end;
4698	case RTL_FW_PLA:
4699	if (test_bit(FW_FLAGS_PLA, &fw_flags)) {
4700	dev_err(&tp->intf->dev,
4701	"multiple PLA firmware encountered");
4702	goto fail;
4703	}
4704
4705	if (!rtl8152_is_fw_mac_ok(tp, mac: (struct fw_mac *)block)) {
4706	dev_err(&tp->intf->dev,
4707	"check PLA firmware failed\n");
4708	goto fail;
4709	}
4710	__set_bit(FW_FLAGS_PLA, &fw_flags);
4711	break;
4712	case RTL_FW_USB:
4713	if (test_bit(FW_FLAGS_USB, &fw_flags)) {
4714	dev_err(&tp->intf->dev,
4715	"multiple USB firmware encountered");
4716	goto fail;
4717	}
4718
4719	if (!rtl8152_is_fw_mac_ok(tp, mac: (struct fw_mac *)block)) {
4720	dev_err(&tp->intf->dev,
4721	"check USB firmware failed\n");
4722	goto fail;
4723	}
4724	__set_bit(FW_FLAGS_USB, &fw_flags);
4725	break;
4726	case RTL_FW_PHY_START:
4727	if (test_bit(FW_FLAGS_START, &fw_flags) ||
4728	test_bit(FW_FLAGS_NC, &fw_flags) ||
4729	test_bit(FW_FLAGS_NC1, &fw_flags) ||
4730	test_bit(FW_FLAGS_NC2, &fw_flags) ||
4731	test_bit(FW_FLAGS_UC2, &fw_flags) ||
4732	test_bit(FW_FLAGS_UC, &fw_flags) ||
4733	test_bit(FW_FLAGS_STOP, &fw_flags)) {
4734	dev_err(&tp->intf->dev,
4735	"check PHY_START fail\n");
4736	goto fail;
4737	}
4738
4739	if (__le32_to_cpu(block->length) != sizeof(struct fw_phy_patch_key)) {
4740	dev_err(&tp->intf->dev,
4741	"Invalid length for PHY_START\n");
4742	goto fail;
4743	}
4744	__set_bit(FW_FLAGS_START, &fw_flags);
4745	break;
4746	case RTL_FW_PHY_STOP:
4747	if (test_bit(FW_FLAGS_STOP, &fw_flags) ||
4748	!test_bit(FW_FLAGS_START, &fw_flags)) {
4749	dev_err(&tp->intf->dev,
4750	"Check PHY_STOP fail\n");
4751	goto fail;
4752	}
4753
4754	if (__le32_to_cpu(block->length) != sizeof(*block)) {
4755	dev_err(&tp->intf->dev,
4756	"Invalid length for PHY_STOP\n");
4757	goto fail;
4758	}
4759	__set_bit(FW_FLAGS_STOP, &fw_flags);
4760	break;
4761	case RTL_FW_PHY_NC:
4762	if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4763	test_bit(FW_FLAGS_STOP, &fw_flags)) {
4764	dev_err(&tp->intf->dev,
4765	"check PHY_NC fail\n");
4766	goto fail;
4767	}
4768
4769	if (test_bit(FW_FLAGS_NC, &fw_flags)) {
4770	dev_err(&tp->intf->dev,
4771	"multiple PHY NC encountered\n");
4772	goto fail;
4773	}
4774
4775	if (!rtl8152_is_fw_phy_nc_ok(tp, phy: (struct fw_phy_nc *)block)) {
4776	dev_err(&tp->intf->dev,
4777	"check PHY NC firmware failed\n");
4778	goto fail;
4779	}
4780	__set_bit(FW_FLAGS_NC, &fw_flags);
4781	break;
4782	case RTL_FW_PHY_UNION_NC:
4783	if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4784	test_bit(FW_FLAGS_NC1, &fw_flags) ||
4785	test_bit(FW_FLAGS_NC2, &fw_flags) ||
4786	test_bit(FW_FLAGS_UC2, &fw_flags) ||
4787	test_bit(FW_FLAGS_UC, &fw_flags) ||
4788	test_bit(FW_FLAGS_STOP, &fw_flags)) {
4789	dev_err(&tp->intf->dev, "PHY_UNION_NC out of order\n");
4790	goto fail;
4791	}
4792
4793	if (test_bit(FW_FLAGS_NC, &fw_flags)) {
4794	dev_err(&tp->intf->dev, "multiple PHY_UNION_NC encountered\n");
4795	goto fail;
4796	}
4797
4798	if (!rtl8152_is_fw_phy_union_ok(tp, phy: (struct fw_phy_union *)block)) {
4799	dev_err(&tp->intf->dev, "check PHY_UNION_NC failed\n");
4800	goto fail;
4801	}
4802	__set_bit(FW_FLAGS_NC, &fw_flags);
4803	break;
4804	case RTL_FW_PHY_UNION_NC1:
4805	if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4806	test_bit(FW_FLAGS_NC2, &fw_flags) ||
4807	test_bit(FW_FLAGS_UC2, &fw_flags) ||
4808	test_bit(FW_FLAGS_UC, &fw_flags) ||
4809	test_bit(FW_FLAGS_STOP, &fw_flags)) {
4810	dev_err(&tp->intf->dev, "PHY_UNION_NC1 out of order\n");
4811	goto fail;
4812	}
4813
4814	if (test_bit(FW_FLAGS_NC1, &fw_flags)) {
4815	dev_err(&tp->intf->dev, "multiple PHY NC1 encountered\n");
4816	goto fail;
4817	}
4818
4819	if (!rtl8152_is_fw_phy_union_ok(tp, phy: (struct fw_phy_union *)block)) {
4820	dev_err(&tp->intf->dev, "check PHY_UNION_NC1 failed\n");
4821	goto fail;
4822	}
4823	__set_bit(FW_FLAGS_NC1, &fw_flags);
4824	break;
4825	case RTL_FW_PHY_UNION_NC2:
4826	if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4827	test_bit(FW_FLAGS_UC2, &fw_flags) ||
4828	test_bit(FW_FLAGS_UC, &fw_flags) ||
4829	test_bit(FW_FLAGS_STOP, &fw_flags)) {
4830	dev_err(&tp->intf->dev, "PHY_UNION_NC2 out of order\n");
4831	goto fail;
4832	}
4833
4834	if (test_bit(FW_FLAGS_NC2, &fw_flags)) {
4835	dev_err(&tp->intf->dev, "multiple PHY NC2 encountered\n");
4836	goto fail;
4837	}
4838
4839	if (!rtl8152_is_fw_phy_union_ok(tp, phy: (struct fw_phy_union *)block)) {
4840	dev_err(&tp->intf->dev, "check PHY_UNION_NC2 failed\n");
4841	goto fail;
4842	}
4843	__set_bit(FW_FLAGS_NC2, &fw_flags);
4844	break;
4845	case RTL_FW_PHY_UNION_UC2:
4846	if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4847	test_bit(FW_FLAGS_UC, &fw_flags) ||
4848	test_bit(FW_FLAGS_STOP, &fw_flags)) {
4849	dev_err(&tp->intf->dev, "PHY_UNION_UC2 out of order\n");
4850	goto fail;
4851	}
4852
4853	if (test_bit(FW_FLAGS_UC2, &fw_flags)) {
4854	dev_err(&tp->intf->dev, "multiple PHY UC2 encountered\n");
4855	goto fail;
4856	}
4857
4858	if (!rtl8152_is_fw_phy_union_ok(tp, phy: (struct fw_phy_union *)block)) {
4859	dev_err(&tp->intf->dev, "check PHY_UNION_UC2 failed\n");
4860	goto fail;
4861	}
4862	__set_bit(FW_FLAGS_UC2, &fw_flags);
4863	break;
4864	case RTL_FW_PHY_UNION_UC:
4865	if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4866	test_bit(FW_FLAGS_STOP, &fw_flags)) {
4867	dev_err(&tp->intf->dev, "PHY_UNION_UC out of order\n");
4868	goto fail;
4869	}
4870
4871	if (test_bit(FW_FLAGS_UC, &fw_flags)) {
4872	dev_err(&tp->intf->dev, "multiple PHY UC encountered\n");
4873	goto fail;
4874	}
4875
4876	if (!rtl8152_is_fw_phy_union_ok(tp, phy: (struct fw_phy_union *)block)) {
4877	dev_err(&tp->intf->dev, "check PHY_UNION_UC failed\n");
4878	goto fail;
4879	}
4880	__set_bit(FW_FLAGS_UC, &fw_flags);
4881	break;
4882	case RTL_FW_PHY_UNION_MISC:
4883	if (!rtl8152_is_fw_phy_union_ok(tp, phy: (struct fw_phy_union *)block)) {
4884	dev_err(&tp->intf->dev, "check RTL_FW_PHY_UNION_MISC failed\n");
4885	goto fail;
4886	}
4887	break;
4888	case RTL_FW_PHY_FIXUP:
4889	if (!rtl8152_is_fw_phy_fixup_ok(tp, fix: (struct fw_phy_fixup *)block)) {
4890	dev_err(&tp->intf->dev, "check PHY fixup failed\n");
4891	goto fail;
4892	}
4893	break;
4894	case RTL_FW_PHY_SPEED_UP:
4895	if (test_bit(FW_FLAGS_SPEED_UP, &fw_flags)) {
4896	dev_err(&tp->intf->dev, "multiple PHY firmware encountered");
4897	goto fail;
4898	}
4899
4900	if (!rtl8152_is_fw_phy_speed_up_ok(tp, phy: (struct fw_phy_speed_up *)block)) {
4901	dev_err(&tp->intf->dev, "check PHY speed up failed\n");
4902	goto fail;
4903	}
4904	__set_bit(FW_FLAGS_SPEED_UP, &fw_flags);
4905	break;
4906	case RTL_FW_PHY_VER:
4907	if (test_bit(FW_FLAGS_START, &fw_flags) ||
4908	test_bit(FW_FLAGS_NC, &fw_flags) ||
4909	test_bit(FW_FLAGS_NC1, &fw_flags) ||
4910	test_bit(FW_FLAGS_NC2, &fw_flags) ||
4911	test_bit(FW_FLAGS_UC2, &fw_flags) ||
4912	test_bit(FW_FLAGS_UC, &fw_flags) ||
4913	test_bit(FW_FLAGS_STOP, &fw_flags)) {
4914	dev_err(&tp->intf->dev, "Invalid order to set PHY version\n");
4915	goto fail;
4916	}
4917
4918	if (test_bit(FW_FLAGS_VER, &fw_flags)) {
4919	dev_err(&tp->intf->dev, "multiple PHY version encountered");
4920	goto fail;
4921	}
4922
4923	if (!rtl8152_is_fw_phy_ver_ok(tp, ver: (struct fw_phy_ver *)block)) {
4924	dev_err(&tp->intf->dev, "check PHY version failed\n");
4925	goto fail;
4926	}
4927	__set_bit(FW_FLAGS_VER, &fw_flags);
4928	break;
4929	default:
4930	dev_warn(&tp->intf->dev, "Unknown type %u is found\n",
4931	type);
4932	break;
4933	}
4934
4935	/* next block */
4936	i += ALIGN(__le32_to_cpu(block->length), 8);
4937	}
4938
4939	fw_end:
4940	if (test_bit(FW_FLAGS_START, &fw_flags) && !test_bit(FW_FLAGS_STOP, &fw_flags)) {
4941	dev_err(&tp->intf->dev, "without PHY_STOP\n");
4942	goto fail;
4943	}
4944
4945	return 0;
4946	fail:
4947	return ret;
4948	}
4949
4950	static void rtl_ram_code_speed_up(struct r8152 *tp, struct fw_phy_speed_up *phy, bool wait)
4951	{
4952	u32 len;
4953	u8 *data;
4954
4955	rtl_reset_ocp_base(tp);
4956
4957	if (sram_read(tp, SRAM_GPHY_FW_VER) >= __le16_to_cpu(phy->version)) {
4958	dev_dbg(&tp->intf->dev, "PHY firmware has been the newest\n");
4959	return;
4960	}
4961
4962	len = __le32_to_cpu(phy->blk_hdr.length);
4963	len -= __le16_to_cpu(phy->fw_offset);
4964	data = (u8 *)phy + __le16_to_cpu(phy->fw_offset);
4965
4966	if (rtl_phy_patch_request(tp, request: true, wait))
4967	return;
4968
4969	while (len) {
4970	u32 ocp_data, size;
4971	int i;
4972
4973	if (len < 2048)
4974	size = len;
4975	else
4976	size = 2048;
4977
4978	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL);
4979	ocp_data |= GPHY_PATCH_DONE | BACKUP_RESTRORE;
4980	ocp_write_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL, data: ocp_data);
4981
4982	generic_ocp_write(tp, __le16_to_cpu(phy->fw_reg), byteen: 0xff, size, data, MCU_TYPE_USB);
4983
4984	data += size;
4985	len -= size;
4986
4987	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL);
4988	ocp_data |= POL_GPHY_PATCH;
4989	ocp_write_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL, data: ocp_data);
4990
4991	for (i = 0; i < 1000; i++) {
4992	if (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & POL_GPHY_PATCH))
4993	break;
4994	}
4995
4996	if (i == 1000) {
4997	dev_err(&tp->intf->dev, "ram code speedup mode timeout\n");
4998	break;
4999	}
5000	}
5001
5002	rtl_reset_ocp_base(tp);
5003
5004	rtl_phy_patch_request(tp, request: false, wait);
5005
5006	if (sram_read(tp, SRAM_GPHY_FW_VER) == __le16_to_cpu(phy->version))
5007	dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
5008	else
5009	dev_err(&tp->intf->dev, "ram code speedup mode fail\n");
5010	}
5011
5012	static int rtl8152_fw_phy_ver(struct r8152 *tp, struct fw_phy_ver *phy_ver)
5013	{
5014	u16 ver_addr, ver;
5015
5016	ver_addr = __le16_to_cpu(phy_ver->ver.addr);
5017	ver = __le16_to_cpu(phy_ver->ver.data);
5018
5019	rtl_reset_ocp_base(tp);
5020
5021	if (sram_read(tp, addr: ver_addr) >= ver) {
5022	dev_dbg(&tp->intf->dev, "PHY firmware has been the newest\n");
5023	return 0;
5024	}
5025
5026	sram_write(tp, addr: ver_addr, data: ver);
5027
5028	dev_dbg(&tp->intf->dev, "PHY firmware version %x\n", ver);
5029
5030	return ver;
5031	}
5032
5033	static void rtl8152_fw_phy_fixup(struct r8152 *tp, struct fw_phy_fixup *fix)
5034	{
5035	u16 addr, data;
5036
5037	rtl_reset_ocp_base(tp);
5038
5039	addr = __le16_to_cpu(fix->setting.addr);
5040	data = ocp_reg_read(tp, addr);
5041
5042	switch (__le16_to_cpu(fix->bit_cmd)) {
5043	case FW_FIXUP_AND:
5044	data &= __le16_to_cpu(fix->setting.data);
5045	break;
5046	case FW_FIXUP_OR:
5047	data |= __le16_to_cpu(fix->setting.data);
5048	break;
5049	case FW_FIXUP_NOT:
5050	data &= ~__le16_to_cpu(fix->setting.data);
5051	break;
5052	case FW_FIXUP_XOR:
5053	data ^= __le16_to_cpu(fix->setting.data);
5054	break;
5055	default:
5056	return;
5057	}
5058
5059	ocp_reg_write(tp, addr, data);
5060
5061	dev_dbg(&tp->intf->dev, "applied ocp %x %x\n", addr, data);
5062	}
5063
5064	static void rtl8152_fw_phy_union_apply(struct r8152 *tp, struct fw_phy_union *phy)
5065	{
5066	__le16 *data;
5067	u32 length;
5068	int i, num;
5069
5070	rtl_reset_ocp_base(tp);
5071
5072	num = phy->pre_num;
5073	for (i = 0; i < num; i++)
5074	sram_write(tp, __le16_to_cpu(phy->pre_set[i].addr),
5075	__le16_to_cpu(phy->pre_set[i].data));
5076
5077	length = __le32_to_cpu(phy->blk_hdr.length);
5078	length -= __le16_to_cpu(phy->fw_offset);
5079	num = length / 2;
5080	data = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset));
5081
5082	ocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg));
5083	for (i = 0; i < num; i++)
5084	ocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i]));
5085
5086	num = phy->bp_num;
5087	for (i = 0; i < num; i++)
5088	sram_write(tp, __le16_to_cpu(phy->bp[i].addr), __le16_to_cpu(phy->bp[i].data));
5089
5090	if (phy->bp_num && phy->bp_en.addr)
5091	sram_write(tp, __le16_to_cpu(phy->bp_en.addr), __le16_to_cpu(phy->bp_en.data));
5092
5093	dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
5094	}
5095
5096	static void rtl8152_fw_phy_nc_apply(struct r8152 *tp, struct fw_phy_nc *phy)
5097	{
5098	u16 mode_reg, bp_index;
5099	u32 length, i, num;
5100	__le16 *data;
5101
5102	rtl_reset_ocp_base(tp);
5103
5104	mode_reg = __le16_to_cpu(phy->mode_reg);
5105	sram_write(tp, addr: mode_reg, __le16_to_cpu(phy->mode_pre));
5106	sram_write(tp, __le16_to_cpu(phy->ba_reg),
5107	__le16_to_cpu(phy->ba_data));
5108
5109	length = __le32_to_cpu(phy->blk_hdr.length);
5110	length -= __le16_to_cpu(phy->fw_offset);
5111	num = length / 2;
5112	data = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset));
5113
5114	ocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg));
5115	for (i = 0; i < num; i++)
5116	ocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i]));
5117
5118	sram_write(tp, __le16_to_cpu(phy->patch_en_addr),
5119	__le16_to_cpu(phy->patch_en_value));
5120
5121	bp_index = __le16_to_cpu(phy->bp_start);
5122	num = __le16_to_cpu(phy->bp_num);
5123	for (i = 0; i < num; i++) {
5124	sram_write(tp, addr: bp_index, __le16_to_cpu(phy->bp[i]));
5125	bp_index += 2;
5126	}
5127
5128	sram_write(tp, addr: mode_reg, __le16_to_cpu(phy->mode_post));
5129
5130	dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
5131	}
5132
5133	static void rtl8152_fw_mac_apply(struct r8152 *tp, struct fw_mac *mac)
5134	{
5135	u16 bp_en_addr, type, fw_ver_reg;
5136	u32 length;
5137	u8 *data;
5138
5139	switch (__le32_to_cpu(mac->blk_hdr.type)) {
5140	case RTL_FW_PLA:
5141	type = MCU_TYPE_PLA;
5142	break;
5143	case RTL_FW_USB:
5144	type = MCU_TYPE_USB;
5145	break;
5146	default:
5147	return;
5148	}
5149
5150	fw_ver_reg = __le16_to_cpu(mac->fw_ver_reg);
5151	if (fw_ver_reg && ocp_read_byte(tp, MCU_TYPE_USB, index: fw_ver_reg) >= mac->fw_ver_data) {
5152	dev_dbg(&tp->intf->dev, "%s firmware has been the newest\n", type ? "PLA" : "USB");
5153	return;
5154	}
5155
5156	rtl_clear_bp(tp, type);
5157
5158	/* Enable backup/restore of MACDBG. This is required after clearing PLA
5159	* break points and before applying the PLA firmware.
5160	*/
5161	if (tp->version == RTL_VER_04 && type == MCU_TYPE_PLA &&
5162	!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST) & DEBUG_OE)) {
5163	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_PRE, DEBUG_LTSSM);
5164	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST, DEBUG_LTSSM);
5165	}
5166
5167	length = __le32_to_cpu(mac->blk_hdr.length);
5168	length -= __le16_to_cpu(mac->fw_offset);
5169
5170	data = (u8 *)mac;
5171	data += __le16_to_cpu(mac->fw_offset);
5172
5173	generic_ocp_write(tp, __le16_to_cpu(mac->fw_reg), byteen: 0xff, size: length, data,
5174	type);
5175
5176	ocp_write_word(tp, type, __le16_to_cpu(mac->bp_ba_addr),
5177	__le16_to_cpu(mac->bp_ba_value));
5178
5179	generic_ocp_write(tp, __le16_to_cpu(mac->bp_start), BYTE_EN_DWORD,
5180	__le16_to_cpu(mac->bp_num) << 1, data: mac->bp, type);
5181
5182	bp_en_addr = __le16_to_cpu(mac->bp_en_addr);
5183	if (bp_en_addr)
5184	ocp_write_word(tp, type, index: bp_en_addr,
5185	__le16_to_cpu(mac->bp_en_value));
5186
5187	if (fw_ver_reg)
5188	ocp_write_byte(tp, MCU_TYPE_USB, index: fw_ver_reg,
5189	data: mac->fw_ver_data);
5190
5191	dev_dbg(&tp->intf->dev, "successfully applied %s\n", mac->info);
5192	}
5193
5194	static void rtl8152_apply_firmware(struct r8152 *tp, bool power_cut)
5195	{
5196	struct rtl_fw *rtl_fw = &tp->rtl_fw;
5197	const struct firmware *fw;
5198	struct fw_header *fw_hdr;
5199	struct fw_phy_patch_key *key;
5200	u16 key_addr = 0;
5201	int i, patch_phy = 1;
5202
5203	if (IS_ERR_OR_NULL(ptr: rtl_fw->fw))
5204	return;
5205
5206	fw = rtl_fw->fw;
5207	fw_hdr = (struct fw_header *)fw->data;
5208
5209	if (rtl_fw->pre_fw)
5210	rtl_fw->pre_fw(tp);
5211
5212	for (i = offsetof(struct fw_header, blocks); i < fw->size;) {
5213	struct fw_block *block = (struct fw_block *)&fw->data[i];
5214
5215	switch (__le32_to_cpu(block->type)) {
5216	case RTL_FW_END:
5217	goto post_fw;
5218	case RTL_FW_PLA:
5219	case RTL_FW_USB:
5220	rtl8152_fw_mac_apply(tp, mac: (struct fw_mac *)block);
5221	break;
5222	case RTL_FW_PHY_START:
5223	if (!patch_phy)
5224	break;
5225	key = (struct fw_phy_patch_key *)block;
5226	key_addr = __le16_to_cpu(key->key_reg);
5227	rtl_pre_ram_code(tp, key_addr, __le16_to_cpu(key->key_data), wait: !power_cut);
5228	break;
5229	case RTL_FW_PHY_STOP:
5230	if (!patch_phy)
5231	break;
5232	WARN_ON(!key_addr);
5233	rtl_post_ram_code(tp, key_addr, wait: !power_cut);
5234	break;
5235	case RTL_FW_PHY_NC:
5236	rtl8152_fw_phy_nc_apply(tp, phy: (struct fw_phy_nc *)block);
5237	break;
5238	case RTL_FW_PHY_VER:
5239	patch_phy = rtl8152_fw_phy_ver(tp, phy_ver: (struct fw_phy_ver *)block);
5240	break;
5241	case RTL_FW_PHY_UNION_NC:
5242	case RTL_FW_PHY_UNION_NC1:
5243	case RTL_FW_PHY_UNION_NC2:
5244	case RTL_FW_PHY_UNION_UC2:
5245	case RTL_FW_PHY_UNION_UC:
5246	case RTL_FW_PHY_UNION_MISC:
5247	if (patch_phy)
5248	rtl8152_fw_phy_union_apply(tp, phy: (struct fw_phy_union *)block);
5249	break;
5250	case RTL_FW_PHY_FIXUP:
5251	if (patch_phy)
5252	rtl8152_fw_phy_fixup(tp, fix: (struct fw_phy_fixup *)block);
5253	break;
5254	case RTL_FW_PHY_SPEED_UP:
5255	rtl_ram_code_speed_up(tp, phy: (struct fw_phy_speed_up *)block, wait: !power_cut);
5256	break;
5257	default:
5258	break;
5259	}
5260
5261	i += ALIGN(__le32_to_cpu(block->length), 8);
5262	}
5263
5264	post_fw:
5265	if (rtl_fw->post_fw)
5266	rtl_fw->post_fw(tp);
5267
5268	rtl_reset_ocp_base(tp);
5269	strscpy(p: rtl_fw->version, q: fw_hdr->version, RTL_VER_SIZE);
5270	dev_info(&tp->intf->dev, "load %s successfully\n", rtl_fw->version);
5271	}
5272
5273	static void rtl8152_release_firmware(struct r8152 *tp)
5274	{
5275	struct rtl_fw *rtl_fw = &tp->rtl_fw;
5276
5277	if (!IS_ERR_OR_NULL(ptr: rtl_fw->fw)) {
5278	release_firmware(fw: rtl_fw->fw);
5279	rtl_fw->fw = NULL;
5280	}
5281	}
5282
5283	static int rtl8152_request_firmware(struct r8152 *tp)
5284	{
5285	struct rtl_fw *rtl_fw = &tp->rtl_fw;
5286	long rc;
5287
5288	if (rtl_fw->fw || !rtl_fw->fw_name) {
5289	dev_info(&tp->intf->dev, "skip request firmware\n");
5290	rc = 0;
5291	goto result;
5292	}
5293
5294	rc = request_firmware(fw: &rtl_fw->fw, name: rtl_fw->fw_name, device: &tp->intf->dev);
5295	if (rc < 0)
5296	goto result;
5297
5298	rc = rtl8152_check_firmware(tp, rtl_fw);
5299	if (rc < 0)
5300	release_firmware(fw: rtl_fw->fw);
5301
5302	result:
5303	if (rc) {
5304	rtl_fw->fw = ERR_PTR(error: rc);
5305
5306	dev_warn(&tp->intf->dev,
5307	"unable to load firmware patch %s (%ld)\n",
5308	rtl_fw->fw_name, rc);
5309	}
5310
5311	return rc;
5312	}
5313
5314	static void r8152_aldps_en(struct r8152 *tp, bool enable)
5315	{
5316	if (enable) {
5317	ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
5318	LINKENA | DIS_SDSAVE);
5319	} else {
5320	ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
5321	DIS_SDSAVE);
5322	msleep(msecs: 20);
5323	}
5324	}
5325
5326	static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
5327	{
5328	ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
5329	ocp_reg_write(tp, OCP_EEE_DATA, data: reg);
5330	ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
5331	}
5332
5333	static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
5334	{
5335	u16 data;
5336
5337	r8152_mmd_indirect(tp, dev, reg);
5338	data = ocp_reg_read(tp, OCP_EEE_DATA);
5339	ocp_reg_write(tp, OCP_EEE_AR, data: 0x0000);
5340
5341	return data;
5342	}
5343
5344	static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
5345	{
5346	r8152_mmd_indirect(tp, dev, reg);
5347	ocp_reg_write(tp, OCP_EEE_DATA, data);
5348	ocp_reg_write(tp, OCP_EEE_AR, data: 0x0000);
5349	}
5350
5351	static void r8152_eee_en(struct r8152 *tp, bool enable)
5352	{
5353	u16 config1, config2, config3;
5354	u32 ocp_data;
5355
5356	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
5357	config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
5358	config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
5359	config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
5360
5361	if (enable) {
5362	ocp_data |= EEE_RX_EN | EEE_TX_EN;
5363	config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
5364	config1 |= sd_rise_time(1);
5365	config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
5366	config3 |= fast_snr(42);
5367	} else {
5368	ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
5369	config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
5370	RX_QUIET_EN);
5371	config1 |= sd_rise_time(7);
5372	config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
5373	config3 |= fast_snr(511);
5374	}
5375
5376	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, data: ocp_data);
5377	ocp_reg_write(tp, OCP_EEE_CONFIG1, data: config1);
5378	ocp_reg_write(tp, OCP_EEE_CONFIG2, data: config2);
5379	ocp_reg_write(tp, OCP_EEE_CONFIG3, data: config3);
5380	}
5381
5382	static void r8153_eee_en(struct r8152 *tp, bool enable)
5383	{
5384	u32 ocp_data;
5385	u16 config;
5386
5387	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
5388	config = ocp_reg_read(tp, OCP_EEE_CFG);
5389
5390	if (enable) {
5391	ocp_data |= EEE_RX_EN | EEE_TX_EN;
5392	config |= EEE10_EN;
5393	} else {
5394	ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
5395	config &= ~EEE10_EN;
5396	}
5397
5398	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, data: ocp_data);
5399	ocp_reg_write(tp, OCP_EEE_CFG, data: config);
5400
5401	tp->ups_info.eee = enable;
5402	}
5403
5404	static void r8156_eee_en(struct r8152 *tp, bool enable)
5405	{
5406	u16 config;
5407
5408	r8153_eee_en(tp, enable);
5409
5410	config = ocp_reg_read(tp, OCP_EEE_ADV2);
5411
5412	if (enable)
5413	config |= MDIO_EEE_2_5GT;
5414	else
5415	config &= ~MDIO_EEE_2_5GT;
5416
5417	ocp_reg_write(tp, OCP_EEE_ADV2, data: config);
5418	}
5419
5420	static void rtl_eee_enable(struct r8152 *tp, bool enable)
5421	{
5422	switch (tp->version) {
5423	case RTL_VER_01:
5424	case RTL_VER_02:
5425	case RTL_VER_07:
5426	if (enable) {
5427	r8152_eee_en(tp, enable: true);
5428	r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV,
5429	data: tp->eee_adv);
5430	} else {
5431	r8152_eee_en(tp, enable: false);
5432	r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, data: 0);
5433	}
5434	break;
5435	case RTL_VER_03:
5436	case RTL_VER_04:
5437	case RTL_VER_05:
5438	case RTL_VER_06:
5439	case RTL_VER_08:
5440	case RTL_VER_09:
5441	case RTL_VER_14:
5442	if (enable) {
5443	r8153_eee_en(tp, enable: true);
5444	ocp_reg_write(tp, OCP_EEE_ADV, data: tp->eee_adv);
5445	} else {
5446	r8153_eee_en(tp, enable: false);
5447	ocp_reg_write(tp, OCP_EEE_ADV, data: 0);
5448	}
5449	break;
5450	case RTL_VER_10:
5451	case RTL_VER_11:
5452	case RTL_VER_12:
5453	case RTL_VER_13:
5454	case RTL_VER_15:
5455	if (enable) {
5456	r8156_eee_en(tp, enable: true);
5457	ocp_reg_write(tp, OCP_EEE_ADV, data: tp->eee_adv);
5458	} else {
5459	r8156_eee_en(tp, enable: false);
5460	ocp_reg_write(tp, OCP_EEE_ADV, data: 0);
5461	}
5462	break;
5463	default:
5464	break;
5465	}
5466	}
5467
5468	static void r8152b_enable_fc(struct r8152 *tp)
5469	{
5470	u16 anar;
5471
5472	anar = r8152_mdio_read(tp, MII_ADVERTISE);
5473	anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
5474	r8152_mdio_write(tp, MII_ADVERTISE, value: anar);
5475
5476	tp->ups_info.flow_control = true;
5477	}
5478
5479	static void rtl8152_disable(struct r8152 *tp)
5480	{
5481	r8152_aldps_en(tp, enable: false);
5482	rtl_disable(tp);
5483	r8152_aldps_en(tp, enable: true);
5484	}
5485
5486	static void r8152b_hw_phy_cfg(struct r8152 *tp)
5487	{
5488	rtl8152_apply_firmware(tp, power_cut: false);
5489	rtl_eee_enable(tp, enable: tp->eee_en);
5490	r8152_aldps_en(tp, enable: true);
5491	r8152b_enable_fc(tp);
5492
5493	set_bit(nr: PHY_RESET, addr: &tp->flags);
5494	}
5495
5496	static void wait_oob_link_list_ready(struct r8152 *tp)
5497	{
5498	u32 ocp_data;
5499	int i;
5500
5501	for (i = 0; i < 1000; i++) {
5502	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5503	if (ocp_data & LINK_LIST_READY)
5504	break;
5505	usleep_range(min: 1000, max: 2000);
5506	}
5507	}
5508
5509	static void r8156b_wait_loading_flash(struct r8152 *tp)
5510	{
5511	if ((ocp_read_word(tp, MCU_TYPE_PLA, PLA_GPHY_CTRL) & GPHY_FLASH) &&
5512	!(ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL) & BYPASS_FLASH)) {
5513	int i;
5514
5515	for (i = 0; i < 100; i++) {
5516	if (ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL) & GPHY_PATCH_DONE)
5517	break;
5518	usleep_range(min: 1000, max: 2000);
5519	}
5520	}
5521	}
5522
5523	static void r8152b_exit_oob(struct r8152 *tp)
5524	{
5525	u32 ocp_data;
5526
5527	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5528	ocp_data &= ~RCR_ACPT_ALL;
5529	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, data: ocp_data);
5530
5531	rxdy_gated_en(tp, enable: true);
5532	r8153_teredo_off(tp);
5533	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
5534	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, data: 0x00);
5535
5536	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5537	ocp_data &= ~NOW_IS_OOB;
5538	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, data: ocp_data);
5539
5540	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5541	ocp_data &= ~MCU_BORW_EN;
5542	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, data: ocp_data);
5543
5544	wait_oob_link_list_ready(tp);
5545
5546	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5547	ocp_data |= RE_INIT_LL;
5548	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, data: ocp_data);
5549
5550	wait_oob_link_list_ready(tp);
5551
5552	rtl8152_nic_reset(tp);
5553
5554	/* rx share fifo credit full threshold */
5555	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
5556
5557	if (tp->udev->speed == USB_SPEED_FULL ||
5558	tp->udev->speed == USB_SPEED_LOW) {
5559	/* rx share fifo credit near full threshold */
5560	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
5561	RXFIFO_THR2_FULL);
5562	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
5563	RXFIFO_THR3_FULL);
5564	} else {
5565	/* rx share fifo credit near full threshold */
5566	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
5567	RXFIFO_THR2_HIGH);
5568	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
5569	RXFIFO_THR3_HIGH);
5570	}
5571
5572	/* TX share fifo free credit full threshold */
5573	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
5574
5575	ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
5576	ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
5577	ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
5578	TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
5579
5580	rtl_rx_vlan_en(tp, enable: tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
5581
5582	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
5583
5584	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
5585	ocp_data |= TCR0_AUTO_FIFO;
5586	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, data: ocp_data);
5587	}
5588
5589	static void r8152b_enter_oob(struct r8152 *tp)
5590	{
5591	u32 ocp_data;
5592
5593	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5594	ocp_data &= ~NOW_IS_OOB;
5595	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, data: ocp_data);
5596
5597	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
5598	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
5599	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
5600
5601	rtl_disable(tp);
5602
5603	wait_oob_link_list_ready(tp);
5604
5605	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5606	ocp_data |= RE_INIT_LL;
5607	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, data: ocp_data);
5608
5609	wait_oob_link_list_ready(tp);
5610
5611	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
5612
5613	rtl_rx_vlan_en(tp, enable: true);
5614
5615	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
5616	ocp_data |= ALDPS_PROXY_MODE;
5617	ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, data: ocp_data);
5618
5619	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5620	ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
5621	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, data: ocp_data);
5622
5623	rxdy_gated_en(tp, enable: false);
5624
5625	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5626	ocp_data |= RCR_APM | RCR_AM | RCR_AB;
5627	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, data: ocp_data);
5628	}
5629
5630	static int r8153_pre_firmware_1(struct r8152 *tp)
5631	{
5632	int i;
5633
5634	/* Wait till the WTD timer is ready. It would take at most 104 ms. */
5635	for (i = 0; i < 104; i++) {
5636	u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_WDT1_CTRL);
5637
5638	if (!(ocp_data & WTD1_EN))
5639	break;
5640	usleep_range(min: 1000, max: 2000);
5641	}
5642
5643	return 0;
5644	}
5645
5646	static int r8153_post_firmware_1(struct r8152 *tp)
5647	{
5648	/* set USB_BP_4 to support USB_SPEED_SUPER only */
5649	if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER)
5650	ocp_write_word(tp, MCU_TYPE_USB, USB_BP_4, BP4_SUPER_ONLY);
5651
5652	/* reset UPHY timer to 36 ms */
5653	ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, data: 36000 / 16);
5654
5655	return 0;
5656	}
5657
5658	static int r8153_pre_firmware_2(struct r8152 *tp)
5659	{
5660	u32 ocp_data;
5661
5662	r8153_pre_firmware_1(tp);
5663
5664	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
5665	ocp_data &= ~FW_FIX_SUSPEND;
5666	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, data: ocp_data);
5667
5668	return 0;
5669	}
5670
5671	static int r8153_post_firmware_2(struct r8152 *tp)
5672	{
5673	u32 ocp_data;
5674
5675	/* enable bp0 if support USB_SPEED_SUPER only */
5676	if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER) {
5677	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
5678	ocp_data |= BIT(0);
5679	ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, data: ocp_data);
5680	}
5681
5682	/* reset UPHY timer to 36 ms */
5683	ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, data: 36000 / 16);
5684
5685	/* enable U3P3 check, set the counter to 4 */
5686	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, U3P3_CHECK_EN | 4);
5687
5688	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
5689	ocp_data |= FW_FIX_SUSPEND;
5690	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, data: ocp_data);
5691
5692	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
5693	ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
5694	ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, data: ocp_data);
5695
5696	return 0;
5697	}
5698
5699	static int r8153_post_firmware_3(struct r8152 *tp)
5700	{
5701	u32 ocp_data;
5702
5703	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
5704	ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
5705	ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, data: ocp_data);
5706
5707	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
5708	ocp_data |= FW_IP_RESET_EN;
5709	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, data: ocp_data);
5710
5711	return 0;
5712	}
5713
5714	static int r8153b_pre_firmware_1(struct r8152 *tp)
5715	{
5716	/* enable fc timer and set timer to 1 second. */
5717	ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER,
5718	CTRL_TIMER_EN | (1000 / 8));
5719
5720	return 0;
5721	}
5722
5723	static int r8153b_post_firmware_1(struct r8152 *tp)
5724	{
5725	u32 ocp_data;
5726
5727	/* enable bp0 for RTL8153-BND */
5728	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
5729	if (ocp_data & BND_MASK) {
5730	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
5731	ocp_data |= BIT(0);
5732	ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, data: ocp_data);
5733	}
5734
5735	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
5736	ocp_data |= FLOW_CTRL_PATCH_OPT;
5737	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, data: ocp_data);
5738
5739	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
5740	ocp_data |= FC_PATCH_TASK;
5741	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, data: ocp_data);
5742
5743	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
5744	ocp_data |= FW_IP_RESET_EN;
5745	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, data: ocp_data);
5746
5747	return 0;
5748	}
5749
5750	static int r8153c_post_firmware_1(struct r8152 *tp)
5751	{
5752	u32 ocp_data;
5753
5754	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
5755	ocp_data |= FLOW_CTRL_PATCH_2;
5756	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, data: ocp_data);
5757
5758	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
5759	ocp_data |= FC_PATCH_TASK;
5760	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, data: ocp_data);
5761
5762	return 0;
5763	}
5764
5765	static int r8156a_post_firmware_1(struct r8152 *tp)
5766	{
5767	u32 ocp_data;
5768
5769	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
5770	ocp_data |= FW_IP_RESET_EN;
5771	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, data: ocp_data);
5772
5773	/* Modify U3PHY parameter for compatibility issue */
5774	ocp_write_dword(tp, MCU_TYPE_USB, USB_UPHY3_MDCMDIO, data: 0x4026840e);
5775	ocp_write_dword(tp, MCU_TYPE_USB, USB_UPHY3_MDCMDIO, data: 0x4001acc9);
5776
5777	return 0;
5778	}
5779
5780	static void r8153_aldps_en(struct r8152 *tp, bool enable)
5781	{
5782	u16 data;
5783
5784	data = ocp_reg_read(tp, OCP_POWER_CFG);
5785	if (enable) {
5786	data |= EN_ALDPS;
5787	ocp_reg_write(tp, OCP_POWER_CFG, data);
5788	} else {
5789	int i;
5790
5791	data &= ~EN_ALDPS;
5792	ocp_reg_write(tp, OCP_POWER_CFG, data);
5793	for (i = 0; i < 20; i++) {
5794	usleep_range(min: 1000, max: 2000);
5795	if (ocp_read_word(tp, MCU_TYPE_PLA, index: 0xe000) & 0x0100)
5796	break;
5797	}
5798	}
5799
5800	tp->ups_info.aldps = enable;
5801	}
5802
5803	static void r8153_hw_phy_cfg(struct r8152 *tp)
5804	{
5805	u32 ocp_data;
5806	u16 data;
5807
5808	/* disable ALDPS before updating the PHY parameters */
5809	r8153_aldps_en(tp, enable: false);
5810
5811	/* disable EEE before updating the PHY parameters */
5812	rtl_eee_enable(tp, enable: false);
5813
5814	rtl8152_apply_firmware(tp, power_cut: false);
5815
5816	if (tp->version == RTL_VER_03) {
5817	data = ocp_reg_read(tp, OCP_EEE_CFG);
5818	data &= ~CTAP_SHORT_EN;
5819	ocp_reg_write(tp, OCP_EEE_CFG, data);
5820	}
5821
5822	data = ocp_reg_read(tp, OCP_POWER_CFG);
5823	data |= EEE_CLKDIV_EN;
5824	ocp_reg_write(tp, OCP_POWER_CFG, data);
5825
5826	data = ocp_reg_read(tp, OCP_DOWN_SPEED);
5827	data |= EN_10M_BGOFF;
5828	ocp_reg_write(tp, OCP_DOWN_SPEED, data);
5829	data = ocp_reg_read(tp, OCP_POWER_CFG);
5830	data |= EN_10M_PLLOFF;
5831	ocp_reg_write(tp, OCP_POWER_CFG, data);
5832	sram_write(tp, SRAM_IMPEDANCE, data: 0x0b13);
5833
5834	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
5835	ocp_data |= PFM_PWM_SWITCH;
5836	ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, data: ocp_data);
5837
5838	/* Enable LPF corner auto tune */
5839	sram_write(tp, SRAM_LPF_CFG, data: 0xf70f);
5840
5841	/* Adjust 10M Amplitude */
5842	sram_write(tp, SRAM_10M_AMP1, data: 0x00af);
5843	sram_write(tp, SRAM_10M_AMP2, data: 0x0208);
5844
5845	if (tp->eee_en)
5846	rtl_eee_enable(tp, enable: true);
5847
5848	r8153_aldps_en(tp, enable: true);
5849	r8152b_enable_fc(tp);
5850
5851	switch (tp->version) {
5852	case RTL_VER_03:
5853	case RTL_VER_04:
5854	break;
5855	case RTL_VER_05:
5856	case RTL_VER_06:
5857	default:
5858	r8153_u2p3en(tp, enable: true);
5859	break;
5860	}
5861
5862	set_bit(nr: PHY_RESET, addr: &tp->flags);
5863	}
5864
5865	static u32 r8152_efuse_read(struct r8152 *tp, u8 addr)
5866	{
5867	u32 ocp_data;
5868
5869	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr);
5870	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD);
5871	ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9; /* data of bit16 */
5872	ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA);
5873
5874	return ocp_data;
5875	}
5876
5877	static void r8153b_hw_phy_cfg(struct r8152 *tp)
5878	{
5879	u32 ocp_data;
5880	u16 data;
5881
5882	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
5883	if (ocp_data & PCUT_STATUS) {
5884	ocp_data &= ~PCUT_STATUS;
5885	ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, data: ocp_data);
5886	}
5887
5888	/* disable ALDPS before updating the PHY parameters */
5889	r8153_aldps_en(tp, enable: false);
5890
5891	/* disable EEE before updating the PHY parameters */
5892	rtl_eee_enable(tp, enable: false);
5893
5894	/* U1/U2/L1 idle timer. 500 us */
5895	ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, data: 500);
5896
5897	data = r8153_phy_status(tp, desired: 0);
5898
5899	switch (data) {
5900	case PHY_STAT_PWRDN:
5901	case PHY_STAT_EXT_INIT:
5902	rtl8152_apply_firmware(tp, power_cut: true);
5903
5904	data = r8152_mdio_read(tp, MII_BMCR);
5905	data &= ~BMCR_PDOWN;
5906	r8152_mdio_write(tp, MII_BMCR, value: data);
5907	break;
5908	case PHY_STAT_LAN_ON:
5909	default:
5910	rtl8152_apply_firmware(tp, power_cut: false);
5911	break;
5912	}
5913
5914	r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
5915
5916	data = sram_read(tp, SRAM_GREEN_CFG);
5917	data |= R_TUNE_EN;
5918	sram_write(tp, SRAM_GREEN_CFG, data);
5919	data = ocp_reg_read(tp, OCP_NCTL_CFG);
5920	data |= PGA_RETURN_EN;
5921	ocp_reg_write(tp, OCP_NCTL_CFG, data);
5922
5923	/* ADC Bias Calibration:
5924	* read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake
5925	* bit (bit3) to rebuild the real 16-bit data. Write the data to the
5926	* ADC ioffset.
5927	*/
5928	ocp_data = r8152_efuse_read(tp, addr: 0x7d);
5929	data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7));
5930	if (data != 0xffff)
5931	ocp_reg_write(tp, OCP_ADC_IOFFSET, data);
5932
5933	/* ups mode tx-link-pulse timing adjustment:
5934	* rg_saw_cnt = OCP reg 0xC426 Bit[13:0]
5935	* swr_cnt_1ms_ini = 16000000 / rg_saw_cnt
5936	*/
5937	ocp_data = ocp_reg_read(tp, addr: 0xc426);
5938	ocp_data &= 0x3fff;
5939	if (ocp_data) {
5940	u32 swr_cnt_1ms_ini;
5941
5942	swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK;
5943	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG);
5944	ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini;
5945	ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, data: ocp_data);
5946	}
5947
5948	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
5949	ocp_data |= PFM_PWM_SWITCH;
5950	ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, data: ocp_data);
5951
5952	/* Advnace EEE */
5953	if (!rtl_phy_patch_request(tp, request: true, wait: true)) {
5954	data = ocp_reg_read(tp, OCP_POWER_CFG);
5955	data |= EEE_CLKDIV_EN;
5956	ocp_reg_write(tp, OCP_POWER_CFG, data);
5957	tp->ups_info.eee_ckdiv = true;
5958
5959	data = ocp_reg_read(tp, OCP_DOWN_SPEED);
5960	data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV;
5961	ocp_reg_write(tp, OCP_DOWN_SPEED, data);
5962	tp->ups_info.eee_cmod_lv = true;
5963	tp->ups_info._10m_ckdiv = true;
5964	tp->ups_info.eee_plloff_giga = true;
5965
5966	ocp_reg_write(tp, OCP_SYSCLK_CFG, data: 0);
5967	ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5));
5968	tp->ups_info._250m_ckdiv = true;
5969
5970	rtl_phy_patch_request(tp, request: false, wait: true);
5971	}
5972
5973	if (tp->eee_en)
5974	rtl_eee_enable(tp, enable: true);
5975
5976	r8153_aldps_en(tp, enable: true);
5977	r8152b_enable_fc(tp);
5978
5979	set_bit(nr: PHY_RESET, addr: &tp->flags);
5980	}
5981
5982	static void r8153c_hw_phy_cfg(struct r8152 *tp)
5983	{
5984	r8153b_hw_phy_cfg(tp);
5985
5986	tp->ups_info.r_tune = true;
5987	}
5988
5989	static void rtl8153_change_mtu(struct r8152 *tp)
5990	{
5991	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu));
5992	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
5993	}
5994
5995	static void r8153_first_init(struct r8152 *tp)
5996	{
5997	u32 ocp_data;
5998
5999	rxdy_gated_en(tp, enable: true);
6000	r8153_teredo_off(tp);
6001
6002	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
6003	ocp_data &= ~RCR_ACPT_ALL;
6004	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, data: ocp_data);
6005
6006	rtl8152_nic_reset(tp);
6007	rtl_reset_bmu(tp);
6008
6009	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6010	ocp_data &= ~NOW_IS_OOB;
6011	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, data: ocp_data);
6012
6013	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6014	ocp_data &= ~MCU_BORW_EN;
6015	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, data: ocp_data);
6016
6017	wait_oob_link_list_ready(tp);
6018
6019	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6020	ocp_data |= RE_INIT_LL;
6021	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, data: ocp_data);
6022
6023	wait_oob_link_list_ready(tp);
6024
6025	rtl_rx_vlan_en(tp, enable: tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
6026
6027	rtl8153_change_mtu(tp);
6028
6029	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
6030	ocp_data |= TCR0_AUTO_FIFO;
6031	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, data: ocp_data);
6032
6033	rtl8152_nic_reset(tp);
6034
6035	/* rx share fifo credit full threshold */
6036	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
6037	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
6038	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
6039	/* TX share fifo free credit full threshold */
6040	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
6041	}
6042
6043	static void r8153_enter_oob(struct r8152 *tp)
6044	{
6045	u32 ocp_data;
6046
6047	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6048	ocp_data &= ~NOW_IS_OOB;
6049	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, data: ocp_data);
6050
6051	/* RX FIFO settings for OOB */
6052	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
6053	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
6054	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
6055
6056	rtl_disable(tp);
6057	rtl_reset_bmu(tp);
6058
6059	wait_oob_link_list_ready(tp);
6060
6061	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6062	ocp_data |= RE_INIT_LL;
6063	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, data: ocp_data);
6064
6065	wait_oob_link_list_ready(tp);
6066
6067	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, data: 1522);
6068	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_DEFAULT);
6069
6070	switch (tp->version) {
6071	case RTL_VER_03:
6072	case RTL_VER_04:
6073	case RTL_VER_05:
6074	case RTL_VER_06:
6075	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
6076	ocp_data &= ~TEREDO_WAKE_MASK;
6077	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, data: ocp_data);
6078	break;
6079
6080	case RTL_VER_08:
6081	case RTL_VER_09:
6082	case RTL_VER_14:
6083	/* Clear teredo wake event. bit[15:8] is the teredo wakeup
6084	* type. Set it to zero. bits[7:0] are the W1C bits about
6085	* the events. Set them to all 1 to clear them.
6086	*/
6087	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, data: 0x00ff);
6088	break;
6089
6090	default:
6091	break;
6092	}
6093
6094	rtl_rx_vlan_en(tp, enable: true);
6095
6096	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
6097	ocp_data |= ALDPS_PROXY_MODE;
6098	ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, data: ocp_data);
6099
6100	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6101	ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
6102	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, data: ocp_data);
6103
6104	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6105	ocp_data |= MCU_BORW_EN;
6106	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, data: ocp_data);
6107
6108	rxdy_gated_en(tp, enable: false);
6109
6110	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
6111	ocp_data |= RCR_APM | RCR_AM | RCR_AB;
6112	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, data: ocp_data);
6113	}
6114
6115	static void rtl8153_disable(struct r8152 *tp)
6116	{
6117	r8153_aldps_en(tp, enable: false);
6118	rtl_disable(tp);
6119	rtl_reset_bmu(tp);
6120	r8153_aldps_en(tp, enable: true);
6121	}
6122
6123	static u32 fc_pause_on_auto(struct r8152 *tp)
6124	{
6125	return (ALIGN(mtu_to_size(tp->netdev->mtu), 1024) + 6 * 1024);
6126	}
6127
6128	static u32 fc_pause_off_auto(struct r8152 *tp)
6129	{
6130	return (ALIGN(mtu_to_size(tp->netdev->mtu), 1024) + 14 * 1024);
6131	}
6132
6133	static void r8156_fc_parameter(struct r8152 *tp)
6134	{
6135	u32 pause_on = tp->fc_pause_on ? tp->fc_pause_on : fc_pause_on_auto(tp);
6136	u32 pause_off = tp->fc_pause_off ? tp->fc_pause_off : fc_pause_off_auto(tp);
6137
6138	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, data: pause_on / 16);
6139	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, data: pause_off / 16);
6140	}
6141
6142	static int rtl8156_enable(struct r8152 *tp)
6143	{
6144	u32 ocp_data;
6145	u16 speed;
6146
6147	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
6148	return -ENODEV;
6149
6150	r8156_fc_parameter(tp);
6151	set_tx_qlen(tp);
6152	rtl_set_eee_plus(tp);
6153	r8153_set_rx_early_timeout(tp);
6154	r8153_set_rx_early_size(tp);
6155
6156	speed = rtl8152_get_speed(tp);
6157	rtl_set_ifg(tp, speed);
6158
6159	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
6160	if (speed & _2500bps)
6161	ocp_data &= ~IDLE_SPDWN_EN;
6162	else
6163	ocp_data |= IDLE_SPDWN_EN;
6164	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, data: ocp_data);
6165
6166	if (speed & _1000bps)
6167	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, data: 0x11);
6168	else if (speed & _500bps)
6169	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, data: 0x3d);
6170
6171	if (tp->udev->speed == USB_SPEED_HIGH) {
6172	/* USB 0xb45e[3:0] l1_nyet_hird */
6173	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_L1_CTRL);
6174	ocp_data &= ~0xf;
6175	if (is_flow_control(speed))
6176	ocp_data |= 0xf;
6177	else
6178	ocp_data |= 0x1;
6179	ocp_write_word(tp, MCU_TYPE_USB, USB_L1_CTRL, data: ocp_data);
6180	}
6181
6182	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
6183	ocp_data &= ~FC_PATCH_TASK;
6184	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, data: ocp_data);
6185	usleep_range(min: 1000, max: 2000);
6186	ocp_data |= FC_PATCH_TASK;
6187	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, data: ocp_data);
6188
6189	return rtl_enable(tp);
6190	}
6191
6192	static void rtl8156_disable(struct r8152 *tp)
6193	{
6194	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, data: 0);
6195	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, data: 0);
6196
6197	rtl8153_disable(tp);
6198	}
6199
6200	static int rtl8156b_enable(struct r8152 *tp)
6201	{
6202	u32 ocp_data;
6203	u16 speed;
6204
6205	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
6206	return -ENODEV;
6207
6208	set_tx_qlen(tp);
6209	rtl_set_eee_plus(tp);
6210
6211	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM);
6212	ocp_data &= ~RX_AGGR_NUM_MASK;
6213	ocp_write_word(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM, data: ocp_data);
6214
6215	r8153_set_rx_early_timeout(tp);
6216	r8153_set_rx_early_size(tp);
6217
6218	speed = rtl8152_get_speed(tp);
6219	rtl_set_ifg(tp, speed);
6220
6221	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
6222	if (speed & _2500bps)
6223	ocp_data &= ~IDLE_SPDWN_EN;
6224	else
6225	ocp_data |= IDLE_SPDWN_EN;
6226	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, data: ocp_data);
6227
6228	if (tp->udev->speed == USB_SPEED_HIGH) {
6229	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_L1_CTRL);
6230	ocp_data &= ~0xf;
6231	if (is_flow_control(speed))
6232	ocp_data |= 0xf;
6233	else
6234	ocp_data |= 0x1;
6235	ocp_write_word(tp, MCU_TYPE_USB, USB_L1_CTRL, data: ocp_data);
6236	}
6237
6238	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
6239	ocp_data &= ~FC_PATCH_TASK;
6240	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, data: ocp_data);
6241	usleep_range(min: 1000, max: 2000);
6242	ocp_data |= FC_PATCH_TASK;
6243	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, data: ocp_data);
6244
6245	return rtl_enable(tp);
6246	}
6247
6248	static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,
6249	u32 advertising)
6250	{
6251	u16 bmcr;
6252	int ret = 0;
6253
6254	if (autoneg == AUTONEG_DISABLE) {
6255	if (duplex != DUPLEX_HALF && duplex != DUPLEX_FULL)
6256	return -EINVAL;
6257
6258	switch (speed) {
6259	case SPEED_10:
6260	bmcr = BMCR_SPEED10;
6261	if (duplex == DUPLEX_FULL) {
6262	bmcr |= BMCR_FULLDPLX;
6263	tp->ups_info.speed_duplex = FORCE_10M_FULL;
6264	} else {
6265	tp->ups_info.speed_duplex = FORCE_10M_HALF;
6266	}
6267	break;
6268	case SPEED_100:
6269	bmcr = BMCR_SPEED100;
6270	if (duplex == DUPLEX_FULL) {
6271	bmcr |= BMCR_FULLDPLX;
6272	tp->ups_info.speed_duplex = FORCE_100M_FULL;
6273	} else {
6274	tp->ups_info.speed_duplex = FORCE_100M_HALF;
6275	}
6276	break;
6277	case SPEED_1000:
6278	if (tp->mii.supports_gmii) {
6279	bmcr = BMCR_SPEED1000 | BMCR_FULLDPLX;
6280	tp->ups_info.speed_duplex = NWAY_1000M_FULL;
6281	break;
6282	}
6283	fallthrough;
6284	default:
6285	ret = -EINVAL;
6286	goto out;
6287	}
6288
6289	if (duplex == DUPLEX_FULL)
6290	tp->mii.full_duplex = 1;
6291	else
6292	tp->mii.full_duplex = 0;
6293
6294	tp->mii.force_media = 1;
6295	} else {
6296	u16 orig, new1;
6297	u32 support;
6298
6299	support = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
6300	RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
6301
6302	if (tp->mii.supports_gmii) {
6303	support |= RTL_ADVERTISED_1000_FULL;
6304
6305	if (tp->support_2500full)
6306	support |= RTL_ADVERTISED_2500_FULL;
6307	}
6308
6309	if (!(advertising & support))
6310	return -EINVAL;
6311
6312	orig = r8152_mdio_read(tp, MII_ADVERTISE);
6313	new1 = orig & ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
6314	ADVERTISE_100HALF | ADVERTISE_100FULL);
6315	if (advertising & RTL_ADVERTISED_10_HALF) {
6316	new1 |= ADVERTISE_10HALF;
6317	tp->ups_info.speed_duplex = NWAY_10M_HALF;
6318	}
6319	if (advertising & RTL_ADVERTISED_10_FULL) {
6320	new1 |= ADVERTISE_10FULL;
6321	tp->ups_info.speed_duplex = NWAY_10M_FULL;
6322	}
6323
6324	if (advertising & RTL_ADVERTISED_100_HALF) {
6325	new1 |= ADVERTISE_100HALF;
6326	tp->ups_info.speed_duplex = NWAY_100M_HALF;
6327	}
6328	if (advertising & RTL_ADVERTISED_100_FULL) {
6329	new1 |= ADVERTISE_100FULL;
6330	tp->ups_info.speed_duplex = NWAY_100M_FULL;
6331	}
6332
6333	if (orig != new1) {
6334	r8152_mdio_write(tp, MII_ADVERTISE, value: new1);
6335	tp->mii.advertising = new1;
6336	}
6337
6338	if (tp->mii.supports_gmii) {
6339	orig = r8152_mdio_read(tp, MII_CTRL1000);
6340	new1 = orig & ~(ADVERTISE_1000FULL |
6341	ADVERTISE_1000HALF);
6342
6343	if (advertising & RTL_ADVERTISED_1000_FULL) {
6344	new1 |= ADVERTISE_1000FULL;
6345	tp->ups_info.speed_duplex = NWAY_1000M_FULL;
6346	}
6347
6348	if (orig != new1)
6349	r8152_mdio_write(tp, MII_CTRL1000, value: new1);
6350	}
6351
6352	if (tp->support_2500full) {
6353	orig = ocp_reg_read(tp, OCP_10GBT_CTRL);
6354	new1 = orig & ~MDIO_AN_10GBT_CTRL_ADV2_5G;
6355
6356	if (advertising & RTL_ADVERTISED_2500_FULL) {
6357	new1 |= MDIO_AN_10GBT_CTRL_ADV2_5G;
6358	tp->ups_info.speed_duplex = NWAY_2500M_FULL;
6359	}
6360
6361	if (orig != new1)
6362	ocp_reg_write(tp, OCP_10GBT_CTRL, data: new1);
6363	}
6364
6365	bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
6366
6367	tp->mii.force_media = 0;
6368	}
6369
6370	if (test_and_clear_bit(nr: PHY_RESET, addr: &tp->flags))
6371	bmcr |= BMCR_RESET;
6372
6373	r8152_mdio_write(tp, MII_BMCR, value: bmcr);
6374
6375	if (bmcr & BMCR_RESET) {
6376	int i;
6377
6378	for (i = 0; i < 50; i++) {
6379	msleep(msecs: 20);
6380	if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
6381	break;
6382	}
6383	}
6384
6385	out:
6386	return ret;
6387	}
6388
6389	static void rtl8152_up(struct r8152 *tp)
6390	{
6391	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
6392	return;
6393
6394	r8152_aldps_en(tp, enable: false);
6395	r8152b_exit_oob(tp);
6396	r8152_aldps_en(tp, enable: true);
6397	}
6398
6399	static void rtl8152_down(struct r8152 *tp)
6400	{
6401	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
6402	rtl_drop_queued_tx(tp);
6403	return;
6404	}
6405
6406	r8152_power_cut_en(tp, enable: false);
6407	r8152_aldps_en(tp, enable: false);
6408	r8152b_enter_oob(tp);
6409	r8152_aldps_en(tp, enable: true);
6410	}
6411
6412	static void rtl8153_up(struct r8152 *tp)
6413	{
6414	u32 ocp_data;
6415
6416	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
6417	return;
6418
6419	r8153_u1u2en(tp, enable: false);
6420	r8153_u2p3en(tp, enable: false);
6421	r8153_aldps_en(tp, enable: false);
6422	r8153_first_init(tp);
6423
6424	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
6425	ocp_data |= LANWAKE_CLR_EN;
6426	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, data: ocp_data);
6427
6428	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
6429	ocp_data &= ~LANWAKE_PIN;
6430	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, data: ocp_data);
6431
6432	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1);
6433	ocp_data &= ~DELAY_PHY_PWR_CHG;
6434	ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1, data: ocp_data);
6435
6436	r8153_aldps_en(tp, enable: true);
6437
6438	switch (tp->version) {
6439	case RTL_VER_03:
6440	case RTL_VER_04:
6441	break;
6442	case RTL_VER_05:
6443	case RTL_VER_06:
6444	default:
6445	r8153_u2p3en(tp, enable: true);
6446	break;
6447	}
6448
6449	r8153_u1u2en(tp, enable: true);
6450	}
6451
6452	static void rtl8153_down(struct r8152 *tp)
6453	{
6454	u32 ocp_data;
6455
6456	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
6457	rtl_drop_queued_tx(tp);
6458	return;
6459	}
6460
6461	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
6462	ocp_data &= ~LANWAKE_CLR_EN;
6463	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, data: ocp_data);
6464
6465	r8153_u1u2en(tp, enable: false);
6466	r8153_u2p3en(tp, enable: false);
6467	r8153_power_cut_en(tp, enable: false);
6468	r8153_aldps_en(tp, enable: false);
6469	r8153_enter_oob(tp);
6470	r8153_aldps_en(tp, enable: true);
6471	}
6472
6473	static void rtl8153b_up(struct r8152 *tp)
6474	{
6475	u32 ocp_data;
6476
6477	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
6478	return;
6479
6480	r8153b_u1u2en(tp, enable: false);
6481	r8153_u2p3en(tp, enable: false);
6482	r8153_aldps_en(tp, enable: false);
6483
6484	r8153_first_init(tp);
6485	ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
6486
6487	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6488	ocp_data &= ~PLA_MCU_SPDWN_EN;
6489	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, data: ocp_data);
6490
6491	r8153_aldps_en(tp, enable: true);
6492
6493	if (tp->udev->speed >= USB_SPEED_SUPER)
6494	r8153b_u1u2en(tp, enable: true);
6495	}
6496
6497	static void rtl8153b_down(struct r8152 *tp)
6498	{
6499	u32 ocp_data;
6500
6501	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
6502	rtl_drop_queued_tx(tp);
6503	return;
6504	}
6505
6506	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6507	ocp_data |= PLA_MCU_SPDWN_EN;
6508	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, data: ocp_data);
6509
6510	r8153b_u1u2en(tp, enable: false);
6511	r8153_u2p3en(tp, enable: false);
6512	r8153b_power_cut_en(tp, enable: false);
6513	r8153_aldps_en(tp, enable: false);
6514	r8153_enter_oob(tp);
6515	r8153_aldps_en(tp, enable: true);
6516	}
6517
6518	static void rtl8153c_change_mtu(struct r8152 *tp)
6519	{
6520	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu));
6521	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, data: 10 * 1024 / 64);
6522
6523	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, data: 512 / 64);
6524
6525	/* Adjust the tx fifo free credit full threshold, otherwise
6526	* the fifo would be too small to send a jumbo frame packet.
6527	*/
6528	if (tp->netdev->mtu < 8000)
6529	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, data: 2048 / 8);
6530	else
6531	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, data: 900 / 8);
6532	}
6533
6534	static void rtl8153c_up(struct r8152 *tp)
6535	{
6536	u32 ocp_data;
6537
6538	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
6539	return;
6540
6541	r8153b_u1u2en(tp, enable: false);
6542	r8153_u2p3en(tp, enable: false);
6543	r8153_aldps_en(tp, enable: false);
6544
6545	rxdy_gated_en(tp, enable: true);
6546	r8153_teredo_off(tp);
6547
6548	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
6549	ocp_data &= ~RCR_ACPT_ALL;
6550	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, data: ocp_data);
6551
6552	rtl8152_nic_reset(tp);
6553	rtl_reset_bmu(tp);
6554
6555	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6556	ocp_data &= ~NOW_IS_OOB;
6557	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, data: ocp_data);
6558
6559	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6560	ocp_data &= ~MCU_BORW_EN;
6561	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, data: ocp_data);
6562
6563	wait_oob_link_list_ready(tp);
6564
6565	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6566	ocp_data |= RE_INIT_LL;
6567	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, data: ocp_data);
6568
6569	wait_oob_link_list_ready(tp);
6570
6571	rtl_rx_vlan_en(tp, enable: tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
6572
6573	rtl8153c_change_mtu(tp);
6574
6575	rtl8152_nic_reset(tp);
6576
6577	/* rx share fifo credit full threshold */
6578	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, data: 0x02);
6579	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, data: 0x08);
6580	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
6581	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
6582
6583	ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
6584
6585	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
6586
6587	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
6588	ocp_data |= BIT(8);
6589	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, data: ocp_data);
6590
6591	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
6592
6593	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6594	ocp_data &= ~PLA_MCU_SPDWN_EN;
6595	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, data: ocp_data);
6596
6597	r8153_aldps_en(tp, enable: true);
6598	r8153b_u1u2en(tp, enable: true);
6599	}
6600
6601	static void rtl8156_change_mtu(struct r8152 *tp)
6602	{
6603	u32 rx_max_size = mtu_to_size(tp->netdev->mtu);
6604
6605	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, data: rx_max_size);
6606	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
6607	r8156_fc_parameter(tp);
6608
6609	/* TX share fifo free credit full threshold */
6610	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, data: 512 / 64);
6611	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL,
6612	ALIGN(rx_max_size + sizeof(struct tx_desc), 1024) / 16);
6613	}
6614
6615	static void rtl8156_up(struct r8152 *tp)
6616	{
6617	u32 ocp_data;
6618
6619	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
6620	return;
6621
6622	r8153b_u1u2en(tp, enable: false);
6623	r8153_u2p3en(tp, enable: false);
6624	r8153_aldps_en(tp, enable: false);
6625
6626	rxdy_gated_en(tp, enable: true);
6627	r8153_teredo_off(tp);
6628
6629	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
6630	ocp_data &= ~RCR_ACPT_ALL;
6631	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, data: ocp_data);
6632
6633	rtl8152_nic_reset(tp);
6634	rtl_reset_bmu(tp);
6635
6636	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6637	ocp_data &= ~NOW_IS_OOB;
6638	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, data: ocp_data);
6639
6640	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6641	ocp_data &= ~MCU_BORW_EN;
6642	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, data: ocp_data);
6643
6644	rtl_rx_vlan_en(tp, enable: tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
6645
6646	rtl8156_change_mtu(tp);
6647
6648	switch (tp->version) {
6649	case RTL_TEST_01:
6650	case RTL_VER_10:
6651	case RTL_VER_11:
6652	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_CONFIG);
6653	ocp_data |= ACT_ODMA;
6654	ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_CONFIG, data: ocp_data);
6655	break;
6656	default:
6657	break;
6658	}
6659
6660	/* share FIFO settings */
6661	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL);
6662	ocp_data &= ~RXFIFO_FULL_MASK;
6663	ocp_data |= 0x08;
6664	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, data: ocp_data);
6665
6666	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6667	ocp_data &= ~PLA_MCU_SPDWN_EN;
6668	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, data: ocp_data);
6669
6670	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION);
6671	ocp_data &= ~(RG_PWRDN_EN | ALL_SPEED_OFF);
6672	ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, data: ocp_data);
6673
6674	ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, data: 0x00600400);
6675
6676	if (tp->saved_wolopts != __rtl_get_wol(tp)) {
6677	netif_warn(tp, ifup, tp->netdev, "wol setting is changed\n");
6678	__rtl_set_wol(tp, wolopts: tp->saved_wolopts);
6679	}
6680
6681	r8153_aldps_en(tp, enable: true);
6682	r8153_u2p3en(tp, enable: true);
6683
6684	if (tp->udev->speed >= USB_SPEED_SUPER)
6685	r8153b_u1u2en(tp, enable: true);
6686	}
6687
6688	static void rtl8156_down(struct r8152 *tp)
6689	{
6690	u32 ocp_data;
6691
6692	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
6693	rtl_drop_queued_tx(tp);
6694	return;
6695	}
6696
6697	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6698	ocp_data |= PLA_MCU_SPDWN_EN;
6699	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, data: ocp_data);
6700
6701	r8153b_u1u2en(tp, enable: false);
6702	r8153_u2p3en(tp, enable: false);
6703	r8153b_power_cut_en(tp, enable: false);
6704	r8153_aldps_en(tp, enable: false);
6705
6706	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6707	ocp_data &= ~NOW_IS_OOB;
6708	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, data: ocp_data);
6709
6710	/* RX FIFO settings for OOB */
6711	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, data: 64 / 16);
6712	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, data: 1024 / 16);
6713	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, data: 4096 / 16);
6714
6715	rtl_disable(tp);
6716	rtl_reset_bmu(tp);
6717
6718	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, data: 1522);
6719	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_DEFAULT);
6720
6721	/* Clear teredo wake event. bit[15:8] is the teredo wakeup
6722	* type. Set it to zero. bits[7:0] are the W1C bits about
6723	* the events. Set them to all 1 to clear them.
6724	*/
6725	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, data: 0x00ff);
6726
6727	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6728	ocp_data |= NOW_IS_OOB;
6729	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, data: ocp_data);
6730
6731	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6732	ocp_data |= MCU_BORW_EN;
6733	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, data: ocp_data);
6734
6735	rtl_rx_vlan_en(tp, enable: true);
6736	rxdy_gated_en(tp, enable: false);
6737
6738	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
6739	ocp_data |= RCR_APM | RCR_AM | RCR_AB;
6740	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, data: ocp_data);
6741
6742	r8153_aldps_en(tp, enable: true);
6743	}
6744
6745	static bool rtl8152_in_nway(struct r8152 *tp)
6746	{
6747	u16 nway_state;
6748
6749	ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, data: 0x2000);
6750	tp->ocp_base = 0x2000;
6751	ocp_write_byte(tp, MCU_TYPE_PLA, index: 0xb014, data: 0x4c); /* phy state */
6752	nway_state = ocp_read_word(tp, MCU_TYPE_PLA, index: 0xb01a);
6753
6754	/* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
6755	if (nway_state & 0xc000)
6756	return false;
6757	else
6758	return true;
6759	}
6760
6761	static bool rtl8153_in_nway(struct r8152 *tp)
6762	{
6763	u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
6764
6765	if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
6766	return false;
6767	else
6768	return true;
6769	}
6770
6771	static void r8156_mdio_force_mode(struct r8152 *tp)
6772	{
6773	u16 data;
6774
6775	/* Select force mode through 0xa5b4 bit 15
6776	* 0: MDIO force mode
6777	* 1: MMD force mode
6778	*/
6779	data = ocp_reg_read(tp, addr: 0xa5b4);
6780	if (data & BIT(15)) {
6781	data &= ~BIT(15);
6782	ocp_reg_write(tp, addr: 0xa5b4, data);
6783	}
6784	}
6785
6786	static void set_carrier(struct r8152 *tp)
6787	{
6788	struct net_device *netdev = tp->netdev;
6789	struct napi_struct *napi = &tp->napi;
6790	u16 speed;
6791
6792	speed = rtl8152_get_speed(tp);
6793
6794	if (speed & LINK_STATUS) {
6795	if (!netif_carrier_ok(dev: netdev)) {
6796	tp->rtl_ops.enable(tp);
6797	netif_stop_queue(dev: netdev);
6798	napi_disable(n: napi);
6799	netif_carrier_on(dev: netdev);
6800	rtl_start_rx(tp);
6801	clear_bit(nr: RTL8152_SET_RX_MODE, addr: &tp->flags);
6802	_rtl8152_set_rx_mode(netdev);
6803	napi_enable(n: napi);
6804	netif_wake_queue(dev: netdev);
6805	netif_info(tp, link, netdev, "carrier on\n");
6806	} else if (netif_queue_stopped(dev: netdev) &&
6807	skb_queue_len(list_: &tp->tx_queue) < tp->tx_qlen) {
6808	netif_wake_queue(dev: netdev);
6809	}
6810	} else {
6811	if (netif_carrier_ok(dev: netdev)) {
6812	netif_carrier_off(dev: netdev);
6813	tasklet_disable(t: &tp->tx_tl);
6814	napi_disable(n: napi);
6815	tp->rtl_ops.disable(tp);
6816	napi_enable(n: napi);
6817	tasklet_enable(t: &tp->tx_tl);
6818	netif_info(tp, link, netdev, "carrier off\n");
6819	}
6820	}
6821	}
6822
6823	static void rtl_work_func_t(struct work_struct *work)
6824	{
6825	struct r8152 *tp = container_of(work, struct r8152, schedule.work);
6826
6827	/* If the device is unplugged or !netif_running(), the workqueue
6828	* doesn't need to wake the device, and could return directly.
6829	*/
6830	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags) || !netif_running(dev: tp->netdev))
6831	return;
6832
6833	if (usb_autopm_get_interface(intf: tp->intf) < 0)
6834	return;
6835
6836	if (!test_bit(WORK_ENABLE, &tp->flags))
6837	goto out1;
6838
6839	if (!mutex_trylock(lock: &tp->control)) {
6840	schedule_delayed_work(dwork: &tp->schedule, delay: 0);
6841	goto out1;
6842	}
6843
6844	if (test_and_clear_bit(nr: RTL8152_LINK_CHG, addr: &tp->flags))
6845	set_carrier(tp);
6846
6847	if (test_and_clear_bit(nr: RTL8152_SET_RX_MODE, addr: &tp->flags))
6848	_rtl8152_set_rx_mode(netdev: tp->netdev);
6849
6850	/* don't schedule tasket before linking */
6851	if (test_and_clear_bit(nr: SCHEDULE_TASKLET, addr: &tp->flags) &&
6852	netif_carrier_ok(dev: tp->netdev))
6853	tasklet_schedule(t: &tp->tx_tl);
6854
6855	if (test_and_clear_bit(nr: RX_EPROTO, addr: &tp->flags) &&
6856	!list_empty(head: &tp->rx_done))
6857	napi_schedule(n: &tp->napi);
6858
6859	mutex_unlock(lock: &tp->control);
6860
6861	out1:
6862	usb_autopm_put_interface(intf: tp->intf);
6863	}
6864
6865	static void rtl_hw_phy_work_func_t(struct work_struct *work)
6866	{
6867	struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);
6868
6869	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
6870	return;
6871
6872	if (usb_autopm_get_interface(intf: tp->intf) < 0)
6873	return;
6874
6875	mutex_lock(&tp->control);
6876
6877	if (rtl8152_request_firmware(tp) == -ENODEV && tp->rtl_fw.retry) {
6878	tp->rtl_fw.retry = false;
6879	tp->rtl_fw.fw = NULL;
6880
6881	/* Delay execution in case request_firmware() is not ready yet.
6882	*/
6883	queue_delayed_work(wq: system_long_wq, dwork: &tp->hw_phy_work, HZ * 10);
6884	goto ignore_once;
6885	}
6886
6887	tp->rtl_ops.hw_phy_cfg(tp);
6888
6889	rtl8152_set_speed(tp, autoneg: tp->autoneg, speed: tp->speed, duplex: tp->duplex,
6890	advertising: tp->advertising);
6891
6892	ignore_once:
6893	mutex_unlock(lock: &tp->control);
6894
6895	usb_autopm_put_interface(intf: tp->intf);
6896	}
6897
6898	#ifdef CONFIG_PM_SLEEP
6899	static int rtl_notifier(struct notifier_block *nb, unsigned long action,
6900	void *data)
6901	{
6902	struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
6903
6904	switch (action) {
6905	case PM_HIBERNATION_PREPARE:
6906	case PM_SUSPEND_PREPARE:
6907	usb_autopm_get_interface(intf: tp->intf);
6908	break;
6909
6910	case PM_POST_HIBERNATION:
6911	case PM_POST_SUSPEND:
6912	usb_autopm_put_interface(intf: tp->intf);
6913	break;
6914
6915	case PM_POST_RESTORE:
6916	case PM_RESTORE_PREPARE:
6917	default:
6918	break;
6919	}
6920
6921	return NOTIFY_DONE;
6922	}
6923	#endif
6924
6925	static int rtl8152_open(struct net_device *netdev)
6926	{
6927	struct r8152 *tp = netdev_priv(dev: netdev);
6928	int res = 0;
6929
6930	if (work_busy(work: &tp->hw_phy_work.work) & WORK_BUSY_PENDING) {
6931	cancel_delayed_work_sync(dwork: &tp->hw_phy_work);
6932	rtl_hw_phy_work_func_t(work: &tp->hw_phy_work.work);
6933	}
6934
6935	res = alloc_all_mem(tp);
6936	if (res)
6937	goto out;
6938
6939	res = usb_autopm_get_interface(intf: tp->intf);
6940	if (res < 0)
6941	goto out_free;
6942
6943	mutex_lock(&tp->control);
6944
6945	tp->rtl_ops.up(tp);
6946
6947	netif_carrier_off(dev: netdev);
6948	netif_start_queue(dev: netdev);
6949	set_bit(nr: WORK_ENABLE, addr: &tp->flags);
6950
6951	res = usb_submit_urb(urb: tp->intr_urb, GFP_KERNEL);
6952	if (res) {
6953	if (res == -ENODEV)
6954	netif_device_detach(dev: tp->netdev);
6955	netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
6956	res);
6957	goto out_unlock;
6958	}
6959	napi_enable(n: &tp->napi);
6960	tasklet_enable(t: &tp->tx_tl);
6961
6962	mutex_unlock(lock: &tp->control);
6963
6964	usb_autopm_put_interface(intf: tp->intf);
6965	#ifdef CONFIG_PM_SLEEP
6966	tp->pm_notifier.notifier_call = rtl_notifier;
6967	register_pm_notifier(nb: &tp->pm_notifier);
6968	#endif
6969	return 0;
6970
6971	out_unlock:
6972	mutex_unlock(lock: &tp->control);
6973	usb_autopm_put_interface(intf: tp->intf);
6974	out_free:
6975	free_all_mem(tp);
6976	out:
6977	return res;
6978	}
6979
6980	static int rtl8152_close(struct net_device *netdev)
6981	{
6982	struct r8152 *tp = netdev_priv(dev: netdev);
6983	int res = 0;
6984
6985	#ifdef CONFIG_PM_SLEEP
6986	unregister_pm_notifier(nb: &tp->pm_notifier);
6987	#endif
6988	tasklet_disable(t: &tp->tx_tl);
6989	clear_bit(nr: WORK_ENABLE, addr: &tp->flags);
6990	usb_kill_urb(urb: tp->intr_urb);
6991	cancel_delayed_work_sync(dwork: &tp->schedule);
6992	napi_disable(n: &tp->napi);
6993	netif_stop_queue(dev: netdev);
6994
6995	res = usb_autopm_get_interface(intf: tp->intf);
6996	if (res < 0 || test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
6997	rtl_drop_queued_tx(tp);
6998	rtl_stop_rx(tp);
6999	} else {
7000	mutex_lock(&tp->control);
7001
7002	tp->rtl_ops.down(tp);
7003
7004	mutex_unlock(lock: &tp->control);
7005	}
7006
7007	if (!res)
7008	usb_autopm_put_interface(intf: tp->intf);
7009
7010	free_all_mem(tp);
7011
7012	return res;
7013	}
7014
7015	static void rtl_tally_reset(struct r8152 *tp)
7016	{
7017	u32 ocp_data;
7018
7019	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
7020	ocp_data |= TALLY_RESET;
7021	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, data: ocp_data);
7022	}
7023
7024	static void r8152b_init(struct r8152 *tp)
7025	{
7026	u32 ocp_data;
7027	u16 data;
7028
7029	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
7030	return;
7031
7032	data = r8152_mdio_read(tp, MII_BMCR);
7033	if (data & BMCR_PDOWN) {
7034	data &= ~BMCR_PDOWN;
7035	r8152_mdio_write(tp, MII_BMCR, value: data);
7036	}
7037
7038	r8152_aldps_en(tp, enable: false);
7039
7040	if (tp->version == RTL_VER_01) {
7041	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
7042	ocp_data &= ~LED_MODE_MASK;
7043	ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, data: ocp_data);
7044	}
7045
7046	r8152_power_cut_en(tp, enable: false);
7047
7048	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
7049	ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
7050	ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, data: ocp_data);
7051	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
7052	ocp_data &= ~MCU_CLK_RATIO_MASK;
7053	ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
7054	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, data: ocp_data);
7055	ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
7056	SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
7057	ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, data: ocp_data);
7058
7059	rtl_tally_reset(tp);
7060
7061	/* enable rx aggregation */
7062	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
7063	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
7064	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, data: ocp_data);
7065	}
7066
7067	static void r8153_init(struct r8152 *tp)
7068	{
7069	u32 ocp_data;
7070	u16 data;
7071	int i;
7072
7073	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
7074	return;
7075
7076	r8153_u1u2en(tp, enable: false);
7077
7078	for (i = 0; i < 500; i++) {
7079	if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
7080	AUTOLOAD_DONE)
7081	break;
7082
7083	msleep(msecs: 20);
7084	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
7085	break;
7086	}
7087
7088	data = r8153_phy_status(tp, desired: 0);
7089
7090	if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
7091	tp->version == RTL_VER_05)
7092	ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
7093
7094	data = r8152_mdio_read(tp, MII_BMCR);
7095	if (data & BMCR_PDOWN) {
7096	data &= ~BMCR_PDOWN;
7097	r8152_mdio_write(tp, MII_BMCR, value: data);
7098	}
7099
7100	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7101
7102	r8153_u2p3en(tp, enable: false);
7103
7104	if (tp->version == RTL_VER_04) {
7105	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
7106	ocp_data &= ~pwd_dn_scale_mask;
7107	ocp_data |= pwd_dn_scale(96);
7108	ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, data: ocp_data);
7109
7110	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
7111	ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
7112	ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, data: ocp_data);
7113	} else if (tp->version == RTL_VER_05) {
7114	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
7115	ocp_data &= ~ECM_ALDPS;
7116	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, data: ocp_data);
7117
7118	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
7119	if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
7120	ocp_data &= ~DYNAMIC_BURST;
7121	else
7122	ocp_data |= DYNAMIC_BURST;
7123	ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, data: ocp_data);
7124	} else if (tp->version == RTL_VER_06) {
7125	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
7126	if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
7127	ocp_data &= ~DYNAMIC_BURST;
7128	else
7129	ocp_data |= DYNAMIC_BURST;
7130	ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, data: ocp_data);
7131
7132	r8153_queue_wake(tp, enable: false);
7133
7134	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
7135	if (rtl8152_get_speed(tp) & LINK_STATUS)
7136	ocp_data |= CUR_LINK_OK;
7137	else
7138	ocp_data &= ~CUR_LINK_OK;
7139	ocp_data |= POLL_LINK_CHG;
7140	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, data: ocp_data);
7141	}
7142
7143	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
7144	ocp_data |= EP4_FULL_FC;
7145	ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, data: ocp_data);
7146
7147	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
7148	ocp_data &= ~TIMER11_EN;
7149	ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, data: ocp_data);
7150
7151	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
7152	ocp_data &= ~LED_MODE_MASK;
7153	ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, data: ocp_data);
7154
7155	ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
7156	if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)
7157	ocp_data |= LPM_TIMER_500MS;
7158	else
7159	ocp_data |= LPM_TIMER_500US;
7160	ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, data: ocp_data);
7161
7162	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
7163	ocp_data &= ~SEN_VAL_MASK;
7164	ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
7165	ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, data: ocp_data);
7166
7167	ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, data: 0x0001);
7168
7169	r8153_power_cut_en(tp, enable: false);
7170	rtl_runtime_suspend_enable(tp, enable: false);
7171	r8153_mac_clk_speed_down(tp, enable: false);
7172	r8153_u1u2en(tp, enable: true);
7173	usb_enable_lpm(udev: tp->udev);
7174
7175	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
7176	ocp_data |= LANWAKE_CLR_EN;
7177	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, data: ocp_data);
7178
7179	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
7180	ocp_data &= ~LANWAKE_PIN;
7181	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, data: ocp_data);
7182
7183	/* rx aggregation */
7184	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
7185	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
7186	if (tp->dell_tb_rx_agg_bug)
7187	ocp_data |= RX_AGG_DISABLE;
7188
7189	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, data: ocp_data);
7190
7191	rtl_tally_reset(tp);
7192
7193	switch (tp->udev->speed) {
7194	case USB_SPEED_SUPER:
7195	case USB_SPEED_SUPER_PLUS:
7196	tp->coalesce = COALESCE_SUPER;
7197	break;
7198	case USB_SPEED_HIGH:
7199	tp->coalesce = COALESCE_HIGH;
7200	break;
7201	default:
7202	tp->coalesce = COALESCE_SLOW;
7203	break;
7204	}
7205	}
7206
7207	static void r8153b_init(struct r8152 *tp)
7208	{
7209	u32 ocp_data;
7210	u16 data;
7211	int i;
7212
7213	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
7214	return;
7215
7216	r8153b_u1u2en(tp, enable: false);
7217
7218	for (i = 0; i < 500; i++) {
7219	if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
7220	AUTOLOAD_DONE)
7221	break;
7222
7223	msleep(msecs: 20);
7224	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
7225	break;
7226	}
7227
7228	data = r8153_phy_status(tp, desired: 0);
7229
7230	data = r8152_mdio_read(tp, MII_BMCR);
7231	if (data & BMCR_PDOWN) {
7232	data &= ~BMCR_PDOWN;
7233	r8152_mdio_write(tp, MII_BMCR, value: data);
7234	}
7235
7236	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7237
7238	r8153_u2p3en(tp, enable: false);
7239
7240	/* MSC timer = 0xfff * 8ms = 32760 ms */
7241	ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, data: 0x0fff);
7242
7243	r8153b_power_cut_en(tp, enable: false);
7244	r8153b_ups_en(tp, enable: false);
7245	r8153_queue_wake(tp, enable: false);
7246	rtl_runtime_suspend_enable(tp, enable: false);
7247
7248	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
7249	if (rtl8152_get_speed(tp) & LINK_STATUS)
7250	ocp_data |= CUR_LINK_OK;
7251	else
7252	ocp_data &= ~CUR_LINK_OK;
7253	ocp_data |= POLL_LINK_CHG;
7254	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, data: ocp_data);
7255
7256	if (tp->udev->speed >= USB_SPEED_SUPER)
7257	r8153b_u1u2en(tp, enable: true);
7258
7259	usb_enable_lpm(udev: tp->udev);
7260
7261	/* MAC clock speed down */
7262	r8153_mac_clk_speed_down(tp, enable: true);
7263
7264	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
7265	ocp_data &= ~PLA_MCU_SPDWN_EN;
7266	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, data: ocp_data);
7267
7268	if (tp->version == RTL_VER_09) {
7269	/* Disable Test IO for 32QFN */
7270	if (ocp_read_byte(tp, MCU_TYPE_PLA, index: 0xdc00) & BIT(5)) {
7271	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
7272	ocp_data |= TEST_IO_OFF;
7273	ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, data: ocp_data);
7274	}
7275	}
7276
7277	set_bit(nr: GREEN_ETHERNET, addr: &tp->flags);
7278
7279	/* rx aggregation */
7280	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
7281	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
7282	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, data: ocp_data);
7283
7284	rtl_tally_reset(tp);
7285
7286	tp->coalesce = 15000; /* 15 us */
7287	}
7288
7289	static void r8153c_init(struct r8152 *tp)
7290	{
7291	u32 ocp_data;
7292	u16 data;
7293	int i;
7294
7295	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
7296	return;
7297
7298	r8153b_u1u2en(tp, enable: false);
7299
7300	/* Disable spi_en */
7301	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
7302	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
7303	ocp_data &= ~BIT(3);
7304	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, data: ocp_data);
7305	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, index: 0xcbf0);
7306	ocp_data |= BIT(1);
7307	ocp_write_word(tp, MCU_TYPE_USB, index: 0xcbf0, data: ocp_data);
7308
7309	for (i = 0; i < 500; i++) {
7310	if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
7311	AUTOLOAD_DONE)
7312	break;
7313
7314	msleep(msecs: 20);
7315	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
7316	return;
7317	}
7318
7319	data = r8153_phy_status(tp, desired: 0);
7320
7321	data = r8152_mdio_read(tp, MII_BMCR);
7322	if (data & BMCR_PDOWN) {
7323	data &= ~BMCR_PDOWN;
7324	r8152_mdio_write(tp, MII_BMCR, value: data);
7325	}
7326
7327	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7328
7329	r8153_u2p3en(tp, enable: false);
7330
7331	/* MSC timer = 0xfff * 8ms = 32760 ms */
7332	ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, data: 0x0fff);
7333
7334	r8153b_power_cut_en(tp, enable: false);
7335	r8153c_ups_en(tp, enable: false);
7336	r8153_queue_wake(tp, enable: false);
7337	rtl_runtime_suspend_enable(tp, enable: false);
7338
7339	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
7340	if (rtl8152_get_speed(tp) & LINK_STATUS)
7341	ocp_data |= CUR_LINK_OK;
7342	else
7343	ocp_data &= ~CUR_LINK_OK;
7344
7345	ocp_data |= POLL_LINK_CHG;
7346	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, data: ocp_data);
7347
7348	r8153b_u1u2en(tp, enable: true);
7349
7350	usb_enable_lpm(udev: tp->udev);
7351
7352	/* MAC clock speed down */
7353	r8153_mac_clk_speed_down(tp, enable: true);
7354
7355	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
7356	ocp_data &= ~BIT(7);
7357	ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, data: ocp_data);
7358
7359	set_bit(nr: GREEN_ETHERNET, addr: &tp->flags);
7360
7361	/* rx aggregation */
7362	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
7363	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
7364	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, data: ocp_data);
7365
7366	rtl_tally_reset(tp);
7367
7368	tp->coalesce = 15000; /* 15 us */
7369	}
7370
7371	static void r8156_hw_phy_cfg(struct r8152 *tp)
7372	{
7373	u32 ocp_data;
7374	u16 data;
7375
7376	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
7377	if (ocp_data & PCUT_STATUS) {
7378	ocp_data &= ~PCUT_STATUS;
7379	ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, data: ocp_data);
7380	}
7381
7382	data = r8153_phy_status(tp, desired: 0);
7383	switch (data) {
7384	case PHY_STAT_EXT_INIT:
7385	rtl8152_apply_firmware(tp, power_cut: true);
7386
7387	data = ocp_reg_read(tp, addr: 0xa468);
7388	data &= ~(BIT(3) | BIT(1));
7389	ocp_reg_write(tp, addr: 0xa468, data);
7390	break;
7391	case PHY_STAT_LAN_ON:
7392	case PHY_STAT_PWRDN:
7393	default:
7394	rtl8152_apply_firmware(tp, power_cut: false);
7395	break;
7396	}
7397
7398	/* disable ALDPS before updating the PHY parameters */
7399	r8153_aldps_en(tp, enable: false);
7400
7401	/* disable EEE before updating the PHY parameters */
7402	rtl_eee_enable(tp, enable: false);
7403
7404	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7405	WARN_ON_ONCE(data != PHY_STAT_LAN_ON);
7406
7407	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
7408	ocp_data |= PFM_PWM_SWITCH;
7409	ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, data: ocp_data);
7410
7411	switch (tp->version) {
7412	case RTL_VER_10:
7413	data = ocp_reg_read(tp, addr: 0xad40);
7414	data &= ~0x3ff;
7415	data |= BIT(7) | BIT(2);
7416	ocp_reg_write(tp, addr: 0xad40, data);
7417
7418	data = ocp_reg_read(tp, addr: 0xad4e);
7419	data |= BIT(4);
7420	ocp_reg_write(tp, addr: 0xad4e, data);
7421	data = ocp_reg_read(tp, addr: 0xad16);
7422	data &= ~0x3ff;
7423	data |= 0x6;
7424	ocp_reg_write(tp, addr: 0xad16, data);
7425	data = ocp_reg_read(tp, addr: 0xad32);
7426	data &= ~0x3f;
7427	data |= 6;
7428	ocp_reg_write(tp, addr: 0xad32, data);
7429	data = ocp_reg_read(tp, addr: 0xac08);
7430	data &= ~(BIT(12) | BIT(8));
7431	ocp_reg_write(tp, addr: 0xac08, data);
7432	data = ocp_reg_read(tp, addr: 0xac8a);
7433	data |= BIT(12) | BIT(13) | BIT(14);
7434	data &= ~BIT(15);
7435	ocp_reg_write(tp, addr: 0xac8a, data);
7436	data = ocp_reg_read(tp, addr: 0xad18);
7437	data |= BIT(10);
7438	ocp_reg_write(tp, addr: 0xad18, data);
7439	data = ocp_reg_read(tp, addr: 0xad1a);
7440	data |= 0x3ff;
7441	ocp_reg_write(tp, addr: 0xad1a, data);
7442	data = ocp_reg_read(tp, addr: 0xad1c);
7443	data |= 0x3ff;
7444	ocp_reg_write(tp, addr: 0xad1c, data);
7445
7446	data = sram_read(tp, addr: 0x80ea);
7447	data &= ~0xff00;
7448	data |= 0xc400;
7449	sram_write(tp, addr: 0x80ea, data);
7450	data = sram_read(tp, addr: 0x80eb);
7451	data &= ~0x0700;
7452	data |= 0x0300;
7453	sram_write(tp, addr: 0x80eb, data);
7454	data = sram_read(tp, addr: 0x80f8);
7455	data &= ~0xff00;
7456	data |= 0x1c00;
7457	sram_write(tp, addr: 0x80f8, data);
7458	data = sram_read(tp, addr: 0x80f1);
7459	data &= ~0xff00;
7460	data |= 0x3000;
7461	sram_write(tp, addr: 0x80f1, data);
7462
7463	data = sram_read(tp, addr: 0x80fe);
7464	data &= ~0xff00;
7465	data |= 0xa500;
7466	sram_write(tp, addr: 0x80fe, data);
7467	data = sram_read(tp, addr: 0x8102);
7468	data &= ~0xff00;
7469	data |= 0x5000;
7470	sram_write(tp, addr: 0x8102, data);
7471	data = sram_read(tp, addr: 0x8015);
7472	data &= ~0xff00;
7473	data |= 0x3300;
7474	sram_write(tp, addr: 0x8015, data);
7475	data = sram_read(tp, addr: 0x8100);
7476	data &= ~0xff00;
7477	data |= 0x7000;
7478	sram_write(tp, addr: 0x8100, data);
7479	data = sram_read(tp, addr: 0x8014);
7480	data &= ~0xff00;
7481	data |= 0xf000;
7482	sram_write(tp, addr: 0x8014, data);
7483	data = sram_read(tp, addr: 0x8016);
7484	data &= ~0xff00;
7485	data |= 0x6500;
7486	sram_write(tp, addr: 0x8016, data);
7487	data = sram_read(tp, addr: 0x80dc);
7488	data &= ~0xff00;
7489	data |= 0xed00;
7490	sram_write(tp, addr: 0x80dc, data);
7491	data = sram_read(tp, addr: 0x80df);
7492	data |= BIT(8);
7493	sram_write(tp, addr: 0x80df, data);
7494	data = sram_read(tp, addr: 0x80e1);
7495	data &= ~BIT(8);
7496	sram_write(tp, addr: 0x80e1, data);
7497
7498	data = ocp_reg_read(tp, addr: 0xbf06);
7499	data &= ~0x003f;
7500	data |= 0x0038;
7501	ocp_reg_write(tp, addr: 0xbf06, data);
7502
7503	sram_write(tp, addr: 0x819f, data: 0xddb6);
7504
7505	ocp_reg_write(tp, addr: 0xbc34, data: 0x5555);
7506	data = ocp_reg_read(tp, addr: 0xbf0a);
7507	data &= ~0x0e00;
7508	data |= 0x0a00;
7509	ocp_reg_write(tp, addr: 0xbf0a, data);
7510
7511	data = ocp_reg_read(tp, addr: 0xbd2c);
7512	data &= ~BIT(13);
7513	ocp_reg_write(tp, addr: 0xbd2c, data);
7514	break;
7515	case RTL_VER_11:
7516	data = ocp_reg_read(tp, addr: 0xad16);
7517	data |= 0x3ff;
7518	ocp_reg_write(tp, addr: 0xad16, data);
7519	data = ocp_reg_read(tp, addr: 0xad32);
7520	data &= ~0x3f;
7521	data |= 6;
7522	ocp_reg_write(tp, addr: 0xad32, data);
7523	data = ocp_reg_read(tp, addr: 0xac08);
7524	data &= ~(BIT(12) | BIT(8));
7525	ocp_reg_write(tp, addr: 0xac08, data);
7526	data = ocp_reg_read(tp, addr: 0xacc0);
7527	data &= ~0x3;
7528	data |= BIT(1);
7529	ocp_reg_write(tp, addr: 0xacc0, data);
7530	data = ocp_reg_read(tp, addr: 0xad40);
7531	data &= ~0xe7;
7532	data |= BIT(6) | BIT(2);
7533	ocp_reg_write(tp, addr: 0xad40, data);
7534	data = ocp_reg_read(tp, addr: 0xac14);
7535	data &= ~BIT(7);
7536	ocp_reg_write(tp, addr: 0xac14, data);
7537	data = ocp_reg_read(tp, addr: 0xac80);
7538	data &= ~(BIT(8) | BIT(9));
7539	ocp_reg_write(tp, addr: 0xac80, data);
7540	data = ocp_reg_read(tp, addr: 0xac5e);
7541	data &= ~0x7;
7542	data |= BIT(1);
7543	ocp_reg_write(tp, addr: 0xac5e, data);
7544	ocp_reg_write(tp, addr: 0xad4c, data: 0x00a8);
7545	ocp_reg_write(tp, addr: 0xac5c, data: 0x01ff);
7546	data = ocp_reg_read(tp, addr: 0xac8a);
7547	data &= ~0xf0;
7548	data |= BIT(4) | BIT(5);
7549	ocp_reg_write(tp, addr: 0xac8a, data);
7550	ocp_reg_write(tp, addr: 0xb87c, data: 0x8157);
7551	data = ocp_reg_read(tp, addr: 0xb87e);
7552	data &= ~0xff00;
7553	data |= 0x0500;
7554	ocp_reg_write(tp, addr: 0xb87e, data);
7555	ocp_reg_write(tp, addr: 0xb87c, data: 0x8159);
7556	data = ocp_reg_read(tp, addr: 0xb87e);
7557	data &= ~0xff00;
7558	data |= 0x0700;
7559	ocp_reg_write(tp, addr: 0xb87e, data);
7560
7561	/* AAGC */
7562	ocp_reg_write(tp, addr: 0xb87c, data: 0x80a2);
7563	ocp_reg_write(tp, addr: 0xb87e, data: 0x0153);
7564	ocp_reg_write(tp, addr: 0xb87c, data: 0x809c);
7565	ocp_reg_write(tp, addr: 0xb87e, data: 0x0153);
7566
7567	/* EEE parameter */
7568	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS_2P5G, data: 0x0056);
7569
7570	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_USB_CFG);
7571	ocp_data |= EN_XG_LIP | EN_G_LIP;
7572	ocp_write_word(tp, MCU_TYPE_PLA, PLA_USB_CFG, data: ocp_data);
7573
7574	sram_write(tp, addr: 0x8257, data: 0x020f); /* XG PLL */
7575	sram_write(tp, addr: 0x80ea, data: 0x7843); /* GIGA Master */
7576
7577	if (rtl_phy_patch_request(tp, request: true, wait: true))
7578	return;
7579
7580	/* Advance EEE */
7581	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
7582	ocp_data |= EEE_SPDWN_EN;
7583	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, data: ocp_data);
7584
7585	data = ocp_reg_read(tp, OCP_DOWN_SPEED);
7586	data &= ~(EN_EEE_100 | EN_EEE_1000);
7587	data |= EN_10M_CLKDIV;
7588	ocp_reg_write(tp, OCP_DOWN_SPEED, data);
7589	tp->ups_info._10m_ckdiv = true;
7590	tp->ups_info.eee_plloff_100 = false;
7591	tp->ups_info.eee_plloff_giga = false;
7592
7593	data = ocp_reg_read(tp, OCP_POWER_CFG);
7594	data &= ~EEE_CLKDIV_EN;
7595	ocp_reg_write(tp, OCP_POWER_CFG, data);
7596	tp->ups_info.eee_ckdiv = false;
7597
7598	ocp_reg_write(tp, OCP_SYSCLK_CFG, data: 0);
7599	ocp_reg_write(tp, OCP_SYSCLK_CFG, sysclk_div_expo(5));
7600	tp->ups_info._250m_ckdiv = false;
7601
7602	rtl_phy_patch_request(tp, request: false, wait: true);
7603
7604	/* enable ADC Ibias Cal */
7605	data = ocp_reg_read(tp, addr: 0xd068);
7606	data |= BIT(13);
7607	ocp_reg_write(tp, addr: 0xd068, data);
7608
7609	/* enable Thermal Sensor */
7610	data = sram_read(tp, addr: 0x81a2);
7611	data &= ~BIT(8);
7612	sram_write(tp, addr: 0x81a2, data);
7613	data = ocp_reg_read(tp, addr: 0xb54c);
7614	data &= ~0xff00;
7615	data |= 0xdb00;
7616	ocp_reg_write(tp, addr: 0xb54c, data);
7617
7618	/* Nway 2.5G Lite */
7619	data = ocp_reg_read(tp, addr: 0xa454);
7620	data &= ~BIT(0);
7621	ocp_reg_write(tp, addr: 0xa454, data);
7622
7623	/* CS DSP solution */
7624	data = ocp_reg_read(tp, OCP_10GBT_CTRL);
7625	data |= RTL_ADV2_5G_F_R;
7626	ocp_reg_write(tp, OCP_10GBT_CTRL, data);
7627	data = ocp_reg_read(tp, addr: 0xad4e);
7628	data &= ~BIT(4);
7629	ocp_reg_write(tp, addr: 0xad4e, data);
7630	data = ocp_reg_read(tp, addr: 0xa86a);
7631	data &= ~BIT(0);
7632	ocp_reg_write(tp, addr: 0xa86a, data);
7633
7634	/* MDI SWAP */
7635	if ((ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG) & MID_REVERSE) &&
7636	(ocp_reg_read(tp, addr: 0xd068) & BIT(1))) {
7637	u16 swap_a, swap_b;
7638
7639	data = ocp_reg_read(tp, addr: 0xd068);
7640	data &= ~0x1f;
7641	data |= 0x1; /* p0 */
7642	ocp_reg_write(tp, addr: 0xd068, data);
7643	swap_a = ocp_reg_read(tp, addr: 0xd06a);
7644	data &= ~0x18;
7645	data |= 0x18; /* p3 */
7646	ocp_reg_write(tp, addr: 0xd068, data);
7647	swap_b = ocp_reg_read(tp, addr: 0xd06a);
7648	data &= ~0x18; /* p0 */
7649	ocp_reg_write(tp, addr: 0xd068, data);
7650	ocp_reg_write(tp, addr: 0xd06a,
7651	data: (swap_a & ~0x7ff) | (swap_b & 0x7ff));
7652	data |= 0x18; /* p3 */
7653	ocp_reg_write(tp, addr: 0xd068, data);
7654	ocp_reg_write(tp, addr: 0xd06a,
7655	data: (swap_b & ~0x7ff) | (swap_a & 0x7ff));
7656	data &= ~0x18;
7657	data |= 0x08; /* p1 */
7658	ocp_reg_write(tp, addr: 0xd068, data);
7659	swap_a = ocp_reg_read(tp, addr: 0xd06a);
7660	data &= ~0x18;
7661	data |= 0x10; /* p2 */
7662	ocp_reg_write(tp, addr: 0xd068, data);
7663	swap_b = ocp_reg_read(tp, addr: 0xd06a);
7664	data &= ~0x18;
7665	data |= 0x08; /* p1 */
7666	ocp_reg_write(tp, addr: 0xd068, data);
7667	ocp_reg_write(tp, addr: 0xd06a,
7668	data: (swap_a & ~0x7ff) | (swap_b & 0x7ff));
7669	data &= ~0x18;
7670	data |= 0x10; /* p2 */
7671	ocp_reg_write(tp, addr: 0xd068, data);
7672	ocp_reg_write(tp, addr: 0xd06a,
7673	data: (swap_b & ~0x7ff) | (swap_a & 0x7ff));
7674	swap_a = ocp_reg_read(tp, addr: 0xbd5a);
7675	swap_b = ocp_reg_read(tp, addr: 0xbd5c);
7676	ocp_reg_write(tp, addr: 0xbd5a, data: (swap_a & ~0x1f1f) |
7677	((swap_b & 0x1f) << 8) |
7678	((swap_b >> 8) & 0x1f));
7679	ocp_reg_write(tp, addr: 0xbd5c, data: (swap_b & ~0x1f1f) |
7680	((swap_a & 0x1f) << 8) |
7681	((swap_a >> 8) & 0x1f));
7682	swap_a = ocp_reg_read(tp, addr: 0xbc18);
7683	swap_b = ocp_reg_read(tp, addr: 0xbc1a);
7684	ocp_reg_write(tp, addr: 0xbc18, data: (swap_a & ~0x1f1f) |
7685	((swap_b & 0x1f) << 8) |
7686	((swap_b >> 8) & 0x1f));
7687	ocp_reg_write(tp, addr: 0xbc1a, data: (swap_b & ~0x1f1f) |
7688	((swap_a & 0x1f) << 8) |
7689	((swap_a >> 8) & 0x1f));
7690	}
7691
7692	/* Notify the MAC when the speed is changed to force mode. */
7693	data = ocp_reg_read(tp, OCP_INTR_EN);
7694	data |= INTR_SPEED_FORCE;
7695	ocp_reg_write(tp, OCP_INTR_EN, data);
7696	break;
7697	default:
7698	break;
7699	}
7700
7701	rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
7702
7703	data = ocp_reg_read(tp, addr: 0xa428);
7704	data &= ~BIT(9);
7705	ocp_reg_write(tp, addr: 0xa428, data);
7706	data = ocp_reg_read(tp, addr: 0xa5ea);
7707	data &= ~BIT(0);
7708	ocp_reg_write(tp, addr: 0xa5ea, data);
7709	tp->ups_info.lite_mode = 0;
7710
7711	if (tp->eee_en)
7712	rtl_eee_enable(tp, enable: true);
7713
7714	r8153_aldps_en(tp, enable: true);
7715	r8152b_enable_fc(tp);
7716	r8153_u2p3en(tp, enable: true);
7717
7718	set_bit(nr: PHY_RESET, addr: &tp->flags);
7719	}
7720
7721	static void r8156b_hw_phy_cfg(struct r8152 *tp)
7722	{
7723	u32 ocp_data;
7724	u16 data;
7725
7726	switch (tp->version) {
7727	case RTL_VER_12:
7728	ocp_reg_write(tp, addr: 0xbf86, data: 0x9000);
7729	data = ocp_reg_read(tp, addr: 0xc402);
7730	data |= BIT(10);
7731	ocp_reg_write(tp, addr: 0xc402, data);
7732	data &= ~BIT(10);
7733	ocp_reg_write(tp, addr: 0xc402, data);
7734	ocp_reg_write(tp, addr: 0xbd86, data: 0x1010);
7735	ocp_reg_write(tp, addr: 0xbd88, data: 0x1010);
7736	data = ocp_reg_read(tp, addr: 0xbd4e);
7737	data &= ~(BIT(10) | BIT(11));
7738	data |= BIT(11);
7739	ocp_reg_write(tp, addr: 0xbd4e, data);
7740	data = ocp_reg_read(tp, addr: 0xbf46);
7741	data &= ~0xf00;
7742	data |= 0x700;
7743	ocp_reg_write(tp, addr: 0xbf46, data);
7744	break;
7745	case RTL_VER_13:
7746	case RTL_VER_15:
7747	r8156b_wait_loading_flash(tp);
7748	break;
7749	default:
7750	break;
7751	}
7752
7753	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
7754	if (ocp_data & PCUT_STATUS) {
7755	ocp_data &= ~PCUT_STATUS;
7756	ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, data: ocp_data);
7757	}
7758
7759	data = r8153_phy_status(tp, desired: 0);
7760	switch (data) {
7761	case PHY_STAT_EXT_INIT:
7762	rtl8152_apply_firmware(tp, power_cut: true);
7763
7764	data = ocp_reg_read(tp, addr: 0xa466);
7765	data &= ~BIT(0);
7766	ocp_reg_write(tp, addr: 0xa466, data);
7767
7768	data = ocp_reg_read(tp, addr: 0xa468);
7769	data &= ~(BIT(3) | BIT(1));
7770	ocp_reg_write(tp, addr: 0xa468, data);
7771	break;
7772	case PHY_STAT_LAN_ON:
7773	case PHY_STAT_PWRDN:
7774	default:
7775	rtl8152_apply_firmware(tp, power_cut: false);
7776	break;
7777	}
7778
7779	data = r8152_mdio_read(tp, MII_BMCR);
7780	if (data & BMCR_PDOWN) {
7781	data &= ~BMCR_PDOWN;
7782	r8152_mdio_write(tp, MII_BMCR, value: data);
7783	}
7784
7785	/* disable ALDPS before updating the PHY parameters */
7786	r8153_aldps_en(tp, enable: false);
7787
7788	/* disable EEE before updating the PHY parameters */
7789	rtl_eee_enable(tp, enable: false);
7790
7791	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7792	WARN_ON_ONCE(data != PHY_STAT_LAN_ON);
7793
7794	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
7795	ocp_data |= PFM_PWM_SWITCH;
7796	ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, data: ocp_data);
7797
7798	switch (tp->version) {
7799	case RTL_VER_12:
7800	data = ocp_reg_read(tp, addr: 0xbc08);
7801	data |= BIT(3) | BIT(2);
7802	ocp_reg_write(tp, addr: 0xbc08, data);
7803
7804	data = sram_read(tp, addr: 0x8fff);
7805	data &= ~0xff00;
7806	data |= 0x0400;
7807	sram_write(tp, addr: 0x8fff, data);
7808
7809	data = ocp_reg_read(tp, addr: 0xacda);
7810	data |= 0xff00;
7811	ocp_reg_write(tp, addr: 0xacda, data);
7812	data = ocp_reg_read(tp, addr: 0xacde);
7813	data |= 0xf000;
7814	ocp_reg_write(tp, addr: 0xacde, data);
7815	ocp_reg_write(tp, addr: 0xac8c, data: 0x0ffc);
7816	ocp_reg_write(tp, addr: 0xac46, data: 0xb7b4);
7817	ocp_reg_write(tp, addr: 0xac50, data: 0x0fbc);
7818	ocp_reg_write(tp, addr: 0xac3c, data: 0x9240);
7819	ocp_reg_write(tp, addr: 0xac4e, data: 0x0db4);
7820	ocp_reg_write(tp, addr: 0xacc6, data: 0x0707);
7821	ocp_reg_write(tp, addr: 0xacc8, data: 0xa0d3);
7822	ocp_reg_write(tp, addr: 0xad08, data: 0x0007);
7823
7824	ocp_reg_write(tp, addr: 0xb87c, data: 0x8560);
7825	ocp_reg_write(tp, addr: 0xb87e, data: 0x19cc);
7826	ocp_reg_write(tp, addr: 0xb87c, data: 0x8562);
7827	ocp_reg_write(tp, addr: 0xb87e, data: 0x19cc);
7828	ocp_reg_write(tp, addr: 0xb87c, data: 0x8564);
7829	ocp_reg_write(tp, addr: 0xb87e, data: 0x19cc);
7830	ocp_reg_write(tp, addr: 0xb87c, data: 0x8566);
7831	ocp_reg_write(tp, addr: 0xb87e, data: 0x147d);
7832	ocp_reg_write(tp, addr: 0xb87c, data: 0x8568);
7833	ocp_reg_write(tp, addr: 0xb87e, data: 0x147d);
7834	ocp_reg_write(tp, addr: 0xb87c, data: 0x856a);
7835	ocp_reg_write(tp, addr: 0xb87e, data: 0x147d);
7836	ocp_reg_write(tp, addr: 0xb87c, data: 0x8ffe);
7837	ocp_reg_write(tp, addr: 0xb87e, data: 0x0907);
7838	ocp_reg_write(tp, addr: 0xb87c, data: 0x80d6);
7839	ocp_reg_write(tp, addr: 0xb87e, data: 0x2801);
7840	ocp_reg_write(tp, addr: 0xb87c, data: 0x80f2);
7841	ocp_reg_write(tp, addr: 0xb87e, data: 0x2801);
7842	ocp_reg_write(tp, addr: 0xb87c, data: 0x80f4);
7843	ocp_reg_write(tp, addr: 0xb87e, data: 0x6077);
7844	ocp_reg_write(tp, addr: 0xb506, data: 0x01e7);
7845
7846	ocp_reg_write(tp, addr: 0xb87c, data: 0x8013);
7847	ocp_reg_write(tp, addr: 0xb87e, data: 0x0700);
7848	ocp_reg_write(tp, addr: 0xb87c, data: 0x8fb9);
7849	ocp_reg_write(tp, addr: 0xb87e, data: 0x2801);
7850	ocp_reg_write(tp, addr: 0xb87c, data: 0x8fba);
7851	ocp_reg_write(tp, addr: 0xb87e, data: 0x0100);
7852	ocp_reg_write(tp, addr: 0xb87c, data: 0x8fbc);
7853	ocp_reg_write(tp, addr: 0xb87e, data: 0x1900);
7854	ocp_reg_write(tp, addr: 0xb87c, data: 0x8fbe);
7855	ocp_reg_write(tp, addr: 0xb87e, data: 0xe100);
7856	ocp_reg_write(tp, addr: 0xb87c, data: 0x8fc0);
7857	ocp_reg_write(tp, addr: 0xb87e, data: 0x0800);
7858	ocp_reg_write(tp, addr: 0xb87c, data: 0x8fc2);
7859	ocp_reg_write(tp, addr: 0xb87e, data: 0xe500);
7860	ocp_reg_write(tp, addr: 0xb87c, data: 0x8fc4);
7861	ocp_reg_write(tp, addr: 0xb87e, data: 0x0f00);
7862	ocp_reg_write(tp, addr: 0xb87c, data: 0x8fc6);
7863	ocp_reg_write(tp, addr: 0xb87e, data: 0xf100);
7864	ocp_reg_write(tp, addr: 0xb87c, data: 0x8fc8);
7865	ocp_reg_write(tp, addr: 0xb87e, data: 0x0400);
7866	ocp_reg_write(tp, addr: 0xb87c, data: 0x8fca);
7867	ocp_reg_write(tp, addr: 0xb87e, data: 0xf300);
7868	ocp_reg_write(tp, addr: 0xb87c, data: 0x8fcc);
7869	ocp_reg_write(tp, addr: 0xb87e, data: 0xfd00);
7870	ocp_reg_write(tp, addr: 0xb87c, data: 0x8fce);
7871	ocp_reg_write(tp, addr: 0xb87e, data: 0xff00);
7872	ocp_reg_write(tp, addr: 0xb87c, data: 0x8fd0);
7873	ocp_reg_write(tp, addr: 0xb87e, data: 0xfb00);
7874	ocp_reg_write(tp, addr: 0xb87c, data: 0x8fd2);
7875	ocp_reg_write(tp, addr: 0xb87e, data: 0x0100);
7876	ocp_reg_write(tp, addr: 0xb87c, data: 0x8fd4);
7877	ocp_reg_write(tp, addr: 0xb87e, data: 0xf400);
7878	ocp_reg_write(tp, addr: 0xb87c, data: 0x8fd6);
7879	ocp_reg_write(tp, addr: 0xb87e, data: 0xff00);
7880	ocp_reg_write(tp, addr: 0xb87c, data: 0x8fd8);
7881	ocp_reg_write(tp, addr: 0xb87e, data: 0xf600);
7882
7883	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_USB_CFG);
7884	ocp_data |= EN_XG_LIP | EN_G_LIP;
7885	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_USB_CFG, data: ocp_data);
7886	ocp_reg_write(tp, addr: 0xb87c, data: 0x813d);
7887	ocp_reg_write(tp, addr: 0xb87e, data: 0x390e);
7888	ocp_reg_write(tp, addr: 0xb87c, data: 0x814f);
7889	ocp_reg_write(tp, addr: 0xb87e, data: 0x790e);
7890	ocp_reg_write(tp, addr: 0xb87c, data: 0x80b0);
7891	ocp_reg_write(tp, addr: 0xb87e, data: 0x0f31);
7892	data = ocp_reg_read(tp, addr: 0xbf4c);
7893	data |= BIT(1);
7894	ocp_reg_write(tp, addr: 0xbf4c, data);
7895	data = ocp_reg_read(tp, addr: 0xbcca);
7896	data |= BIT(9) | BIT(8);
7897	ocp_reg_write(tp, addr: 0xbcca, data);
7898	ocp_reg_write(tp, addr: 0xb87c, data: 0x8141);
7899	ocp_reg_write(tp, addr: 0xb87e, data: 0x320e);
7900	ocp_reg_write(tp, addr: 0xb87c, data: 0x8153);
7901	ocp_reg_write(tp, addr: 0xb87e, data: 0x720e);
7902	ocp_reg_write(tp, addr: 0xb87c, data: 0x8529);
7903	ocp_reg_write(tp, addr: 0xb87e, data: 0x050e);
7904	data = ocp_reg_read(tp, OCP_EEE_CFG);
7905	data &= ~CTAP_SHORT_EN;
7906	ocp_reg_write(tp, OCP_EEE_CFG, data);
7907
7908	sram_write(tp, addr: 0x816c, data: 0xc4a0);
7909	sram_write(tp, addr: 0x8170, data: 0xc4a0);
7910	sram_write(tp, addr: 0x8174, data: 0x04a0);
7911	sram_write(tp, addr: 0x8178, data: 0x04a0);
7912	sram_write(tp, addr: 0x817c, data: 0x0719);
7913	sram_write(tp, addr: 0x8ff4, data: 0x0400);
7914	sram_write(tp, addr: 0x8ff1, data: 0x0404);
7915
7916	ocp_reg_write(tp, addr: 0xbf4a, data: 0x001b);
7917	ocp_reg_write(tp, addr: 0xb87c, data: 0x8033);
7918	ocp_reg_write(tp, addr: 0xb87e, data: 0x7c13);
7919	ocp_reg_write(tp, addr: 0xb87c, data: 0x8037);
7920	ocp_reg_write(tp, addr: 0xb87e, data: 0x7c13);
7921	ocp_reg_write(tp, addr: 0xb87c, data: 0x803b);
7922	ocp_reg_write(tp, addr: 0xb87e, data: 0xfc32);
7923	ocp_reg_write(tp, addr: 0xb87c, data: 0x803f);
7924	ocp_reg_write(tp, addr: 0xb87e, data: 0x7c13);
7925	ocp_reg_write(tp, addr: 0xb87c, data: 0x8043);
7926	ocp_reg_write(tp, addr: 0xb87e, data: 0x7c13);
7927	ocp_reg_write(tp, addr: 0xb87c, data: 0x8047);
7928	ocp_reg_write(tp, addr: 0xb87e, data: 0x7c13);
7929
7930	ocp_reg_write(tp, addr: 0xb87c, data: 0x8145);
7931	ocp_reg_write(tp, addr: 0xb87e, data: 0x370e);
7932	ocp_reg_write(tp, addr: 0xb87c, data: 0x8157);
7933	ocp_reg_write(tp, addr: 0xb87e, data: 0x770e);
7934	ocp_reg_write(tp, addr: 0xb87c, data: 0x8169);
7935	ocp_reg_write(tp, addr: 0xb87e, data: 0x0d0a);
7936	ocp_reg_write(tp, addr: 0xb87c, data: 0x817b);
7937	ocp_reg_write(tp, addr: 0xb87e, data: 0x1d0a);
7938
7939	data = sram_read(tp, addr: 0x8217);
7940	data &= ~0xff00;
7941	data |= 0x5000;
7942	sram_write(tp, addr: 0x8217, data);
7943	data = sram_read(tp, addr: 0x821a);
7944	data &= ~0xff00;
7945	data |= 0x5000;
7946	sram_write(tp, addr: 0x821a, data);
7947	sram_write(tp, addr: 0x80da, data: 0x0403);
7948	data = sram_read(tp, addr: 0x80dc);
7949	data &= ~0xff00;
7950	data |= 0x1000;
7951	sram_write(tp, addr: 0x80dc, data);
7952	sram_write(tp, addr: 0x80b3, data: 0x0384);
7953	sram_write(tp, addr: 0x80b7, data: 0x2007);
7954	data = sram_read(tp, addr: 0x80ba);
7955	data &= ~0xff00;
7956	data |= 0x6c00;
7957	sram_write(tp, addr: 0x80ba, data);
7958	sram_write(tp, addr: 0x80b5, data: 0xf009);
7959	data = sram_read(tp, addr: 0x80bd);
7960	data &= ~0xff00;
7961	data |= 0x9f00;
7962	sram_write(tp, addr: 0x80bd, data);
7963	sram_write(tp, addr: 0x80c7, data: 0xf083);
7964	sram_write(tp, addr: 0x80dd, data: 0x03f0);
7965	data = sram_read(tp, addr: 0x80df);
7966	data &= ~0xff00;
7967	data |= 0x1000;
7968	sram_write(tp, addr: 0x80df, data);
7969	sram_write(tp, addr: 0x80cb, data: 0x2007);
7970	data = sram_read(tp, addr: 0x80ce);
7971	data &= ~0xff00;
7972	data |= 0x6c00;
7973	sram_write(tp, addr: 0x80ce, data);
7974	sram_write(tp, addr: 0x80c9, data: 0x8009);
7975	data = sram_read(tp, addr: 0x80d1);
7976	data &= ~0xff00;
7977	data |= 0x8000;
7978	sram_write(tp, addr: 0x80d1, data);
7979	sram_write(tp, addr: 0x80a3, data: 0x200a);
7980	sram_write(tp, addr: 0x80a5, data: 0xf0ad);
7981	sram_write(tp, addr: 0x809f, data: 0x6073);
7982	sram_write(tp, addr: 0x80a1, data: 0x000b);
7983	data = sram_read(tp, addr: 0x80a9);
7984	data &= ~0xff00;
7985	data |= 0xc000;
7986	sram_write(tp, addr: 0x80a9, data);
7987
7988	if (rtl_phy_patch_request(tp, request: true, wait: true))
7989	return;
7990
7991	data = ocp_reg_read(tp, addr: 0xb896);
7992	data &= ~BIT(0);
7993	ocp_reg_write(tp, addr: 0xb896, data);
7994	data = ocp_reg_read(tp, addr: 0xb892);
7995	data &= ~0xff00;
7996	ocp_reg_write(tp, addr: 0xb892, data);
7997	ocp_reg_write(tp, addr: 0xb88e, data: 0xc23e);
7998	ocp_reg_write(tp, addr: 0xb890, data: 0x0000);
7999	ocp_reg_write(tp, addr: 0xb88e, data: 0xc240);
8000	ocp_reg_write(tp, addr: 0xb890, data: 0x0103);
8001	ocp_reg_write(tp, addr: 0xb88e, data: 0xc242);
8002	ocp_reg_write(tp, addr: 0xb890, data: 0x0507);
8003	ocp_reg_write(tp, addr: 0xb88e, data: 0xc244);
8004	ocp_reg_write(tp, addr: 0xb890, data: 0x090b);
8005	ocp_reg_write(tp, addr: 0xb88e, data: 0xc246);
8006	ocp_reg_write(tp, addr: 0xb890, data: 0x0c0e);
8007	ocp_reg_write(tp, addr: 0xb88e, data: 0xc248);
8008	ocp_reg_write(tp, addr: 0xb890, data: 0x1012);
8009	ocp_reg_write(tp, addr: 0xb88e, data: 0xc24a);
8010	ocp_reg_write(tp, addr: 0xb890, data: 0x1416);
8011	data = ocp_reg_read(tp, addr: 0xb896);
8012	data |= BIT(0);
8013	ocp_reg_write(tp, addr: 0xb896, data);
8014
8015	rtl_phy_patch_request(tp, request: false, wait: true);
8016
8017	data = ocp_reg_read(tp, addr: 0xa86a);
8018	data |= BIT(0);
8019	ocp_reg_write(tp, addr: 0xa86a, data);
8020	data = ocp_reg_read(tp, addr: 0xa6f0);
8021	data |= BIT(0);
8022	ocp_reg_write(tp, addr: 0xa6f0, data);
8023
8024	ocp_reg_write(tp, addr: 0xbfa0, data: 0xd70d);
8025	ocp_reg_write(tp, addr: 0xbfa2, data: 0x4100);
8026	ocp_reg_write(tp, addr: 0xbfa4, data: 0xe868);
8027	ocp_reg_write(tp, addr: 0xbfa6, data: 0xdc59);
8028	ocp_reg_write(tp, addr: 0xb54c, data: 0x3c18);
8029	data = ocp_reg_read(tp, addr: 0xbfa4);
8030	data &= ~BIT(5);
8031	ocp_reg_write(tp, addr: 0xbfa4, data);
8032	data = sram_read(tp, addr: 0x817d);
8033	data |= BIT(12);
8034	sram_write(tp, addr: 0x817d, data);
8035	break;
8036	case RTL_VER_13:
8037	/* 2.5G INRX */
8038	data = ocp_reg_read(tp, addr: 0xac46);
8039	data &= ~0x00f0;
8040	data |= 0x0090;
8041	ocp_reg_write(tp, addr: 0xac46, data);
8042	data = ocp_reg_read(tp, addr: 0xad30);
8043	data &= ~0x0003;
8044	data |= 0x0001;
8045	ocp_reg_write(tp, addr: 0xad30, data);
8046	fallthrough;
8047	case RTL_VER_15:
8048	/* EEE parameter */
8049	ocp_reg_write(tp, addr: 0xb87c, data: 0x80f5);
8050	ocp_reg_write(tp, addr: 0xb87e, data: 0x760e);
8051	ocp_reg_write(tp, addr: 0xb87c, data: 0x8107);
8052	ocp_reg_write(tp, addr: 0xb87e, data: 0x360e);
8053	ocp_reg_write(tp, addr: 0xb87c, data: 0x8551);
8054	data = ocp_reg_read(tp, addr: 0xb87e);
8055	data &= ~0xff00;
8056	data |= 0x0800;
8057	ocp_reg_write(tp, addr: 0xb87e, data);
8058
8059	/* ADC_PGA parameter */
8060	data = ocp_reg_read(tp, addr: 0xbf00);
8061	data &= ~0xe000;
8062	data |= 0xa000;
8063	ocp_reg_write(tp, addr: 0xbf00, data);
8064	data = ocp_reg_read(tp, addr: 0xbf46);
8065	data &= ~0x0f00;
8066	data |= 0x0300;
8067	ocp_reg_write(tp, addr: 0xbf46, data);
8068
8069	/* Green Table-PGA, 1G full viterbi */
8070	sram_write(tp, addr: 0x8044, data: 0x2417);
8071	sram_write(tp, addr: 0x804a, data: 0x2417);
8072	sram_write(tp, addr: 0x8050, data: 0x2417);
8073	sram_write(tp, addr: 0x8056, data: 0x2417);
8074	sram_write(tp, addr: 0x805c, data: 0x2417);
8075	sram_write(tp, addr: 0x8062, data: 0x2417);
8076	sram_write(tp, addr: 0x8068, data: 0x2417);
8077	sram_write(tp, addr: 0x806e, data: 0x2417);
8078	sram_write(tp, addr: 0x8074, data: 0x2417);
8079	sram_write(tp, addr: 0x807a, data: 0x2417);
8080
8081	/* XG PLL */
8082	data = ocp_reg_read(tp, addr: 0xbf84);
8083	data &= ~0xe000;
8084	data |= 0xa000;
8085	ocp_reg_write(tp, addr: 0xbf84, data);
8086	break;
8087	default:
8088	break;
8089	}
8090
8091	/* Notify the MAC when the speed is changed to force mode. */
8092	data = ocp_reg_read(tp, OCP_INTR_EN);
8093	data |= INTR_SPEED_FORCE;
8094	ocp_reg_write(tp, OCP_INTR_EN, data);
8095
8096	if (rtl_phy_patch_request(tp, request: true, wait: true))
8097	return;
8098
8099	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
8100	ocp_data |= EEE_SPDWN_EN;
8101	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, data: ocp_data);
8102
8103	data = ocp_reg_read(tp, OCP_DOWN_SPEED);
8104	data &= ~(EN_EEE_100 | EN_EEE_1000);
8105	data |= EN_10M_CLKDIV;
8106	ocp_reg_write(tp, OCP_DOWN_SPEED, data);
8107	tp->ups_info._10m_ckdiv = true;
8108	tp->ups_info.eee_plloff_100 = false;
8109	tp->ups_info.eee_plloff_giga = false;
8110
8111	data = ocp_reg_read(tp, OCP_POWER_CFG);
8112	data &= ~EEE_CLKDIV_EN;
8113	ocp_reg_write(tp, OCP_POWER_CFG, data);
8114	tp->ups_info.eee_ckdiv = false;
8115
8116	rtl_phy_patch_request(tp, request: false, wait: true);
8117
8118	rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
8119
8120	data = ocp_reg_read(tp, addr: 0xa428);
8121	data &= ~BIT(9);
8122	ocp_reg_write(tp, addr: 0xa428, data);
8123	data = ocp_reg_read(tp, addr: 0xa5ea);
8124	data &= ~BIT(0);
8125	ocp_reg_write(tp, addr: 0xa5ea, data);
8126	tp->ups_info.lite_mode = 0;
8127
8128	if (tp->eee_en)
8129	rtl_eee_enable(tp, enable: true);
8130
8131	r8153_aldps_en(tp, enable: true);
8132	r8152b_enable_fc(tp);
8133	r8153_u2p3en(tp, enable: true);
8134
8135	set_bit(nr: PHY_RESET, addr: &tp->flags);
8136	}
8137
8138	static void r8156_init(struct r8152 *tp)
8139	{
8140	u32 ocp_data;
8141	u16 data;
8142	int i;
8143
8144	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
8145	return;
8146
8147	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP);
8148	ocp_data &= ~EN_ALL_SPEED;
8149	ocp_write_byte(tp, MCU_TYPE_USB, USB_ECM_OP, data: ocp_data);
8150
8151	ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, data: 0);
8152
8153	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_ECM_OPTION);
8154	ocp_data |= BYPASS_MAC_RESET;
8155	ocp_write_word(tp, MCU_TYPE_USB, USB_ECM_OPTION, data: ocp_data);
8156
8157	r8153b_u1u2en(tp, enable: false);
8158
8159	for (i = 0; i < 500; i++) {
8160	if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
8161	AUTOLOAD_DONE)
8162	break;
8163
8164	msleep(msecs: 20);
8165	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
8166	return;
8167	}
8168
8169	data = r8153_phy_status(tp, desired: 0);
8170	if (data == PHY_STAT_EXT_INIT) {
8171	data = ocp_reg_read(tp, addr: 0xa468);
8172	data &= ~(BIT(3) | BIT(1));
8173	ocp_reg_write(tp, addr: 0xa468, data);
8174	}
8175
8176	data = r8152_mdio_read(tp, MII_BMCR);
8177	if (data & BMCR_PDOWN) {
8178	data &= ~BMCR_PDOWN;
8179	r8152_mdio_write(tp, MII_BMCR, value: data);
8180	}
8181
8182	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
8183	WARN_ON_ONCE(data != PHY_STAT_LAN_ON);
8184
8185	r8153_u2p3en(tp, enable: false);
8186
8187	/* MSC timer = 0xfff * 8ms = 32760 ms */
8188	ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, data: 0x0fff);
8189
8190	/* U1/U2/L1 idle timer. 500 us */
8191	ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, data: 500);
8192
8193	r8153b_power_cut_en(tp, enable: false);
8194	r8156_ups_en(tp, enable: false);
8195	r8153_queue_wake(tp, enable: false);
8196	rtl_runtime_suspend_enable(tp, enable: false);
8197
8198	if (tp->udev->speed >= USB_SPEED_SUPER)
8199	r8153b_u1u2en(tp, enable: true);
8200
8201	usb_enable_lpm(udev: tp->udev);
8202
8203	r8156_mac_clk_spd(tp, enable: true);
8204
8205	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
8206	ocp_data &= ~PLA_MCU_SPDWN_EN;
8207	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, data: ocp_data);
8208
8209	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
8210	if (rtl8152_get_speed(tp) & LINK_STATUS)
8211	ocp_data |= CUR_LINK_OK;
8212	else
8213	ocp_data &= ~CUR_LINK_OK;
8214	ocp_data |= POLL_LINK_CHG;
8215	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, data: ocp_data);
8216
8217	set_bit(nr: GREEN_ETHERNET, addr: &tp->flags);
8218
8219	/* rx aggregation */
8220	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
8221	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
8222	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, data: ocp_data);
8223
8224	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_CONFIG);
8225	ocp_data |= ACT_ODMA;
8226	ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_CONFIG, data: ocp_data);
8227
8228	r8156_mdio_force_mode(tp);
8229	rtl_tally_reset(tp);
8230
8231	tp->coalesce = 15000; /* 15 us */
8232	}
8233
8234	static void r8156b_init(struct r8152 *tp)
8235	{
8236	u32 ocp_data;
8237	u16 data;
8238	int i;
8239
8240	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
8241	return;
8242
8243	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP);
8244	ocp_data &= ~EN_ALL_SPEED;
8245	ocp_write_byte(tp, MCU_TYPE_USB, USB_ECM_OP, data: ocp_data);
8246
8247	ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, data: 0);
8248
8249	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_ECM_OPTION);
8250	ocp_data |= BYPASS_MAC_RESET;
8251	ocp_write_word(tp, MCU_TYPE_USB, USB_ECM_OPTION, data: ocp_data);
8252
8253	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
8254	ocp_data |= RX_DETECT8;
8255	ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, data: ocp_data);
8256
8257	r8153b_u1u2en(tp, enable: false);
8258
8259	switch (tp->version) {
8260	case RTL_VER_13:
8261	case RTL_VER_15:
8262	r8156b_wait_loading_flash(tp);
8263	break;
8264	default:
8265	break;
8266	}
8267
8268	for (i = 0; i < 500; i++) {
8269	if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
8270	AUTOLOAD_DONE)
8271	break;
8272
8273	msleep(msecs: 20);
8274	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
8275	return;
8276	}
8277
8278	data = r8153_phy_status(tp, desired: 0);
8279	if (data == PHY_STAT_EXT_INIT) {
8280	data = ocp_reg_read(tp, addr: 0xa468);
8281	data &= ~(BIT(3) | BIT(1));
8282	ocp_reg_write(tp, addr: 0xa468, data);
8283
8284	data = ocp_reg_read(tp, addr: 0xa466);
8285	data &= ~BIT(0);
8286	ocp_reg_write(tp, addr: 0xa466, data);
8287	}
8288
8289	data = r8152_mdio_read(tp, MII_BMCR);
8290	if (data & BMCR_PDOWN) {
8291	data &= ~BMCR_PDOWN;
8292	r8152_mdio_write(tp, MII_BMCR, value: data);
8293	}
8294
8295	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
8296
8297	r8153_u2p3en(tp, enable: false);
8298
8299	/* MSC timer = 0xfff * 8ms = 32760 ms */
8300	ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, data: 0x0fff);
8301
8302	/* U1/U2/L1 idle timer. 500 us */
8303	ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, data: 500);
8304
8305	r8153b_power_cut_en(tp, enable: false);
8306	r8156_ups_en(tp, enable: false);
8307	r8153_queue_wake(tp, enable: false);
8308	rtl_runtime_suspend_enable(tp, enable: false);
8309
8310	if (tp->udev->speed >= USB_SPEED_SUPER)
8311	r8153b_u1u2en(tp, enable: true);
8312
8313	usb_enable_lpm(udev: tp->udev);
8314
8315	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR);
8316	ocp_data &= ~SLOT_EN;
8317	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR, data: ocp_data);
8318
8319	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
8320	ocp_data |= FLOW_CTRL_EN;
8321	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, data: ocp_data);
8322
8323	/* enable fc timer and set timer to 600 ms. */
8324	ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER,
8325	CTRL_TIMER_EN | (600 / 8));
8326
8327	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
8328	if (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & DACK_DET_EN))
8329	ocp_data |= FLOW_CTRL_PATCH_2;
8330	ocp_data &= ~AUTO_SPEEDUP;
8331	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, data: ocp_data);
8332
8333	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
8334	ocp_data |= FC_PATCH_TASK;
8335	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, data: ocp_data);
8336
8337	r8156_mac_clk_spd(tp, enable: true);
8338
8339	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
8340	ocp_data &= ~PLA_MCU_SPDWN_EN;
8341	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, data: ocp_data);
8342
8343	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
8344	if (rtl8152_get_speed(tp) & LINK_STATUS)
8345	ocp_data |= CUR_LINK_OK;
8346	else
8347	ocp_data &= ~CUR_LINK_OK;
8348	ocp_data |= POLL_LINK_CHG;
8349	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, data: ocp_data);
8350
8351	set_bit(nr: GREEN_ETHERNET, addr: &tp->flags);
8352
8353	/* rx aggregation */
8354	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
8355	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
8356	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, data: ocp_data);
8357
8358	r8156_mdio_force_mode(tp);
8359	rtl_tally_reset(tp);
8360
8361	tp->coalesce = 15000; /* 15 us */
8362	}
8363
8364	static bool rtl_check_vendor_ok(struct usb_interface *intf)
8365	{
8366	struct usb_host_interface *alt = intf->cur_altsetting;
8367	struct usb_endpoint_descriptor *in, *out, *intr;
8368
8369	if (usb_find_common_endpoints(alt, bulk_in: &in, bulk_out: &out, int_in: &intr, NULL) < 0) {
8370	dev_err(&intf->dev, "Expected endpoints are not found\n");
8371	return false;
8372	}
8373
8374	/* Check Rx endpoint address */
8375	if (usb_endpoint_num(epd: in) != 1) {
8376	dev_err(&intf->dev, "Invalid Rx endpoint address\n");
8377	return false;
8378	}
8379
8380	/* Check Tx endpoint address */
8381	if (usb_endpoint_num(epd: out) != 2) {
8382	dev_err(&intf->dev, "Invalid Tx endpoint address\n");
8383	return false;
8384	}
8385
8386	/* Check interrupt endpoint address */
8387	if (usb_endpoint_num(epd: intr) != 3) {
8388	dev_err(&intf->dev, "Invalid interrupt endpoint address\n");
8389	return false;
8390	}
8391
8392	return true;
8393	}
8394
8395	static int rtl8152_pre_reset(struct usb_interface *intf)
8396	{
8397	struct r8152 *tp = usb_get_intfdata(intf);
8398	struct net_device *netdev;
8399
8400	if (!tp || !test_bit(PROBED_WITH_NO_ERRORS, &tp->flags))
8401	return 0;
8402
8403	netdev = tp->netdev;
8404	if (!netif_running(dev: netdev))
8405	return 0;
8406
8407	netif_stop_queue(dev: netdev);
8408	tasklet_disable(t: &tp->tx_tl);
8409	clear_bit(nr: WORK_ENABLE, addr: &tp->flags);
8410	usb_kill_urb(urb: tp->intr_urb);
8411	cancel_delayed_work_sync(dwork: &tp->schedule);
8412	napi_disable(n: &tp->napi);
8413	if (netif_carrier_ok(dev: netdev)) {
8414	mutex_lock(&tp->control);
8415	set_bit(nr: IN_PRE_RESET, addr: &tp->flags);
8416	tp->rtl_ops.disable(tp);
8417	clear_bit(nr: IN_PRE_RESET, addr: &tp->flags);
8418	mutex_unlock(lock: &tp->control);
8419	}
8420
8421	return 0;
8422	}
8423
8424	static int rtl8152_post_reset(struct usb_interface *intf)
8425	{
8426	struct r8152 *tp = usb_get_intfdata(intf);
8427	struct net_device *netdev;
8428	struct sockaddr sa;
8429
8430	if (!tp || !test_bit(PROBED_WITH_NO_ERRORS, &tp->flags))
8431	return 0;
8432
8433	rtl_set_accessible(tp);
8434
8435	/* reset the MAC address in case of policy change */
8436	if (determine_ethernet_addr(tp, sa: &sa) >= 0) {
8437	rtnl_lock();
8438	dev_set_mac_address (dev: tp->netdev, sa: &sa, NULL);
8439	rtnl_unlock();
8440	}
8441
8442	netdev = tp->netdev;
8443	if (!netif_running(dev: netdev))
8444	return 0;
8445
8446	set_bit(nr: WORK_ENABLE, addr: &tp->flags);
8447	if (netif_carrier_ok(dev: netdev)) {
8448	mutex_lock(&tp->control);
8449	tp->rtl_ops.enable(tp);
8450	rtl_start_rx(tp);
8451	_rtl8152_set_rx_mode(netdev);
8452	mutex_unlock(lock: &tp->control);
8453	}
8454
8455	napi_enable(n: &tp->napi);
8456	tasklet_enable(t: &tp->tx_tl);
8457	netif_wake_queue(dev: netdev);
8458	usb_submit_urb(urb: tp->intr_urb, GFP_KERNEL);
8459
8460	if (!list_empty(head: &tp->rx_done))
8461	napi_schedule(n: &tp->napi);
8462
8463	return 0;
8464	}
8465
8466	static bool delay_autosuspend(struct r8152 *tp)
8467	{
8468	bool sw_linking = !!netif_carrier_ok(dev: tp->netdev);
8469	bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
8470
8471	/* This means a linking change occurs and the driver doesn't detect it,
8472	* yet. If the driver has disabled tx/rx and hw is linking on, the
8473	* device wouldn't wake up by receiving any packet.
8474	*/
8475	if (work_busy(work: &tp->schedule.work) || sw_linking != hw_linking)
8476	return true;
8477
8478	/* If the linking down is occurred by nway, the device may miss the
8479	* linking change event. And it wouldn't wake when linking on.
8480	*/
8481	if (!sw_linking && tp->rtl_ops.in_nway(tp))
8482	return true;
8483	else if (!skb_queue_empty(list: &tp->tx_queue))
8484	return true;
8485	else
8486	return false;
8487	}
8488
8489	static int rtl8152_runtime_resume(struct r8152 *tp)
8490	{
8491	struct net_device *netdev = tp->netdev;
8492
8493	if (netif_running(dev: netdev) && netdev->flags & IFF_UP) {
8494	struct napi_struct *napi = &tp->napi;
8495
8496	tp->rtl_ops.autosuspend_en(tp, false);
8497	napi_disable(n: napi);
8498	set_bit(nr: WORK_ENABLE, addr: &tp->flags);
8499
8500	if (netif_carrier_ok(dev: netdev)) {
8501	if (rtl8152_get_speed(tp) & LINK_STATUS) {
8502	rtl_start_rx(tp);
8503	} else {
8504	netif_carrier_off(dev: netdev);
8505	tp->rtl_ops.disable(tp);
8506	netif_info(tp, link, netdev, "linking down\n");
8507	}
8508	}
8509
8510	napi_enable(n: napi);
8511	clear_bit(nr: SELECTIVE_SUSPEND, addr: &tp->flags);
8512	smp_mb__after_atomic();
8513
8514	if (!list_empty(head: &tp->rx_done))
8515	napi_schedule(n: &tp->napi);
8516
8517	usb_submit_urb(urb: tp->intr_urb, GFP_NOIO);
8518	} else {
8519	if (netdev->flags & IFF_UP)
8520	tp->rtl_ops.autosuspend_en(tp, false);
8521
8522	clear_bit(nr: SELECTIVE_SUSPEND, addr: &tp->flags);
8523	}
8524
8525	return 0;
8526	}
8527
8528	static int rtl8152_system_resume(struct r8152 *tp)
8529	{
8530	struct net_device *netdev = tp->netdev;
8531
8532	netif_device_attach(dev: netdev);
8533
8534	if (netif_running(dev: netdev) && (netdev->flags & IFF_UP)) {
8535	tp->rtl_ops.up(tp);
8536	netif_carrier_off(dev: netdev);
8537	set_bit(nr: WORK_ENABLE, addr: &tp->flags);
8538	usb_submit_urb(urb: tp->intr_urb, GFP_NOIO);
8539	}
8540
8541	return 0;
8542	}
8543
8544	static int rtl8152_runtime_suspend(struct r8152 *tp)
8545	{
8546	struct net_device *netdev = tp->netdev;
8547	int ret = 0;
8548
8549	if (!tp->rtl_ops.autosuspend_en)
8550	return -EBUSY;
8551
8552	set_bit(nr: SELECTIVE_SUSPEND, addr: &tp->flags);
8553	smp_mb__after_atomic();
8554
8555	if (netif_running(dev: netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
8556	u32 rcr = 0;
8557
8558	if (netif_carrier_ok(dev: netdev)) {
8559	u32 ocp_data;
8560
8561	rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
8562	ocp_data = rcr & ~RCR_ACPT_ALL;
8563	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, data: ocp_data);
8564	rxdy_gated_en(tp, enable: true);
8565	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA,
8566	PLA_OOB_CTRL);
8567	if (!(ocp_data & RXFIFO_EMPTY)) {
8568	rxdy_gated_en(tp, enable: false);
8569	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, data: rcr);
8570	clear_bit(nr: SELECTIVE_SUSPEND, addr: &tp->flags);
8571	smp_mb__after_atomic();
8572	ret = -EBUSY;
8573	goto out1;
8574	}
8575	}
8576
8577	clear_bit(nr: WORK_ENABLE, addr: &tp->flags);
8578	usb_kill_urb(urb: tp->intr_urb);
8579
8580	tp->rtl_ops.autosuspend_en(tp, true);
8581
8582	if (netif_carrier_ok(dev: netdev)) {
8583	struct napi_struct *napi = &tp->napi;
8584
8585	napi_disable(n: napi);
8586	rtl_stop_rx(tp);
8587	rxdy_gated_en(tp, enable: false);
8588	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, data: rcr);
8589	napi_enable(n: napi);
8590	}
8591
8592	if (delay_autosuspend(tp)) {
8593	rtl8152_runtime_resume(tp);
8594	ret = -EBUSY;
8595	}
8596	}
8597
8598	out1:
8599	return ret;
8600	}
8601
8602	static int rtl8152_system_suspend(struct r8152 *tp)
8603	{
8604	struct net_device *netdev = tp->netdev;
8605
8606	netif_device_detach(dev: netdev);
8607
8608	if (netif_running(dev: netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
8609	struct napi_struct *napi = &tp->napi;
8610
8611	clear_bit(nr: WORK_ENABLE, addr: &tp->flags);
8612	usb_kill_urb(urb: tp->intr_urb);
8613	tasklet_disable(t: &tp->tx_tl);
8614	napi_disable(n: napi);
8615	cancel_delayed_work_sync(dwork: &tp->schedule);
8616	tp->rtl_ops.down(tp);
8617	napi_enable(n: napi);
8618	tasklet_enable(t: &tp->tx_tl);
8619	}
8620
8621	return 0;
8622	}
8623
8624	static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
8625	{
8626	struct r8152 *tp = usb_get_intfdata(intf);
8627	int ret;
8628
8629	mutex_lock(&tp->control);
8630
8631	if (PMSG_IS_AUTO(message))
8632	ret = rtl8152_runtime_suspend(tp);
8633	else
8634	ret = rtl8152_system_suspend(tp);
8635
8636	mutex_unlock(lock: &tp->control);
8637
8638	return ret;
8639	}
8640
8641	static int rtl8152_resume(struct usb_interface *intf)
8642	{
8643	struct r8152 *tp = usb_get_intfdata(intf);
8644	int ret;
8645
8646	mutex_lock(&tp->control);
8647
8648	rtl_reset_ocp_base(tp);
8649
8650	if (test_bit(SELECTIVE_SUSPEND, &tp->flags))
8651	ret = rtl8152_runtime_resume(tp);
8652	else
8653	ret = rtl8152_system_resume(tp);
8654
8655	mutex_unlock(lock: &tp->control);
8656
8657	return ret;
8658	}
8659
8660	static int rtl8152_reset_resume(struct usb_interface *intf)
8661	{
8662	struct r8152 *tp = usb_get_intfdata(intf);
8663
8664	clear_bit(nr: SELECTIVE_SUSPEND, addr: &tp->flags);
8665	rtl_reset_ocp_base(tp);
8666	tp->rtl_ops.init(tp);
8667	queue_delayed_work(wq: system_long_wq, dwork: &tp->hw_phy_work, delay: 0);
8668	set_ethernet_addr(tp, in_resume: true);
8669	return rtl8152_resume(intf);
8670	}
8671
8672	static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8673	{
8674	struct r8152 *tp = netdev_priv(dev);
8675
8676	if (usb_autopm_get_interface(intf: tp->intf) < 0)
8677	return;
8678
8679	if (!rtl_can_wakeup(tp)) {
8680	wol->supported = 0;
8681	wol->wolopts = 0;
8682	} else {
8683	mutex_lock(&tp->control);
8684	wol->supported = WAKE_ANY;
8685	wol->wolopts = __rtl_get_wol(tp);
8686	mutex_unlock(lock: &tp->control);
8687	}
8688
8689	usb_autopm_put_interface(intf: tp->intf);
8690	}
8691
8692	static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8693	{
8694	struct r8152 *tp = netdev_priv(dev);
8695	int ret;
8696
8697	if (!rtl_can_wakeup(tp))
8698	return -EOPNOTSUPP;
8699
8700	if (wol->wolopts & ~WAKE_ANY)
8701	return -EINVAL;
8702
8703	ret = usb_autopm_get_interface(intf: tp->intf);
8704	if (ret < 0)
8705	goto out_set_wol;
8706
8707	mutex_lock(&tp->control);
8708
8709	__rtl_set_wol(tp, wolopts: wol->wolopts);
8710	tp->saved_wolopts = wol->wolopts & WAKE_ANY;
8711
8712	mutex_unlock(lock: &tp->control);
8713
8714	usb_autopm_put_interface(intf: tp->intf);
8715
8716	out_set_wol:
8717	return ret;
8718	}
8719
8720	static u32 rtl8152_get_msglevel(struct net_device *dev)
8721	{
8722	struct r8152 *tp = netdev_priv(dev);
8723
8724	return tp->msg_enable;
8725	}
8726
8727	static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
8728	{
8729	struct r8152 *tp = netdev_priv(dev);
8730
8731	tp->msg_enable = value;
8732	}
8733
8734	static void rtl8152_get_drvinfo(struct net_device *netdev,
8735	struct ethtool_drvinfo *info)
8736	{
8737	struct r8152 *tp = netdev_priv(dev: netdev);
8738
8739	strscpy(p: info->driver, MODULENAME, size: sizeof(info->driver));
8740	strscpy(p: info->version, DRIVER_VERSION, size: sizeof(info->version));
8741	usb_make_path(dev: tp->udev, buf: info->bus_info, size: sizeof(info->bus_info));
8742	if (!IS_ERR_OR_NULL(ptr: tp->rtl_fw.fw))
8743	strscpy(p: info->fw_version, q: tp->rtl_fw.version,
8744	size: sizeof(info->fw_version));
8745	}
8746
8747	static
8748	int rtl8152_get_link_ksettings(struct net_device *netdev,
8749	struct ethtool_link_ksettings *cmd)
8750	{
8751	struct r8152 *tp = netdev_priv(dev: netdev);
8752	int ret;
8753
8754	if (!tp->mii.mdio_read)
8755	return -EOPNOTSUPP;
8756
8757	ret = usb_autopm_get_interface(intf: tp->intf);
8758	if (ret < 0)
8759	goto out;
8760
8761	mutex_lock(&tp->control);
8762
8763	mii_ethtool_get_link_ksettings(mii: &tp->mii, cmd);
8764
8765	linkmode_mod_bit(nr: ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
8766	addr: cmd->link_modes.supported, set: tp->support_2500full);
8767
8768	if (tp->support_2500full) {
8769	linkmode_mod_bit(nr: ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
8770	addr: cmd->link_modes.advertising,
8771	set: ocp_reg_read(tp, OCP_10GBT_CTRL) & MDIO_AN_10GBT_CTRL_ADV2_5G);
8772
8773	linkmode_mod_bit(nr: ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
8774	addr: cmd->link_modes.lp_advertising,
8775	set: ocp_reg_read(tp, OCP_10GBT_STAT) & MDIO_AN_10GBT_STAT_LP2_5G);
8776
8777	if (is_speed_2500(rtl8152_get_speed(tp)))
8778	cmd->base.speed = SPEED_2500;
8779	}
8780
8781	mutex_unlock(lock: &tp->control);
8782
8783	usb_autopm_put_interface(intf: tp->intf);
8784
8785	out:
8786	return ret;
8787	}
8788
8789	static int rtl8152_set_link_ksettings(struct net_device *dev,
8790	const struct ethtool_link_ksettings *cmd)
8791	{
8792	struct r8152 *tp = netdev_priv(dev);
8793	u32 advertising = 0;
8794	int ret;
8795
8796	ret = usb_autopm_get_interface(intf: tp->intf);
8797	if (ret < 0)
8798	goto out;
8799
8800	if (test_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
8801	cmd->link_modes.advertising))
8802	advertising |= RTL_ADVERTISED_10_HALF;
8803
8804	if (test_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
8805	cmd->link_modes.advertising))
8806	advertising |= RTL_ADVERTISED_10_FULL;
8807
8808	if (test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
8809	cmd->link_modes.advertising))
8810	advertising |= RTL_ADVERTISED_100_HALF;
8811
8812	if (test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
8813	cmd->link_modes.advertising))
8814	advertising |= RTL_ADVERTISED_100_FULL;
8815
8816	if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
8817	cmd->link_modes.advertising))
8818	advertising |= RTL_ADVERTISED_1000_HALF;
8819
8820	if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
8821	cmd->link_modes.advertising))
8822	advertising |= RTL_ADVERTISED_1000_FULL;
8823
8824	if (test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
8825	cmd->link_modes.advertising))
8826	advertising |= RTL_ADVERTISED_2500_FULL;
8827
8828	mutex_lock(&tp->control);
8829
8830	ret = rtl8152_set_speed(tp, autoneg: cmd->base.autoneg, speed: cmd->base.speed,
8831	duplex: cmd->base.duplex, advertising);
8832	if (!ret) {
8833	tp->autoneg = cmd->base.autoneg;
8834	tp->speed = cmd->base.speed;
8835	tp->duplex = cmd->base.duplex;
8836	tp->advertising = advertising;
8837	}
8838
8839	mutex_unlock(lock: &tp->control);
8840
8841	usb_autopm_put_interface(intf: tp->intf);
8842
8843	out:
8844	return ret;
8845	}
8846
8847	static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
8848	"tx_packets",
8849	"rx_packets",
8850	"tx_errors",
8851	"rx_errors",
8852	"rx_missed",
8853	"align_errors",
8854	"tx_single_collisions",
8855	"tx_multi_collisions",
8856	"rx_unicast",
8857	"rx_broadcast",
8858	"rx_multicast",
8859	"tx_aborted",
8860	"tx_underrun",
8861	};
8862
8863	static int rtl8152_get_sset_count(struct net_device *dev, int sset)
8864	{
8865	switch (sset) {
8866	case ETH_SS_STATS:
8867	return ARRAY_SIZE(rtl8152_gstrings);
8868	default:
8869	return -EOPNOTSUPP;
8870	}
8871	}
8872
8873	static void rtl8152_get_ethtool_stats(struct net_device *dev,
8874	struct ethtool_stats *stats, u64 *data)
8875	{
8876	struct r8152 *tp = netdev_priv(dev);
8877	struct tally_counter tally;
8878
8879	if (usb_autopm_get_interface(intf: tp->intf) < 0)
8880	return;
8881
8882	generic_ocp_read(tp, PLA_TALLYCNT, size: sizeof(tally), data: &tally, MCU_TYPE_PLA);
8883
8884	usb_autopm_put_interface(intf: tp->intf);
8885
8886	data[0] = le64_to_cpu(tally.tx_packets);
8887	data[1] = le64_to_cpu(tally.rx_packets);
8888	data[2] = le64_to_cpu(tally.tx_errors);
8889	data[3] = le32_to_cpu(tally.rx_errors);
8890	data[4] = le16_to_cpu(tally.rx_missed);
8891	data[5] = le16_to_cpu(tally.align_errors);
8892	data[6] = le32_to_cpu(tally.tx_one_collision);
8893	data[7] = le32_to_cpu(tally.tx_multi_collision);
8894	data[8] = le64_to_cpu(tally.rx_unicast);
8895	data[9] = le64_to_cpu(tally.rx_broadcast);
8896	data[10] = le32_to_cpu(tally.rx_multicast);
8897	data[11] = le16_to_cpu(tally.tx_aborted);
8898	data[12] = le16_to_cpu(tally.tx_underrun);
8899	}
8900
8901	static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
8902	{
8903	switch (stringset) {
8904	case ETH_SS_STATS:
8905	memcpy(data, rtl8152_gstrings, sizeof(rtl8152_gstrings));
8906	break;
8907	}
8908	}
8909
8910	static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
8911	{
8912	u32 lp, adv, supported = 0;
8913	u16 val;
8914
8915	val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
8916	supported = mmd_eee_cap_to_ethtool_sup_t(eee_cap: val);
8917
8918	val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
8919	adv = mmd_eee_adv_to_ethtool_adv_t(eee_adv: val);
8920
8921	val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
8922	lp = mmd_eee_adv_to_ethtool_adv_t(eee_adv: val);
8923
8924	eee->eee_enabled = tp->eee_en;
8925	eee->eee_active = !!(supported & adv & lp);
8926	eee->supported = supported;
8927	eee->advertised = tp->eee_adv;
8928	eee->lp_advertised = lp;
8929
8930	return 0;
8931	}
8932
8933	static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
8934	{
8935	u16 val = ethtool_adv_to_mmd_eee_adv_t(adv: eee->advertised);
8936
8937	tp->eee_en = eee->eee_enabled;
8938	tp->eee_adv = val;
8939
8940	rtl_eee_enable(tp, enable: tp->eee_en);
8941
8942	return 0;
8943	}
8944
8945	static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
8946	{
8947	u32 lp, adv, supported = 0;
8948	u16 val;
8949
8950	val = ocp_reg_read(tp, OCP_EEE_ABLE);
8951	supported = mmd_eee_cap_to_ethtool_sup_t(eee_cap: val);
8952
8953	val = ocp_reg_read(tp, OCP_EEE_ADV);
8954	adv = mmd_eee_adv_to_ethtool_adv_t(eee_adv: val);
8955
8956	val = ocp_reg_read(tp, OCP_EEE_LPABLE);
8957	lp = mmd_eee_adv_to_ethtool_adv_t(eee_adv: val);
8958
8959	eee->eee_enabled = tp->eee_en;
8960	eee->eee_active = !!(supported & adv & lp);
8961	eee->supported = supported;
8962	eee->advertised = tp->eee_adv;
8963	eee->lp_advertised = lp;
8964
8965	return 0;
8966	}
8967
8968	static int
8969	rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
8970	{
8971	struct r8152 *tp = netdev_priv(dev: net);
8972	int ret;
8973
8974	if (!tp->rtl_ops.eee_get) {
8975	ret = -EOPNOTSUPP;
8976	goto out;
8977	}
8978
8979	ret = usb_autopm_get_interface(intf: tp->intf);
8980	if (ret < 0)
8981	goto out;
8982
8983	mutex_lock(&tp->control);
8984
8985	ret = tp->rtl_ops.eee_get(tp, edata);
8986
8987	mutex_unlock(lock: &tp->control);
8988
8989	usb_autopm_put_interface(intf: tp->intf);
8990
8991	out:
8992	return ret;
8993	}
8994
8995	static int
8996	rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
8997	{
8998	struct r8152 *tp = netdev_priv(dev: net);
8999	int ret;
9000
9001	if (!tp->rtl_ops.eee_set) {
9002	ret = -EOPNOTSUPP;
9003	goto out;
9004	}
9005
9006	ret = usb_autopm_get_interface(intf: tp->intf);
9007	if (ret < 0)
9008	goto out;
9009
9010	mutex_lock(&tp->control);
9011
9012	ret = tp->rtl_ops.eee_set(tp, edata);
9013	if (!ret)
9014	ret = mii_nway_restart(mii: &tp->mii);
9015
9016	mutex_unlock(lock: &tp->control);
9017
9018	usb_autopm_put_interface(intf: tp->intf);
9019
9020	out:
9021	return ret;
9022	}
9023
9024	static int rtl8152_nway_reset(struct net_device *dev)
9025	{
9026	struct r8152 *tp = netdev_priv(dev);
9027	int ret;
9028
9029	ret = usb_autopm_get_interface(intf: tp->intf);
9030	if (ret < 0)
9031	goto out;
9032
9033	mutex_lock(&tp->control);
9034
9035	ret = mii_nway_restart(mii: &tp->mii);
9036
9037	mutex_unlock(lock: &tp->control);
9038
9039	usb_autopm_put_interface(intf: tp->intf);
9040
9041	out:
9042	return ret;
9043	}
9044
9045	static int rtl8152_get_coalesce(struct net_device *netdev,
9046	struct ethtool_coalesce *coalesce,
9047	struct kernel_ethtool_coalesce *kernel_coal,
9048	struct netlink_ext_ack *extack)
9049	{
9050	struct r8152 *tp = netdev_priv(dev: netdev);
9051
9052	switch (tp->version) {
9053	case RTL_VER_01:
9054	case RTL_VER_02:
9055	case RTL_VER_07:
9056	return -EOPNOTSUPP;
9057	default:
9058	break;
9059	}
9060
9061	coalesce->rx_coalesce_usecs = tp->coalesce;
9062
9063	return 0;
9064	}
9065
9066	static int rtl8152_set_coalesce(struct net_device *netdev,
9067	struct ethtool_coalesce *coalesce,
9068	struct kernel_ethtool_coalesce *kernel_coal,
9069	struct netlink_ext_ack *extack)
9070	{
9071	struct r8152 *tp = netdev_priv(dev: netdev);
9072	int ret;
9073
9074	switch (tp->version) {
9075	case RTL_VER_01:
9076	case RTL_VER_02:
9077	case RTL_VER_07:
9078	return -EOPNOTSUPP;
9079	default:
9080	break;
9081	}
9082
9083	if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
9084	return -EINVAL;
9085
9086	ret = usb_autopm_get_interface(intf: tp->intf);
9087	if (ret < 0)
9088	return ret;
9089
9090	mutex_lock(&tp->control);
9091
9092	if (tp->coalesce != coalesce->rx_coalesce_usecs) {
9093	tp->coalesce = coalesce->rx_coalesce_usecs;
9094
9095	if (netif_running(dev: netdev) && netif_carrier_ok(dev: netdev)) {
9096	netif_stop_queue(dev: netdev);
9097	napi_disable(n: &tp->napi);
9098	tp->rtl_ops.disable(tp);
9099	tp->rtl_ops.enable(tp);
9100	rtl_start_rx(tp);
9101	clear_bit(nr: RTL8152_SET_RX_MODE, addr: &tp->flags);
9102	_rtl8152_set_rx_mode(netdev);
9103	napi_enable(n: &tp->napi);
9104	netif_wake_queue(dev: netdev);
9105	}
9106	}
9107
9108	mutex_unlock(lock: &tp->control);
9109
9110	usb_autopm_put_interface(intf: tp->intf);
9111
9112	return ret;
9113	}
9114
9115	static int rtl8152_get_tunable(struct net_device *netdev,
9116	const struct ethtool_tunable *tunable, void *d)
9117	{
9118	struct r8152 *tp = netdev_priv(dev: netdev);
9119
9120	switch (tunable->id) {
9121	case ETHTOOL_RX_COPYBREAK:
9122	*(u32 *)d = tp->rx_copybreak;
9123	break;
9124	default:
9125	return -EOPNOTSUPP;
9126	}
9127
9128	return 0;
9129	}
9130
9131	static int rtl8152_set_tunable(struct net_device *netdev,
9132	const struct ethtool_tunable *tunable,
9133	const void *d)
9134	{
9135	struct r8152 *tp = netdev_priv(dev: netdev);
9136	u32 val;
9137
9138	switch (tunable->id) {
9139	case ETHTOOL_RX_COPYBREAK:
9140	val = *(u32 *)d;
9141	if (val < ETH_ZLEN) {
9142	netif_err(tp, rx_err, netdev,
9143	"Invalid rx copy break value\n");
9144	return -EINVAL;
9145	}
9146
9147	if (tp->rx_copybreak != val) {
9148	if (netdev->flags & IFF_UP) {
9149	mutex_lock(&tp->control);
9150	napi_disable(n: &tp->napi);
9151	tp->rx_copybreak = val;
9152	napi_enable(n: &tp->napi);
9153	mutex_unlock(lock: &tp->control);
9154	} else {
9155	tp->rx_copybreak = val;
9156	}
9157	}
9158	break;
9159	default:
9160	return -EOPNOTSUPP;
9161	}
9162
9163	return 0;
9164	}
9165
9166	static void rtl8152_get_ringparam(struct net_device *netdev,
9167	struct ethtool_ringparam *ring,
9168	struct kernel_ethtool_ringparam *kernel_ring,
9169	struct netlink_ext_ack *extack)
9170	{
9171	struct r8152 *tp = netdev_priv(dev: netdev);
9172
9173	ring->rx_max_pending = RTL8152_RX_MAX_PENDING;
9174	ring->rx_pending = tp->rx_pending;
9175	}
9176
9177	static int rtl8152_set_ringparam(struct net_device *netdev,
9178	struct ethtool_ringparam *ring,
9179	struct kernel_ethtool_ringparam *kernel_ring,
9180	struct netlink_ext_ack *extack)
9181	{
9182	struct r8152 *tp = netdev_priv(dev: netdev);
9183
9184	if (ring->rx_pending < (RTL8152_MAX_RX * 2))
9185	return -EINVAL;
9186
9187	if (tp->rx_pending != ring->rx_pending) {
9188	if (netdev->flags & IFF_UP) {
9189	mutex_lock(&tp->control);
9190	napi_disable(n: &tp->napi);
9191	tp->rx_pending = ring->rx_pending;
9192	napi_enable(n: &tp->napi);
9193	mutex_unlock(lock: &tp->control);
9194	} else {
9195	tp->rx_pending = ring->rx_pending;
9196	}
9197	}
9198
9199	return 0;
9200	}
9201
9202	static void rtl8152_get_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause)
9203	{
9204	struct r8152 *tp = netdev_priv(dev: netdev);
9205	u16 bmcr, lcladv, rmtadv;
9206	u8 cap;
9207
9208	if (usb_autopm_get_interface(intf: tp->intf) < 0)
9209	return;
9210
9211	mutex_lock(&tp->control);
9212
9213	bmcr = r8152_mdio_read(tp, MII_BMCR);
9214	lcladv = r8152_mdio_read(tp, MII_ADVERTISE);
9215	rmtadv = r8152_mdio_read(tp, MII_LPA);
9216
9217	mutex_unlock(lock: &tp->control);
9218
9219	usb_autopm_put_interface(intf: tp->intf);
9220
9221	if (!(bmcr & BMCR_ANENABLE)) {
9222	pause->autoneg = 0;
9223	pause->rx_pause = 0;
9224	pause->tx_pause = 0;
9225	return;
9226	}
9227
9228	pause->autoneg = 1;
9229
9230	cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
9231
9232	if (cap & FLOW_CTRL_RX)
9233	pause->rx_pause = 1;
9234
9235	if (cap & FLOW_CTRL_TX)
9236	pause->tx_pause = 1;
9237	}
9238
9239	static int rtl8152_set_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause)
9240	{
9241	struct r8152 *tp = netdev_priv(dev: netdev);
9242	u16 old, new1;
9243	u8 cap = 0;
9244	int ret;
9245
9246	ret = usb_autopm_get_interface(intf: tp->intf);
9247	if (ret < 0)
9248	return ret;
9249
9250	mutex_lock(&tp->control);
9251
9252	if (pause->autoneg && !(r8152_mdio_read(tp, MII_BMCR) & BMCR_ANENABLE)) {
9253	ret = -EINVAL;
9254	goto out;
9255	}
9256
9257	if (pause->rx_pause)
9258	cap |= FLOW_CTRL_RX;
9259
9260	if (pause->tx_pause)
9261	cap |= FLOW_CTRL_TX;
9262
9263	old = r8152_mdio_read(tp, MII_ADVERTISE);
9264	new1 = (old & ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) | mii_advertise_flowctrl(cap);
9265	if (old != new1)
9266	r8152_mdio_write(tp, MII_ADVERTISE, value: new1);
9267
9268	out:
9269	mutex_unlock(lock: &tp->control);
9270	usb_autopm_put_interface(intf: tp->intf);
9271
9272	return ret;
9273	}
9274
9275	static const struct ethtool_ops ops = {
9276	.supported_coalesce_params = ETHTOOL_COALESCE_USECS,
9277	.get_drvinfo = rtl8152_get_drvinfo,
9278	.get_link = ethtool_op_get_link,
9279	.nway_reset = rtl8152_nway_reset,
9280	.get_msglevel = rtl8152_get_msglevel,
9281	.set_msglevel = rtl8152_set_msglevel,
9282	.get_wol = rtl8152_get_wol,
9283	.set_wol = rtl8152_set_wol,
9284	.get_strings = rtl8152_get_strings,
9285	.get_sset_count = rtl8152_get_sset_count,
9286	.get_ethtool_stats = rtl8152_get_ethtool_stats,
9287	.get_coalesce = rtl8152_get_coalesce,
9288	.set_coalesce = rtl8152_set_coalesce,
9289	.get_eee = rtl_ethtool_get_eee,
9290	.set_eee = rtl_ethtool_set_eee,
9291	.get_link_ksettings = rtl8152_get_link_ksettings,
9292	.set_link_ksettings = rtl8152_set_link_ksettings,
9293	.get_tunable = rtl8152_get_tunable,
9294	.set_tunable = rtl8152_set_tunable,
9295	.get_ringparam = rtl8152_get_ringparam,
9296	.set_ringparam = rtl8152_set_ringparam,
9297	.get_pauseparam = rtl8152_get_pauseparam,
9298	.set_pauseparam = rtl8152_set_pauseparam,
9299	};
9300
9301	static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
9302	{
9303	struct r8152 *tp = netdev_priv(dev: netdev);
9304	struct mii_ioctl_data *data = if_mii(rq);
9305	int res;
9306
9307	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
9308	return -ENODEV;
9309
9310	res = usb_autopm_get_interface(intf: tp->intf);
9311	if (res < 0)
9312	goto out;
9313
9314	switch (cmd) {
9315	case SIOCGMIIPHY:
9316	data->phy_id = R8152_PHY_ID; /* Internal PHY */
9317	break;
9318
9319	case SIOCGMIIREG:
9320	mutex_lock(&tp->control);
9321	data->val_out = r8152_mdio_read(tp, reg_addr: data->reg_num);
9322	mutex_unlock(lock: &tp->control);
9323	break;
9324
9325	case SIOCSMIIREG:
9326	if (!capable(CAP_NET_ADMIN)) {
9327	res = -EPERM;
9328	break;
9329	}
9330	mutex_lock(&tp->control);
9331	r8152_mdio_write(tp, reg_addr: data->reg_num, value: data->val_in);
9332	mutex_unlock(lock: &tp->control);
9333	break;
9334
9335	default:
9336	res = -EOPNOTSUPP;
9337	}
9338
9339	usb_autopm_put_interface(intf: tp->intf);
9340
9341	out:
9342	return res;
9343	}
9344
9345	static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
9346	{
9347	struct r8152 *tp = netdev_priv(dev);
9348	int ret;
9349
9350	switch (tp->version) {
9351	case RTL_VER_01:
9352	case RTL_VER_02:
9353	case RTL_VER_07:
9354	dev->mtu = new_mtu;
9355	return 0;
9356	default:
9357	break;
9358	}
9359
9360	ret = usb_autopm_get_interface(intf: tp->intf);
9361	if (ret < 0)
9362	return ret;
9363
9364	mutex_lock(&tp->control);
9365
9366	dev->mtu = new_mtu;
9367
9368	if (netif_running(dev)) {
9369	if (tp->rtl_ops.change_mtu)
9370	tp->rtl_ops.change_mtu(tp);
9371
9372	if (netif_carrier_ok(dev)) {
9373	netif_stop_queue(dev);
9374	napi_disable(n: &tp->napi);
9375	tasklet_disable(t: &tp->tx_tl);
9376	tp->rtl_ops.disable(tp);
9377	tp->rtl_ops.enable(tp);
9378	rtl_start_rx(tp);
9379	tasklet_enable(t: &tp->tx_tl);
9380	napi_enable(n: &tp->napi);
9381	rtl8152_set_rx_mode(netdev: dev);
9382	netif_wake_queue(dev);
9383	}
9384	}
9385
9386	mutex_unlock(lock: &tp->control);
9387
9388	usb_autopm_put_interface(intf: tp->intf);
9389
9390	return ret;
9391	}
9392
9393	static const struct net_device_ops rtl8152_netdev_ops = {
9394	.ndo_open = rtl8152_open,
9395	.ndo_stop = rtl8152_close,
9396	.ndo_eth_ioctl = rtl8152_ioctl,
9397	.ndo_start_xmit = rtl8152_start_xmit,
9398	.ndo_tx_timeout = rtl8152_tx_timeout,
9399	.ndo_set_features = rtl8152_set_features,
9400	.ndo_set_rx_mode = rtl8152_set_rx_mode,
9401	.ndo_set_mac_address = rtl8152_set_mac_address,
9402	.ndo_change_mtu = rtl8152_change_mtu,
9403	.ndo_validate_addr = eth_validate_addr,
9404	.ndo_features_check = rtl8152_features_check,
9405	};
9406
9407	static void rtl8152_unload(struct r8152 *tp)
9408	{
9409	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
9410	return;
9411
9412	if (tp->version != RTL_VER_01)
9413	r8152_power_cut_en(tp, enable: true);
9414	}
9415
9416	static void rtl8153_unload(struct r8152 *tp)
9417	{
9418	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
9419	return;
9420
9421	r8153_power_cut_en(tp, enable: false);
9422	}
9423
9424	static void rtl8153b_unload(struct r8152 *tp)
9425	{
9426	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
9427	return;
9428
9429	r8153b_power_cut_en(tp, enable: false);
9430	}
9431
9432	static int rtl_ops_init(struct r8152 *tp)
9433	{
9434	struct rtl_ops *ops = &tp->rtl_ops;
9435	int ret = 0;
9436
9437	switch (tp->version) {
9438	case RTL_VER_01:
9439	case RTL_VER_02:
9440	case RTL_VER_07:
9441	ops->init = r8152b_init;
9442	ops->enable = rtl8152_enable;
9443	ops->disable = rtl8152_disable;
9444	ops->up = rtl8152_up;
9445	ops->down = rtl8152_down;
9446	ops->unload = rtl8152_unload;
9447	ops->eee_get = r8152_get_eee;
9448	ops->eee_set = r8152_set_eee;
9449	ops->in_nway = rtl8152_in_nway;
9450	ops->hw_phy_cfg = r8152b_hw_phy_cfg;
9451	ops->autosuspend_en = rtl_runtime_suspend_enable;
9452	tp->rx_buf_sz = 16 * 1024;
9453	tp->eee_en = true;
9454	tp->eee_adv = MDIO_EEE_100TX;
9455	break;
9456
9457	case RTL_VER_03:
9458	case RTL_VER_04:
9459	case RTL_VER_05:
9460	case RTL_VER_06:
9461	ops->init = r8153_init;
9462	ops->enable = rtl8153_enable;
9463	ops->disable = rtl8153_disable;
9464	ops->up = rtl8153_up;
9465	ops->down = rtl8153_down;
9466	ops->unload = rtl8153_unload;
9467	ops->eee_get = r8153_get_eee;
9468	ops->eee_set = r8152_set_eee;
9469	ops->in_nway = rtl8153_in_nway;
9470	ops->hw_phy_cfg = r8153_hw_phy_cfg;
9471	ops->autosuspend_en = rtl8153_runtime_enable;
9472	ops->change_mtu = rtl8153_change_mtu;
9473	if (tp->udev->speed < USB_SPEED_SUPER)
9474	tp->rx_buf_sz = 16 * 1024;
9475	else
9476	tp->rx_buf_sz = 32 * 1024;
9477	tp->eee_en = true;
9478	tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
9479	break;
9480
9481	case RTL_VER_08:
9482	case RTL_VER_09:
9483	ops->init = r8153b_init;
9484	ops->enable = rtl8153_enable;
9485	ops->disable = rtl8153_disable;
9486	ops->up = rtl8153b_up;
9487	ops->down = rtl8153b_down;
9488	ops->unload = rtl8153b_unload;
9489	ops->eee_get = r8153_get_eee;
9490	ops->eee_set = r8152_set_eee;
9491	ops->in_nway = rtl8153_in_nway;
9492	ops->hw_phy_cfg = r8153b_hw_phy_cfg;
9493	ops->autosuspend_en = rtl8153b_runtime_enable;
9494	ops->change_mtu = rtl8153_change_mtu;
9495	tp->rx_buf_sz = 32 * 1024;
9496	tp->eee_en = true;
9497	tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
9498	break;
9499
9500	case RTL_VER_11:
9501	tp->eee_en = true;
9502	tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
9503	fallthrough;
9504	case RTL_VER_10:
9505	ops->init = r8156_init;
9506	ops->enable = rtl8156_enable;
9507	ops->disable = rtl8156_disable;
9508	ops->up = rtl8156_up;
9509	ops->down = rtl8156_down;
9510	ops->unload = rtl8153_unload;
9511	ops->eee_get = r8153_get_eee;
9512	ops->eee_set = r8152_set_eee;
9513	ops->in_nway = rtl8153_in_nway;
9514	ops->hw_phy_cfg = r8156_hw_phy_cfg;
9515	ops->autosuspend_en = rtl8156_runtime_enable;
9516	ops->change_mtu = rtl8156_change_mtu;
9517	tp->rx_buf_sz = 48 * 1024;
9518	tp->support_2500full = 1;
9519	break;
9520
9521	case RTL_VER_12:
9522	case RTL_VER_13:
9523	tp->support_2500full = 1;
9524	fallthrough;
9525	case RTL_VER_15:
9526	tp->eee_en = true;
9527	tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
9528	ops->init = r8156b_init;
9529	ops->enable = rtl8156b_enable;
9530	ops->disable = rtl8153_disable;
9531	ops->up = rtl8156_up;
9532	ops->down = rtl8156_down;
9533	ops->unload = rtl8153_unload;
9534	ops->eee_get = r8153_get_eee;
9535	ops->eee_set = r8152_set_eee;
9536	ops->in_nway = rtl8153_in_nway;
9537	ops->hw_phy_cfg = r8156b_hw_phy_cfg;
9538	ops->autosuspend_en = rtl8156_runtime_enable;
9539	ops->change_mtu = rtl8156_change_mtu;
9540	tp->rx_buf_sz = 48 * 1024;
9541	break;
9542
9543	case RTL_VER_14:
9544	ops->init = r8153c_init;
9545	ops->enable = rtl8153_enable;
9546	ops->disable = rtl8153_disable;
9547	ops->up = rtl8153c_up;
9548	ops->down = rtl8153b_down;
9549	ops->unload = rtl8153_unload;
9550	ops->eee_get = r8153_get_eee;
9551	ops->eee_set = r8152_set_eee;
9552	ops->in_nway = rtl8153_in_nway;
9553	ops->hw_phy_cfg = r8153c_hw_phy_cfg;
9554	ops->autosuspend_en = rtl8153c_runtime_enable;
9555	ops->change_mtu = rtl8153c_change_mtu;
9556	tp->rx_buf_sz = 32 * 1024;
9557	tp->eee_en = true;
9558	tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
9559	break;
9560
9561	default:
9562	ret = -ENODEV;
9563	dev_err(&tp->intf->dev, "Unknown Device\n");
9564	break;
9565	}
9566
9567	return ret;
9568	}
9569
9570	#define FIRMWARE_8153A_2 "rtl_nic/rtl8153a-2.fw"
9571	#define FIRMWARE_8153A_3 "rtl_nic/rtl8153a-3.fw"
9572	#define FIRMWARE_8153A_4 "rtl_nic/rtl8153a-4.fw"
9573	#define FIRMWARE_8153B_2 "rtl_nic/rtl8153b-2.fw"
9574	#define FIRMWARE_8153C_1 "rtl_nic/rtl8153c-1.fw"
9575	#define FIRMWARE_8156A_2 "rtl_nic/rtl8156a-2.fw"
9576	#define FIRMWARE_8156B_2 "rtl_nic/rtl8156b-2.fw"
9577
9578	MODULE_FIRMWARE(FIRMWARE_8153A_2);
9579	MODULE_FIRMWARE(FIRMWARE_8153A_3);
9580	MODULE_FIRMWARE(FIRMWARE_8153A_4);
9581	MODULE_FIRMWARE(FIRMWARE_8153B_2);
9582	MODULE_FIRMWARE(FIRMWARE_8153C_1);
9583	MODULE_FIRMWARE(FIRMWARE_8156A_2);
9584	MODULE_FIRMWARE(FIRMWARE_8156B_2);
9585
9586	static int rtl_fw_init(struct r8152 *tp)
9587	{
9588	struct rtl_fw *rtl_fw = &tp->rtl_fw;
9589
9590	switch (tp->version) {
9591	case RTL_VER_04:
9592	rtl_fw->fw_name = FIRMWARE_8153A_2;
9593	rtl_fw->pre_fw = r8153_pre_firmware_1;
9594	rtl_fw->post_fw = r8153_post_firmware_1;
9595	break;
9596	case RTL_VER_05:
9597	rtl_fw->fw_name = FIRMWARE_8153A_3;
9598	rtl_fw->pre_fw = r8153_pre_firmware_2;
9599	rtl_fw->post_fw = r8153_post_firmware_2;
9600	break;
9601	case RTL_VER_06:
9602	rtl_fw->fw_name = FIRMWARE_8153A_4;
9603	rtl_fw->post_fw = r8153_post_firmware_3;
9604	break;
9605	case RTL_VER_09:
9606	rtl_fw->fw_name = FIRMWARE_8153B_2;
9607	rtl_fw->pre_fw = r8153b_pre_firmware_1;
9608	rtl_fw->post_fw = r8153b_post_firmware_1;
9609	break;
9610	case RTL_VER_11:
9611	rtl_fw->fw_name = FIRMWARE_8156A_2;
9612	rtl_fw->post_fw = r8156a_post_firmware_1;
9613	break;
9614	case RTL_VER_13:
9615	case RTL_VER_15:
9616	rtl_fw->fw_name = FIRMWARE_8156B_2;
9617	break;
9618	case RTL_VER_14:
9619	rtl_fw->fw_name = FIRMWARE_8153C_1;
9620	rtl_fw->pre_fw = r8153b_pre_firmware_1;
9621	rtl_fw->post_fw = r8153c_post_firmware_1;
9622	break;
9623	default:
9624	break;
9625	}
9626
9627	return 0;
9628	}
9629
9630	static u8 __rtl_get_hw_ver(struct usb_device *udev)
9631	{
9632	u32 ocp_data = 0;
9633	__le32 *tmp;
9634	u8 version;
9635	int ret;
9636	int i;
9637
9638	tmp = kmalloc(size: sizeof(*tmp), GFP_KERNEL);
9639	if (!tmp)
9640	return 0;
9641
9642	/* Retry up to 3 times in case there is a transitory error. We do this
9643	* since retrying a read of the version is always safe and this
9644	* function doesn't take advantage of r8152_control_msg().
9645	*/
9646	for (i = 0; i < 3; i++) {
9647	ret = usb_control_msg(dev: udev, usb_rcvctrlpipe(udev, 0),
9648	RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
9649	PLA_TCR0, MCU_TYPE_PLA, data: tmp, size: sizeof(*tmp),
9650	USB_CTRL_GET_TIMEOUT);
9651	if (ret > 0) {
9652	ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK;
9653	break;
9654	}
9655	}
9656
9657	if (i != 0 && ret > 0)
9658	dev_warn(&udev->dev, "Needed %d retries to read version\n", i);
9659
9660	kfree(objp: tmp);
9661
9662	switch (ocp_data) {
9663	case 0x4c00:
9664	version = RTL_VER_01;
9665	break;
9666	case 0x4c10:
9667	version = RTL_VER_02;
9668	break;
9669	case 0x5c00:
9670	version = RTL_VER_03;
9671	break;
9672	case 0x5c10:
9673	version = RTL_VER_04;
9674	break;
9675	case 0x5c20:
9676	version = RTL_VER_05;
9677	break;
9678	case 0x5c30:
9679	version = RTL_VER_06;
9680	break;
9681	case 0x4800:
9682	version = RTL_VER_07;
9683	break;
9684	case 0x6000:
9685	version = RTL_VER_08;
9686	break;
9687	case 0x6010:
9688	version = RTL_VER_09;
9689	break;
9690	case 0x7010:
9691	version = RTL_TEST_01;
9692	break;
9693	case 0x7020:
9694	version = RTL_VER_10;
9695	break;
9696	case 0x7030:
9697	version = RTL_VER_11;
9698	break;
9699	case 0x7400:
9700	version = RTL_VER_12;
9701	break;
9702	case 0x7410:
9703	version = RTL_VER_13;
9704	break;
9705	case 0x6400:
9706	version = RTL_VER_14;
9707	break;
9708	case 0x7420:
9709	version = RTL_VER_15;
9710	break;
9711	default:
9712	version = RTL_VER_UNKNOWN;
9713	dev_info(&udev->dev, "Unknown version 0x%04x\n", ocp_data);
9714	break;
9715	}
9716
9717	return version;
9718	}
9719
9720	u8 rtl8152_get_version(struct usb_interface *intf)
9721	{
9722	u8 version;
9723
9724	version = __rtl_get_hw_ver(interface_to_usbdev(intf));
9725
9726	dev_dbg(&intf->dev, "Detected version 0x%04x\n", version);
9727
9728	return version;
9729	}
9730	EXPORT_SYMBOL_GPL(rtl8152_get_version);
9731
9732	static bool rtl8152_supports_lenovo_macpassthru(struct usb_device *udev)
9733	{
9734	int parent_vendor_id = le16_to_cpu(udev->parent->descriptor.idVendor);
9735	int product_id = le16_to_cpu(udev->descriptor.idProduct);
9736	int vendor_id = le16_to_cpu(udev->descriptor.idVendor);
9737
9738	if (vendor_id == VENDOR_ID_LENOVO) {
9739	switch (product_id) {
9740	case DEVICE_ID_LENOVO_USB_C_TRAVEL_HUB:
9741	case DEVICE_ID_THINKPAD_ONELINK_PLUS_DOCK:
9742	case DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2:
9743	case DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2:
9744	case DEVICE_ID_THINKPAD_USB_C_DOCK_GEN3:
9745	case DEVICE_ID_THINKPAD_USB_C_DONGLE:
9746	return 1;
9747	}
9748	} else if (vendor_id == VENDOR_ID_REALTEK && parent_vendor_id == VENDOR_ID_LENOVO) {
9749	switch (product_id) {
9750	case 0x8153:
9751	return 1;
9752	}
9753	}
9754	return 0;
9755	}
9756
9757	static int rtl8152_probe_once(struct usb_interface *intf,
9758	const struct usb_device_id *id, u8 version)
9759	{
9760	struct usb_device *udev = interface_to_usbdev(intf);
9761	struct r8152 *tp;
9762	struct net_device *netdev;
9763	int ret;
9764
9765	usb_reset_device(dev: udev);
9766	netdev = alloc_etherdev(sizeof(struct r8152));
9767	if (!netdev) {
9768	dev_err(&intf->dev, "Out of memory\n");
9769	return -ENOMEM;
9770	}
9771
9772	SET_NETDEV_DEV(netdev, &intf->dev);
9773	tp = netdev_priv(dev: netdev);
9774	tp->msg_enable = 0x7FFF;
9775
9776	tp->udev = udev;
9777	tp->netdev = netdev;
9778	tp->intf = intf;
9779	tp->version = version;
9780
9781	tp->pipe_ctrl_in = usb_rcvctrlpipe(udev, 0);
9782	tp->pipe_ctrl_out = usb_sndctrlpipe(udev, 0);
9783	tp->pipe_in = usb_rcvbulkpipe(udev, 1);
9784	tp->pipe_out = usb_sndbulkpipe(udev, 2);
9785	tp->pipe_intr = usb_rcvintpipe(udev, 3);
9786
9787	switch (version) {
9788	case RTL_VER_01:
9789	case RTL_VER_02:
9790	case RTL_VER_07:
9791	tp->mii.supports_gmii = 0;
9792	break;
9793	default:
9794	tp->mii.supports_gmii = 1;
9795	break;
9796	}
9797
9798	ret = rtl_ops_init(tp);
9799	if (ret)
9800	goto out;
9801
9802	rtl_fw_init(tp);
9803
9804	mutex_init(&tp->control);
9805	INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
9806	INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);
9807	tasklet_setup(t: &tp->tx_tl, callback: bottom_half);
9808	tasklet_disable(t: &tp->tx_tl);
9809
9810	netdev->netdev_ops = &rtl8152_netdev_ops;
9811	netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
9812
9813	netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
9814	NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
9815	NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
9816	NETIF_F_HW_VLAN_CTAG_TX;
9817	netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
9818	NETIF_F_TSO | NETIF_F_FRAGLIST |
9819	NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
9820	NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
9821	netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
9822	NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
9823	NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
9824
9825	if (tp->version == RTL_VER_01) {
9826	netdev->features &= ~NETIF_F_RXCSUM;
9827	netdev->hw_features &= ~NETIF_F_RXCSUM;
9828	}
9829
9830	tp->lenovo_macpassthru = rtl8152_supports_lenovo_macpassthru(udev);
9831
9832	if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial &&
9833	(!strcmp(udev->serial, "000001000000") ||
9834	!strcmp(udev->serial, "000002000000"))) {
9835	dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation");
9836	tp->dell_tb_rx_agg_bug = 1;
9837	}
9838
9839	netdev->ethtool_ops = &ops;
9840	netif_set_tso_max_size(dev: netdev, RTL_LIMITED_TSO_SIZE);
9841
9842	/* MTU range: 68 - 1500 or 9194 */
9843	netdev->min_mtu = ETH_MIN_MTU;
9844	switch (tp->version) {
9845	case RTL_VER_03:
9846	case RTL_VER_04:
9847	case RTL_VER_05:
9848	case RTL_VER_06:
9849	case RTL_VER_08:
9850	case RTL_VER_09:
9851	case RTL_VER_14:
9852	netdev->max_mtu = size_to_mtu(9 * 1024);
9853	break;
9854	case RTL_VER_10:
9855	case RTL_VER_11:
9856	netdev->max_mtu = size_to_mtu(15 * 1024);
9857	break;
9858	case RTL_VER_12:
9859	case RTL_VER_13:
9860	case RTL_VER_15:
9861	netdev->max_mtu = size_to_mtu(16 * 1024);
9862	break;
9863	case RTL_VER_01:
9864	case RTL_VER_02:
9865	case RTL_VER_07:
9866	default:
9867	netdev->max_mtu = ETH_DATA_LEN;
9868	break;
9869	}
9870
9871	tp->mii.dev = netdev;
9872	tp->mii.mdio_read = read_mii_word;
9873	tp->mii.mdio_write = write_mii_word;
9874	tp->mii.phy_id_mask = 0x3f;
9875	tp->mii.reg_num_mask = 0x1f;
9876	tp->mii.phy_id = R8152_PHY_ID;
9877
9878	tp->autoneg = AUTONEG_ENABLE;
9879	tp->speed = SPEED_100;
9880	tp->advertising = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
9881	RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
9882	if (tp->mii.supports_gmii) {
9883	if (tp->support_2500full &&
9884	tp->udev->speed >= USB_SPEED_SUPER) {
9885	tp->speed = SPEED_2500;
9886	tp->advertising |= RTL_ADVERTISED_2500_FULL;
9887	} else {
9888	tp->speed = SPEED_1000;
9889	}
9890	tp->advertising |= RTL_ADVERTISED_1000_FULL;
9891	}
9892	tp->duplex = DUPLEX_FULL;
9893
9894	tp->rx_copybreak = RTL8152_RXFG_HEADSZ;
9895	tp->rx_pending = 10 * RTL8152_MAX_RX;
9896
9897	intf->needs_remote_wakeup = 1;
9898
9899	if (!rtl_can_wakeup(tp))
9900	__rtl_set_wol(tp, wolopts: 0);
9901	else
9902	tp->saved_wolopts = __rtl_get_wol(tp);
9903
9904	tp->rtl_ops.init(tp);
9905	#if IS_BUILTIN(CONFIG_USB_RTL8152)
9906	/* Retry in case request_firmware() is not ready yet. */
9907	tp->rtl_fw.retry = true;
9908	#endif
9909	queue_delayed_work(wq: system_long_wq, dwork: &tp->hw_phy_work, delay: 0);
9910	set_ethernet_addr(tp, in_resume: false);
9911
9912	usb_set_intfdata(intf, data: tp);
9913
9914	netif_napi_add(dev: netdev, napi: &tp->napi, poll: r8152_poll);
9915
9916	ret = register_netdev(dev: netdev);
9917	if (ret != 0) {
9918	dev_err(&intf->dev, "couldn't register the device\n");
9919	goto out1;
9920	}
9921
9922	if (tp->saved_wolopts)
9923	device_set_wakeup_enable(dev: &udev->dev, enable: true);
9924	else
9925	device_set_wakeup_enable(dev: &udev->dev, enable: false);
9926
9927	/* If we saw a control transfer error while probing then we may
9928	* want to try probe() again. Consider this an error.
9929	*/
9930	if (test_bit(PROBE_SHOULD_RETRY, &tp->flags))
9931	goto out2;
9932
9933	set_bit(nr: PROBED_WITH_NO_ERRORS, addr: &tp->flags);
9934	netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
9935
9936	return 0;
9937
9938	out2:
9939	unregister_netdev(dev: netdev);
9940
9941	out1:
9942	tasklet_kill(t: &tp->tx_tl);
9943	cancel_delayed_work_sync(dwork: &tp->hw_phy_work);
9944	if (tp->rtl_ops.unload)
9945	tp->rtl_ops.unload(tp);
9946	rtl8152_release_firmware(tp);
9947	usb_set_intfdata(intf, NULL);
9948	out:
9949	if (test_bit(PROBE_SHOULD_RETRY, &tp->flags))
9950	ret = -EAGAIN;
9951
9952	free_netdev(dev: netdev);
9953	return ret;
9954	}
9955
9956	#define RTL8152_PROBE_TRIES 3
9957
9958	static int rtl8152_probe(struct usb_interface *intf,
9959	const struct usb_device_id *id)
9960	{
9961	u8 version;
9962	int ret;
9963	int i;
9964
9965	if (intf->cur_altsetting->desc.bInterfaceClass != USB_CLASS_VENDOR_SPEC)
9966	return -ENODEV;
9967
9968	if (!rtl_check_vendor_ok(intf))
9969	return -ENODEV;
9970
9971	version = rtl8152_get_version(intf);
9972	if (version == RTL_VER_UNKNOWN)
9973	return -ENODEV;
9974
9975	for (i = 0; i < RTL8152_PROBE_TRIES; i++) {
9976	ret = rtl8152_probe_once(intf, id, version);
9977	if (ret != -EAGAIN)
9978	break;
9979	}
9980	if (ret == -EAGAIN) {
9981	dev_err(&intf->dev,
9982	"r8152 failed probe after %d tries; giving up\n", i);
9983	return -ENODEV;
9984	}
9985
9986	return ret;
9987	}
9988
9989	static void rtl8152_disconnect(struct usb_interface *intf)
9990	{
9991	struct r8152 *tp = usb_get_intfdata(intf);
9992
9993	usb_set_intfdata(intf, NULL);
9994	if (tp) {
9995	rtl_set_unplug(tp);
9996
9997	unregister_netdev(dev: tp->netdev);
9998	tasklet_kill(t: &tp->tx_tl);
9999	cancel_delayed_work_sync(dwork: &tp->hw_phy_work);
10000	if (tp->rtl_ops.unload)
10001	tp->rtl_ops.unload(tp);
10002	rtl8152_release_firmware(tp);
10003	free_netdev(dev: tp->netdev);
10004	}
10005	}
10006
10007	/* table of devices that work with this driver */
10008	static const struct usb_device_id rtl8152_table[] = {
10009	/* Realtek */
10010	{ USB_DEVICE(VENDOR_ID_REALTEK, 0x8050) },
10011	{ USB_DEVICE(VENDOR_ID_REALTEK, 0x8053) },
10012	{ USB_DEVICE(VENDOR_ID_REALTEK, 0x8152) },
10013	{ USB_DEVICE(VENDOR_ID_REALTEK, 0x8153) },
10014	{ USB_DEVICE(VENDOR_ID_REALTEK, 0x8155) },
10015	{ USB_DEVICE(VENDOR_ID_REALTEK, 0x8156) },
10016
10017	/* Microsoft */
10018	{ USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab) },
10019	{ USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6) },
10020	{ USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0927) },
10021	{ USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0c5e) },
10022	{ USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101) },
10023	{ USB_DEVICE(VENDOR_ID_LENOVO, 0x304f) },
10024	{ USB_DEVICE(VENDOR_ID_LENOVO, 0x3054) },
10025	{ USB_DEVICE(VENDOR_ID_LENOVO, 0x3062) },
10026	{ USB_DEVICE(VENDOR_ID_LENOVO, 0x3069) },
10027	{ USB_DEVICE(VENDOR_ID_LENOVO, 0x3082) },
10028	{ USB_DEVICE(VENDOR_ID_LENOVO, 0x7205) },
10029	{ USB_DEVICE(VENDOR_ID_LENOVO, 0x720c) },
10030	{ USB_DEVICE(VENDOR_ID_LENOVO, 0x7214) },
10031	{ USB_DEVICE(VENDOR_ID_LENOVO, 0x721e) },
10032	{ USB_DEVICE(VENDOR_ID_LENOVO, 0xa387) },
10033	{ USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041) },
10034	{ USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff) },
10035	{ USB_DEVICE(VENDOR_ID_TPLINK, 0x0601) },
10036	{ USB_DEVICE(VENDOR_ID_DLINK, 0xb301) },
10037	{}
10038	};
10039
10040	MODULE_DEVICE_TABLE(usb, rtl8152_table);
10041
10042	static struct usb_driver rtl8152_driver = {
10043	.name = MODULENAME,
10044	.id_table = rtl8152_table,
10045	.probe = rtl8152_probe,
10046	.disconnect = rtl8152_disconnect,
10047	.suspend = rtl8152_suspend,
10048	.resume = rtl8152_resume,
10049	.reset_resume = rtl8152_reset_resume,
10050	.pre_reset = rtl8152_pre_reset,
10051	.post_reset = rtl8152_post_reset,
10052	.supports_autosuspend = 1,
10053	.disable_hub_initiated_lpm = 1,
10054	};
10055
10056	static int rtl8152_cfgselector_probe(struct usb_device *udev)
10057	{
10058	struct usb_host_config *c;
10059	int i, num_configs;
10060
10061	/* Switch the device to vendor mode, if and only if the vendor mode
10062	* driver supports it.
10063	*/
10064	if (__rtl_get_hw_ver(udev) == RTL_VER_UNKNOWN)
10065	return 0;
10066
10067	/* The vendor mode is not always config #1, so to find it out. */
10068	c = udev->config;
10069	num_configs = udev->descriptor.bNumConfigurations;
10070	for (i = 0; i < num_configs; (i++, c++)) {
10071	struct usb_interface_descriptor *desc = NULL;
10072
10073	if (!c->desc.bNumInterfaces)
10074	continue;
10075	desc = &c->intf_cache[0]->altsetting->desc;
10076	if (desc->bInterfaceClass == USB_CLASS_VENDOR_SPEC)
10077	break;
10078	}
10079
10080	if (i == num_configs)
10081	return -ENODEV;
10082
10083	if (usb_set_configuration(dev: udev, configuration: c->desc.bConfigurationValue)) {
10084	dev_err(&udev->dev, "Failed to set configuration %d\n",
10085	c->desc.bConfigurationValue);
10086	return -ENODEV;
10087	}
10088
10089	return 0;
10090	}
10091
10092	static struct usb_device_driver rtl8152_cfgselector_driver = {
10093	.name = MODULENAME "-cfgselector",
10094	.probe = rtl8152_cfgselector_probe,
10095	.id_table = rtl8152_table,
10096	.generic_subclass = 1,
10097	.supports_autosuspend = 1,
10098	};
10099
10100	static int __init rtl8152_driver_init(void)
10101	{
10102	int ret;
10103
10104	ret = usb_register_device_driver(&rtl8152_cfgselector_driver, THIS_MODULE);
10105	if (ret)
10106	return ret;
10107	return usb_register(&rtl8152_driver);
10108	}
10109
10110	static void __exit rtl8152_driver_exit(void)
10111	{
10112	usb_deregister(&rtl8152_driver);
10113	usb_deregister_device_driver(&rtl8152_cfgselector_driver);
10114	}
10115
10116	module_init(rtl8152_driver_init);
10117	module_exit(rtl8152_driver_exit);
10118
10119	MODULE_AUTHOR(DRIVER_AUTHOR);
10120	MODULE_DESCRIPTION(DRIVER_DESC);
10121	MODULE_LICENSE("GPL");
10122	MODULE_VERSION(DRIVER_VERSION);
10123