| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * CoreChip-sz SR9700 one chip USB 1.1 Ethernet Devices |
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| 4 | * |
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| 5 | * Author : Liu Junliang <liujunliang_ljl@163.com> |
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| 6 | */ |
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| 7 | |
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| 8 | #ifndef _SR9700_H |
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| 9 | #define _SR9700_H |
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| 10 | |
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| 11 | /* sr9700 spec. register table on Linux platform */ |
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| 12 | |
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| 13 | /* Network Control Reg */ |
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| 14 | #define SR_NCR 0x00 |
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| 15 | #define NCR_RST (1 << 0) |
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| 16 | #define NCR_LBK (3 << 1) |
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| 17 | #define NCR_FDX (1 << 3) |
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| 18 | #define NCR_WAKEEN (1 << 6) |
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| 19 | /* Network Status Reg */ |
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| 20 | #define SR_NSR 0x01 |
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| 21 | #define NSR_RXRDY (1 << 0) |
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| 22 | #define NSR_RXOV (1 << 1) |
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| 23 | #define NSR_TX1END (1 << 2) |
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| 24 | #define NSR_TX2END (1 << 3) |
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| 25 | #define NSR_TXFULL (1 << 4) |
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| 26 | #define NSR_WAKEST (1 << 5) |
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| 27 | #define NSR_LINKST (1 << 6) |
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| 28 | #define NSR_SPEED (1 << 7) |
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| 29 | /* Tx Control Reg */ |
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| 30 | #define SR_TCR 0x02 |
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| 31 | #define TCR_CRC_DIS (1 << 1) |
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| 32 | #define TCR_PAD_DIS (1 << 2) |
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| 33 | #define TCR_LC_CARE (1 << 3) |
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| 34 | #define TCR_CRS_CARE (1 << 4) |
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| 35 | #define TCR_EXCECM (1 << 5) |
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| 36 | #define TCR_LF_EN (1 << 6) |
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| 37 | /* Tx Status Reg for Packet Index 1 */ |
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| 38 | #define SR_TSR1 0x03 |
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| 39 | #define TSR1_EC (1 << 2) |
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| 40 | #define TSR1_COL (1 << 3) |
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| 41 | #define TSR1_LC (1 << 4) |
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| 42 | #define TSR1_NC (1 << 5) |
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| 43 | #define TSR1_LOC (1 << 6) |
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| 44 | #define TSR1_TLF (1 << 7) |
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| 45 | /* Tx Status Reg for Packet Index 2 */ |
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| 46 | #define SR_TSR2 0x04 |
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| 47 | #define TSR2_EC (1 << 2) |
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| 48 | #define TSR2_COL (1 << 3) |
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| 49 | #define TSR2_LC (1 << 4) |
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| 50 | #define TSR2_NC (1 << 5) |
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| 51 | #define TSR2_LOC (1 << 6) |
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| 52 | #define TSR2_TLF (1 << 7) |
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| 53 | /* Rx Control Reg*/ |
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| 54 | #define SR_RCR 0x05 |
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| 55 | #define RCR_RXEN (1 << 0) |
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| 56 | #define RCR_PRMSC (1 << 1) |
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| 57 | #define RCR_RUNT (1 << 2) |
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| 58 | #define RCR_ALL (1 << 3) |
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| 59 | #define RCR_DIS_CRC (1 << 4) |
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| 60 | #define RCR_DIS_LONG (1 << 5) |
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| 61 | /* Rx Status Reg */ |
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| 62 | #define SR_RSR 0x06 |
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| 63 | #define RSR_AE (1 << 2) |
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| 64 | #define RSR_MF (1 << 6) |
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| 65 | #define RSR_RF (1 << 7) |
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| 66 | /* Rx Overflow Counter Reg */ |
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| 67 | #define SR_ROCR 0x07 |
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| 68 | #define ROCR_ROC (0x7F << 0) |
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| 69 | #define ROCR_RXFU (1 << 7) |
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| 70 | /* Back Pressure Threshold Reg */ |
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| 71 | #define SR_BPTR 0x08 |
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| 72 | #define BPTR_JPT (0x0F << 0) |
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| 73 | #define BPTR_BPHW (0x0F << 4) |
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| 74 | /* Flow Control Threshold Reg */ |
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| 75 | #define SR_FCTR 0x09 |
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| 76 | #define FCTR_LWOT (0x0F << 0) |
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| 77 | #define FCTR_HWOT (0x0F << 4) |
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| 78 | /* rx/tx Flow Control Reg */ |
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| 79 | #define SR_FCR 0x0A |
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| 80 | #define FCR_FLCE (1 << 0) |
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| 81 | #define FCR_BKPA (1 << 4) |
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| 82 | #define FCR_TXPEN (1 << 5) |
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| 83 | #define FCR_TXPF (1 << 6) |
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| 84 | #define FCR_TXP0 (1 << 7) |
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| 85 | /* Eeprom & Phy Control Reg */ |
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| 86 | #define SR_EPCR 0x0B |
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| 87 | #define EPCR_ERRE (1 << 0) |
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| 88 | #define EPCR_ERPRW (1 << 1) |
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| 89 | #define EPCR_ERPRR (1 << 2) |
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| 90 | #define EPCR_EPOS (1 << 3) |
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| 91 | #define EPCR_WEP (1 << 4) |
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| 92 | /* Eeprom & Phy Address Reg */ |
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| 93 | #define SR_EPAR 0x0C |
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| 94 | #define EPAR_EROA (0x3F << 0) |
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| 95 | #define EPAR_PHY_ADR_MASK (0x03 << 6) |
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| 96 | #define EPAR_PHY_ADR (0x01 << 6) |
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| 97 | /* Eeprom & Phy Data Reg */ |
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| 98 | #define SR_EPDR 0x0D /* 0x0D ~ 0x0E for Data Reg Low & High */ |
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| 99 | /* Wakeup Control Reg */ |
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| 100 | #define SR_WCR 0x0F |
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| 101 | #define WCR_MAGICST (1 << 0) |
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| 102 | #define WCR_LINKST (1 << 2) |
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| 103 | #define WCR_MAGICEN (1 << 3) |
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| 104 | #define WCR_LINKEN (1 << 5) |
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| 105 | /* Physical Address Reg */ |
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| 106 | #define SR_PAR 0x10 /* 0x10 ~ 0x15 6 bytes for PAR */ |
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| 107 | /* Multicast Address Reg */ |
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| 108 | #define SR_MAR 0x16 /* 0x16 ~ 0x1D 8 bytes for MAR */ |
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| 109 | /* 0x1e unused */ |
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| 110 | /* Phy Reset Reg */ |
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| 111 | #define SR_PRR 0x1F |
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| 112 | #define PRR_PHY_RST (1 << 0) |
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| 113 | /* Tx sdram Write Pointer Address Low */ |
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| 114 | #define SR_TWPAL 0x20 |
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| 115 | /* Tx sdram Write Pointer Address High */ |
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| 116 | #define SR_TWPAH 0x21 |
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| 117 | /* Tx sdram Read Pointer Address Low */ |
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| 118 | #define SR_TRPAL 0x22 |
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| 119 | /* Tx sdram Read Pointer Address High */ |
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| 120 | #define SR_TRPAH 0x23 |
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| 121 | /* Rx sdram Write Pointer Address Low */ |
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| 122 | #define SR_RWPAL 0x24 |
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| 123 | /* Rx sdram Write Pointer Address High */ |
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| 124 | #define SR_RWPAH 0x25 |
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| 125 | /* Rx sdram Read Pointer Address Low */ |
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| 126 | #define SR_RRPAL 0x26 |
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| 127 | /* Rx sdram Read Pointer Address High */ |
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| 128 | #define SR_RRPAH 0x27 |
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| 129 | /* Vendor ID register */ |
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| 130 | #define SR_VID 0x28 /* 0x28 ~ 0x29 2 bytes for VID */ |
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| 131 | /* Product ID register */ |
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| 132 | #define SR_PID 0x2A /* 0x2A ~ 0x2B 2 bytes for PID */ |
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| 133 | /* CHIP Revision register */ |
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| 134 | #define SR_CHIPR 0x2C |
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| 135 | /* 0x2D --> 0xEF unused */ |
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| 136 | /* USB Device Address */ |
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| 137 | #define SR_USBDA 0xF0 |
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| 138 | #define USBDA_USBFA (0x7F << 0) |
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| 139 | /* RX packet Counter Reg */ |
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| 140 | #define SR_RXC 0xF1 |
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| 141 | /* Tx packet Counter & USB Status Reg */ |
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| 142 | #define SR_TXC_USBS 0xF2 |
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| 143 | #define TXC_USBS_TXC0 (1 << 0) |
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| 144 | #define TXC_USBS_TXC1 (1 << 1) |
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| 145 | #define TXC_USBS_TXC2 (1 << 2) |
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| 146 | #define TXC_USBS_EP1RDY (1 << 5) |
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| 147 | #define TXC_USBS_SUSFLAG (1 << 6) |
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| 148 | #define TXC_USBS_RXFAULT (1 << 7) |
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| 149 | /* USB Control register */ |
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| 150 | #define SR_USBC 0xF4 |
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| 151 | #define USBC_EP3NAK (1 << 4) |
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| 152 | #define USBC_EP3ACK (1 << 5) |
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| 153 | |
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| 154 | /* Register access commands and flags */ |
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| 155 | #define SR_RD_REGS 0x00 |
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| 156 | #define SR_WR_REGS 0x01 |
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| 157 | #define SR_WR_REG 0x03 |
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| 158 | #define SR_REQ_RD_REG (USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE) |
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| 159 | #define SR_REQ_WR_REG (USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE) |
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| 160 | |
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| 161 | /* parameters */ |
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| 162 | #define SR_SHARE_TIMEOUT 1000 |
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| 163 | #define SR_EEPROM_LEN 256 |
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| 164 | #define SR_MCAST_SIZE 8 |
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| 165 | #define SR_MCAST_ADDR_FLAG 0x80 |
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| 166 | #define SR_MCAST_MAX 64 |
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| 167 | #define SR_TX_OVERHEAD 2 /* 2bytes header */ |
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| 168 | #define SR_RX_OVERHEAD 7 /* 3bytes header + 4crc tail */ |
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| 169 | |
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| 170 | #endif /* _SR9700_H */ |
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| 171 | |
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