1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
2 | /* |
3 | * FarSync X21 driver for Linux |
4 | * |
5 | * Actually sync driver for X.21, V.35 and V.24 on FarSync T-series cards |
6 | * |
7 | * Copyright (C) 2001 FarSite Communications Ltd. |
8 | * www.farsite.co.uk |
9 | * |
10 | * Author: R.J.Dunlop <bob.dunlop@farsite.co.uk> |
11 | * |
12 | * For the most part this file only contains structures and information |
13 | * that is visible to applications outside the driver. Shared memory |
14 | * layout etc is internal to the driver and described within farsync.c. |
15 | * Overlap exists in that the values used for some fields within the |
16 | * ioctl interface extend into the cards firmware interface so values in |
17 | * this file may not be changed arbitrarily. |
18 | */ |
19 | |
20 | /* What's in a name |
21 | * |
22 | * The project name for this driver is Oscar. The driver is intended to be |
23 | * used with the FarSite T-Series cards (T2P & T4P) running in the high |
24 | * speed frame shifter mode. This is sometimes referred to as X.21 mode |
25 | * which is a complete misnomer as the card continues to support V.24 and |
26 | * V.35 as well as X.21. |
27 | * |
28 | * A short common prefix is useful for routines within the driver to avoid |
29 | * conflict with other similar drivers and I chosen to use "fst_" for this |
30 | * purpose (FarSite T-series). |
31 | * |
32 | * Finally the device driver needs a short network interface name. Since |
33 | * "hdlc" is already in use I've chosen the even less informative "sync" |
34 | * for the present. |
35 | */ |
36 | #define FST_NAME "fst" /* In debug/info etc */ |
37 | #define FST_NDEV_NAME "sync" /* For net interface */ |
38 | #define FST_DEV_NAME "farsync" /* For misc interfaces */ |
39 | |
40 | |
41 | /* User version number |
42 | * |
43 | * This version number is incremented with each official release of the |
44 | * package and is a simplified number for normal user reference. |
45 | * Individual files are tracked by the version control system and may |
46 | * have individual versions (or IDs) that move much faster than |
47 | * the release version as individual updates are tracked. |
48 | */ |
49 | #define FST_USER_VERSION "1.04" |
50 | |
51 | |
52 | /* Ioctl call command values |
53 | */ |
54 | #define FSTWRITE (SIOCDEVPRIVATE+10) |
55 | #define FSTCPURESET (SIOCDEVPRIVATE+11) |
56 | #define FSTCPURELEASE (SIOCDEVPRIVATE+12) |
57 | #define FSTGETCONF (SIOCDEVPRIVATE+13) |
58 | #define FSTSETCONF (SIOCDEVPRIVATE+14) |
59 | |
60 | |
61 | /* FSTWRITE |
62 | * |
63 | * Used to write a block of data (firmware etc) before the card is running |
64 | */ |
65 | struct fstioc_write { |
66 | unsigned int size; |
67 | unsigned int offset; |
68 | unsigned char data[]; |
69 | }; |
70 | |
71 | |
72 | /* FSTCPURESET and FSTCPURELEASE |
73 | * |
74 | * These take no additional data. |
75 | * FSTCPURESET forces the cards CPU into a reset state and holds it there. |
76 | * FSTCPURELEASE releases the CPU from this reset state allowing it to run, |
77 | * the reset vector should be setup before this ioctl is run. |
78 | */ |
79 | |
80 | /* FSTGETCONF and FSTSETCONF |
81 | * |
82 | * Get and set a card/ports configuration. |
83 | * In order to allow selective setting of items and for the kernel to |
84 | * indicate a partial status response the first field "valid" is a bitmask |
85 | * indicating which other fields in the structure are valid. |
86 | * Many of the field names in this structure match those used in the |
87 | * firmware shared memory configuration interface and come originally from |
88 | * the NT header file Smc.h |
89 | * |
90 | * When used with FSTGETCONF this structure should be zeroed before use. |
91 | * This is to allow for possible future expansion when some of the fields |
92 | * might be used to indicate a different (expanded) structure. |
93 | */ |
94 | struct fstioc_info { |
95 | unsigned int valid; /* Bits of structure that are valid */ |
96 | unsigned int nports; /* Number of serial ports */ |
97 | unsigned int type; /* Type index of card */ |
98 | unsigned int state; /* State of card */ |
99 | unsigned int index; /* Index of port ioctl was issued on */ |
100 | unsigned int smcFirmwareVersion; |
101 | unsigned long kernelVersion; /* What Kernel version we are working with */ |
102 | unsigned short lineInterface; /* Physical interface type */ |
103 | unsigned char proto; /* Line protocol */ |
104 | unsigned char internalClock; /* 1 => internal clock, 0 => external */ |
105 | unsigned int lineSpeed; /* Speed in bps */ |
106 | unsigned int v24IpSts; /* V.24 control input status */ |
107 | unsigned int v24OpSts; /* V.24 control output status */ |
108 | unsigned short clockStatus; /* lsb: 0=> present, 1=> absent */ |
109 | unsigned short cableStatus; /* lsb: 0=> present, 1=> absent */ |
110 | unsigned short cardMode; /* lsb: LED id mode */ |
111 | unsigned short debug; /* Debug flags */ |
112 | unsigned char transparentMode; /* Not used always 0 */ |
113 | unsigned char invertClock; /* Invert clock feature for syncing */ |
114 | unsigned char startingSlot; /* Time slot to use for start of tx */ |
115 | unsigned char clockSource; /* External or internal */ |
116 | unsigned char framing; /* E1, T1 or J1 */ |
117 | unsigned char structure; /* unframed, double, crc4, f4, f12, */ |
118 | /* f24 f72 */ |
119 | unsigned char interface; /* rj48c or bnc */ |
120 | unsigned char coding; /* hdb3 b8zs */ |
121 | unsigned char lineBuildOut; /* 0, -7.5, -15, -22 */ |
122 | unsigned char equalizer; /* short or lon haul settings */ |
123 | unsigned char loopMode; /* various loopbacks */ |
124 | unsigned char range; /* cable lengths */ |
125 | unsigned char txBufferMode; /* tx elastic buffer depth */ |
126 | unsigned char rxBufferMode; /* rx elastic buffer depth */ |
127 | unsigned char losThreshold; /* Attenuation on LOS signal */ |
128 | unsigned char idleCode; /* Value to send as idle timeslot */ |
129 | unsigned int receiveBufferDelay; /* delay thro rx buffer timeslots */ |
130 | unsigned int framingErrorCount; /* framing errors */ |
131 | unsigned int codeViolationCount; /* code violations */ |
132 | unsigned int crcErrorCount; /* CRC errors */ |
133 | int lineAttenuation; /* in dB*/ |
134 | unsigned short lossOfSignal; |
135 | unsigned short receiveRemoteAlarm; |
136 | unsigned short alarmIndicationSignal; |
137 | }; |
138 | |
139 | /* "valid" bitmask */ |
140 | #define FSTVAL_NONE 0x00000000 /* Nothing valid (firmware not running). |
141 | * Slight misnomer. In fact nports, |
142 | * type, state and index will be set |
143 | * based on hardware detected. |
144 | */ |
145 | #define FSTVAL_OMODEM 0x0000001F /* First 5 bits correspond to the |
146 | * output status bits defined for |
147 | * v24OpSts |
148 | */ |
149 | #define FSTVAL_SPEED 0x00000020 /* internalClock, lineSpeed, clockStatus |
150 | */ |
151 | #define FSTVAL_CABLE 0x00000040 /* lineInterface, cableStatus */ |
152 | #define FSTVAL_IMODEM 0x00000080 /* v24IpSts */ |
153 | #define FSTVAL_CARD 0x00000100 /* nports, type, state, index, |
154 | * smcFirmwareVersion |
155 | */ |
156 | #define FSTVAL_PROTO 0x00000200 /* proto */ |
157 | #define FSTVAL_MODE 0x00000400 /* cardMode */ |
158 | #define FSTVAL_PHASE 0x00000800 /* Clock phase */ |
159 | #define FSTVAL_TE1 0x00001000 /* T1E1 Configuration */ |
160 | #define FSTVAL_DEBUG 0x80000000 /* debug */ |
161 | #define FSTVAL_ALL 0x00001FFF /* Note: does not include DEBUG flag */ |
162 | |
163 | /* "type" */ |
164 | #define FST_TYPE_NONE 0 /* Probably should never happen */ |
165 | #define FST_TYPE_T2P 1 /* T2P X21 2 port card */ |
166 | #define FST_TYPE_T4P 2 /* T4P X21 4 port card */ |
167 | #define FST_TYPE_T1U 3 /* T1U X21 1 port card */ |
168 | #define FST_TYPE_T2U 4 /* T2U X21 2 port card */ |
169 | #define FST_TYPE_T4U 5 /* T4U X21 4 port card */ |
170 | #define FST_TYPE_TE1 6 /* T1E1 X21 1 port card */ |
171 | |
172 | /* "family" */ |
173 | #define FST_FAMILY_TXP 0 /* T2P or T4P */ |
174 | #define FST_FAMILY_TXU 1 /* T1U or T2U or T4U */ |
175 | |
176 | /* "state" */ |
177 | #define FST_UNINIT 0 /* Raw uninitialised state following |
178 | * system startup */ |
179 | #define FST_RESET 1 /* Processor held in reset state */ |
180 | #define FST_DOWNLOAD 2 /* Card being downloaded */ |
181 | #define FST_STARTING 3 /* Released following download */ |
182 | #define FST_RUNNING 4 /* Processor running */ |
183 | #define FST_BADVERSION 5 /* Bad shared memory version detected */ |
184 | #define FST_HALTED 6 /* Processor flagged a halt */ |
185 | #define FST_IFAILED 7 /* Firmware issued initialisation failed |
186 | * interrupt |
187 | */ |
188 | /* "lineInterface" */ |
189 | #define V24 1 |
190 | #define X21 2 |
191 | #define V35 3 |
192 | #define X21D 4 |
193 | #define T1 5 |
194 | #define E1 6 |
195 | #define J1 7 |
196 | |
197 | /* "proto" */ |
198 | #define FST_RAW 4 /* Two way raw packets */ |
199 | #define FST_GEN_HDLC 5 /* Using "Generic HDLC" module */ |
200 | |
201 | /* "internalClock" */ |
202 | #define INTCLK 1 |
203 | #define EXTCLK 0 |
204 | |
205 | /* "v24IpSts" bitmask */ |
206 | #define IPSTS_CTS 0x00000001 /* Clear To Send (Indicate for X.21) */ |
207 | #define IPSTS_INDICATE IPSTS_CTS |
208 | #define IPSTS_DSR 0x00000002 /* Data Set Ready (T2P Port A) */ |
209 | #define IPSTS_DCD 0x00000004 /* Data Carrier Detect */ |
210 | #define IPSTS_RI 0x00000008 /* Ring Indicator (T2P Port A) */ |
211 | #define IPSTS_TMI 0x00000010 /* Test Mode Indicator (Not Supported)*/ |
212 | |
213 | /* "v24OpSts" bitmask */ |
214 | #define OPSTS_RTS 0x00000001 /* Request To Send (Control for X.21) */ |
215 | #define OPSTS_CONTROL OPSTS_RTS |
216 | #define OPSTS_DTR 0x00000002 /* Data Terminal Ready */ |
217 | #define OPSTS_DSRS 0x00000004 /* Data Signalling Rate Select (Not |
218 | * Supported) */ |
219 | #define OPSTS_SS 0x00000008 /* Select Standby (Not Supported) */ |
220 | #define OPSTS_LL 0x00000010 /* Maintenance Test (Not Supported) */ |
221 | |
222 | /* "cardMode" bitmask */ |
223 | #define CARD_MODE_IDENTIFY 0x0001 |
224 | |
225 | /* |
226 | * Constants for T1/E1 configuration |
227 | */ |
228 | |
229 | /* |
230 | * Clock source |
231 | */ |
232 | #define CLOCKING_SLAVE 0 |
233 | #define CLOCKING_MASTER 1 |
234 | |
235 | /* |
236 | * Framing |
237 | */ |
238 | #define FRAMING_E1 0 |
239 | #define FRAMING_J1 1 |
240 | #define FRAMING_T1 2 |
241 | |
242 | /* |
243 | * Structure |
244 | */ |
245 | #define STRUCTURE_UNFRAMED 0 |
246 | #define STRUCTURE_E1_DOUBLE 1 |
247 | #define STRUCTURE_E1_CRC4 2 |
248 | #define STRUCTURE_E1_CRC4M 3 |
249 | #define STRUCTURE_T1_4 4 |
250 | #define STRUCTURE_T1_12 5 |
251 | #define STRUCTURE_T1_24 6 |
252 | #define STRUCTURE_T1_72 7 |
253 | |
254 | /* |
255 | * Interface |
256 | */ |
257 | #define INTERFACE_RJ48C 0 |
258 | #define INTERFACE_BNC 1 |
259 | |
260 | /* |
261 | * Coding |
262 | */ |
263 | |
264 | #define CODING_HDB3 0 |
265 | #define CODING_NRZ 1 |
266 | #define CODING_CMI 2 |
267 | #define CODING_CMI_HDB3 3 |
268 | #define CODING_CMI_B8ZS 4 |
269 | #define CODING_AMI 5 |
270 | #define CODING_AMI_ZCS 6 |
271 | #define CODING_B8ZS 7 |
272 | |
273 | /* |
274 | * Line Build Out |
275 | */ |
276 | #define LBO_0dB 0 |
277 | #define LBO_7dB5 1 |
278 | #define LBO_15dB 2 |
279 | #define LBO_22dB5 3 |
280 | |
281 | /* |
282 | * Range for long haul t1 > 655ft |
283 | */ |
284 | #define RANGE_0_133_FT 0 |
285 | #define RANGE_0_40_M RANGE_0_133_FT |
286 | #define RANGE_133_266_FT 1 |
287 | #define RANGE_40_81_M RANGE_133_266_FT |
288 | #define RANGE_266_399_FT 2 |
289 | #define RANGE_81_122_M RANGE_266_399_FT |
290 | #define RANGE_399_533_FT 3 |
291 | #define RANGE_122_162_M RANGE_399_533_FT |
292 | #define RANGE_533_655_FT 4 |
293 | #define RANGE_162_200_M RANGE_533_655_FT |
294 | /* |
295 | * Receive Equaliser |
296 | */ |
297 | #define EQUALIZER_SHORT 0 |
298 | #define EQUALIZER_LONG 1 |
299 | |
300 | /* |
301 | * Loop modes |
302 | */ |
303 | #define LOOP_NONE 0 |
304 | #define LOOP_LOCAL 1 |
305 | #define LOOP_PAYLOAD_EXC_TS0 2 |
306 | #define LOOP_PAYLOAD_INC_TS0 3 |
307 | #define LOOP_REMOTE 4 |
308 | |
309 | /* |
310 | * Buffer modes |
311 | */ |
312 | #define BUFFER_2_FRAME 0 |
313 | #define BUFFER_1_FRAME 1 |
314 | #define BUFFER_96_BIT 2 |
315 | #define BUFFER_NONE 3 |
316 | |
317 | /* Debug support |
318 | * |
319 | * These should only be enabled for development kernels, production code |
320 | * should define FST_DEBUG=0 in order to exclude the code. |
321 | * Setting FST_DEBUG=1 will include all the debug code but in a disabled |
322 | * state, use the FSTSETCONF ioctl to enable specific debug actions, or |
323 | * FST_DEBUG can be set to prime the debug selection. |
324 | */ |
325 | #define FST_DEBUG 0x0000 |
326 | #if FST_DEBUG |
327 | |
328 | extern int fst_debug_mask; /* Bit mask of actions to debug, bits |
329 | * listed below. Note: Bit 0 is used |
330 | * to trigger the inclusion of this |
331 | * code, without enabling any actions. |
332 | */ |
333 | #define DBG_INIT 0x0002 /* Card detection and initialisation */ |
334 | #define DBG_OPEN 0x0004 /* Open and close sequences */ |
335 | #define DBG_PCI 0x0008 /* PCI config operations */ |
336 | #define DBG_IOCTL 0x0010 /* Ioctls and other config */ |
337 | #define DBG_INTR 0x0020 /* Interrupt routines (be careful) */ |
338 | #define DBG_TX 0x0040 /* Packet transmission */ |
339 | #define DBG_RX 0x0080 /* Packet reception */ |
340 | #define DBG_CMD 0x0100 /* Port command issuing */ |
341 | |
342 | #define DBG_ASS 0xFFFF /* Assert like statements. Code that |
343 | * should never be reached, if you see |
344 | * one of these then I've been an ass |
345 | */ |
346 | #endif /* FST_DEBUG */ |
347 | |
348 | |