| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 2 | /* |
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| 3 | * hd64572.h Description of the Hitachi HD64572 (SCA-II), valid for |
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| 4 | * CPU modes 0 & 2. |
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| 5 | * |
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| 6 | * Author: Ivan Passos <ivan@cyclades.com> |
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| 7 | * |
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| 8 | * Copyright: (c) 2000-2001 Cyclades Corp. |
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| 9 | * |
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| 10 | * $Log: hd64572.h,v $ |
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| 11 | * Revision 3.1 2001/06/15 12:41:10 regina |
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| 12 | * upping major version number |
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| 13 | * |
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| 14 | * Revision 1.1.1.1 2001/06/13 20:24:49 daniela |
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| 15 | * PC300 initial CVS version (3.4.0-pre1) |
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| 16 | * |
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| 17 | * Revision 1.0 2000/01/25 ivan |
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| 18 | * Initial version. |
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| 19 | */ |
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| 20 | |
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| 21 | #ifndef __HD64572_H |
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| 22 | #define __HD64572_H |
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| 23 | |
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| 24 | /* Illegal Access Register */ |
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| 25 | #define ILAR 0x00 |
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| 26 | |
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| 27 | /* Wait Controller Registers */ |
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| 28 | #define PABR0L 0x20 /* Physical Addr Boundary Register 0 L */ |
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| 29 | #define PABR0H 0x21 /* Physical Addr Boundary Register 0 H */ |
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| 30 | #define PABR1L 0x22 /* Physical Addr Boundary Register 1 L */ |
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| 31 | #define PABR1H 0x23 /* Physical Addr Boundary Register 1 H */ |
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| 32 | #define WCRL 0x24 /* Wait Control Register L */ |
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| 33 | #define WCRM 0x25 /* Wait Control Register M */ |
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| 34 | #define WCRH 0x26 /* Wait Control Register H */ |
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| 35 | |
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| 36 | /* Interrupt Registers */ |
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| 37 | #define IVR 0x60 /* Interrupt Vector Register */ |
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| 38 | #define IMVR 0x64 /* Interrupt Modified Vector Register */ |
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| 39 | #define ITCR 0x68 /* Interrupt Control Register */ |
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| 40 | #define ISR0 0x6c /* Interrupt Status Register 0 */ |
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| 41 | #define ISR1 0x70 /* Interrupt Status Register 1 */ |
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| 42 | #define IER0 0x74 /* Interrupt Enable Register 0 */ |
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| 43 | #define IER1 0x78 /* Interrupt Enable Register 1 */ |
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| 44 | |
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| 45 | /* Register Access Macros (chan is 0 or 1 in _any_ case) */ |
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| 46 | #define M_REG(reg, chan) (reg + 0x80*chan) /* MSCI */ |
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| 47 | #define DRX_REG(reg, chan) (reg + 0x40*chan) /* DMA Rx */ |
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| 48 | #define DTX_REG(reg, chan) (reg + 0x20*(2*chan + 1)) /* DMA Tx */ |
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| 49 | #define TRX_REG(reg, chan) (reg + 0x20*chan) /* Timer Rx */ |
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| 50 | #define TTX_REG(reg, chan) (reg + 0x10*(2*chan + 1)) /* Timer Tx */ |
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| 51 | #define ST_REG(reg, chan) (reg + 0x80*chan) /* Status Cnt */ |
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| 52 | #define IR0_DRX(val, chan) ((val)<<(8*(chan))) /* Int DMA Rx */ |
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| 53 | #define IR0_DTX(val, chan) ((val)<<(4*(2*chan + 1))) /* Int DMA Tx */ |
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| 54 | #define IR0_M(val, chan) ((val)<<(8*(chan))) /* Int MSCI */ |
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| 55 | |
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| 56 | /* MSCI Channel Registers */ |
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| 57 | #define MSCI0_OFFSET 0x00 |
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| 58 | #define MSCI1_OFFSET 0x80 |
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| 59 | |
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| 60 | #define MD0 0x138 /* Mode reg 0 */ |
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| 61 | #define MD1 0x139 /* Mode reg 1 */ |
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| 62 | #define MD2 0x13a /* Mode reg 2 */ |
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| 63 | #define MD3 0x13b /* Mode reg 3 */ |
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| 64 | #define CTL 0x130 /* Control reg */ |
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| 65 | #define RXS 0x13c /* RX clock source */ |
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| 66 | #define TXS 0x13d /* TX clock source */ |
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| 67 | #define EXS 0x13e /* External clock input selection */ |
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| 68 | #define TMCT 0x144 /* Time constant (Tx) */ |
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| 69 | #define TMCR 0x145 /* Time constant (Rx) */ |
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| 70 | #define CMD 0x128 /* Command reg */ |
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| 71 | #define ST0 0x118 /* Status reg 0 */ |
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| 72 | #define ST1 0x119 /* Status reg 1 */ |
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| 73 | #define ST2 0x11a /* Status reg 2 */ |
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| 74 | #define ST3 0x11b /* Status reg 3 */ |
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| 75 | #define ST4 0x11c /* Status reg 4 */ |
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| 76 | #define FST 0x11d /* frame Status reg */ |
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| 77 | #define IE0 0x120 /* Interrupt enable reg 0 */ |
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| 78 | #define IE1 0x121 /* Interrupt enable reg 1 */ |
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| 79 | #define IE2 0x122 /* Interrupt enable reg 2 */ |
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| 80 | #define IE4 0x124 /* Interrupt enable reg 4 */ |
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| 81 | #define FIE 0x125 /* Frame Interrupt enable reg */ |
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| 82 | #define SA0 0x140 /* Syn Address reg 0 */ |
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| 83 | #define SA1 0x141 /* Syn Address reg 1 */ |
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| 84 | #define IDL 0x142 /* Idle register */ |
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| 85 | #define TRBL 0x100 /* TX/RX buffer reg L */ |
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| 86 | #define TRBK 0x101 /* TX/RX buffer reg K */ |
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| 87 | #define TRBJ 0x102 /* TX/RX buffer reg J */ |
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| 88 | #define TRBH 0x103 /* TX/RX buffer reg H */ |
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| 89 | #define TRC0 0x148 /* TX Ready control reg 0 */ |
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| 90 | #define TRC1 0x149 /* TX Ready control reg 1 */ |
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| 91 | #define RRC 0x14a /* RX Ready control reg */ |
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| 92 | #define CST0 0x108 /* Current Status Register 0 */ |
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| 93 | #define CST1 0x109 /* Current Status Register 1 */ |
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| 94 | #define CST2 0x10a /* Current Status Register 2 */ |
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| 95 | #define CST3 0x10b /* Current Status Register 3 */ |
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| 96 | #define GPO 0x131 /* General Purpose Output Pin Ctl Reg */ |
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| 97 | #define TFS 0x14b /* Tx Start Threshold Ctl Reg */ |
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| 98 | #define TFN 0x143 /* Inter-transmit-frame Time Fill Ctl Reg */ |
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| 99 | #define TBN 0x110 /* Tx Buffer Number Reg */ |
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| 100 | #define RBN 0x111 /* Rx Buffer Number Reg */ |
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| 101 | #define TNR0 0x150 /* Tx DMA Request Ctl Reg 0 */ |
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| 102 | #define TNR1 0x151 /* Tx DMA Request Ctl Reg 1 */ |
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| 103 | #define TCR 0x152 /* Tx DMA Critical Request Reg */ |
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| 104 | #define RNR 0x154 /* Rx DMA Request Ctl Reg */ |
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| 105 | #define RCR 0x156 /* Rx DMA Critical Request Reg */ |
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| 106 | |
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| 107 | /* Timer Registers */ |
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| 108 | #define TIMER0RX_OFFSET 0x00 |
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| 109 | #define TIMER0TX_OFFSET 0x10 |
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| 110 | #define TIMER1RX_OFFSET 0x20 |
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| 111 | #define TIMER1TX_OFFSET 0x30 |
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| 112 | |
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| 113 | #define TCNTL 0x200 /* Timer Upcounter L */ |
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| 114 | #define TCNTH 0x201 /* Timer Upcounter H */ |
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| 115 | #define TCONRL 0x204 /* Timer Constant Register L */ |
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| 116 | #define TCONRH 0x205 /* Timer Constant Register H */ |
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| 117 | #define TCSR 0x206 /* Timer Control/Status Register */ |
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| 118 | #define TEPR 0x207 /* Timer Expand Prescale Register */ |
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| 119 | |
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| 120 | /* DMA registers */ |
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| 121 | #define PCR 0x40 /* DMA priority control reg */ |
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| 122 | #define DRR 0x44 /* DMA reset reg */ |
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| 123 | #define DMER 0x07 /* DMA Master Enable reg */ |
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| 124 | #define BTCR 0x08 /* Burst Tx Ctl Reg */ |
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| 125 | #define BOLR 0x0c /* Back-off Length Reg */ |
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| 126 | #define DSR_RX(chan) (0x48 + 2*chan) /* DMA Status Reg (Rx) */ |
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| 127 | #define DSR_TX(chan) (0x49 + 2*chan) /* DMA Status Reg (Tx) */ |
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| 128 | #define DIR_RX(chan) (0x4c + 2*chan) /* DMA Interrupt Enable Reg (Rx) */ |
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| 129 | #define DIR_TX(chan) (0x4d + 2*chan) /* DMA Interrupt Enable Reg (Tx) */ |
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| 130 | #define FCT_RX(chan) (0x50 + 2*chan) /* Frame End Interrupt Counter (Rx) */ |
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| 131 | #define FCT_TX(chan) (0x51 + 2*chan) /* Frame End Interrupt Counter (Tx) */ |
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| 132 | #define DMR_RX(chan) (0x54 + 2*chan) /* DMA Mode Reg (Rx) */ |
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| 133 | #define DMR_TX(chan) (0x55 + 2*chan) /* DMA Mode Reg (Tx) */ |
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| 134 | #define DCR_RX(chan) (0x58 + 2*chan) /* DMA Command Reg (Rx) */ |
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| 135 | #define DCR_TX(chan) (0x59 + 2*chan) /* DMA Command Reg (Tx) */ |
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| 136 | |
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| 137 | /* DMA Channel Registers */ |
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| 138 | #define DMAC0RX_OFFSET 0x00 |
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| 139 | #define DMAC0TX_OFFSET 0x20 |
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| 140 | #define DMAC1RX_OFFSET 0x40 |
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| 141 | #define DMAC1TX_OFFSET 0x60 |
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| 142 | |
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| 143 | #define DARL 0x80 /* Dest Addr Register L (single-block, RX only) */ |
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| 144 | #define DARH 0x81 /* Dest Addr Register H (single-block, RX only) */ |
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| 145 | #define DARB 0x82 /* Dest Addr Register B (single-block, RX only) */ |
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| 146 | #define DARBH 0x83 /* Dest Addr Register BH (single-block, RX only) */ |
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| 147 | #define SARL 0x80 /* Source Addr Register L (single-block, TX only) */ |
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| 148 | #define SARH 0x81 /* Source Addr Register H (single-block, TX only) */ |
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| 149 | #define SARB 0x82 /* Source Addr Register B (single-block, TX only) */ |
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| 150 | #define DARBH 0x83 /* Source Addr Register BH (single-block, TX only) */ |
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| 151 | #define BARL 0x80 /* Buffer Addr Register L (chained-block) */ |
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| 152 | #define BARH 0x81 /* Buffer Addr Register H (chained-block) */ |
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| 153 | #define BARB 0x82 /* Buffer Addr Register B (chained-block) */ |
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| 154 | #define BARBH 0x83 /* Buffer Addr Register BH (chained-block) */ |
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| 155 | #define CDAL 0x84 /* Current Descriptor Addr Register L */ |
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| 156 | #define CDAH 0x85 /* Current Descriptor Addr Register H */ |
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| 157 | #define CDAB 0x86 /* Current Descriptor Addr Register B */ |
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| 158 | #define CDABH 0x87 /* Current Descriptor Addr Register BH */ |
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| 159 | #define EDAL 0x88 /* Error Descriptor Addr Register L */ |
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| 160 | #define EDAH 0x89 /* Error Descriptor Addr Register H */ |
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| 161 | #define EDAB 0x8a /* Error Descriptor Addr Register B */ |
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| 162 | #define EDABH 0x8b /* Error Descriptor Addr Register BH */ |
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| 163 | #define BFLL 0x90 /* RX Buffer Length L (only RX) */ |
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| 164 | #define BFLH 0x91 /* RX Buffer Length H (only RX) */ |
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| 165 | #define BCRL 0x8c /* Byte Count Register L */ |
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| 166 | #define BCRH 0x8d /* Byte Count Register H */ |
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| 167 | |
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| 168 | /* Block Descriptor Structure */ |
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| 169 | typedef struct { |
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| 170 | unsigned long next; /* pointer to next block descriptor */ |
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| 171 | unsigned long ptbuf; /* buffer pointer */ |
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| 172 | unsigned short len; /* data length */ |
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| 173 | unsigned char status; /* status */ |
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| 174 | unsigned char filler[5]; /* alignment filler (16 bytes) */ |
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| 175 | } pcsca_bd_t; |
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| 176 | |
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| 177 | /* Block Descriptor Structure */ |
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| 178 | typedef struct { |
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| 179 | u32 cp; /* pointer to next block descriptor */ |
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| 180 | u32 bp; /* buffer pointer */ |
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| 181 | u16 len; /* data length */ |
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| 182 | u8 stat; /* status */ |
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| 183 | u8 unused; /* pads to 4-byte boundary */ |
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| 184 | }pkt_desc; |
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| 185 | |
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| 186 | |
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| 187 | /* |
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| 188 | Descriptor Status definitions: |
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| 189 | |
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| 190 | Bit Transmission Reception |
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| 191 | |
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| 192 | 7 EOM EOM |
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| 193 | 6 - Short Frame |
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| 194 | 5 - Abort |
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| 195 | 4 - Residual bit |
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| 196 | 3 Underrun Overrun |
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| 197 | 2 - CRC |
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| 198 | 1 Ownership Ownership |
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| 199 | 0 EOT - |
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| 200 | */ |
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| 201 | #define DST_EOT 0x01 /* End of transmit command */ |
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| 202 | #define DST_OSB 0x02 /* Ownership bit */ |
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| 203 | #define DST_CRC 0x04 /* CRC Error */ |
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| 204 | #define DST_OVR 0x08 /* Overrun */ |
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| 205 | #define DST_UDR 0x08 /* Underrun */ |
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| 206 | #define DST_RBIT 0x10 /* Residual bit */ |
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| 207 | #define DST_ABT 0x20 /* Abort */ |
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| 208 | #define DST_SHRT 0x40 /* Short Frame */ |
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| 209 | #define DST_EOM 0x80 /* End of Message */ |
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| 210 | |
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| 211 | /* Packet Descriptor Status bits */ |
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| 212 | |
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| 213 | #define ST_TX_EOM 0x80 /* End of frame */ |
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| 214 | #define ST_TX_UNDRRUN 0x08 |
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| 215 | #define ST_TX_OWNRSHP 0x02 |
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| 216 | #define ST_TX_EOT 0x01 /* End of transmission */ |
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| 217 | |
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| 218 | #define ST_RX_EOM 0x80 /* End of frame */ |
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| 219 | #define ST_RX_SHORT 0x40 /* Short frame */ |
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| 220 | #define ST_RX_ABORT 0x20 /* Abort */ |
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| 221 | #define ST_RX_RESBIT 0x10 /* Residual bit */ |
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| 222 | #define ST_RX_OVERRUN 0x08 /* Overrun */ |
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| 223 | #define ST_RX_CRC 0x04 /* CRC */ |
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| 224 | #define ST_RX_OWNRSHP 0x02 |
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| 225 | |
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| 226 | #define ST_ERROR_MASK 0x7C |
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| 227 | |
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| 228 | /* Status Counter Registers */ |
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| 229 | #define CMCR 0x158 /* Counter Master Ctl Reg */ |
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| 230 | #define TECNTL 0x160 /* Tx EOM Counter L */ |
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| 231 | #define TECNTM 0x161 /* Tx EOM Counter M */ |
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| 232 | #define TECNTH 0x162 /* Tx EOM Counter H */ |
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| 233 | #define TECCR 0x163 /* Tx EOM Counter Ctl Reg */ |
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| 234 | #define URCNTL 0x164 /* Underrun Counter L */ |
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| 235 | #define URCNTH 0x165 /* Underrun Counter H */ |
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| 236 | #define URCCR 0x167 /* Underrun Counter Ctl Reg */ |
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| 237 | #define RECNTL 0x168 /* Rx EOM Counter L */ |
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| 238 | #define RECNTM 0x169 /* Rx EOM Counter M */ |
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| 239 | #define RECNTH 0x16a /* Rx EOM Counter H */ |
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| 240 | #define RECCR 0x16b /* Rx EOM Counter Ctl Reg */ |
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| 241 | #define ORCNTL 0x16c /* Overrun Counter L */ |
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| 242 | #define ORCNTH 0x16d /* Overrun Counter H */ |
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| 243 | #define ORCCR 0x16f /* Overrun Counter Ctl Reg */ |
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| 244 | #define CECNTL 0x170 /* CRC Counter L */ |
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| 245 | #define CECNTH 0x171 /* CRC Counter H */ |
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| 246 | #define CECCR 0x173 /* CRC Counter Ctl Reg */ |
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| 247 | #define ABCNTL 0x174 /* Abort frame Counter L */ |
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| 248 | #define ABCNTH 0x175 /* Abort frame Counter H */ |
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| 249 | #define ABCCR 0x177 /* Abort frame Counter Ctl Reg */ |
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| 250 | #define SHCNTL 0x178 /* Short frame Counter L */ |
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| 251 | #define SHCNTH 0x179 /* Short frame Counter H */ |
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| 252 | #define SHCCR 0x17b /* Short frame Counter Ctl Reg */ |
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| 253 | #define RSCNTL 0x17c /* Residual bit Counter L */ |
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| 254 | #define RSCNTH 0x17d /* Residual bit Counter H */ |
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| 255 | #define RSCCR 0x17f /* Residual bit Counter Ctl Reg */ |
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| 256 | |
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| 257 | /* Register Programming Constants */ |
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| 258 | |
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| 259 | #define IR0_DMIC 0x00000001 |
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| 260 | #define IR0_DMIB 0x00000002 |
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| 261 | #define IR0_DMIA 0x00000004 |
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| 262 | #define IR0_EFT 0x00000008 |
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| 263 | #define IR0_DMAREQ 0x00010000 |
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| 264 | #define IR0_TXINT 0x00020000 |
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| 265 | #define IR0_RXINTB 0x00040000 |
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| 266 | #define IR0_RXINTA 0x00080000 |
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| 267 | #define IR0_TXRDY 0x00100000 |
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| 268 | #define IR0_RXRDY 0x00200000 |
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| 269 | |
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| 270 | #define MD0_CRC16_0 0x00 |
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| 271 | #define MD0_CRC16_1 0x01 |
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| 272 | #define MD0_CRC32 0x02 |
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| 273 | #define MD0_CRC_CCITT 0x03 |
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| 274 | #define MD0_CRCC0 0x04 |
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| 275 | #define MD0_CRCC1 0x08 |
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| 276 | #define MD0_AUTO_ENA 0x10 |
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| 277 | #define MD0_ASYNC 0x00 |
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| 278 | #define MD0_BY_MSYNC 0x20 |
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| 279 | #define MD0_BY_BISYNC 0x40 |
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| 280 | #define MD0_BY_EXT 0x60 |
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| 281 | #define MD0_BIT_SYNC 0x80 |
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| 282 | #define MD0_TRANSP 0xc0 |
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| 283 | |
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| 284 | #define MD0_HDLC 0x80 /* Bit-sync HDLC mode */ |
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| 285 | |
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| 286 | #define MD0_CRC_NONE 0x00 |
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| 287 | #define MD0_CRC_16_0 0x04 |
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| 288 | #define MD0_CRC_16 0x05 |
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| 289 | #define MD0_CRC_ITU32 0x06 |
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| 290 | #define MD0_CRC_ITU 0x07 |
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| 291 | |
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| 292 | #define MD1_NOADDR 0x00 |
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| 293 | #define MD1_SADDR1 0x40 |
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| 294 | #define MD1_SADDR2 0x80 |
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| 295 | #define MD1_DADDR 0xc0 |
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| 296 | |
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| 297 | #define MD2_NRZI_IEEE 0x40 |
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| 298 | #define MD2_MANCHESTER 0x80 |
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| 299 | #define MD2_FM_MARK 0xA0 |
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| 300 | #define MD2_FM_SPACE 0xC0 |
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| 301 | #define MD2_LOOPBACK 0x03 /* Local data Loopback */ |
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| 302 | |
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| 303 | #define MD2_F_DUPLEX 0x00 |
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| 304 | #define MD2_AUTO_ECHO 0x01 |
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| 305 | #define MD2_LOOP_HI_Z 0x02 |
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| 306 | #define MD2_LOOP_MIR 0x03 |
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| 307 | #define MD2_ADPLL_X8 0x00 |
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| 308 | #define MD2_ADPLL_X16 0x08 |
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| 309 | #define MD2_ADPLL_X32 0x10 |
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| 310 | #define MD2_NRZ 0x00 |
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| 311 | #define MD2_NRZI 0x20 |
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| 312 | #define MD2_NRZ_IEEE 0x40 |
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| 313 | #define MD2_MANCH 0x00 |
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| 314 | #define MD2_FM1 0x20 |
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| 315 | #define MD2_FM0 0x40 |
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| 316 | #define MD2_FM 0x80 |
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| 317 | |
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| 318 | #define CTL_RTS 0x01 |
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| 319 | #define CTL_DTR 0x02 |
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| 320 | #define CTL_SYN 0x04 |
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| 321 | #define CTL_IDLC 0x10 |
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| 322 | #define CTL_UDRNC 0x20 |
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| 323 | #define CTL_URSKP 0x40 |
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| 324 | #define CTL_URCT 0x80 |
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| 325 | |
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| 326 | #define CTL_NORTS 0x01 |
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| 327 | #define CTL_NODTR 0x02 |
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| 328 | #define CTL_IDLE 0x10 |
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| 329 | |
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| 330 | #define RXS_BR0 0x01 |
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| 331 | #define RXS_BR1 0x02 |
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| 332 | #define RXS_BR2 0x04 |
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| 333 | #define RXS_BR3 0x08 |
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| 334 | #define RXS_ECLK 0x00 |
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| 335 | #define RXS_ECLK_NS 0x20 |
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| 336 | #define RXS_IBRG 0x40 |
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| 337 | #define RXS_PLL1 0x50 |
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| 338 | #define RXS_PLL2 0x60 |
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| 339 | #define RXS_PLL3 0x70 |
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| 340 | #define RXS_DRTXC 0x80 |
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| 341 | |
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| 342 | #define TXS_BR0 0x01 |
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| 343 | #define TXS_BR1 0x02 |
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| 344 | #define TXS_BR2 0x04 |
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| 345 | #define TXS_BR3 0x08 |
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| 346 | #define TXS_ECLK 0x00 |
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| 347 | #define TXS_IBRG 0x40 |
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| 348 | #define TXS_RCLK 0x60 |
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| 349 | #define TXS_DTRXC 0x80 |
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| 350 | |
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| 351 | #define EXS_RES0 0x01 |
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| 352 | #define EXS_RES1 0x02 |
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| 353 | #define EXS_RES2 0x04 |
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| 354 | #define EXS_TES0 0x10 |
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| 355 | #define EXS_TES1 0x20 |
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| 356 | #define EXS_TES2 0x40 |
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| 357 | |
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| 358 | #define CLK_BRG_MASK 0x0F |
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| 359 | #define CLK_PIN_OUT 0x80 |
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| 360 | #define CLK_LINE 0x00 /* clock line input */ |
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| 361 | #define CLK_BRG 0x40 /* internal baud rate generator */ |
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| 362 | #define CLK_TX_RXCLK 0x60 /* TX clock from RX clock */ |
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| 363 | |
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| 364 | #define CMD_RX_RST 0x11 |
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| 365 | #define CMD_RX_ENA 0x12 |
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| 366 | #define CMD_RX_DIS 0x13 |
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| 367 | #define CMD_RX_CRC_INIT 0x14 |
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| 368 | #define CMD_RX_MSG_REJ 0x15 |
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| 369 | #define CMD_RX_MP_SRCH 0x16 |
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| 370 | #define CMD_RX_CRC_EXC 0x17 |
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| 371 | #define CMD_RX_CRC_FRC 0x18 |
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| 372 | #define CMD_TX_RST 0x01 |
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| 373 | #define CMD_TX_ENA 0x02 |
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| 374 | #define CMD_TX_DISA 0x03 |
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| 375 | #define CMD_TX_CRC_INIT 0x04 |
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| 376 | #define CMD_TX_CRC_EXC 0x05 |
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| 377 | #define CMD_TX_EOM 0x06 |
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| 378 | #define CMD_TX_ABORT 0x07 |
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| 379 | #define CMD_TX_MP_ON 0x08 |
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| 380 | #define CMD_TX_BUF_CLR 0x09 |
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| 381 | #define CMD_TX_DISB 0x0b |
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| 382 | #define CMD_CH_RST 0x21 |
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| 383 | #define CMD_SRCH_MODE 0x31 |
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| 384 | #define CMD_NOP 0x00 |
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| 385 | |
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| 386 | #define CMD_RESET 0x21 |
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| 387 | #define CMD_TX_ENABLE 0x02 |
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| 388 | #define CMD_RX_ENABLE 0x12 |
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| 389 | |
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| 390 | #define ST0_RXRDY 0x01 |
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| 391 | #define ST0_TXRDY 0x02 |
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| 392 | #define ST0_RXINTB 0x20 |
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| 393 | #define ST0_RXINTA 0x40 |
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| 394 | #define ST0_TXINT 0x80 |
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| 395 | |
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| 396 | #define ST1_IDLE 0x01 |
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| 397 | #define ST1_ABORT 0x02 |
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| 398 | #define ST1_CDCD 0x04 |
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| 399 | #define ST1_CCTS 0x08 |
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| 400 | #define ST1_SYN_FLAG 0x10 |
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| 401 | #define ST1_CLMD 0x20 |
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| 402 | #define ST1_TXIDLE 0x40 |
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| 403 | #define ST1_UDRN 0x80 |
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| 404 | |
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| 405 | #define ST2_CRCE 0x04 |
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| 406 | #define ST2_ONRN 0x08 |
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| 407 | #define ST2_RBIT 0x10 |
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| 408 | #define ST2_ABORT 0x20 |
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| 409 | #define ST2_SHORT 0x40 |
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| 410 | #define ST2_EOM 0x80 |
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| 411 | |
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| 412 | #define ST3_RX_ENA 0x01 |
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| 413 | #define ST3_TX_ENA 0x02 |
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| 414 | #define ST3_DCD 0x04 |
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| 415 | #define ST3_CTS 0x08 |
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| 416 | #define ST3_SRCH_MODE 0x10 |
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| 417 | #define ST3_SLOOP 0x20 |
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| 418 | #define ST3_GPI 0x80 |
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| 419 | |
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| 420 | #define ST4_RDNR 0x01 |
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| 421 | #define ST4_RDCR 0x02 |
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| 422 | #define ST4_TDNR 0x04 |
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| 423 | #define ST4_TDCR 0x08 |
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| 424 | #define ST4_OCLM 0x20 |
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| 425 | #define ST4_CFT 0x40 |
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| 426 | #define ST4_CGPI 0x80 |
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| 427 | |
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| 428 | #define FST_CRCEF 0x04 |
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| 429 | #define FST_OVRNF 0x08 |
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| 430 | #define FST_RBIF 0x10 |
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| 431 | #define FST_ABTF 0x20 |
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| 432 | #define FST_SHRTF 0x40 |
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| 433 | #define FST_EOMF 0x80 |
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| 434 | |
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| 435 | #define IE0_RXRDY 0x01 |
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| 436 | #define IE0_TXRDY 0x02 |
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| 437 | #define IE0_RXINTB 0x20 |
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| 438 | #define IE0_RXINTA 0x40 |
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| 439 | #define IE0_TXINT 0x80 |
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| 440 | #define IE0_UDRN 0x00008000 /* TX underrun MSCI interrupt enable */ |
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| 441 | #define IE0_CDCD 0x00000400 /* CD level change interrupt enable */ |
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| 442 | |
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| 443 | #define IE1_IDLD 0x01 |
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| 444 | #define IE1_ABTD 0x02 |
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| 445 | #define IE1_CDCD 0x04 |
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| 446 | #define IE1_CCTS 0x08 |
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| 447 | #define IE1_SYNCD 0x10 |
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| 448 | #define IE1_CLMD 0x20 |
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| 449 | #define IE1_IDL 0x40 |
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| 450 | #define IE1_UDRN 0x80 |
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| 451 | |
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| 452 | #define IE2_CRCE 0x04 |
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| 453 | #define IE2_OVRN 0x08 |
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| 454 | #define IE2_RBIT 0x10 |
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| 455 | #define IE2_ABT 0x20 |
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| 456 | #define IE2_SHRT 0x40 |
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| 457 | #define IE2_EOM 0x80 |
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| 458 | |
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| 459 | #define IE4_RDNR 0x01 |
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| 460 | #define IE4_RDCR 0x02 |
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| 461 | #define IE4_TDNR 0x04 |
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| 462 | #define IE4_TDCR 0x08 |
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| 463 | #define IE4_OCLM 0x20 |
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| 464 | #define IE4_CFT 0x40 |
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| 465 | #define IE4_CGPI 0x80 |
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| 466 | |
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| 467 | #define FIE_CRCEF 0x04 |
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| 468 | #define FIE_OVRNF 0x08 |
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| 469 | #define FIE_RBIF 0x10 |
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| 470 | #define FIE_ABTF 0x20 |
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| 471 | #define FIE_SHRTF 0x40 |
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| 472 | #define FIE_EOMF 0x80 |
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| 473 | |
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| 474 | #define DSR_DWE 0x01 |
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| 475 | #define DSR_DE 0x02 |
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| 476 | #define DSR_REF 0x04 |
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| 477 | #define DSR_UDRF 0x04 |
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| 478 | #define DSR_COA 0x08 |
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| 479 | #define DSR_COF 0x10 |
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| 480 | #define DSR_BOF 0x20 |
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| 481 | #define DSR_EOM 0x40 |
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| 482 | #define DSR_EOT 0x80 |
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| 483 | |
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| 484 | #define DIR_REF 0x04 |
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| 485 | #define DIR_UDRF 0x04 |
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| 486 | #define DIR_COA 0x08 |
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| 487 | #define DIR_COF 0x10 |
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| 488 | #define DIR_BOF 0x20 |
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| 489 | #define DIR_EOM 0x40 |
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| 490 | #define DIR_EOT 0x80 |
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| 491 | |
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| 492 | #define DIR_REFE 0x04 |
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| 493 | #define DIR_UDRFE 0x04 |
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| 494 | #define DIR_COAE 0x08 |
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| 495 | #define DIR_COFE 0x10 |
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| 496 | #define DIR_BOFE 0x20 |
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| 497 | #define DIR_EOME 0x40 |
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| 498 | #define DIR_EOTE 0x80 |
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| 499 | |
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| 500 | #define DMR_CNTE 0x02 |
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| 501 | #define DMR_NF 0x04 |
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| 502 | #define DMR_SEOME 0x08 |
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| 503 | #define DMR_TMOD 0x10 |
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| 504 | |
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| 505 | #define DMER_DME 0x80 /* DMA Master Enable */ |
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| 506 | |
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| 507 | #define DCR_SW_ABT 0x01 |
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| 508 | #define DCR_FCT_CLR 0x02 |
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| 509 | |
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| 510 | #define DCR_ABORT 0x01 |
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| 511 | #define DCR_CLEAR_EOF 0x02 |
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| 512 | |
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| 513 | #define PCR_COTE 0x80 |
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| 514 | #define PCR_PR0 0x01 |
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| 515 | #define PCR_PR1 0x02 |
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| 516 | #define PCR_PR2 0x04 |
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| 517 | #define PCR_CCC 0x08 |
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| 518 | #define PCR_BRC 0x10 |
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| 519 | #define PCR_OSB 0x40 |
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| 520 | #define PCR_BURST 0x80 |
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| 521 | |
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| 522 | #endif /* (__HD64572_H) */ |
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| 523 | |
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