1	// SPDX-License-Identifier: GPL-2.0
2	/*
3	* NVM Express device driver
4	* Copyright (c) 2011-2014, Intel Corporation.
5	*/
6
7	#include <linux/acpi.h>
8	#include <linux/async.h>
9	#include <linux/blkdev.h>
10	#include <linux/blk-mq.h>
11	#include <linux/blk-mq-pci.h>
12	#include <linux/blk-integrity.h>
13	#include <linux/dmi.h>
14	#include <linux/init.h>
15	#include <linux/interrupt.h>
16	#include <linux/io.h>
17	#include <linux/kstrtox.h>
18	#include <linux/memremap.h>
19	#include <linux/mm.h>
20	#include <linux/module.h>
21	#include <linux/mutex.h>
22	#include <linux/once.h>
23	#include <linux/pci.h>
24	#include <linux/suspend.h>
25	#include <linux/t10-pi.h>
26	#include <linux/types.h>
27	#include <linux/io-64-nonatomic-lo-hi.h>
28	#include <linux/io-64-nonatomic-hi-lo.h>
29	#include <linux/sed-opal.h>
30	#include <linux/pci-p2pdma.h>
31
32	#include "trace.h"
33	#include "nvme.h"
34
35	#define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
36	#define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
37
38	#define SGES_PER_PAGE (NVME_CTRL_PAGE_SIZE / sizeof(struct nvme_sgl_desc))
39
40	/*
41	* These can be higher, but we need to ensure that any command doesn't
42	* require an sg allocation that needs more than a page of data.
43	*/
44	#define NVME_MAX_KB_SZ 8192
45	#define NVME_MAX_SEGS 128
46	#define NVME_MAX_NR_ALLOCATIONS 5
47
48	static int use_threaded_interrupts;
49	module_param(use_threaded_interrupts, int, 0444);
50
51	static bool use_cmb_sqes = true;
52	module_param(use_cmb_sqes, bool, 0444);
53	MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
54
55	static unsigned int max_host_mem_size_mb = 128;
56	module_param(max_host_mem_size_mb, uint, 0444);
57	MODULE_PARM_DESC(max_host_mem_size_mb,
58	"Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
59
60	static unsigned int sgl_threshold = SZ_32K;
61	module_param(sgl_threshold, uint, 0644);
62	MODULE_PARM_DESC(sgl_threshold,
63	"Use SGLs when average request segment size is larger or equal to "
64	"this size. Use 0 to disable SGLs.");
65
66	#define NVME_PCI_MIN_QUEUE_SIZE 2
67	#define NVME_PCI_MAX_QUEUE_SIZE 4095
68	static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
69	static const struct kernel_param_ops io_queue_depth_ops = {
70	.set = io_queue_depth_set,
71	.get = param_get_uint,
72	};
73
74	static unsigned int io_queue_depth = 1024;
75	module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
76	MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096");
77
78	static int io_queue_count_set(const char *val, const struct kernel_param *kp)
79	{
80	unsigned int n;
81	int ret;
82
83	ret = kstrtouint(s: val, base: 10, res: &n);
84	if (ret != 0 || n > num_possible_cpus())
85	return -EINVAL;
86	return param_set_uint(val, kp);
87	}
88
89	static const struct kernel_param_ops io_queue_count_ops = {
90	.set = io_queue_count_set,
91	.get = param_get_uint,
92	};
93
94	static unsigned int write_queues;
95	module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
96	MODULE_PARM_DESC(write_queues,
97	"Number of queues to use for writes. If not set, reads and writes "
98	"will share a queue set.");
99
100	static unsigned int poll_queues;
101	module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
102	MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
103
104	static bool noacpi;
105	module_param(noacpi, bool, 0444);
106	MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
107
108	struct nvme_dev;
109	struct nvme_queue;
110
111	static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
112	static void nvme_delete_io_queues(struct nvme_dev *dev);
113	static void nvme_update_attrs(struct nvme_dev *dev);
114
115	/*
116	* Represents an NVM Express device. Each nvme_dev is a PCI function.
117	*/
118	struct nvme_dev {
119	struct nvme_queue *queues;
120	struct blk_mq_tag_set tagset;
121	struct blk_mq_tag_set admin_tagset;
122	u32 __iomem *dbs;
123	struct device *dev;
124	struct dma_pool *prp_page_pool;
125	struct dma_pool *prp_small_pool;
126	unsigned online_queues;
127	unsigned max_qid;
128	unsigned io_queues[HCTX_MAX_TYPES];
129	unsigned int num_vecs;
130	u32 q_depth;
131	int io_sqes;
132	u32 db_stride;
133	void __iomem *bar;
134	unsigned long bar_mapped_size;
135	struct mutex shutdown_lock;
136	bool subsystem;
137	u64 cmb_size;
138	bool cmb_use_sqes;
139	u32 cmbsz;
140	u32 cmbloc;
141	struct nvme_ctrl ctrl;
142	u32 last_ps;
143	bool hmb;
144
145	mempool_t *iod_mempool;
146
147	/* shadow doorbell buffer support: */
148	__le32 *dbbuf_dbs;
149	dma_addr_t dbbuf_dbs_dma_addr;
150	__le32 *dbbuf_eis;
151	dma_addr_t dbbuf_eis_dma_addr;
152
153	/* host memory buffer support: */
154	u64 host_mem_size;
155	u32 nr_host_mem_descs;
156	dma_addr_t host_mem_descs_dma;
157	struct nvme_host_mem_buf_desc *host_mem_descs;
158	void **host_mem_desc_bufs;
159	unsigned int nr_allocated_queues;
160	unsigned int nr_write_queues;
161	unsigned int nr_poll_queues;
162	};
163
164	static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
165	{
166	return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE,
167	NVME_PCI_MAX_QUEUE_SIZE);
168	}
169
170	static inline unsigned int sq_idx(unsigned int qid, u32 stride)
171	{
172	return qid * 2 * stride;
173	}
174
175	static inline unsigned int cq_idx(unsigned int qid, u32 stride)
176	{
177	return (qid * 2 + 1) * stride;
178	}
179
180	static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
181	{
182	return container_of(ctrl, struct nvme_dev, ctrl);
183	}
184
185	/*
186	* An NVM Express queue. Each device has at least two (one for admin
187	* commands and one for I/O commands).
188	*/
189	struct nvme_queue {
190	struct nvme_dev *dev;
191	spinlock_t sq_lock;
192	void *sq_cmds;
193	/* only used for poll queues: */
194	spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
195	struct nvme_completion *cqes;
196	dma_addr_t sq_dma_addr;
197	dma_addr_t cq_dma_addr;
198	u32 __iomem *q_db;
199	u32 q_depth;
200	u16 cq_vector;
201	u16 sq_tail;
202	u16 last_sq_tail;
203	u16 cq_head;
204	u16 qid;
205	u8 cq_phase;
206	u8 sqes;
207	unsigned long flags;
208	#define NVMEQ_ENABLED 0
209	#define NVMEQ_SQ_CMB 1
210	#define NVMEQ_DELETE_ERROR 2
211	#define NVMEQ_POLLED 3
212	__le32 *dbbuf_sq_db;
213	__le32 *dbbuf_cq_db;
214	__le32 *dbbuf_sq_ei;
215	__le32 *dbbuf_cq_ei;
216	struct completion delete_done;
217	};
218
219	union nvme_descriptor {
220	struct nvme_sgl_desc *sg_list;
221	__le64 *prp_list;
222	};
223
224	/*
225	* The nvme_iod describes the data in an I/O.
226	*
227	* The sg pointer contains the list of PRP/SGL chunk allocations in addition
228	* to the actual struct scatterlist.
229	*/
230	struct nvme_iod {
231	struct nvme_request req;
232	struct nvme_command cmd;
233	bool aborted;
234	s8 nr_allocations; /* PRP list pool allocations. 0 means small
235	pool in use */
236	unsigned int dma_len; /* length of single DMA segment mapping */
237	dma_addr_t first_dma;
238	dma_addr_t meta_dma;
239	struct sg_table sgt;
240	union nvme_descriptor list[NVME_MAX_NR_ALLOCATIONS];
241	};
242
243	static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
244	{
245	return dev->nr_allocated_queues * 8 * dev->db_stride;
246	}
247
248	static void nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
249	{
250	unsigned int mem_size = nvme_dbbuf_size(dev);
251
252	if (!(dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP))
253	return;
254
255	if (dev->dbbuf_dbs) {
256	/*
257	* Clear the dbbuf memory so the driver doesn't observe stale
258	* values from the previous instantiation.
259	*/
260	memset(dev->dbbuf_dbs, 0, mem_size);
261	memset(dev->dbbuf_eis, 0, mem_size);
262	return;
263	}
264
265	dev->dbbuf_dbs = dma_alloc_coherent(dev: dev->dev, size: mem_size,
266	dma_handle: &dev->dbbuf_dbs_dma_addr,
267	GFP_KERNEL);
268	if (!dev->dbbuf_dbs)
269	goto fail;
270	dev->dbbuf_eis = dma_alloc_coherent(dev: dev->dev, size: mem_size,
271	dma_handle: &dev->dbbuf_eis_dma_addr,
272	GFP_KERNEL);
273	if (!dev->dbbuf_eis)
274	goto fail_free_dbbuf_dbs;
275	return;
276
277	fail_free_dbbuf_dbs:
278	dma_free_coherent(dev: dev->dev, size: mem_size, cpu_addr: dev->dbbuf_dbs,
279	dma_handle: dev->dbbuf_dbs_dma_addr);
280	dev->dbbuf_dbs = NULL;
281	fail:
282	dev_warn(dev->dev, "unable to allocate dma for dbbuf\n");
283	}
284
285	static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
286	{
287	unsigned int mem_size = nvme_dbbuf_size(dev);
288
289	if (dev->dbbuf_dbs) {
290	dma_free_coherent(dev: dev->dev, size: mem_size,
291	cpu_addr: dev->dbbuf_dbs, dma_handle: dev->dbbuf_dbs_dma_addr);
292	dev->dbbuf_dbs = NULL;
293	}
294	if (dev->dbbuf_eis) {
295	dma_free_coherent(dev: dev->dev, size: mem_size,
296	cpu_addr: dev->dbbuf_eis, dma_handle: dev->dbbuf_eis_dma_addr);
297	dev->dbbuf_eis = NULL;
298	}
299	}
300
301	static void nvme_dbbuf_init(struct nvme_dev *dev,
302	struct nvme_queue *nvmeq, int qid)
303	{
304	if (!dev->dbbuf_dbs || !qid)
305	return;
306
307	nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, stride: dev->db_stride)];
308	nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, stride: dev->db_stride)];
309	nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, stride: dev->db_stride)];
310	nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, stride: dev->db_stride)];
311	}
312
313	static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
314	{
315	if (!nvmeq->qid)
316	return;
317
318	nvmeq->dbbuf_sq_db = NULL;
319	nvmeq->dbbuf_cq_db = NULL;
320	nvmeq->dbbuf_sq_ei = NULL;
321	nvmeq->dbbuf_cq_ei = NULL;
322	}
323
324	static void nvme_dbbuf_set(struct nvme_dev *dev)
325	{
326	struct nvme_command c = { };
327	unsigned int i;
328
329	if (!dev->dbbuf_dbs)
330	return;
331
332	c.dbbuf.opcode = nvme_admin_dbbuf;
333	c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
334	c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
335
336	if (nvme_submit_sync_cmd(q: dev->ctrl.admin_q, cmd: &c, NULL, bufflen: 0)) {
337	dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
338	/* Free memory and continue on */
339	nvme_dbbuf_dma_free(dev);
340
341	for (i = 1; i <= dev->online_queues; i++)
342	nvme_dbbuf_free(nvmeq: &dev->queues[i]);
343	}
344	}
345
346	static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
347	{
348	return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
349	}
350
351	/* Update dbbuf and return true if an MMIO is required */
352	static bool nvme_dbbuf_update_and_check_event(u16 value, __le32 *dbbuf_db,
353	volatile __le32 *dbbuf_ei)
354	{
355	if (dbbuf_db) {
356	u16 old_value, event_idx;
357
358	/*
359	* Ensure that the queue is written before updating
360	* the doorbell in memory
361	*/
362	wmb();
363
364	old_value = le32_to_cpu(*dbbuf_db);
365	*dbbuf_db = cpu_to_le32(value);
366
367	/*
368	* Ensure that the doorbell is updated before reading the event
369	* index from memory. The controller needs to provide similar
370	* ordering to ensure the envent index is updated before reading
371	* the doorbell.
372	*/
373	mb();
374
375	event_idx = le32_to_cpu(*dbbuf_ei);
376	if (!nvme_dbbuf_need_event(event_idx, new_idx: value, old: old_value))
377	return false;
378	}
379
380	return true;
381	}
382
383	/*
384	* Will slightly overestimate the number of pages needed. This is OK
385	* as it only leads to a small amount of wasted memory for the lifetime of
386	* the I/O.
387	*/
388	static int nvme_pci_npages_prp(void)
389	{
390	unsigned max_bytes = (NVME_MAX_KB_SZ * 1024) + NVME_CTRL_PAGE_SIZE;
391	unsigned nprps = DIV_ROUND_UP(max_bytes, NVME_CTRL_PAGE_SIZE);
392	return DIV_ROUND_UP(8 * nprps, NVME_CTRL_PAGE_SIZE - 8);
393	}
394
395	static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
396	unsigned int hctx_idx)
397	{
398	struct nvme_dev *dev = to_nvme_dev(ctrl: data);
399	struct nvme_queue *nvmeq = &dev->queues[0];
400
401	WARN_ON(hctx_idx != 0);
402	WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
403
404	hctx->driver_data = nvmeq;
405	return 0;
406	}
407
408	static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
409	unsigned int hctx_idx)
410	{
411	struct nvme_dev *dev = to_nvme_dev(ctrl: data);
412	struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
413
414	WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
415	hctx->driver_data = nvmeq;
416	return 0;
417	}
418
419	static int nvme_pci_init_request(struct blk_mq_tag_set *set,
420	struct request *req, unsigned int hctx_idx,
421	unsigned int numa_node)
422	{
423	struct nvme_iod *iod = blk_mq_rq_to_pdu(rq: req);
424
425	nvme_req(req)->ctrl = set->driver_data;
426	nvme_req(req)->cmd = &iod->cmd;
427	return 0;
428	}
429
430	static int queue_irq_offset(struct nvme_dev *dev)
431	{
432	/* if we have more than 1 vec, admin queue offsets us by 1 */
433	if (dev->num_vecs > 1)
434	return 1;
435
436	return 0;
437	}
438
439	static void nvme_pci_map_queues(struct blk_mq_tag_set *set)
440	{
441	struct nvme_dev *dev = to_nvme_dev(ctrl: set->driver_data);
442	int i, qoff, offset;
443
444	offset = queue_irq_offset(dev);
445	for (i = 0, qoff = 0; i < set->nr_maps; i++) {
446	struct blk_mq_queue_map *map = &set->map[i];
447
448	map->nr_queues = dev->io_queues[i];
449	if (!map->nr_queues) {
450	BUG_ON(i == HCTX_TYPE_DEFAULT);
451	continue;
452	}
453
454	/*
455	* The poll queue(s) doesn't have an IRQ (and hence IRQ
456	* affinity), so use the regular blk-mq cpu mapping
457	*/
458	map->queue_offset = qoff;
459	if (i != HCTX_TYPE_POLL && offset)
460	blk_mq_pci_map_queues(qmap: map, to_pci_dev(dev->dev), offset);
461	else
462	blk_mq_map_queues(qmap: map);
463	qoff += map->nr_queues;
464	offset += map->nr_queues;
465	}
466	}
467
468	/*
469	* Write sq tail if we are asked to, or if the next command would wrap.
470	*/
471	static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
472	{
473	if (!write_sq) {
474	u16 next_tail = nvmeq->sq_tail + 1;
475
476	if (next_tail == nvmeq->q_depth)
477	next_tail = 0;
478	if (next_tail != nvmeq->last_sq_tail)
479	return;
480	}
481
482	if (nvme_dbbuf_update_and_check_event(value: nvmeq->sq_tail,
483	dbbuf_db: nvmeq->dbbuf_sq_db, dbbuf_ei: nvmeq->dbbuf_sq_ei))
484	writel(val: nvmeq->sq_tail, addr: nvmeq->q_db);
485	nvmeq->last_sq_tail = nvmeq->sq_tail;
486	}
487
488	static inline void nvme_sq_copy_cmd(struct nvme_queue *nvmeq,
489	struct nvme_command *cmd)
490	{
491	memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
492	absolute_pointer(cmd), sizeof(*cmd));
493	if (++nvmeq->sq_tail == nvmeq->q_depth)
494	nvmeq->sq_tail = 0;
495	}
496
497	static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
498	{
499	struct nvme_queue *nvmeq = hctx->driver_data;
500
501	spin_lock(lock: &nvmeq->sq_lock);
502	if (nvmeq->sq_tail != nvmeq->last_sq_tail)
503	nvme_write_sq_db(nvmeq, write_sq: true);
504	spin_unlock(lock: &nvmeq->sq_lock);
505	}
506
507	static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req,
508	int nseg)
509	{
510	struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
511	unsigned int avg_seg_size;
512
513	avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
514
515	if (!nvme_ctrl_sgl_supported(ctrl: &dev->ctrl))
516	return false;
517	if (!nvmeq->qid)
518	return false;
519	if (!sgl_threshold || avg_seg_size < sgl_threshold)
520	return false;
521	return true;
522	}
523
524	static void nvme_free_prps(struct nvme_dev *dev, struct request *req)
525	{
526	const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
527	struct nvme_iod *iod = blk_mq_rq_to_pdu(rq: req);
528	dma_addr_t dma_addr = iod->first_dma;
529	int i;
530
531	for (i = 0; i < iod->nr_allocations; i++) {
532	__le64 *prp_list = iod->list[i].prp_list;
533	dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]);
534
535	dma_pool_free(pool: dev->prp_page_pool, vaddr: prp_list, addr: dma_addr);
536	dma_addr = next_dma_addr;
537	}
538	}
539
540	static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
541	{
542	struct nvme_iod *iod = blk_mq_rq_to_pdu(rq: req);
543
544	if (iod->dma_len) {
545	dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len,
546	rq_dma_dir(req));
547	return;
548	}
549
550	WARN_ON_ONCE(!iod->sgt.nents);
551
552	dma_unmap_sgtable(dev: dev->dev, sgt: &iod->sgt, rq_dma_dir(req), attrs: 0);
553
554	if (iod->nr_allocations == 0)
555	dma_pool_free(pool: dev->prp_small_pool, vaddr: iod->list[0].sg_list,
556	addr: iod->first_dma);
557	else if (iod->nr_allocations == 1)
558	dma_pool_free(pool: dev->prp_page_pool, vaddr: iod->list[0].sg_list,
559	addr: iod->first_dma);
560	else
561	nvme_free_prps(dev, req);
562	mempool_free(element: iod->sgt.sgl, pool: dev->iod_mempool);
563	}
564
565	static void nvme_print_sgl(struct scatterlist *sgl, int nents)
566	{
567	int i;
568	struct scatterlist *sg;
569
570	for_each_sg(sgl, sg, nents, i) {
571	dma_addr_t phys = sg_phys(sg);
572	pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
573	"dma_address:%pad dma_length:%d\n",
574	i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
575	sg_dma_len(sg));
576	}
577	}
578
579	static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
580	struct request *req, struct nvme_rw_command *cmnd)
581	{
582	struct nvme_iod *iod = blk_mq_rq_to_pdu(rq: req);
583	struct dma_pool *pool;
584	int length = blk_rq_payload_bytes(rq: req);
585	struct scatterlist *sg = iod->sgt.sgl;
586	int dma_len = sg_dma_len(sg);
587	u64 dma_addr = sg_dma_address(sg);
588	int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1);
589	__le64 *prp_list;
590	dma_addr_t prp_dma;
591	int nprps, i;
592
593	length -= (NVME_CTRL_PAGE_SIZE - offset);
594	if (length <= 0) {
595	iod->first_dma = 0;
596	goto done;
597	}
598
599	dma_len -= (NVME_CTRL_PAGE_SIZE - offset);
600	if (dma_len) {
601	dma_addr += (NVME_CTRL_PAGE_SIZE - offset);
602	} else {
603	sg = sg_next(sg);
604	dma_addr = sg_dma_address(sg);
605	dma_len = sg_dma_len(sg);
606	}
607
608	if (length <= NVME_CTRL_PAGE_SIZE) {
609	iod->first_dma = dma_addr;
610	goto done;
611	}
612
613	nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE);
614	if (nprps <= (256 / 8)) {
615	pool = dev->prp_small_pool;
616	iod->nr_allocations = 0;
617	} else {
618	pool = dev->prp_page_pool;
619	iod->nr_allocations = 1;
620	}
621
622	prp_list = dma_pool_alloc(pool, GFP_ATOMIC, handle: &prp_dma);
623	if (!prp_list) {
624	iod->nr_allocations = -1;
625	return BLK_STS_RESOURCE;
626	}
627	iod->list[0].prp_list = prp_list;
628	iod->first_dma = prp_dma;
629	i = 0;
630	for (;;) {
631	if (i == NVME_CTRL_PAGE_SIZE >> 3) {
632	__le64 *old_prp_list = prp_list;
633	prp_list = dma_pool_alloc(pool, GFP_ATOMIC, handle: &prp_dma);
634	if (!prp_list)
635	goto free_prps;
636	iod->list[iod->nr_allocations++].prp_list = prp_list;
637	prp_list[0] = old_prp_list[i - 1];
638	old_prp_list[i - 1] = cpu_to_le64(prp_dma);
639	i = 1;
640	}
641	prp_list[i++] = cpu_to_le64(dma_addr);
642	dma_len -= NVME_CTRL_PAGE_SIZE;
643	dma_addr += NVME_CTRL_PAGE_SIZE;
644	length -= NVME_CTRL_PAGE_SIZE;
645	if (length <= 0)
646	break;
647	if (dma_len > 0)
648	continue;
649	if (unlikely(dma_len < 0))
650	goto bad_sgl;
651	sg = sg_next(sg);
652	dma_addr = sg_dma_address(sg);
653	dma_len = sg_dma_len(sg);
654	}
655	done:
656	cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sgt.sgl));
657	cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
658	return BLK_STS_OK;
659	free_prps:
660	nvme_free_prps(dev, req);
661	return BLK_STS_RESOURCE;
662	bad_sgl:
663	WARN(DO_ONCE(nvme_print_sgl, iod->sgt.sgl, iod->sgt.nents),
664	"Invalid SGL for payload:%d nents:%d\n",
665	blk_rq_payload_bytes(req), iod->sgt.nents);
666	return BLK_STS_IOERR;
667	}
668
669	static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
670	struct scatterlist *sg)
671	{
672	sge->addr = cpu_to_le64(sg_dma_address(sg));
673	sge->length = cpu_to_le32(sg_dma_len(sg));
674	sge->type = NVME_SGL_FMT_DATA_DESC << 4;
675	}
676
677	static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
678	dma_addr_t dma_addr, int entries)
679	{
680	sge->addr = cpu_to_le64(dma_addr);
681	sge->length = cpu_to_le32(entries * sizeof(*sge));
682	sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
683	}
684
685	static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
686	struct request *req, struct nvme_rw_command *cmd)
687	{
688	struct nvme_iod *iod = blk_mq_rq_to_pdu(rq: req);
689	struct dma_pool *pool;
690	struct nvme_sgl_desc *sg_list;
691	struct scatterlist *sg = iod->sgt.sgl;
692	unsigned int entries = iod->sgt.nents;
693	dma_addr_t sgl_dma;
694	int i = 0;
695
696	/* setting the transfer type as SGL */
697	cmd->flags = NVME_CMD_SGL_METABUF;
698
699	if (entries == 1) {
700	nvme_pci_sgl_set_data(sge: &cmd->dptr.sgl, sg);
701	return BLK_STS_OK;
702	}
703
704	if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
705	pool = dev->prp_small_pool;
706	iod->nr_allocations = 0;
707	} else {
708	pool = dev->prp_page_pool;
709	iod->nr_allocations = 1;
710	}
711
712	sg_list = dma_pool_alloc(pool, GFP_ATOMIC, handle: &sgl_dma);
713	if (!sg_list) {
714	iod->nr_allocations = -1;
715	return BLK_STS_RESOURCE;
716	}
717
718	iod->list[0].sg_list = sg_list;
719	iod->first_dma = sgl_dma;
720
721	nvme_pci_sgl_set_seg(sge: &cmd->dptr.sgl, dma_addr: sgl_dma, entries);
722	do {
723	nvme_pci_sgl_set_data(sge: &sg_list[i++], sg);
724	sg = sg_next(sg);
725	} while (--entries > 0);
726
727	return BLK_STS_OK;
728	}
729
730	static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
731	struct request *req, struct nvme_rw_command *cmnd,
732	struct bio_vec *bv)
733	{
734	struct nvme_iod *iod = blk_mq_rq_to_pdu(rq: req);
735	unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
736	unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset;
737
738	iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
739	if (dma_mapping_error(dev: dev->dev, dma_addr: iod->first_dma))
740	return BLK_STS_RESOURCE;
741	iod->dma_len = bv->bv_len;
742
743	cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
744	if (bv->bv_len > first_prp_len)
745	cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
746	else
747	cmnd->dptr.prp2 = 0;
748	return BLK_STS_OK;
749	}
750
751	static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
752	struct request *req, struct nvme_rw_command *cmnd,
753	struct bio_vec *bv)
754	{
755	struct nvme_iod *iod = blk_mq_rq_to_pdu(rq: req);
756
757	iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
758	if (dma_mapping_error(dev: dev->dev, dma_addr: iod->first_dma))
759	return BLK_STS_RESOURCE;
760	iod->dma_len = bv->bv_len;
761
762	cmnd->flags = NVME_CMD_SGL_METABUF;
763	cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
764	cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
765	cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
766	return BLK_STS_OK;
767	}
768
769	static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
770	struct nvme_command *cmnd)
771	{
772	struct nvme_iod *iod = blk_mq_rq_to_pdu(rq: req);
773	blk_status_t ret = BLK_STS_RESOURCE;
774	int rc;
775
776	if (blk_rq_nr_phys_segments(rq: req) == 1) {
777	struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
778	struct bio_vec bv = req_bvec(rq: req);
779
780	if (!is_pci_p2pdma_page(page: bv.bv_page)) {
781	if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2)
782	return nvme_setup_prp_simple(dev, req,
783	cmnd: &cmnd->rw, bv: &bv);
784
785	if (nvmeq->qid && sgl_threshold &&
786	nvme_ctrl_sgl_supported(ctrl: &dev->ctrl))
787	return nvme_setup_sgl_simple(dev, req,
788	cmnd: &cmnd->rw, bv: &bv);
789	}
790	}
791
792	iod->dma_len = 0;
793	iod->sgt.sgl = mempool_alloc(pool: dev->iod_mempool, GFP_ATOMIC);
794	if (!iod->sgt.sgl)
795	return BLK_STS_RESOURCE;
796	sg_init_table(iod->sgt.sgl, blk_rq_nr_phys_segments(rq: req));
797	iod->sgt.orig_nents = blk_rq_map_sg(q: req->q, rq: req, sglist: iod->sgt.sgl);
798	if (!iod->sgt.orig_nents)
799	goto out_free_sg;
800
801	rc = dma_map_sgtable(dev: dev->dev, sgt: &iod->sgt, rq_dma_dir(req),
802	DMA_ATTR_NO_WARN);
803	if (rc) {
804	if (rc == -EREMOTEIO)
805	ret = BLK_STS_TARGET;
806	goto out_free_sg;
807	}
808
809	if (nvme_pci_use_sgls(dev, req, nseg: iod->sgt.nents))
810	ret = nvme_pci_setup_sgls(dev, req, cmd: &cmnd->rw);
811	else
812	ret = nvme_pci_setup_prps(dev, req, cmnd: &cmnd->rw);
813	if (ret != BLK_STS_OK)
814	goto out_unmap_sg;
815	return BLK_STS_OK;
816
817	out_unmap_sg:
818	dma_unmap_sgtable(dev: dev->dev, sgt: &iod->sgt, rq_dma_dir(req), attrs: 0);
819	out_free_sg:
820	mempool_free(element: iod->sgt.sgl, pool: dev->iod_mempool);
821	return ret;
822	}
823
824	static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
825	struct nvme_command *cmnd)
826	{
827	struct nvme_iod *iod = blk_mq_rq_to_pdu(rq: req);
828
829	iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
830	rq_dma_dir(req), 0);
831	if (dma_mapping_error(dev: dev->dev, dma_addr: iod->meta_dma))
832	return BLK_STS_IOERR;
833	cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
834	return BLK_STS_OK;
835	}
836
837	static blk_status_t nvme_prep_rq(struct nvme_dev *dev, struct request *req)
838	{
839	struct nvme_iod *iod = blk_mq_rq_to_pdu(rq: req);
840	blk_status_t ret;
841
842	iod->aborted = false;
843	iod->nr_allocations = -1;
844	iod->sgt.nents = 0;
845
846	ret = nvme_setup_cmd(ns: req->q->queuedata, req);
847	if (ret)
848	return ret;
849
850	if (blk_rq_nr_phys_segments(rq: req)) {
851	ret = nvme_map_data(dev, req, cmnd: &iod->cmd);
852	if (ret)
853	goto out_free_cmd;
854	}
855
856	if (blk_integrity_rq(rq: req)) {
857	ret = nvme_map_metadata(dev, req, cmnd: &iod->cmd);
858	if (ret)
859	goto out_unmap_data;
860	}
861
862	nvme_start_request(rq: req);
863	return BLK_STS_OK;
864	out_unmap_data:
865	nvme_unmap_data(dev, req);
866	out_free_cmd:
867	nvme_cleanup_cmd(req);
868	return ret;
869	}
870
871	/*
872	* NOTE: ns is NULL when called on the admin queue.
873	*/
874	static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
875	const struct blk_mq_queue_data *bd)
876	{
877	struct nvme_queue *nvmeq = hctx->driver_data;
878	struct nvme_dev *dev = nvmeq->dev;
879	struct request *req = bd->rq;
880	struct nvme_iod *iod = blk_mq_rq_to_pdu(rq: req);
881	blk_status_t ret;
882
883	/*
884	* We should not need to do this, but we're still using this to
885	* ensure we can drain requests on a dying queue.
886	*/
887	if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
888	return BLK_STS_IOERR;
889
890	if (unlikely(!nvme_check_ready(&dev->ctrl, req, true)))
891	return nvme_fail_nonready_command(ctrl: &dev->ctrl, req);
892
893	ret = nvme_prep_rq(dev, req);
894	if (unlikely(ret))
895	return ret;
896	spin_lock(lock: &nvmeq->sq_lock);
897	nvme_sq_copy_cmd(nvmeq, cmd: &iod->cmd);
898	nvme_write_sq_db(nvmeq, write_sq: bd->last);
899	spin_unlock(lock: &nvmeq->sq_lock);
900	return BLK_STS_OK;
901	}
902
903	static void nvme_submit_cmds(struct nvme_queue *nvmeq, struct request **rqlist)
904	{
905	spin_lock(lock: &nvmeq->sq_lock);
906	while (!rq_list_empty(*rqlist)) {
907	struct request *req = rq_list_pop(rqlist);
908	struct nvme_iod *iod = blk_mq_rq_to_pdu(rq: req);
909
910	nvme_sq_copy_cmd(nvmeq, cmd: &iod->cmd);
911	}
912	nvme_write_sq_db(nvmeq, write_sq: true);
913	spin_unlock(lock: &nvmeq->sq_lock);
914	}
915
916	static bool nvme_prep_rq_batch(struct nvme_queue *nvmeq, struct request *req)
917	{
918	/*
919	* We should not need to do this, but we're still using this to
920	* ensure we can drain requests on a dying queue.
921	*/
922	if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
923	return false;
924	if (unlikely(!nvme_check_ready(&nvmeq->dev->ctrl, req, true)))
925	return false;
926
927	return nvme_prep_rq(dev: nvmeq->dev, req) == BLK_STS_OK;
928	}
929
930	static void nvme_queue_rqs(struct request **rqlist)
931	{
932	struct request *req, *next, *prev = NULL;
933	struct request *requeue_list = NULL;
934
935	rq_list_for_each_safe(rqlist, req, next) {
936	struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
937
938	if (!nvme_prep_rq_batch(nvmeq, req)) {
939	/* detach 'req' and add to remainder list */
940	rq_list_move(src: rqlist, dst: &requeue_list, rq: req, prev);
941
942	req = prev;
943	if (!req)
944	continue;
945	}
946
947	if (!next || req->mq_hctx != next->mq_hctx) {
948	/* detach rest of list, and submit */
949	req->rq_next = NULL;
950	nvme_submit_cmds(nvmeq, rqlist);
951	*rqlist = next;
952	prev = NULL;
953	} else
954	prev = req;
955	}
956
957	*rqlist = requeue_list;
958	}
959
960	static __always_inline void nvme_pci_unmap_rq(struct request *req)
961	{
962	struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
963	struct nvme_dev *dev = nvmeq->dev;
964
965	if (blk_integrity_rq(rq: req)) {
966	struct nvme_iod *iod = blk_mq_rq_to_pdu(rq: req);
967
968	dma_unmap_page(dev->dev, iod->meta_dma,
969	rq_integrity_vec(req)->bv_len, rq_dma_dir(req));
970	}
971
972	if (blk_rq_nr_phys_segments(rq: req))
973	nvme_unmap_data(dev, req);
974	}
975
976	static void nvme_pci_complete_rq(struct request *req)
977	{
978	nvme_pci_unmap_rq(req);
979	nvme_complete_rq(req);
980	}
981
982	static void nvme_pci_complete_batch(struct io_comp_batch *iob)
983	{
984	nvme_complete_batch(iob, fn: nvme_pci_unmap_rq);
985	}
986
987	/* We read the CQE phase first to check if the rest of the entry is valid */
988	static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
989	{
990	struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
991
992	return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
993	}
994
995	static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
996	{
997	u16 head = nvmeq->cq_head;
998
999	if (nvme_dbbuf_update_and_check_event(value: head, dbbuf_db: nvmeq->dbbuf_cq_db,
1000	dbbuf_ei: nvmeq->dbbuf_cq_ei))
1001	writel(val: head, addr: nvmeq->q_db + nvmeq->dev->db_stride);
1002	}
1003
1004	static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
1005	{
1006	if (!nvmeq->qid)
1007	return nvmeq->dev->admin_tagset.tags[0];
1008	return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
1009	}
1010
1011	static inline void nvme_handle_cqe(struct nvme_queue *nvmeq,
1012	struct io_comp_batch *iob, u16 idx)
1013	{
1014	struct nvme_completion *cqe = &nvmeq->cqes[idx];
1015	__u16 command_id = READ_ONCE(cqe->command_id);
1016	struct request *req;
1017
1018	/*
1019	* AEN requests are special as they don't time out and can
1020	* survive any kind of queue freeze and often don't respond to
1021	* aborts. We don't even bother to allocate a struct request
1022	* for them but rather special case them here.
1023	*/
1024	if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) {
1025	nvme_complete_async_event(ctrl: &nvmeq->dev->ctrl,
1026	status: cqe->status, res: &cqe->result);
1027	return;
1028	}
1029
1030	req = nvme_find_rq(tags: nvme_queue_tagset(nvmeq), command_id);
1031	if (unlikely(!req)) {
1032	dev_warn(nvmeq->dev->ctrl.device,
1033	"invalid id %d completed on queue %d\n",
1034	command_id, le16_to_cpu(cqe->sq_id));
1035	return;
1036	}
1037
1038	trace_nvme_sq(req, sq_head: cqe->sq_head, sq_tail: nvmeq->sq_tail);
1039	if (!nvme_try_complete_req(req, status: cqe->status, result: cqe->result) &&
1040	!blk_mq_add_to_batch(req, iob, ioerror: nvme_req(req)->status,
1041	complete: nvme_pci_complete_batch))
1042	nvme_pci_complete_rq(req);
1043	}
1044
1045	static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1046	{
1047	u32 tmp = nvmeq->cq_head + 1;
1048
1049	if (tmp == nvmeq->q_depth) {
1050	nvmeq->cq_head = 0;
1051	nvmeq->cq_phase ^= 1;
1052	} else {
1053	nvmeq->cq_head = tmp;
1054	}
1055	}
1056
1057	static inline int nvme_poll_cq(struct nvme_queue *nvmeq,
1058	struct io_comp_batch *iob)
1059	{
1060	int found = 0;
1061
1062	while (nvme_cqe_pending(nvmeq)) {
1063	found++;
1064	/*
1065	* load-load control dependency between phase and the rest of
1066	* the cqe requires a full read memory barrier
1067	*/
1068	dma_rmb();
1069	nvme_handle_cqe(nvmeq, iob, idx: nvmeq->cq_head);
1070	nvme_update_cq_head(nvmeq);
1071	}
1072
1073	if (found)
1074	nvme_ring_cq_doorbell(nvmeq);
1075	return found;
1076	}
1077
1078	static irqreturn_t nvme_irq(int irq, void *data)
1079	{
1080	struct nvme_queue *nvmeq = data;
1081	DEFINE_IO_COMP_BATCH(iob);
1082
1083	if (nvme_poll_cq(nvmeq, iob: &iob)) {
1084	if (!rq_list_empty(iob.req_list))
1085	nvme_pci_complete_batch(iob: &iob);
1086	return IRQ_HANDLED;
1087	}
1088	return IRQ_NONE;
1089	}
1090
1091	static irqreturn_t nvme_irq_check(int irq, void *data)
1092	{
1093	struct nvme_queue *nvmeq = data;
1094
1095	if (nvme_cqe_pending(nvmeq))
1096	return IRQ_WAKE_THREAD;
1097	return IRQ_NONE;
1098	}
1099
1100	/*
1101	* Poll for completions for any interrupt driven queue
1102	* Can be called from any context.
1103	*/
1104	static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
1105	{
1106	struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1107
1108	WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
1109
1110	disable_irq(irq: pci_irq_vector(dev: pdev, nr: nvmeq->cq_vector));
1111	nvme_poll_cq(nvmeq, NULL);
1112	enable_irq(irq: pci_irq_vector(dev: pdev, nr: nvmeq->cq_vector));
1113	}
1114
1115	static int nvme_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob)
1116	{
1117	struct nvme_queue *nvmeq = hctx->driver_data;
1118	bool found;
1119
1120	if (!nvme_cqe_pending(nvmeq))
1121	return 0;
1122
1123	spin_lock(lock: &nvmeq->cq_poll_lock);
1124	found = nvme_poll_cq(nvmeq, iob);
1125	spin_unlock(lock: &nvmeq->cq_poll_lock);
1126
1127	return found;
1128	}
1129
1130	static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
1131	{
1132	struct nvme_dev *dev = to_nvme_dev(ctrl);
1133	struct nvme_queue *nvmeq = &dev->queues[0];
1134	struct nvme_command c = { };
1135
1136	c.common.opcode = nvme_admin_async_event;
1137	c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
1138
1139	spin_lock(lock: &nvmeq->sq_lock);
1140	nvme_sq_copy_cmd(nvmeq, cmd: &c);
1141	nvme_write_sq_db(nvmeq, write_sq: true);
1142	spin_unlock(lock: &nvmeq->sq_lock);
1143	}
1144
1145	static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1146	{
1147	struct nvme_command c = { };
1148
1149	c.delete_queue.opcode = opcode;
1150	c.delete_queue.qid = cpu_to_le16(id);
1151
1152	return nvme_submit_sync_cmd(q: dev->ctrl.admin_q, cmd: &c, NULL, bufflen: 0);
1153	}
1154
1155	static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1156	struct nvme_queue *nvmeq, s16 vector)
1157	{
1158	struct nvme_command c = { };
1159	int flags = NVME_QUEUE_PHYS_CONTIG;
1160
1161	if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
1162	flags |= NVME_CQ_IRQ_ENABLED;
1163
1164	/*
1165	* Note: we (ab)use the fact that the prp fields survive if no data
1166	* is attached to the request.
1167	*/
1168	c.create_cq.opcode = nvme_admin_create_cq;
1169	c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1170	c.create_cq.cqid = cpu_to_le16(qid);
1171	c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1172	c.create_cq.cq_flags = cpu_to_le16(flags);
1173	c.create_cq.irq_vector = cpu_to_le16(vector);
1174
1175	return nvme_submit_sync_cmd(q: dev->ctrl.admin_q, cmd: &c, NULL, bufflen: 0);
1176	}
1177
1178	static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1179	struct nvme_queue *nvmeq)
1180	{
1181	struct nvme_ctrl *ctrl = &dev->ctrl;
1182	struct nvme_command c = { };
1183	int flags = NVME_QUEUE_PHYS_CONTIG;
1184
1185	/*
1186	* Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1187	* set. Since URGENT priority is zeroes, it makes all queues
1188	* URGENT.
1189	*/
1190	if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1191	flags |= NVME_SQ_PRIO_MEDIUM;
1192
1193	/*
1194	* Note: we (ab)use the fact that the prp fields survive if no data
1195	* is attached to the request.
1196	*/
1197	c.create_sq.opcode = nvme_admin_create_sq;
1198	c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1199	c.create_sq.sqid = cpu_to_le16(qid);
1200	c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1201	c.create_sq.sq_flags = cpu_to_le16(flags);
1202	c.create_sq.cqid = cpu_to_le16(qid);
1203
1204	return nvme_submit_sync_cmd(q: dev->ctrl.admin_q, cmd: &c, NULL, bufflen: 0);
1205	}
1206
1207	static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1208	{
1209	return adapter_delete_queue(dev, opcode: nvme_admin_delete_cq, id: cqid);
1210	}
1211
1212	static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1213	{
1214	return adapter_delete_queue(dev, opcode: nvme_admin_delete_sq, id: sqid);
1215	}
1216
1217	static enum rq_end_io_ret abort_endio(struct request *req, blk_status_t error)
1218	{
1219	struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
1220
1221	dev_warn(nvmeq->dev->ctrl.device,
1222	"Abort status: 0x%x", nvme_req(req)->status);
1223	atomic_inc(v: &nvmeq->dev->ctrl.abort_limit);
1224	blk_mq_free_request(rq: req);
1225	return RQ_END_IO_NONE;
1226	}
1227
1228	static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1229	{
1230	/* If true, indicates loss of adapter communication, possibly by a
1231	* NVMe Subsystem reset.
1232	*/
1233	bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1234
1235	/* If there is a reset/reinit ongoing, we shouldn't reset again. */
1236	switch (dev->ctrl.state) {
1237	case NVME_CTRL_RESETTING:
1238	case NVME_CTRL_CONNECTING:
1239	return false;
1240	default:
1241	break;
1242	}
1243
1244	/* We shouldn't reset unless the controller is on fatal error state
1245	* _or_ if we lost the communication with it.
1246	*/
1247	if (!(csts & NVME_CSTS_CFS) && !nssro)
1248	return false;
1249
1250	return true;
1251	}
1252
1253	static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1254	{
1255	/* Read a config register to help see what died. */
1256	u16 pci_status;
1257	int result;
1258
1259	result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1260	val: &pci_status);
1261	if (result == PCIBIOS_SUCCESSFUL)
1262	dev_warn(dev->ctrl.device,
1263	"controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1264	csts, pci_status);
1265	else
1266	dev_warn(dev->ctrl.device,
1267	"controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1268	csts, result);
1269
1270	if (csts != ~0)
1271	return;
1272
1273	dev_warn(dev->ctrl.device,
1274	"Does your device have a faulty power saving mode enabled?\n");
1275	dev_warn(dev->ctrl.device,
1276	"Try \"nvme_core.default_ps_max_latency_us=0 pcie_aspm=off\" and report a bug\n");
1277	}
1278
1279	static enum blk_eh_timer_return nvme_timeout(struct request *req)
1280	{
1281	struct nvme_iod *iod = blk_mq_rq_to_pdu(rq: req);
1282	struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
1283	struct nvme_dev *dev = nvmeq->dev;
1284	struct request *abort_req;
1285	struct nvme_command cmd = { };
1286	u32 csts = readl(addr: dev->bar + NVME_REG_CSTS);
1287
1288	/* If PCI error recovery process is happening, we cannot reset or
1289	* the recovery mechanism will surely fail.
1290	*/
1291	mb();
1292	if (pci_channel_offline(to_pci_dev(dev->dev)))
1293	return BLK_EH_RESET_TIMER;
1294
1295	/*
1296	* Reset immediately if the controller is failed
1297	*/
1298	if (nvme_should_reset(dev, csts)) {
1299	nvme_warn_reset(dev, csts);
1300	goto disable;
1301	}
1302
1303	/*
1304	* Did we miss an interrupt?
1305	*/
1306	if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
1307	nvme_poll(hctx: req->mq_hctx, NULL);
1308	else
1309	nvme_poll_irqdisable(nvmeq);
1310
1311	if (blk_mq_rq_state(rq: req) != MQ_RQ_IN_FLIGHT) {
1312	dev_warn(dev->ctrl.device,
1313	"I/O %d QID %d timeout, completion polled\n",
1314	req->tag, nvmeq->qid);
1315	return BLK_EH_DONE;
1316	}
1317
1318	/*
1319	* Shutdown immediately if controller times out while starting. The
1320	* reset work will see the pci device disabled when it gets the forced
1321	* cancellation error. All outstanding requests are completed on
1322	* shutdown, so we return BLK_EH_DONE.
1323	*/
1324	switch (dev->ctrl.state) {
1325	case NVME_CTRL_CONNECTING:
1326	nvme_change_ctrl_state(ctrl: &dev->ctrl, new_state: NVME_CTRL_DELETING);
1327	fallthrough;
1328	case NVME_CTRL_DELETING:
1329	dev_warn_ratelimited(dev->ctrl.device,
1330	"I/O %d QID %d timeout, disable controller\n",
1331	req->tag, nvmeq->qid);
1332	nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1333	nvme_dev_disable(dev, shutdown: true);
1334	return BLK_EH_DONE;
1335	case NVME_CTRL_RESETTING:
1336	return BLK_EH_RESET_TIMER;
1337	default:
1338	break;
1339	}
1340
1341	/*
1342	* Shutdown the controller immediately and schedule a reset if the
1343	* command was already aborted once before and still hasn't been
1344	* returned to the driver, or if this is the admin queue.
1345	*/
1346	if (!nvmeq->qid || iod->aborted) {
1347	dev_warn(dev->ctrl.device,
1348	"I/O %d QID %d timeout, reset controller\n",
1349	req->tag, nvmeq->qid);
1350	nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1351	goto disable;
1352	}
1353
1354	if (atomic_dec_return(v: &dev->ctrl.abort_limit) < 0) {
1355	atomic_inc(v: &dev->ctrl.abort_limit);
1356	return BLK_EH_RESET_TIMER;
1357	}
1358	iod->aborted = true;
1359
1360	cmd.abort.opcode = nvme_admin_abort_cmd;
1361	cmd.abort.cid = nvme_cid(rq: req);
1362	cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1363
1364	dev_warn(nvmeq->dev->ctrl.device,
1365	"I/O %d (%s) QID %d timeout, aborting\n",
1366	req->tag,
1367	nvme_get_opcode_str(nvme_req(req)->cmd->common.opcode),
1368	nvmeq->qid);
1369
1370	abort_req = blk_mq_alloc_request(q: dev->ctrl.admin_q, opf: nvme_req_op(cmd: &cmd),
1371	flags: BLK_MQ_REQ_NOWAIT);
1372	if (IS_ERR(ptr: abort_req)) {
1373	atomic_inc(v: &dev->ctrl.abort_limit);
1374	return BLK_EH_RESET_TIMER;
1375	}
1376	nvme_init_request(req: abort_req, cmd: &cmd);
1377
1378	abort_req->end_io = abort_endio;
1379	abort_req->end_io_data = NULL;
1380	blk_execute_rq_nowait(rq: abort_req, at_head: false);
1381
1382	/*
1383	* The aborted req will be completed on receiving the abort req.
1384	* We enable the timer again. If hit twice, it'll cause a device reset,
1385	* as the device then is in a faulty state.
1386	*/
1387	return BLK_EH_RESET_TIMER;
1388
1389	disable:
1390	if (!nvme_change_ctrl_state(ctrl: &dev->ctrl, new_state: NVME_CTRL_RESETTING))
1391	return BLK_EH_DONE;
1392
1393	nvme_dev_disable(dev, shutdown: false);
1394	if (nvme_try_sched_reset(ctrl: &dev->ctrl))
1395	nvme_unquiesce_io_queues(ctrl: &dev->ctrl);
1396	return BLK_EH_DONE;
1397	}
1398
1399	static void nvme_free_queue(struct nvme_queue *nvmeq)
1400	{
1401	dma_free_coherent(dev: nvmeq->dev->dev, CQ_SIZE(nvmeq),
1402	cpu_addr: (void *)nvmeq->cqes, dma_handle: nvmeq->cq_dma_addr);
1403	if (!nvmeq->sq_cmds)
1404	return;
1405
1406	if (test_and_clear_bit(NVMEQ_SQ_CMB, addr: &nvmeq->flags)) {
1407	pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
1408	addr: nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1409	} else {
1410	dma_free_coherent(dev: nvmeq->dev->dev, SQ_SIZE(nvmeq),
1411	cpu_addr: nvmeq->sq_cmds, dma_handle: nvmeq->sq_dma_addr);
1412	}
1413	}
1414
1415	static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1416	{
1417	int i;
1418
1419	for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1420	dev->ctrl.queue_count--;
1421	nvme_free_queue(nvmeq: &dev->queues[i]);
1422	}
1423	}
1424
1425	static void nvme_suspend_queue(struct nvme_dev *dev, unsigned int qid)
1426	{
1427	struct nvme_queue *nvmeq = &dev->queues[qid];
1428
1429	if (!test_and_clear_bit(NVMEQ_ENABLED, addr: &nvmeq->flags))
1430	return;
1431
1432	/* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
1433	mb();
1434
1435	nvmeq->dev->online_queues--;
1436	if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1437	nvme_quiesce_admin_queue(ctrl: &nvmeq->dev->ctrl);
1438	if (!test_and_clear_bit(NVMEQ_POLLED, addr: &nvmeq->flags))
1439	pci_free_irq(to_pci_dev(dev->dev), nr: nvmeq->cq_vector, dev_id: nvmeq);
1440	}
1441
1442	static void nvme_suspend_io_queues(struct nvme_dev *dev)
1443	{
1444	int i;
1445
1446	for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1447	nvme_suspend_queue(dev, qid: i);
1448	}
1449
1450	/*
1451	* Called only on a device that has been disabled and after all other threads
1452	* that can check this device's completion queues have synced, except
1453	* nvme_poll(). This is the last chance for the driver to see a natural
1454	* completion before nvme_cancel_request() terminates all incomplete requests.
1455	*/
1456	static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1457	{
1458	int i;
1459
1460	for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1461	spin_lock(lock: &dev->queues[i].cq_poll_lock);
1462	nvme_poll_cq(nvmeq: &dev->queues[i], NULL);
1463	spin_unlock(lock: &dev->queues[i].cq_poll_lock);
1464	}
1465	}
1466
1467	static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1468	int entry_size)
1469	{
1470	int q_depth = dev->q_depth;
1471	unsigned q_size_aligned = roundup(q_depth * entry_size,
1472	NVME_CTRL_PAGE_SIZE);
1473
1474	if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1475	u64 mem_per_q = div_u64(dividend: dev->cmb_size, divisor: nr_io_queues);
1476
1477	mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
1478	q_depth = div_u64(dividend: mem_per_q, divisor: entry_size);
1479
1480	/*
1481	* Ensure the reduced q_depth is above some threshold where it
1482	* would be better to map queues in system memory with the
1483	* original depth
1484	*/
1485	if (q_depth < 64)
1486	return -ENOMEM;
1487	}
1488
1489	return q_depth;
1490	}
1491
1492	static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1493	int qid)
1494	{
1495	struct pci_dev *pdev = to_pci_dev(dev->dev);
1496
1497	if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1498	nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
1499	if (nvmeq->sq_cmds) {
1500	nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1501	addr: nvmeq->sq_cmds);
1502	if (nvmeq->sq_dma_addr) {
1503	set_bit(NVMEQ_SQ_CMB, addr: &nvmeq->flags);
1504	return 0;
1505	}
1506
1507	pci_free_p2pmem(pdev, addr: nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1508	}
1509	}
1510
1511	nvmeq->sq_cmds = dma_alloc_coherent(dev: dev->dev, SQ_SIZE(nvmeq),
1512	dma_handle: &nvmeq->sq_dma_addr, GFP_KERNEL);
1513	if (!nvmeq->sq_cmds)
1514	return -ENOMEM;
1515	return 0;
1516	}
1517
1518	static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
1519	{
1520	struct nvme_queue *nvmeq = &dev->queues[qid];
1521
1522	if (dev->ctrl.queue_count > qid)
1523	return 0;
1524
1525	nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
1526	nvmeq->q_depth = depth;
1527	nvmeq->cqes = dma_alloc_coherent(dev: dev->dev, CQ_SIZE(nvmeq),
1528	dma_handle: &nvmeq->cq_dma_addr, GFP_KERNEL);
1529	if (!nvmeq->cqes)
1530	goto free_nvmeq;
1531
1532	if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
1533	goto free_cqdma;
1534
1535	nvmeq->dev = dev;
1536	spin_lock_init(&nvmeq->sq_lock);
1537	spin_lock_init(&nvmeq->cq_poll_lock);
1538	nvmeq->cq_head = 0;
1539	nvmeq->cq_phase = 1;
1540	nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1541	nvmeq->qid = qid;
1542	dev->ctrl.queue_count++;
1543
1544	return 0;
1545
1546	free_cqdma:
1547	dma_free_coherent(dev: dev->dev, CQ_SIZE(nvmeq), cpu_addr: (void *)nvmeq->cqes,
1548	dma_handle: nvmeq->cq_dma_addr);
1549	free_nvmeq:
1550	return -ENOMEM;
1551	}
1552
1553	static int queue_request_irq(struct nvme_queue *nvmeq)
1554	{
1555	struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1556	int nr = nvmeq->dev->ctrl.instance;
1557
1558	if (use_threaded_interrupts) {
1559	return pci_request_irq(dev: pdev, nr: nvmeq->cq_vector, handler: nvme_irq_check,
1560	thread_fn: nvme_irq, dev_id: nvmeq, fmt: "nvme%dq%d", nr, nvmeq->qid);
1561	} else {
1562	return pci_request_irq(dev: pdev, nr: nvmeq->cq_vector, handler: nvme_irq,
1563	NULL, dev_id: nvmeq, fmt: "nvme%dq%d", nr, nvmeq->qid);
1564	}
1565	}
1566
1567	static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1568	{
1569	struct nvme_dev *dev = nvmeq->dev;
1570
1571	nvmeq->sq_tail = 0;
1572	nvmeq->last_sq_tail = 0;
1573	nvmeq->cq_head = 0;
1574	nvmeq->cq_phase = 1;
1575	nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1576	memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
1577	nvme_dbbuf_init(dev, nvmeq, qid);
1578	dev->online_queues++;
1579	wmb(); /* ensure the first interrupt sees the initialization */
1580	}
1581
1582	/*
1583	* Try getting shutdown_lock while setting up IO queues.
1584	*/
1585	static int nvme_setup_io_queues_trylock(struct nvme_dev *dev)
1586	{
1587	/*
1588	* Give up if the lock is being held by nvme_dev_disable.
1589	*/
1590	if (!mutex_trylock(lock: &dev->shutdown_lock))
1591	return -ENODEV;
1592
1593	/*
1594	* Controller is in wrong state, fail early.
1595	*/
1596	if (dev->ctrl.state != NVME_CTRL_CONNECTING) {
1597	mutex_unlock(lock: &dev->shutdown_lock);
1598	return -ENODEV;
1599	}
1600
1601	return 0;
1602	}
1603
1604	static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
1605	{
1606	struct nvme_dev *dev = nvmeq->dev;
1607	int result;
1608	u16 vector = 0;
1609
1610	clear_bit(NVMEQ_DELETE_ERROR, addr: &nvmeq->flags);
1611
1612	/*
1613	* A queue's vector matches the queue identifier unless the controller
1614	* has only one vector available.
1615	*/
1616	if (!polled)
1617	vector = dev->num_vecs == 1 ? 0 : qid;
1618	else
1619	set_bit(NVMEQ_POLLED, addr: &nvmeq->flags);
1620
1621	result = adapter_alloc_cq(dev, qid, nvmeq, vector);
1622	if (result)
1623	return result;
1624
1625	result = adapter_alloc_sq(dev, qid, nvmeq);
1626	if (result < 0)
1627	return result;
1628	if (result)
1629	goto release_cq;
1630
1631	nvmeq->cq_vector = vector;
1632
1633	result = nvme_setup_io_queues_trylock(dev);
1634	if (result)
1635	return result;
1636	nvme_init_queue(nvmeq, qid);
1637	if (!polled) {
1638	result = queue_request_irq(nvmeq);
1639	if (result < 0)
1640	goto release_sq;
1641	}
1642
1643	set_bit(NVMEQ_ENABLED, addr: &nvmeq->flags);
1644	mutex_unlock(lock: &dev->shutdown_lock);
1645	return result;
1646
1647	release_sq:
1648	dev->online_queues--;
1649	mutex_unlock(lock: &dev->shutdown_lock);
1650	adapter_delete_sq(dev, sqid: qid);
1651	release_cq:
1652	adapter_delete_cq(dev, cqid: qid);
1653	return result;
1654	}
1655
1656	static const struct blk_mq_ops nvme_mq_admin_ops = {
1657	.queue_rq = nvme_queue_rq,
1658	.complete = nvme_pci_complete_rq,
1659	.init_hctx = nvme_admin_init_hctx,
1660	.init_request = nvme_pci_init_request,
1661	.timeout = nvme_timeout,
1662	};
1663
1664	static const struct blk_mq_ops nvme_mq_ops = {
1665	.queue_rq = nvme_queue_rq,
1666	.queue_rqs = nvme_queue_rqs,
1667	.complete = nvme_pci_complete_rq,
1668	.commit_rqs = nvme_commit_rqs,
1669	.init_hctx = nvme_init_hctx,
1670	.init_request = nvme_pci_init_request,
1671	.map_queues = nvme_pci_map_queues,
1672	.timeout = nvme_timeout,
1673	.poll = nvme_poll,
1674	};
1675
1676	static void nvme_dev_remove_admin(struct nvme_dev *dev)
1677	{
1678	if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1679	/*
1680	* If the controller was reset during removal, it's possible
1681	* user requests may be waiting on a stopped queue. Start the
1682	* queue to flush these to completion.
1683	*/
1684	nvme_unquiesce_admin_queue(ctrl: &dev->ctrl);
1685	nvme_remove_admin_tag_set(ctrl: &dev->ctrl);
1686	}
1687	}
1688
1689	static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1690	{
1691	return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1692	}
1693
1694	static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1695	{
1696	struct pci_dev *pdev = to_pci_dev(dev->dev);
1697
1698	if (size <= dev->bar_mapped_size)
1699	return 0;
1700	if (size > pci_resource_len(pdev, 0))
1701	return -ENOMEM;
1702	if (dev->bar)
1703	iounmap(addr: dev->bar);
1704	dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1705	if (!dev->bar) {
1706	dev->bar_mapped_size = 0;
1707	return -ENOMEM;
1708	}
1709	dev->bar_mapped_size = size;
1710	dev->dbs = dev->bar + NVME_REG_DBS;
1711
1712	return 0;
1713	}
1714
1715	static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1716	{
1717	int result;
1718	u32 aqa;
1719	struct nvme_queue *nvmeq;
1720
1721	result = nvme_remap_bar(dev, size: db_bar_size(dev, nr_io_queues: 0));
1722	if (result < 0)
1723	return result;
1724
1725	dev->subsystem = readl(addr: dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1726	NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1727
1728	if (dev->subsystem &&
1729	(readl(addr: dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1730	writel(val: NVME_CSTS_NSSRO, addr: dev->bar + NVME_REG_CSTS);
1731
1732	/*
1733	* If the device has been passed off to us in an enabled state, just
1734	* clear the enabled bit. The spec says we should set the 'shutdown
1735	* notification bits', but doing so may cause the device to complete
1736	* commands to the admin queue ... and we don't know what memory that
1737	* might be pointing at!
1738	*/
1739	result = nvme_disable_ctrl(ctrl: &dev->ctrl, shutdown: false);
1740	if (result < 0)
1741	return result;
1742
1743	result = nvme_alloc_queue(dev, qid: 0, NVME_AQ_DEPTH);
1744	if (result)
1745	return result;
1746
1747	dev->ctrl.numa_node = dev_to_node(dev: dev->dev);
1748
1749	nvmeq = &dev->queues[0];
1750	aqa = nvmeq->q_depth - 1;
1751	aqa |= aqa << 16;
1752
1753	writel(val: aqa, addr: dev->bar + NVME_REG_AQA);
1754	lo_hi_writeq(val: nvmeq->sq_dma_addr, addr: dev->bar + NVME_REG_ASQ);
1755	lo_hi_writeq(val: nvmeq->cq_dma_addr, addr: dev->bar + NVME_REG_ACQ);
1756
1757	result = nvme_enable_ctrl(ctrl: &dev->ctrl);
1758	if (result)
1759	return result;
1760
1761	nvmeq->cq_vector = 0;
1762	nvme_init_queue(nvmeq, qid: 0);
1763	result = queue_request_irq(nvmeq);
1764	if (result) {
1765	dev->online_queues--;
1766	return result;
1767	}
1768
1769	set_bit(NVMEQ_ENABLED, addr: &nvmeq->flags);
1770	return result;
1771	}
1772
1773	static int nvme_create_io_queues(struct nvme_dev *dev)
1774	{
1775	unsigned i, max, rw_queues;
1776	int ret = 0;
1777
1778	for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1779	if (nvme_alloc_queue(dev, qid: i, depth: dev->q_depth)) {
1780	ret = -ENOMEM;
1781	break;
1782	}
1783	}
1784
1785	max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1786	if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1787	rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1788	dev->io_queues[HCTX_TYPE_READ];
1789	} else {
1790	rw_queues = max;
1791	}
1792
1793	for (i = dev->online_queues; i <= max; i++) {
1794	bool polled = i > rw_queues;
1795
1796	ret = nvme_create_queue(nvmeq: &dev->queues[i], qid: i, polled);
1797	if (ret)
1798	break;
1799	}
1800
1801	/*
1802	* Ignore failing Create SQ/CQ commands, we can continue with less
1803	* than the desired amount of queues, and even a controller without
1804	* I/O queues can still be used to issue admin commands. This might
1805	* be useful to upgrade a buggy firmware for example.
1806	*/
1807	return ret >= 0 ? 0 : ret;
1808	}
1809
1810	static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
1811	{
1812	u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1813
1814	return 1ULL << (12 + 4 * szu);
1815	}
1816
1817	static u32 nvme_cmb_size(struct nvme_dev *dev)
1818	{
1819	return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1820	}
1821
1822	static void nvme_map_cmb(struct nvme_dev *dev)
1823	{
1824	u64 size, offset;
1825	resource_size_t bar_size;
1826	struct pci_dev *pdev = to_pci_dev(dev->dev);
1827	int bar;
1828
1829	if (dev->cmb_size)
1830	return;
1831
1832	if (NVME_CAP_CMBS(dev->ctrl.cap))
1833	writel(val: NVME_CMBMSC_CRE, addr: dev->bar + NVME_REG_CMBMSC);
1834
1835	dev->cmbsz = readl(addr: dev->bar + NVME_REG_CMBSZ);
1836	if (!dev->cmbsz)
1837	return;
1838	dev->cmbloc = readl(addr: dev->bar + NVME_REG_CMBLOC);
1839
1840	size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1841	offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
1842	bar = NVME_CMB_BIR(dev->cmbloc);
1843	bar_size = pci_resource_len(pdev, bar);
1844
1845	if (offset > bar_size)
1846	return;
1847
1848	/*
1849	* Tell the controller about the host side address mapping the CMB,
1850	* and enable CMB decoding for the NVMe 1.4+ scheme:
1851	*/
1852	if (NVME_CAP_CMBS(dev->ctrl.cap)) {
1853	hi_lo_writeq(val: NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE |
1854	(pci_bus_address(pdev, bar) + offset),
1855	addr: dev->bar + NVME_REG_CMBMSC);
1856	}
1857
1858	/*
1859	* Controllers may support a CMB size larger than their BAR,
1860	* for example, due to being behind a bridge. Reduce the CMB to
1861	* the reported size of the BAR
1862	*/
1863	if (size > bar_size - offset)
1864	size = bar_size - offset;
1865
1866	if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1867	dev_warn(dev->ctrl.device,
1868	"failed to register the CMB\n");
1869	return;
1870	}
1871
1872	dev->cmb_size = size;
1873	dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1874
1875	if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1876	(NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1877	pci_p2pmem_publish(pdev, publish: true);
1878
1879	nvme_update_attrs(dev);
1880	}
1881
1882	static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1883	{
1884	u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
1885	u64 dma_addr = dev->host_mem_descs_dma;
1886	struct nvme_command c = { };
1887	int ret;
1888
1889	c.features.opcode = nvme_admin_set_features;
1890	c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1891	c.features.dword11 = cpu_to_le32(bits);
1892	c.features.dword12 = cpu_to_le32(host_mem_size);
1893	c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1894	c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1895	c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1896
1897	ret = nvme_submit_sync_cmd(q: dev->ctrl.admin_q, cmd: &c, NULL, bufflen: 0);
1898	if (ret) {
1899	dev_warn(dev->ctrl.device,
1900	"failed to set host mem (err %d, flags %#x).\n",
1901	ret, bits);
1902	} else
1903	dev->hmb = bits & NVME_HOST_MEM_ENABLE;
1904
1905	return ret;
1906	}
1907
1908	static void nvme_free_host_mem(struct nvme_dev *dev)
1909	{
1910	int i;
1911
1912	for (i = 0; i < dev->nr_host_mem_descs; i++) {
1913	struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1914	size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
1915
1916	dma_free_attrs(dev: dev->dev, size, cpu_addr: dev->host_mem_desc_bufs[i],
1917	le64_to_cpu(desc->addr),
1918	DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1919	}
1920
1921	kfree(objp: dev->host_mem_desc_bufs);
1922	dev->host_mem_desc_bufs = NULL;
1923	dma_free_coherent(dev: dev->dev,
1924	size: dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1925	cpu_addr: dev->host_mem_descs, dma_handle: dev->host_mem_descs_dma);
1926	dev->host_mem_descs = NULL;
1927	dev->nr_host_mem_descs = 0;
1928	}
1929
1930	static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1931	u32 chunk_size)
1932	{
1933	struct nvme_host_mem_buf_desc *descs;
1934	u32 max_entries, len;
1935	dma_addr_t descs_dma;
1936	int i = 0;
1937	void **bufs;
1938	u64 size, tmp;
1939
1940	tmp = (preferred + chunk_size - 1);
1941	do_div(tmp, chunk_size);
1942	max_entries = tmp;
1943
1944	if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1945	max_entries = dev->ctrl.hmmaxd;
1946
1947	descs = dma_alloc_coherent(dev: dev->dev, size: max_entries * sizeof(*descs),
1948	dma_handle: &descs_dma, GFP_KERNEL);
1949	if (!descs)
1950	goto out;
1951
1952	bufs = kcalloc(n: max_entries, size: sizeof(*bufs), GFP_KERNEL);
1953	if (!bufs)
1954	goto out_free_descs;
1955
1956	for (size = 0; size < preferred && i < max_entries; size += len) {
1957	dma_addr_t dma_addr;
1958
1959	len = min_t(u64, chunk_size, preferred - size);
1960	bufs[i] = dma_alloc_attrs(dev: dev->dev, size: len, dma_handle: &dma_addr, GFP_KERNEL,
1961	DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1962	if (!bufs[i])
1963	break;
1964
1965	descs[i].addr = cpu_to_le64(dma_addr);
1966	descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
1967	i++;
1968	}
1969
1970	if (!size)
1971	goto out_free_bufs;
1972
1973	dev->nr_host_mem_descs = i;
1974	dev->host_mem_size = size;
1975	dev->host_mem_descs = descs;
1976	dev->host_mem_descs_dma = descs_dma;
1977	dev->host_mem_desc_bufs = bufs;
1978	return 0;
1979
1980	out_free_bufs:
1981	while (--i >= 0) {
1982	size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE;
1983
1984	dma_free_attrs(dev: dev->dev, size, cpu_addr: bufs[i],
1985	le64_to_cpu(descs[i].addr),
1986	DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1987	}
1988
1989	kfree(objp: bufs);
1990	out_free_descs:
1991	dma_free_coherent(dev: dev->dev, size: max_entries * sizeof(*descs), cpu_addr: descs,
1992	dma_handle: descs_dma);
1993	out:
1994	dev->host_mem_descs = NULL;
1995	return -ENOMEM;
1996	}
1997
1998	static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1999	{
2000	u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
2001	u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
2002	u64 chunk_size;
2003
2004	/* start big and work our way down */
2005	for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
2006	if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
2007	if (!min || dev->host_mem_size >= min)
2008	return 0;
2009	nvme_free_host_mem(dev);
2010	}
2011	}
2012
2013	return -ENOMEM;
2014	}
2015
2016	static int nvme_setup_host_mem(struct nvme_dev *dev)
2017	{
2018	u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2019	u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2020	u64 min = (u64)dev->ctrl.hmmin * 4096;
2021	u32 enable_bits = NVME_HOST_MEM_ENABLE;
2022	int ret;
2023
2024	if (!dev->ctrl.hmpre)
2025	return 0;
2026
2027	preferred = min(preferred, max);
2028	if (min > max) {
2029	dev_warn(dev->ctrl.device,
2030	"min host memory (%lld MiB) above limit (%d MiB).\n",
2031	min >> ilog2(SZ_1M), max_host_mem_size_mb);
2032	nvme_free_host_mem(dev);
2033	return 0;
2034	}
2035
2036	/*
2037	* If we already have a buffer allocated check if we can reuse it.
2038	*/
2039	if (dev->host_mem_descs) {
2040	if (dev->host_mem_size >= min)
2041	enable_bits |= NVME_HOST_MEM_RETURN;
2042	else
2043	nvme_free_host_mem(dev);
2044	}
2045
2046	if (!dev->host_mem_descs) {
2047	if (nvme_alloc_host_mem(dev, min, preferred)) {
2048	dev_warn(dev->ctrl.device,
2049	"failed to allocate host memory buffer.\n");
2050	return 0; /* controller must work without HMB */
2051	}
2052
2053	dev_info(dev->ctrl.device,
2054	"allocated %lld MiB host memory buffer.\n",
2055	dev->host_mem_size >> ilog2(SZ_1M));
2056	}
2057
2058	ret = nvme_set_host_mem(dev, bits: enable_bits);
2059	if (ret)
2060	nvme_free_host_mem(dev);
2061	return ret;
2062	}
2063
2064	static ssize_t cmb_show(struct device *dev, struct device_attribute *attr,
2065	char *buf)
2066	{
2067	struct nvme_dev *ndev = to_nvme_dev(ctrl: dev_get_drvdata(dev));
2068
2069	return sysfs_emit(buf, fmt: "cmbloc : x%08x\ncmbsz : x%08x\n",
2070	ndev->cmbloc, ndev->cmbsz);
2071	}
2072	static DEVICE_ATTR_RO(cmb);
2073
2074	static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr,
2075	char *buf)
2076	{
2077	struct nvme_dev *ndev = to_nvme_dev(ctrl: dev_get_drvdata(dev));
2078
2079	return sysfs_emit(buf, fmt: "%u\n", ndev->cmbloc);
2080	}
2081	static DEVICE_ATTR_RO(cmbloc);
2082
2083	static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr,
2084	char *buf)
2085	{
2086	struct nvme_dev *ndev = to_nvme_dev(ctrl: dev_get_drvdata(dev));
2087
2088	return sysfs_emit(buf, fmt: "%u\n", ndev->cmbsz);
2089	}
2090	static DEVICE_ATTR_RO(cmbsz);
2091
2092	static ssize_t hmb_show(struct device *dev, struct device_attribute *attr,
2093	char *buf)
2094	{
2095	struct nvme_dev *ndev = to_nvme_dev(ctrl: dev_get_drvdata(dev));
2096
2097	return sysfs_emit(buf, fmt: "%d\n", ndev->hmb);
2098	}
2099
2100	static ssize_t hmb_store(struct device *dev, struct device_attribute *attr,
2101	const char *buf, size_t count)
2102	{
2103	struct nvme_dev *ndev = to_nvme_dev(ctrl: dev_get_drvdata(dev));
2104	bool new;
2105	int ret;
2106
2107	if (kstrtobool(s: buf, res: &new) < 0)
2108	return -EINVAL;
2109
2110	if (new == ndev->hmb)
2111	return count;
2112
2113	if (new) {
2114	ret = nvme_setup_host_mem(dev: ndev);
2115	} else {
2116	ret = nvme_set_host_mem(dev: ndev, bits: 0);
2117	if (!ret)
2118	nvme_free_host_mem(dev: ndev);
2119	}
2120
2121	if (ret < 0)
2122	return ret;
2123
2124	return count;
2125	}
2126	static DEVICE_ATTR_RW(hmb);
2127
2128	static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj,
2129	struct attribute *a, int n)
2130	{
2131	struct nvme_ctrl *ctrl =
2132	dev_get_drvdata(container_of(kobj, struct device, kobj));
2133	struct nvme_dev *dev = to_nvme_dev(ctrl);
2134
2135	if (a == &dev_attr_cmb.attr ||
2136	a == &dev_attr_cmbloc.attr ||
2137	a == &dev_attr_cmbsz.attr) {
2138	if (!dev->cmbsz)
2139	return 0;
2140	}
2141	if (a == &dev_attr_hmb.attr && !ctrl->hmpre)
2142	return 0;
2143
2144	return a->mode;
2145	}
2146
2147	static struct attribute *nvme_pci_attrs[] = {
2148	&dev_attr_cmb.attr,
2149	&dev_attr_cmbloc.attr,
2150	&dev_attr_cmbsz.attr,
2151	&dev_attr_hmb.attr,
2152	NULL,
2153	};
2154
2155	static const struct attribute_group nvme_pci_dev_attrs_group = {
2156	.attrs = nvme_pci_attrs,
2157	.is_visible = nvme_pci_attrs_are_visible,
2158	};
2159
2160	static const struct attribute_group *nvme_pci_dev_attr_groups[] = {
2161	&nvme_dev_attrs_group,
2162	&nvme_pci_dev_attrs_group,
2163	NULL,
2164	};
2165
2166	static void nvme_update_attrs(struct nvme_dev *dev)
2167	{
2168	sysfs_update_group(kobj: &dev->ctrl.device->kobj, grp: &nvme_pci_dev_attrs_group);
2169	}
2170
2171	/*
2172	* nirqs is the number of interrupts available for write and read
2173	* queues. The core already reserved an interrupt for the admin queue.
2174	*/
2175	static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
2176	{
2177	struct nvme_dev *dev = affd->priv;
2178	unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
2179
2180	/*
2181	* If there is no interrupt available for queues, ensure that
2182	* the default queue is set to 1. The affinity set size is
2183	* also set to one, but the irq core ignores it for this case.
2184	*
2185	* If only one interrupt is available or 'write_queue' == 0, combine
2186	* write and read queues.
2187	*
2188	* If 'write_queues' > 0, ensure it leaves room for at least one read
2189	* queue.
2190	*/
2191	if (!nrirqs) {
2192	nrirqs = 1;
2193	nr_read_queues = 0;
2194	} else if (nrirqs == 1 || !nr_write_queues) {
2195	nr_read_queues = 0;
2196	} else if (nr_write_queues >= nrirqs) {
2197	nr_read_queues = 1;
2198	} else {
2199	nr_read_queues = nrirqs - nr_write_queues;
2200	}
2201
2202	dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2203	affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2204	dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2205	affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2206	affd->nr_sets = nr_read_queues ? 2 : 1;
2207	}
2208
2209	static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
2210	{
2211	struct pci_dev *pdev = to_pci_dev(dev->dev);
2212	struct irq_affinity affd = {
2213	.pre_vectors = 1,
2214	.calc_sets = nvme_calc_irq_sets,
2215	.priv = dev,
2216	};
2217	unsigned int irq_queues, poll_queues;
2218
2219	/*
2220	* Poll queues don't need interrupts, but we need at least one I/O queue
2221	* left over for non-polled I/O.
2222	*/
2223	poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
2224	dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
2225
2226	/*
2227	* Initialize for the single interrupt case, will be updated in
2228	* nvme_calc_irq_sets().
2229	*/
2230	dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2231	dev->io_queues[HCTX_TYPE_READ] = 0;
2232
2233	/*
2234	* We need interrupts for the admin queue and each non-polled I/O queue,
2235	* but some Apple controllers require all queues to use the first
2236	* vector.
2237	*/
2238	irq_queues = 1;
2239	if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
2240	irq_queues += (nr_io_queues - poll_queues);
2241	return pci_alloc_irq_vectors_affinity(dev: pdev, min_vecs: 1, max_vecs: irq_queues,
2242	PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, affd: &affd);
2243	}
2244
2245	static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2246	{
2247	/*
2248	* If tags are shared with admin queue (Apple bug), then
2249	* make sure we only use one IO queue.
2250	*/
2251	if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2252	return 1;
2253	return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2254	}
2255
2256	static int nvme_setup_io_queues(struct nvme_dev *dev)
2257	{
2258	struct nvme_queue *adminq = &dev->queues[0];
2259	struct pci_dev *pdev = to_pci_dev(dev->dev);
2260	unsigned int nr_io_queues;
2261	unsigned long size;
2262	int result;
2263
2264	/*
2265	* Sample the module parameters once at reset time so that we have
2266	* stable values to work with.
2267	*/
2268	dev->nr_write_queues = write_queues;
2269	dev->nr_poll_queues = poll_queues;
2270
2271	nr_io_queues = dev->nr_allocated_queues - 1;
2272	result = nvme_set_queue_count(ctrl: &dev->ctrl, count: &nr_io_queues);
2273	if (result < 0)
2274	return result;
2275
2276	if (nr_io_queues == 0)
2277	return 0;
2278
2279	/*
2280	* Free IRQ resources as soon as NVMEQ_ENABLED bit transitions
2281	* from set to unset. If there is a window to it is truely freed,
2282	* pci_free_irq_vectors() jumping into this window will crash.
2283	* And take lock to avoid racing with pci_free_irq_vectors() in
2284	* nvme_dev_disable() path.
2285	*/
2286	result = nvme_setup_io_queues_trylock(dev);
2287	if (result)
2288	return result;
2289	if (test_and_clear_bit(NVMEQ_ENABLED, addr: &adminq->flags))
2290	pci_free_irq(dev: pdev, nr: 0, dev_id: adminq);
2291
2292	if (dev->cmb_use_sqes) {
2293	result = nvme_cmb_qdepth(dev, nr_io_queues,
2294	entry_size: sizeof(struct nvme_command));
2295	if (result > 0) {
2296	dev->q_depth = result;
2297	dev->ctrl.sqsize = result - 1;
2298	} else {
2299	dev->cmb_use_sqes = false;
2300	}
2301	}
2302
2303	do {
2304	size = db_bar_size(dev, nr_io_queues);
2305	result = nvme_remap_bar(dev, size);
2306	if (!result)
2307	break;
2308	if (!--nr_io_queues) {
2309	result = -ENOMEM;
2310	goto out_unlock;
2311	}
2312	} while (1);
2313	adminq->q_db = dev->dbs;
2314
2315	retry:
2316	/* Deregister the admin queue's interrupt */
2317	if (test_and_clear_bit(NVMEQ_ENABLED, addr: &adminq->flags))
2318	pci_free_irq(dev: pdev, nr: 0, dev_id: adminq);
2319
2320	/*
2321	* If we enable msix early due to not intx, disable it again before
2322	* setting up the full range we need.
2323	*/
2324	pci_free_irq_vectors(dev: pdev);
2325
2326	result = nvme_setup_irqs(dev, nr_io_queues);
2327	if (result <= 0) {
2328	result = -EIO;
2329	goto out_unlock;
2330	}
2331
2332	dev->num_vecs = result;
2333	result = max(result - 1, 1);
2334	dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
2335
2336	/*
2337	* Should investigate if there's a performance win from allocating
2338	* more queues than interrupt vectors; it might allow the submission
2339	* path to scale better, even if the receive path is limited by the
2340	* number of interrupts.
2341	*/
2342	result = queue_request_irq(nvmeq: adminq);
2343	if (result)
2344	goto out_unlock;
2345	set_bit(NVMEQ_ENABLED, addr: &adminq->flags);
2346	mutex_unlock(lock: &dev->shutdown_lock);
2347
2348	result = nvme_create_io_queues(dev);
2349	if (result || dev->online_queues < 2)
2350	return result;
2351
2352	if (dev->online_queues - 1 < dev->max_qid) {
2353	nr_io_queues = dev->online_queues - 1;
2354	nvme_delete_io_queues(dev);
2355	result = nvme_setup_io_queues_trylock(dev);
2356	if (result)
2357	return result;
2358	nvme_suspend_io_queues(dev);
2359	goto retry;
2360	}
2361	dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2362	dev->io_queues[HCTX_TYPE_DEFAULT],
2363	dev->io_queues[HCTX_TYPE_READ],
2364	dev->io_queues[HCTX_TYPE_POLL]);
2365	return 0;
2366	out_unlock:
2367	mutex_unlock(lock: &dev->shutdown_lock);
2368	return result;
2369	}
2370
2371	static enum rq_end_io_ret nvme_del_queue_end(struct request *req,
2372	blk_status_t error)
2373	{
2374	struct nvme_queue *nvmeq = req->end_io_data;
2375
2376	blk_mq_free_request(rq: req);
2377	complete(&nvmeq->delete_done);
2378	return RQ_END_IO_NONE;
2379	}
2380
2381	static enum rq_end_io_ret nvme_del_cq_end(struct request *req,
2382	blk_status_t error)
2383	{
2384	struct nvme_queue *nvmeq = req->end_io_data;
2385
2386	if (error)
2387	set_bit(NVMEQ_DELETE_ERROR, addr: &nvmeq->flags);
2388
2389	return nvme_del_queue_end(req, error);
2390	}
2391
2392	static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
2393	{
2394	struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2395	struct request *req;
2396	struct nvme_command cmd = { };
2397
2398	cmd.delete_queue.opcode = opcode;
2399	cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2400
2401	req = blk_mq_alloc_request(q, opf: nvme_req_op(cmd: &cmd), flags: BLK_MQ_REQ_NOWAIT);
2402	if (IS_ERR(ptr: req))
2403	return PTR_ERR(ptr: req);
2404	nvme_init_request(req, cmd: &cmd);
2405
2406	if (opcode == nvme_admin_delete_cq)
2407	req->end_io = nvme_del_cq_end;
2408	else
2409	req->end_io = nvme_del_queue_end;
2410	req->end_io_data = nvmeq;
2411
2412	init_completion(x: &nvmeq->delete_done);
2413	blk_execute_rq_nowait(rq: req, at_head: false);
2414	return 0;
2415	}
2416
2417	static bool __nvme_delete_io_queues(struct nvme_dev *dev, u8 opcode)
2418	{
2419	int nr_queues = dev->online_queues - 1, sent = 0;
2420	unsigned long timeout;
2421
2422	retry:
2423	timeout = NVME_ADMIN_TIMEOUT;
2424	while (nr_queues > 0) {
2425	if (nvme_delete_queue(nvmeq: &dev->queues[nr_queues], opcode))
2426	break;
2427	nr_queues--;
2428	sent++;
2429	}
2430	while (sent) {
2431	struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2432
2433	timeout = wait_for_completion_io_timeout(x: &nvmeq->delete_done,
2434	timeout);
2435	if (timeout == 0)
2436	return false;
2437
2438	sent--;
2439	if (nr_queues)
2440	goto retry;
2441	}
2442	return true;
2443	}
2444
2445	static void nvme_delete_io_queues(struct nvme_dev *dev)
2446	{
2447	if (__nvme_delete_io_queues(dev, opcode: nvme_admin_delete_sq))
2448	__nvme_delete_io_queues(dev, opcode: nvme_admin_delete_cq);
2449	}
2450
2451	static unsigned int nvme_pci_nr_maps(struct nvme_dev *dev)
2452	{
2453	if (dev->io_queues[HCTX_TYPE_POLL])
2454	return 3;
2455	if (dev->io_queues[HCTX_TYPE_READ])
2456	return 2;
2457	return 1;
2458	}
2459
2460	static void nvme_pci_update_nr_queues(struct nvme_dev *dev)
2461	{
2462	blk_mq_update_nr_hw_queues(set: &dev->tagset, nr_hw_queues: dev->online_queues - 1);
2463	/* free previously allocated queues that are no longer usable */
2464	nvme_free_queues(dev, lowest: dev->online_queues);
2465	}
2466
2467	static int nvme_pci_enable(struct nvme_dev *dev)
2468	{
2469	int result = -ENOMEM;
2470	struct pci_dev *pdev = to_pci_dev(dev->dev);
2471
2472	if (pci_enable_device_mem(dev: pdev))
2473	return result;
2474
2475	pci_set_master(dev: pdev);
2476
2477	if (readl(addr: dev->bar + NVME_REG_CSTS) == -1) {
2478	result = -ENODEV;
2479	goto disable;
2480	}
2481
2482	/*
2483	* Some devices and/or platforms don't advertise or work with INTx
2484	* interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2485	* adjust this later.
2486	*/
2487	result = pci_alloc_irq_vectors(dev: pdev, min_vecs: 1, max_vecs: 1, PCI_IRQ_ALL_TYPES);
2488	if (result < 0)
2489	goto disable;
2490
2491	dev->ctrl.cap = lo_hi_readq(addr: dev->bar + NVME_REG_CAP);
2492
2493	dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
2494	io_queue_depth);
2495	dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
2496	dev->dbs = dev->bar + 4096;
2497
2498	/*
2499	* Some Apple controllers require a non-standard SQE size.
2500	* Interestingly they also seem to ignore the CC:IOSQES register
2501	* so we don't bother updating it here.
2502	*/
2503	if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2504	dev->io_sqes = 7;
2505	else
2506	dev->io_sqes = NVME_NVM_IOSQES;
2507
2508	/*
2509	* Temporary fix for the Apple controller found in the MacBook8,1 and
2510	* some MacBook7,1 to avoid controller resets and data loss.
2511	*/
2512	if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2513	dev->q_depth = 2;
2514	dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2515	"set queue depth=%u to work around controller resets\n",
2516	dev->q_depth);
2517	} else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2518	(pdev->device == 0xa821 || pdev->device == 0xa822) &&
2519	NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2520	dev->q_depth = 64;
2521	dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2522	"set queue depth=%u\n", dev->q_depth);
2523	}
2524
2525	/*
2526	* Controllers with the shared tags quirk need the IO queue to be
2527	* big enough so that we get 32 tags for the admin queue
2528	*/
2529	if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2530	(dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2531	dev->q_depth = NVME_AQ_DEPTH + 2;
2532	dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2533	dev->q_depth);
2534	}
2535	dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
2536
2537	nvme_map_cmb(dev);
2538
2539	pci_save_state(dev: pdev);
2540
2541	result = nvme_pci_configure_admin_queue(dev);
2542	if (result)
2543	goto free_irq;
2544	return result;
2545
2546	free_irq:
2547	pci_free_irq_vectors(dev: pdev);
2548	disable:
2549	pci_disable_device(dev: pdev);
2550	return result;
2551	}
2552
2553	static void nvme_dev_unmap(struct nvme_dev *dev)
2554	{
2555	if (dev->bar)
2556	iounmap(addr: dev->bar);
2557	pci_release_mem_regions(to_pci_dev(dev->dev));
2558	}
2559
2560	static bool nvme_pci_ctrl_is_dead(struct nvme_dev *dev)
2561	{
2562	struct pci_dev *pdev = to_pci_dev(dev->dev);
2563	u32 csts;
2564
2565	if (!pci_is_enabled(pdev) || !pci_device_is_present(pdev))
2566	return true;
2567	if (pdev->error_state != pci_channel_io_normal)
2568	return true;
2569
2570	csts = readl(addr: dev->bar + NVME_REG_CSTS);
2571	return (csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY);
2572	}
2573
2574	static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2575	{
2576	struct pci_dev *pdev = to_pci_dev(dev->dev);
2577	bool dead;
2578
2579	mutex_lock(&dev->shutdown_lock);
2580	dead = nvme_pci_ctrl_is_dead(dev);
2581	if (dev->ctrl.state == NVME_CTRL_LIVE ||
2582	dev->ctrl.state == NVME_CTRL_RESETTING) {
2583	if (pci_is_enabled(pdev))
2584	nvme_start_freeze(ctrl: &dev->ctrl);
2585	/*
2586	* Give the controller a chance to complete all entered requests
2587	* if doing a safe shutdown.
2588	*/
2589	if (!dead && shutdown)
2590	nvme_wait_freeze_timeout(ctrl: &dev->ctrl, NVME_IO_TIMEOUT);
2591	}
2592
2593	nvme_quiesce_io_queues(ctrl: &dev->ctrl);
2594
2595	if (!dead && dev->ctrl.queue_count > 0) {
2596	nvme_delete_io_queues(dev);
2597	nvme_disable_ctrl(ctrl: &dev->ctrl, shutdown);
2598	nvme_poll_irqdisable(nvmeq: &dev->queues[0]);
2599	}
2600	nvme_suspend_io_queues(dev);
2601	nvme_suspend_queue(dev, qid: 0);
2602	pci_free_irq_vectors(dev: pdev);
2603	if (pci_is_enabled(pdev))
2604	pci_disable_device(dev: pdev);
2605	nvme_reap_pending_cqes(dev);
2606
2607	nvme_cancel_tagset(ctrl: &dev->ctrl);
2608	nvme_cancel_admin_tagset(ctrl: &dev->ctrl);
2609
2610	/*
2611	* The driver will not be starting up queues again if shutting down so
2612	* must flush all entered requests to their failed completion to avoid
2613	* deadlocking blk-mq hot-cpu notifier.
2614	*/
2615	if (shutdown) {
2616	nvme_unquiesce_io_queues(ctrl: &dev->ctrl);
2617	if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2618	nvme_unquiesce_admin_queue(ctrl: &dev->ctrl);
2619	}
2620	mutex_unlock(lock: &dev->shutdown_lock);
2621	}
2622
2623	static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2624	{
2625	if (!nvme_wait_reset(ctrl: &dev->ctrl))
2626	return -EBUSY;
2627	nvme_dev_disable(dev, shutdown);
2628	return 0;
2629	}
2630
2631	static int nvme_setup_prp_pools(struct nvme_dev *dev)
2632	{
2633	dev->prp_page_pool = dma_pool_create(name: "prp list page", dev: dev->dev,
2634	NVME_CTRL_PAGE_SIZE,
2635	NVME_CTRL_PAGE_SIZE, allocation: 0);
2636	if (!dev->prp_page_pool)
2637	return -ENOMEM;
2638
2639	/* Optimisation for I/Os between 4k and 128k */
2640	dev->prp_small_pool = dma_pool_create(name: "prp list 256", dev: dev->dev,
2641	size: 256, align: 256, allocation: 0);
2642	if (!dev->prp_small_pool) {
2643	dma_pool_destroy(pool: dev->prp_page_pool);
2644	return -ENOMEM;
2645	}
2646	return 0;
2647	}
2648
2649	static void nvme_release_prp_pools(struct nvme_dev *dev)
2650	{
2651	dma_pool_destroy(pool: dev->prp_page_pool);
2652	dma_pool_destroy(pool: dev->prp_small_pool);
2653	}
2654
2655	static int nvme_pci_alloc_iod_mempool(struct nvme_dev *dev)
2656	{
2657	size_t alloc_size = sizeof(struct scatterlist) * NVME_MAX_SEGS;
2658
2659	dev->iod_mempool = mempool_create_node(min_nr: 1,
2660	alloc_fn: mempool_kmalloc, free_fn: mempool_kfree,
2661	pool_data: (void *)alloc_size, GFP_KERNEL,
2662	nid: dev_to_node(dev: dev->dev));
2663	if (!dev->iod_mempool)
2664	return -ENOMEM;
2665	return 0;
2666	}
2667
2668	static void nvme_free_tagset(struct nvme_dev *dev)
2669	{
2670	if (dev->tagset.tags)
2671	nvme_remove_io_tag_set(ctrl: &dev->ctrl);
2672	dev->ctrl.tagset = NULL;
2673	}
2674
2675	/* pairs with nvme_pci_alloc_dev */
2676	static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2677	{
2678	struct nvme_dev *dev = to_nvme_dev(ctrl);
2679
2680	nvme_free_tagset(dev);
2681	put_device(dev: dev->dev);
2682	kfree(objp: dev->queues);
2683	kfree(objp: dev);
2684	}
2685
2686	static void nvme_reset_work(struct work_struct *work)
2687	{
2688	struct nvme_dev *dev =
2689	container_of(work, struct nvme_dev, ctrl.reset_work);
2690	bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2691	int result;
2692
2693	if (dev->ctrl.state != NVME_CTRL_RESETTING) {
2694	dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n",
2695	dev->ctrl.state);
2696	result = -ENODEV;
2697	goto out;
2698	}
2699
2700	/*
2701	* If we're called to reset a live controller first shut it down before
2702	* moving on.
2703	*/
2704	if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2705	nvme_dev_disable(dev, shutdown: false);
2706	nvme_sync_queues(ctrl: &dev->ctrl);
2707
2708	mutex_lock(&dev->shutdown_lock);
2709	result = nvme_pci_enable(dev);
2710	if (result)
2711	goto out_unlock;
2712	nvme_unquiesce_admin_queue(ctrl: &dev->ctrl);
2713	mutex_unlock(lock: &dev->shutdown_lock);
2714
2715	/*
2716	* Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2717	* initializing procedure here.
2718	*/
2719	if (!nvme_change_ctrl_state(ctrl: &dev->ctrl, new_state: NVME_CTRL_CONNECTING)) {
2720	dev_warn(dev->ctrl.device,
2721	"failed to mark controller CONNECTING\n");
2722	result = -EBUSY;
2723	goto out;
2724	}
2725
2726	result = nvme_init_ctrl_finish(ctrl: &dev->ctrl, was_suspended: was_suspend);
2727	if (result)
2728	goto out;
2729
2730	nvme_dbbuf_dma_alloc(dev);
2731
2732	result = nvme_setup_host_mem(dev);
2733	if (result < 0)
2734	goto out;
2735
2736	result = nvme_setup_io_queues(dev);
2737	if (result)
2738	goto out;
2739
2740	/*
2741	* Freeze and update the number of I/O queues as thos might have
2742	* changed. If there are no I/O queues left after this reset, keep the
2743	* controller around but remove all namespaces.
2744	*/
2745	if (dev->online_queues > 1) {
2746	nvme_unquiesce_io_queues(ctrl: &dev->ctrl);
2747	nvme_wait_freeze(ctrl: &dev->ctrl);
2748	nvme_pci_update_nr_queues(dev);
2749	nvme_dbbuf_set(dev);
2750	nvme_unfreeze(ctrl: &dev->ctrl);
2751	} else {
2752	dev_warn(dev->ctrl.device, "IO queues lost\n");
2753	nvme_mark_namespaces_dead(ctrl: &dev->ctrl);
2754	nvme_unquiesce_io_queues(ctrl: &dev->ctrl);
2755	nvme_remove_namespaces(ctrl: &dev->ctrl);
2756	nvme_free_tagset(dev);
2757	}
2758
2759	/*
2760	* If only admin queue live, keep it to do further investigation or
2761	* recovery.
2762	*/
2763	if (!nvme_change_ctrl_state(ctrl: &dev->ctrl, new_state: NVME_CTRL_LIVE)) {
2764	dev_warn(dev->ctrl.device,
2765	"failed to mark controller live state\n");
2766	result = -ENODEV;
2767	goto out;
2768	}
2769
2770	nvme_start_ctrl(ctrl: &dev->ctrl);
2771	return;
2772
2773	out_unlock:
2774	mutex_unlock(lock: &dev->shutdown_lock);
2775	out:
2776	/*
2777	* Set state to deleting now to avoid blocking nvme_wait_reset(), which
2778	* may be holding this pci_dev's device lock.
2779	*/
2780	dev_warn(dev->ctrl.device, "Disabling device after reset failure: %d\n",
2781	result);
2782	nvme_change_ctrl_state(ctrl: &dev->ctrl, new_state: NVME_CTRL_DELETING);
2783	nvme_dev_disable(dev, shutdown: true);
2784	nvme_sync_queues(ctrl: &dev->ctrl);
2785	nvme_mark_namespaces_dead(ctrl: &dev->ctrl);
2786	nvme_unquiesce_io_queues(ctrl: &dev->ctrl);
2787	nvme_change_ctrl_state(ctrl: &dev->ctrl, new_state: NVME_CTRL_DEAD);
2788	}
2789
2790	static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2791	{
2792	*val = readl(addr: to_nvme_dev(ctrl)->bar + off);
2793	return 0;
2794	}
2795
2796	static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2797	{
2798	writel(val, addr: to_nvme_dev(ctrl)->bar + off);
2799	return 0;
2800	}
2801
2802	static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2803	{
2804	*val = lo_hi_readq(addr: to_nvme_dev(ctrl)->bar + off);
2805	return 0;
2806	}
2807
2808	static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2809	{
2810	struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2811
2812	return snprintf(buf, size, fmt: "%s\n", dev_name(dev: &pdev->dev));
2813	}
2814
2815	static void nvme_pci_print_device_info(struct nvme_ctrl *ctrl)
2816	{
2817	struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2818	struct nvme_subsystem *subsys = ctrl->subsys;
2819
2820	dev_err(ctrl->device,
2821	"VID:DID %04x:%04x model:%.*s firmware:%.*s\n",
2822	pdev->vendor, pdev->device,
2823	nvme_strlen(subsys->model, sizeof(subsys->model)),
2824	subsys->model, nvme_strlen(subsys->firmware_rev,
2825	sizeof(subsys->firmware_rev)),
2826	subsys->firmware_rev);
2827	}
2828
2829	static bool nvme_pci_supports_pci_p2pdma(struct nvme_ctrl *ctrl)
2830	{
2831	struct nvme_dev *dev = to_nvme_dev(ctrl);
2832
2833	return dma_pci_p2pdma_supported(dev: dev->dev);
2834	}
2835
2836	static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2837	.name = "pcie",
2838	.module = THIS_MODULE,
2839	.flags = NVME_F_METADATA_SUPPORTED,
2840	.dev_attr_groups = nvme_pci_dev_attr_groups,
2841	.reg_read32 = nvme_pci_reg_read32,
2842	.reg_write32 = nvme_pci_reg_write32,
2843	.reg_read64 = nvme_pci_reg_read64,
2844	.free_ctrl = nvme_pci_free_ctrl,
2845	.submit_async_event = nvme_pci_submit_async_event,
2846	.get_address = nvme_pci_get_address,
2847	.print_device_info = nvme_pci_print_device_info,
2848	.supports_pci_p2pdma = nvme_pci_supports_pci_p2pdma,
2849	};
2850
2851	static int nvme_dev_map(struct nvme_dev *dev)
2852	{
2853	struct pci_dev *pdev = to_pci_dev(dev->dev);
2854
2855	if (pci_request_mem_regions(pdev, name: "nvme"))
2856	return -ENODEV;
2857
2858	if (nvme_remap_bar(dev, size: NVME_REG_DBS + 4096))
2859	goto release;
2860
2861	return 0;
2862	release:
2863	pci_release_mem_regions(pdev);
2864	return -ENODEV;
2865	}
2866
2867	static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
2868	{
2869	if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2870	/*
2871	* Several Samsung devices seem to drop off the PCIe bus
2872	* randomly when APST is on and uses the deepest sleep state.
2873	* This has been observed on a Samsung "SM951 NVMe SAMSUNG
2874	* 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2875	* 950 PRO 256GB", but it seems to be restricted to two Dell
2876	* laptops.
2877	*/
2878	if (dmi_match(f: DMI_SYS_VENDOR, str: "Dell Inc.") &&
2879	(dmi_match(f: DMI_PRODUCT_NAME, str: "XPS 15 9550") ||
2880	dmi_match(f: DMI_PRODUCT_NAME, str: "Precision 5510")))
2881	return NVME_QUIRK_NO_DEEPEST_PS;
2882	} else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2883	/*
2884	* Samsung SSD 960 EVO drops off the PCIe bus after system
2885	* suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2886	* within few minutes after bootup on a Coffee Lake board -
2887	* ASUS PRIME Z370-A
2888	*/
2889	if (dmi_match(f: DMI_BOARD_VENDOR, str: "ASUSTeK COMPUTER INC.") &&
2890	(dmi_match(f: DMI_BOARD_NAME, str: "PRIME B350M-A") ||
2891	dmi_match(f: DMI_BOARD_NAME, str: "PRIME Z370-A")))
2892	return NVME_QUIRK_NO_APST;
2893	} else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
2894	pdev->device == 0xa808 || pdev->device == 0xa809)) ||
2895	(pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
2896	/*
2897	* Forcing to use host managed nvme power settings for
2898	* lowest idle power with quick resume latency on
2899	* Samsung and Toshiba SSDs based on suspend behavior
2900	* on Coffee Lake board for LENOVO C640
2901	*/
2902	if ((dmi_match(f: DMI_BOARD_VENDOR, str: "LENOVO")) &&
2903	dmi_match(f: DMI_BOARD_NAME, str: "LNVNB161216"))
2904	return NVME_QUIRK_SIMPLE_SUSPEND;
2905	}
2906
2907	return 0;
2908	}
2909
2910	static struct nvme_dev *nvme_pci_alloc_dev(struct pci_dev *pdev,
2911	const struct pci_device_id *id)
2912	{
2913	unsigned long quirks = id->driver_data;
2914	int node = dev_to_node(dev: &pdev->dev);
2915	struct nvme_dev *dev;
2916	int ret = -ENOMEM;
2917
2918	dev = kzalloc_node(size: sizeof(*dev), GFP_KERNEL, node);
2919	if (!dev)
2920	return ERR_PTR(error: -ENOMEM);
2921	INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2922	mutex_init(&dev->shutdown_lock);
2923
2924	dev->nr_write_queues = write_queues;
2925	dev->nr_poll_queues = poll_queues;
2926	dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
2927	dev->queues = kcalloc_node(n: dev->nr_allocated_queues,
2928	size: sizeof(struct nvme_queue), GFP_KERNEL, node);
2929	if (!dev->queues)
2930	goto out_free_dev;
2931
2932	dev->dev = get_device(dev: &pdev->dev);
2933
2934	quirks |= check_vendor_combination_bug(pdev);
2935	if (!noacpi && acpi_storage_d3(dev: &pdev->dev)) {
2936	/*
2937	* Some systems use a bios work around to ask for D3 on
2938	* platforms that support kernel managed suspend.
2939	*/
2940	dev_info(&pdev->dev,
2941	"platform quirk: setting simple suspend\n");
2942	quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
2943	}
2944	ret = nvme_init_ctrl(ctrl: &dev->ctrl, dev: &pdev->dev, ops: &nvme_pci_ctrl_ops,
2945	quirks);
2946	if (ret)
2947	goto out_put_device;
2948
2949	if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48)
2950	dma_set_mask_and_coherent(dev: &pdev->dev, DMA_BIT_MASK(48));
2951	else
2952	dma_set_mask_and_coherent(dev: &pdev->dev, DMA_BIT_MASK(64));
2953	dma_set_min_align_mask(dev: &pdev->dev, NVME_CTRL_PAGE_SIZE - 1);
2954	dma_set_max_seg_size(dev: &pdev->dev, size: 0xffffffff);
2955
2956	/*
2957	* Limit the max command size to prevent iod->sg allocations going
2958	* over a single page.
2959	*/
2960	dev->ctrl.max_hw_sectors = min_t(u32,
2961	NVME_MAX_KB_SZ << 1, dma_opt_mapping_size(&pdev->dev) >> 9);
2962	dev->ctrl.max_segments = NVME_MAX_SEGS;
2963
2964	/*
2965	* There is no support for SGLs for metadata (yet), so we are limited to
2966	* a single integrity segment for the separate metadata pointer.
2967	*/
2968	dev->ctrl.max_integrity_segments = 1;
2969	return dev;
2970
2971	out_put_device:
2972	put_device(dev: dev->dev);
2973	kfree(objp: dev->queues);
2974	out_free_dev:
2975	kfree(objp: dev);
2976	return ERR_PTR(error: ret);
2977	}
2978
2979	static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2980	{
2981	struct nvme_dev *dev;
2982	int result = -ENOMEM;
2983
2984	dev = nvme_pci_alloc_dev(pdev, id);
2985	if (IS_ERR(ptr: dev))
2986	return PTR_ERR(ptr: dev);
2987
2988	result = nvme_dev_map(dev);
2989	if (result)
2990	goto out_uninit_ctrl;
2991
2992	result = nvme_setup_prp_pools(dev);
2993	if (result)
2994	goto out_dev_unmap;
2995
2996	result = nvme_pci_alloc_iod_mempool(dev);
2997	if (result)
2998	goto out_release_prp_pools;
2999
3000	dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
3001
3002	result = nvme_pci_enable(dev);
3003	if (result)
3004	goto out_release_iod_mempool;
3005
3006	result = nvme_alloc_admin_tag_set(ctrl: &dev->ctrl, set: &dev->admin_tagset,
3007	ops: &nvme_mq_admin_ops, cmd_size: sizeof(struct nvme_iod));
3008	if (result)
3009	goto out_disable;
3010
3011	/*
3012	* Mark the controller as connecting before sending admin commands to
3013	* allow the timeout handler to do the right thing.
3014	*/
3015	if (!nvme_change_ctrl_state(ctrl: &dev->ctrl, new_state: NVME_CTRL_CONNECTING)) {
3016	dev_warn(dev->ctrl.device,
3017	"failed to mark controller CONNECTING\n");
3018	result = -EBUSY;
3019	goto out_disable;
3020	}
3021
3022	result = nvme_init_ctrl_finish(ctrl: &dev->ctrl, was_suspended: false);
3023	if (result)
3024	goto out_disable;
3025
3026	nvme_dbbuf_dma_alloc(dev);
3027
3028	result = nvme_setup_host_mem(dev);
3029	if (result < 0)
3030	goto out_disable;
3031
3032	result = nvme_setup_io_queues(dev);
3033	if (result)
3034	goto out_disable;
3035
3036	if (dev->online_queues > 1) {
3037	nvme_alloc_io_tag_set(ctrl: &dev->ctrl, set: &dev->tagset, ops: &nvme_mq_ops,
3038	nr_maps: nvme_pci_nr_maps(dev), cmd_size: sizeof(struct nvme_iod));
3039	nvme_dbbuf_set(dev);
3040	}
3041
3042	if (!dev->ctrl.tagset)
3043	dev_warn(dev->ctrl.device, "IO queues not created\n");
3044
3045	if (!nvme_change_ctrl_state(ctrl: &dev->ctrl, new_state: NVME_CTRL_LIVE)) {
3046	dev_warn(dev->ctrl.device,
3047	"failed to mark controller live state\n");
3048	result = -ENODEV;
3049	goto out_disable;
3050	}
3051
3052	pci_set_drvdata(pdev, data: dev);
3053
3054	nvme_start_ctrl(ctrl: &dev->ctrl);
3055	nvme_put_ctrl(ctrl: &dev->ctrl);
3056	flush_work(work: &dev->ctrl.scan_work);
3057	return 0;
3058
3059	out_disable:
3060	nvme_change_ctrl_state(ctrl: &dev->ctrl, new_state: NVME_CTRL_DELETING);
3061	nvme_dev_disable(dev, shutdown: true);
3062	nvme_free_host_mem(dev);
3063	nvme_dev_remove_admin(dev);
3064	nvme_dbbuf_dma_free(dev);
3065	nvme_free_queues(dev, lowest: 0);
3066	out_release_iod_mempool:
3067	mempool_destroy(pool: dev->iod_mempool);
3068	out_release_prp_pools:
3069	nvme_release_prp_pools(dev);
3070	out_dev_unmap:
3071	nvme_dev_unmap(dev);
3072	out_uninit_ctrl:
3073	nvme_uninit_ctrl(ctrl: &dev->ctrl);
3074	nvme_put_ctrl(ctrl: &dev->ctrl);
3075	return result;
3076	}
3077
3078	static void nvme_reset_prepare(struct pci_dev *pdev)
3079	{
3080	struct nvme_dev *dev = pci_get_drvdata(pdev);
3081
3082	/*
3083	* We don't need to check the return value from waiting for the reset
3084	* state as pci_dev device lock is held, making it impossible to race
3085	* with ->remove().
3086	*/
3087	nvme_disable_prepare_reset(dev, shutdown: false);
3088	nvme_sync_queues(ctrl: &dev->ctrl);
3089	}
3090
3091	static void nvme_reset_done(struct pci_dev *pdev)
3092	{
3093	struct nvme_dev *dev = pci_get_drvdata(pdev);
3094
3095	if (!nvme_try_sched_reset(ctrl: &dev->ctrl))
3096	flush_work(work: &dev->ctrl.reset_work);
3097	}
3098
3099	static void nvme_shutdown(struct pci_dev *pdev)
3100	{
3101	struct nvme_dev *dev = pci_get_drvdata(pdev);
3102
3103	nvme_disable_prepare_reset(dev, shutdown: true);
3104	}
3105
3106	/*
3107	* The driver's remove may be called on a device in a partially initialized
3108	* state. This function must not have any dependencies on the device state in
3109	* order to proceed.
3110	*/
3111	static void nvme_remove(struct pci_dev *pdev)
3112	{
3113	struct nvme_dev *dev = pci_get_drvdata(pdev);
3114
3115	nvme_change_ctrl_state(ctrl: &dev->ctrl, new_state: NVME_CTRL_DELETING);
3116	pci_set_drvdata(pdev, NULL);
3117
3118	if (!pci_device_is_present(pdev)) {
3119	nvme_change_ctrl_state(ctrl: &dev->ctrl, new_state: NVME_CTRL_DEAD);
3120	nvme_dev_disable(dev, shutdown: true);
3121	}
3122
3123	flush_work(work: &dev->ctrl.reset_work);
3124	nvme_stop_ctrl(ctrl: &dev->ctrl);
3125	nvme_remove_namespaces(ctrl: &dev->ctrl);
3126	nvme_dev_disable(dev, shutdown: true);
3127	nvme_free_host_mem(dev);
3128	nvme_dev_remove_admin(dev);
3129	nvme_dbbuf_dma_free(dev);
3130	nvme_free_queues(dev, lowest: 0);
3131	mempool_destroy(pool: dev->iod_mempool);
3132	nvme_release_prp_pools(dev);
3133	nvme_dev_unmap(dev);
3134	nvme_uninit_ctrl(ctrl: &dev->ctrl);
3135	}
3136
3137	#ifdef CONFIG_PM_SLEEP
3138	static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
3139	{
3140	return nvme_get_features(dev: ctrl, fid: NVME_FEAT_POWER_MGMT, dword11: 0, NULL, buflen: 0, result: ps);
3141	}
3142
3143	static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
3144	{
3145	return nvme_set_features(dev: ctrl, fid: NVME_FEAT_POWER_MGMT, dword11: ps, NULL, buflen: 0, NULL);
3146	}
3147
3148	static int nvme_resume(struct device *dev)
3149	{
3150	struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3151	struct nvme_ctrl *ctrl = &ndev->ctrl;
3152
3153	if (ndev->last_ps == U32_MAX ||
3154	nvme_set_power_state(ctrl, ps: ndev->last_ps) != 0)
3155	goto reset;
3156	if (ctrl->hmpre && nvme_setup_host_mem(dev: ndev))
3157	goto reset;
3158
3159	return 0;
3160	reset:
3161	return nvme_try_sched_reset(ctrl);
3162	}
3163
3164	static int nvme_suspend(struct device *dev)
3165	{
3166	struct pci_dev *pdev = to_pci_dev(dev);
3167	struct nvme_dev *ndev = pci_get_drvdata(pdev);
3168	struct nvme_ctrl *ctrl = &ndev->ctrl;
3169	int ret = -EBUSY;
3170
3171	ndev->last_ps = U32_MAX;
3172
3173	/*
3174	* The platform does not remove power for a kernel managed suspend so
3175	* use host managed nvme power settings for lowest idle power if
3176	* possible. This should have quicker resume latency than a full device
3177	* shutdown. But if the firmware is involved after the suspend or the
3178	* device does not support any non-default power states, shut down the
3179	* device fully.
3180	*
3181	* If ASPM is not enabled for the device, shut down the device and allow
3182	* the PCI bus layer to put it into D3 in order to take the PCIe link
3183	* down, so as to allow the platform to achieve its minimum low-power
3184	* state (which may not be possible if the link is up).
3185	*/
3186	if (pm_suspend_via_firmware() || !ctrl->npss ||
3187	!pcie_aspm_enabled(pdev) ||
3188	(ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
3189	return nvme_disable_prepare_reset(dev: ndev, shutdown: true);
3190
3191	nvme_start_freeze(ctrl);
3192	nvme_wait_freeze(ctrl);
3193	nvme_sync_queues(ctrl);
3194
3195	if (ctrl->state != NVME_CTRL_LIVE)
3196	goto unfreeze;
3197
3198	/*
3199	* Host memory access may not be successful in a system suspend state,
3200	* but the specification allows the controller to access memory in a
3201	* non-operational power state.
3202	*/
3203	if (ndev->hmb) {
3204	ret = nvme_set_host_mem(dev: ndev, bits: 0);
3205	if (ret < 0)
3206	goto unfreeze;
3207	}
3208
3209	ret = nvme_get_power_state(ctrl, ps: &ndev->last_ps);
3210	if (ret < 0)
3211	goto unfreeze;
3212
3213	/*
3214	* A saved state prevents pci pm from generically controlling the
3215	* device's power. If we're using protocol specific settings, we don't
3216	* want pci interfering.
3217	*/
3218	pci_save_state(dev: pdev);
3219
3220	ret = nvme_set_power_state(ctrl, ps: ctrl->npss);
3221	if (ret < 0)
3222	goto unfreeze;
3223
3224	if (ret) {
3225	/* discard the saved state */
3226	pci_load_saved_state(dev: pdev, NULL);
3227
3228	/*
3229	* Clearing npss forces a controller reset on resume. The
3230	* correct value will be rediscovered then.
3231	*/
3232	ret = nvme_disable_prepare_reset(dev: ndev, shutdown: true);
3233	ctrl->npss = 0;
3234	}
3235	unfreeze:
3236	nvme_unfreeze(ctrl);
3237	return ret;
3238	}
3239
3240	static int nvme_simple_suspend(struct device *dev)
3241	{
3242	struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3243
3244	return nvme_disable_prepare_reset(dev: ndev, shutdown: true);
3245	}
3246
3247	static int nvme_simple_resume(struct device *dev)
3248	{
3249	struct pci_dev *pdev = to_pci_dev(dev);
3250	struct nvme_dev *ndev = pci_get_drvdata(pdev);
3251
3252	return nvme_try_sched_reset(ctrl: &ndev->ctrl);
3253	}
3254
3255	static const struct dev_pm_ops nvme_dev_pm_ops = {
3256	.suspend = nvme_suspend,
3257	.resume = nvme_resume,
3258	.freeze = nvme_simple_suspend,
3259	.thaw = nvme_simple_resume,
3260	.poweroff = nvme_simple_suspend,
3261	.restore = nvme_simple_resume,
3262	};
3263	#endif /* CONFIG_PM_SLEEP */
3264
3265	static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3266	pci_channel_state_t state)
3267	{
3268	struct nvme_dev *dev = pci_get_drvdata(pdev);
3269
3270	/*
3271	* A frozen channel requires a reset. When detected, this method will
3272	* shutdown the controller to quiesce. The controller will be restarted
3273	* after the slot reset through driver's slot_reset callback.
3274	*/
3275	switch (state) {
3276	case pci_channel_io_normal:
3277	return PCI_ERS_RESULT_CAN_RECOVER;
3278	case pci_channel_io_frozen:
3279	dev_warn(dev->ctrl.device,
3280	"frozen state error detected, reset controller\n");
3281	if (!nvme_change_ctrl_state(ctrl: &dev->ctrl, new_state: NVME_CTRL_RESETTING)) {
3282	nvme_dev_disable(dev, shutdown: true);
3283	return PCI_ERS_RESULT_DISCONNECT;
3284	}
3285	nvme_dev_disable(dev, shutdown: false);
3286	return PCI_ERS_RESULT_NEED_RESET;
3287	case pci_channel_io_perm_failure:
3288	dev_warn(dev->ctrl.device,
3289	"failure state error detected, request disconnect\n");
3290	return PCI_ERS_RESULT_DISCONNECT;
3291	}
3292	return PCI_ERS_RESULT_NEED_RESET;
3293	}
3294
3295	static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3296	{
3297	struct nvme_dev *dev = pci_get_drvdata(pdev);
3298
3299	dev_info(dev->ctrl.device, "restart after slot reset\n");
3300	pci_restore_state(dev: pdev);
3301	if (!nvme_try_sched_reset(ctrl: &dev->ctrl))
3302	nvme_unquiesce_io_queues(ctrl: &dev->ctrl);
3303	return PCI_ERS_RESULT_RECOVERED;
3304	}
3305
3306	static void nvme_error_resume(struct pci_dev *pdev)
3307	{
3308	struct nvme_dev *dev = pci_get_drvdata(pdev);
3309
3310	flush_work(work: &dev->ctrl.reset_work);
3311	}
3312
3313	static const struct pci_error_handlers nvme_err_handler = {
3314	.error_detected = nvme_error_detected,
3315	.slot_reset = nvme_slot_reset,
3316	.resume = nvme_error_resume,
3317	.reset_prepare = nvme_reset_prepare,
3318	.reset_done = nvme_reset_done,
3319	};
3320
3321	static const struct pci_device_id nvme_id_table[] = {
3322	{ PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */
3323	.driver_data = NVME_QUIRK_STRIPE_SIZE |
3324	NVME_QUIRK_DEALLOCATE_ZEROES, },
3325	{ PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */
3326	.driver_data = NVME_QUIRK_STRIPE_SIZE |
3327	NVME_QUIRK_DEALLOCATE_ZEROES, },
3328	{ PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */
3329	.driver_data = NVME_QUIRK_STRIPE_SIZE |
3330	NVME_QUIRK_DEALLOCATE_ZEROES |
3331	NVME_QUIRK_IGNORE_DEV_SUBNQN |
3332	NVME_QUIRK_BOGUS_NID, },
3333	{ PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */
3334	.driver_data = NVME_QUIRK_STRIPE_SIZE |
3335	NVME_QUIRK_DEALLOCATE_ZEROES, },
3336	{ PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
3337	.driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3338	NVME_QUIRK_MEDIUM_PRIO_SQ |
3339	NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
3340	NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3341	{ PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
3342	.driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3343	{ PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
3344	.driver_data = NVME_QUIRK_IDENTIFY_CNS |
3345	NVME_QUIRK_DISABLE_WRITE_ZEROES |
3346	NVME_QUIRK_BOGUS_NID, },
3347	{ PCI_VDEVICE(REDHAT, 0x0010), /* Qemu emulated controller */
3348	.driver_data = NVME_QUIRK_BOGUS_NID, },
3349	{ PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */
3350	.driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3351	NVME_QUIRK_BOGUS_NID, },
3352	{ PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
3353	.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3354	NVME_QUIRK_NO_NS_DESC_LIST, },
3355	{ PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
3356	.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3357	{ PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
3358	.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3359	{ PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
3360	.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3361	{ PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
3362	.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3363	{ PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
3364	.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3365	NVME_QUIRK_DISABLE_WRITE_ZEROES|
3366	NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3367	{ PCI_DEVICE(0x1987, 0x5012), /* Phison E12 */
3368	.driver_data = NVME_QUIRK_BOGUS_NID, },
3369	{ PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */
3370	.driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
3371	NVME_QUIRK_BOGUS_NID, },
3372	{ PCI_DEVICE(0x1987, 0x5019), /* phison E19 */
3373	.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3374	{ PCI_DEVICE(0x1987, 0x5021), /* Phison E21 */
3375	.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3376	{ PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */
3377	.driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3378	NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3379	{ PCI_DEVICE(0x1cc1, 0x33f8), /* ADATA IM2P33F8ABR1 1 TB */
3380	.driver_data = NVME_QUIRK_BOGUS_NID, },
3381	{ PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */
3382	.driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
3383	NVME_QUIRK_BOGUS_NID, },
3384	{ PCI_DEVICE(0x10ec, 0x5763), /* ADATA SX6000PNP */
3385	.driver_data = NVME_QUIRK_BOGUS_NID, },
3386	{ PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */
3387	.driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3388	NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3389	{ PCI_DEVICE(0x1344, 0x5407), /* Micron Technology Inc NVMe SSD */
3390	.driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN },
3391	{ PCI_DEVICE(0x1344, 0x6001), /* Micron Nitro NVMe */
3392	.driver_data = NVME_QUIRK_BOGUS_NID, },
3393	{ PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */
3394	.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3395	{ PCI_DEVICE(0x1c5c, 0x174a), /* SK Hynix P31 SSD */
3396	.driver_data = NVME_QUIRK_BOGUS_NID, },
3397	{ PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */
3398	.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3399	{ PCI_DEVICE(0x1d97, 0x2263), /* SPCC */
3400	.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3401	{ PCI_DEVICE(0x144d, 0xa80b), /* Samsung PM9B1 256G and 512G */
3402	.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES |
3403	NVME_QUIRK_BOGUS_NID, },
3404	{ PCI_DEVICE(0x144d, 0xa809), /* Samsung MZALQ256HBJD 256G */
3405	.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3406	{ PCI_DEVICE(0x144d, 0xa802), /* Samsung SM953 */
3407	.driver_data = NVME_QUIRK_BOGUS_NID, },
3408	{ PCI_DEVICE(0x1cc4, 0x6303), /* UMIS RPJTJ512MGE1QDY 512G */
3409	.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3410	{ PCI_DEVICE(0x1cc4, 0x6302), /* UMIS RPJTJ256MGE1QDY 256G */
3411	.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3412	{ PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */
3413	.driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3414	{ PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */
3415	.driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3416	{ PCI_DEVICE(0x2646, 0x5013), /* Kingston KC3000, Kingston FURY Renegade */
3417	.driver_data = NVME_QUIRK_NO_SECONDARY_TEMP_THRESH, },
3418	{ PCI_DEVICE(0x2646, 0x5018), /* KINGSTON OM8SFP4xxxxP OS21012 NVMe SSD */
3419	.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3420	{ PCI_DEVICE(0x2646, 0x5016), /* KINGSTON OM3PGP4xxxxP OS21011 NVMe SSD */
3421	.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3422	{ PCI_DEVICE(0x2646, 0x501A), /* KINGSTON OM8PGP4xxxxP OS21005 NVMe SSD */
3423	.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3424	{ PCI_DEVICE(0x2646, 0x501B), /* KINGSTON OM8PGP4xxxxQ OS21005 NVMe SSD */
3425	.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3426	{ PCI_DEVICE(0x2646, 0x501E), /* KINGSTON OM3PGP4xxxxQ OS21011 NVMe SSD */
3427	.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3428	{ PCI_DEVICE(0x1f40, 0x1202), /* Netac Technologies Co. NV3000 NVMe SSD */
3429	.driver_data = NVME_QUIRK_BOGUS_NID, },
3430	{ PCI_DEVICE(0x1f40, 0x5236), /* Netac Technologies Co. NV7000 NVMe SSD */
3431	.driver_data = NVME_QUIRK_BOGUS_NID, },
3432	{ PCI_DEVICE(0x1e4B, 0x1001), /* MAXIO MAP1001 */
3433	.driver_data = NVME_QUIRK_BOGUS_NID, },
3434	{ PCI_DEVICE(0x1e4B, 0x1002), /* MAXIO MAP1002 */
3435	.driver_data = NVME_QUIRK_BOGUS_NID, },
3436	{ PCI_DEVICE(0x1e4B, 0x1202), /* MAXIO MAP1202 */
3437	.driver_data = NVME_QUIRK_BOGUS_NID, },
3438	{ PCI_DEVICE(0x1e4B, 0x1602), /* MAXIO MAP1602 */
3439	.driver_data = NVME_QUIRK_BOGUS_NID, },
3440	{ PCI_DEVICE(0x1cc1, 0x5350), /* ADATA XPG GAMMIX S50 */
3441	.driver_data = NVME_QUIRK_BOGUS_NID, },
3442	{ PCI_DEVICE(0x1dbe, 0x5236), /* ADATA XPG GAMMIX S70 */
3443	.driver_data = NVME_QUIRK_BOGUS_NID, },
3444	{ PCI_DEVICE(0x1e49, 0x0021), /* ZHITAI TiPro5000 NVMe SSD */
3445	.driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3446	{ PCI_DEVICE(0x1e49, 0x0041), /* ZHITAI TiPro7000 NVMe SSD */
3447	.driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3448	{ PCI_DEVICE(0xc0a9, 0x540a), /* Crucial P2 */
3449	.driver_data = NVME_QUIRK_BOGUS_NID, },
3450	{ PCI_DEVICE(0x1d97, 0x2263), /* Lexar NM610 */
3451	.driver_data = NVME_QUIRK_BOGUS_NID, },
3452	{ PCI_DEVICE(0x1d97, 0x1d97), /* Lexar NM620 */
3453	.driver_data = NVME_QUIRK_BOGUS_NID, },
3454	{ PCI_DEVICE(0x1d97, 0x2269), /* Lexar NM760 */
3455	.driver_data = NVME_QUIRK_BOGUS_NID |
3456	NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3457	{ PCI_DEVICE(0x10ec, 0x5763), /* TEAMGROUP T-FORCE CARDEA ZERO Z330 SSD */
3458	.driver_data = NVME_QUIRK_BOGUS_NID, },
3459	{ PCI_DEVICE(0x1e4b, 0x1602), /* HS-SSD-FUTURE 2048G */
3460	.driver_data = NVME_QUIRK_BOGUS_NID, },
3461	{ PCI_DEVICE(0x10ec, 0x5765), /* TEAMGROUP MP33 2TB SSD */
3462	.driver_data = NVME_QUIRK_BOGUS_NID, },
3463	{ PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061),
3464	.driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3465	{ PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065),
3466	.driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3467	{ PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061),
3468	.driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3469	{ PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00),
3470	.driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3471	{ PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01),
3472	.driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3473	{ PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02),
3474	.driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3475	{ PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3476	.driver_data = NVME_QUIRK_SINGLE_VECTOR },
3477	{ PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
3478	{ PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3479	.driver_data = NVME_QUIRK_SINGLE_VECTOR |
3480	NVME_QUIRK_128_BYTES_SQES |
3481	NVME_QUIRK_SHARED_TAGS |
3482	NVME_QUIRK_SKIP_CID_GEN |
3483	NVME_QUIRK_IDENTIFY_CNS },
3484	{ PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3485	{ 0, }
3486	};
3487	MODULE_DEVICE_TABLE(pci, nvme_id_table);
3488
3489	static struct pci_driver nvme_driver = {
3490	.name = "nvme",
3491	.id_table = nvme_id_table,
3492	.probe = nvme_probe,
3493	.remove = nvme_remove,
3494	.shutdown = nvme_shutdown,
3495	.driver = {
3496	.probe_type = PROBE_PREFER_ASYNCHRONOUS,
3497	#ifdef CONFIG_PM_SLEEP
3498	.pm = &nvme_dev_pm_ops,
3499	#endif
3500	},
3501	.sriov_configure = pci_sriov_configure_simple,
3502	.err_handler = &nvme_err_handler,
3503	};
3504
3505	static int __init nvme_init(void)
3506	{
3507	BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3508	BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3509	BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
3510	BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
3511	BUILD_BUG_ON(NVME_MAX_SEGS > SGES_PER_PAGE);
3512	BUILD_BUG_ON(sizeof(struct scatterlist) * NVME_MAX_SEGS > PAGE_SIZE);
3513	BUILD_BUG_ON(nvme_pci_npages_prp() > NVME_MAX_NR_ALLOCATIONS);
3514
3515	return pci_register_driver(&nvme_driver);
3516	}
3517
3518	static void __exit nvme_exit(void)
3519	{
3520	pci_unregister_driver(dev: &nvme_driver);
3521	flush_workqueue(nvme_wq);
3522	}
3523
3524	MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3525	MODULE_LICENSE("GPL");
3526	MODULE_VERSION("1.0");
3527	module_init(nvme_init);
3528	module_exit(nvme_exit);
3529