Warning: That file was not part of the compilation database. It may have many parsing errors.

1/*
2** I/O Sapic Driver - PCI interrupt line support
3**
4** (c) Copyright 1999 Grant Grundler
5** (c) Copyright 1999 Hewlett-Packard Company
6**
7** This program is free software; you can redistribute it and/or modify
8** it under the terms of the GNU General Public License as published by
9** the Free Software Foundation; either version 2 of the License, or
10** (at your option) any later version.
11**
12** The I/O sapic driver manages the Interrupt Redirection Table which is
13** the control logic to convert PCI line based interrupts into a Message
14** Signaled Interrupt (aka Transaction Based Interrupt, TBI).
15**
16** Acronyms
17** --------
18** HPA Hard Physical Address (aka MMIO address)
19** IRQ Interrupt ReQuest. Implies Line based interrupt.
20** IRT Interrupt Routing Table (provided by PAT firmware)
21** IRdT Interrupt Redirection Table. IRQ line to TXN ADDR/DATA
22** table which is implemented in I/O SAPIC.
23** ISR Interrupt Service Routine. aka Interrupt handler.
24** MSI Message Signaled Interrupt. PCI 2.2 functionality.
25** aka Transaction Based Interrupt (or TBI).
26** PA Precision Architecture. HP's RISC architecture.
27** RISC Reduced Instruction Set Computer.
28**
29**
30** What's a Message Signalled Interrupt?
31** -------------------------------------
32** MSI is a write transaction which targets a processor and is similar
33** to a processor write to memory or MMIO. MSIs can be generated by I/O
34** devices as well as processors and require *architecture* to work.
35**
36** PA only supports MSI. So I/O subsystems must either natively generate
37** MSIs (e.g. GSC or HP-PB) or convert line based interrupts into MSIs
38** (e.g. PCI and EISA). IA64 supports MSIs via a "local SAPIC" which
39** acts on behalf of a processor.
40**
41** MSI allows any I/O device to interrupt any processor. This makes
42** load balancing of the interrupt processing possible on an SMP platform.
43** Interrupts are also ordered WRT to DMA data. It's possible on I/O
44** coherent systems to completely eliminate PIO reads from the interrupt
45** path. The device and driver must be designed and implemented to
46** guarantee all DMA has been issued (issues about atomicity here)
47** before the MSI is issued. I/O status can then safely be read from
48** DMA'd data by the ISR.
49**
50**
51** PA Firmware
52** -----------
53** PA-RISC platforms have two fundamentally different types of firmware.
54** For PCI devices, "Legacy" PDC initializes the "INTERRUPT_LINE" register
55** and BARs similar to a traditional PC BIOS.
56** The newer "PAT" firmware supports PDC calls which return tables.
57** PAT firmware only initializes the PCI Console and Boot interface.
58** With these tables, the OS can program all other PCI devices.
59**
60** One such PAT PDC call returns the "Interrupt Routing Table" (IRT).
61** The IRT maps each PCI slot's INTA-D "output" line to an I/O SAPIC
62** input line. If the IRT is not available, this driver assumes
63** INTERRUPT_LINE register has been programmed by firmware. The latter
64** case also means online addition of PCI cards can NOT be supported
65** even if HW support is present.
66**
67** All platforms with PAT firmware to date (Oct 1999) use one Interrupt
68** Routing Table for the entire platform.
69**
70** Where's the iosapic?
71** --------------------
72** I/O sapic is part of the "Core Electronics Complex". And on HP platforms
73** it's integrated as part of the PCI bus adapter, "lba". So no bus walk
74** will discover I/O Sapic. I/O Sapic driver learns about each device
75** when lba driver advertises the presence of the I/O sapic by calling
76** iosapic_register().
77**
78**
79** IRQ handling notes
80** ------------------
81** The IO-SAPIC can indicate to the CPU which interrupt was asserted.
82** So, unlike the GSC-ASIC and Dino, we allocate one CPU interrupt per
83** IO-SAPIC interrupt and call the device driver's handler directly.
84** The IO-SAPIC driver hijacks the CPU interrupt handler so it can
85** issue the End Of Interrupt command to the IO-SAPIC.
86**
87** Overview of exported iosapic functions
88** --------------------------------------
89** (caveat: code isn't finished yet - this is just the plan)
90**
91** iosapic_init:
92** o initialize globals (lock, etc)
93** o try to read IRT. Presence of IRT determines if this is
94** a PAT platform or not.
95**
96** iosapic_register():
97** o create iosapic_info instance data structure
98** o allocate vector_info array for this iosapic
99** o initialize vector_info - read corresponding IRdT?
100**
101** iosapic_xlate_pin: (only called by fixup_irq for PAT platform)
102** o intr_pin = read cfg (INTERRUPT_PIN);
103** o if (device under PCI-PCI bridge)
104** translate slot/pin
105**
106** iosapic_fixup_irq:
107** o if PAT platform (IRT present)
108** intr_pin = iosapic_xlate_pin(isi,pcidev):
109** intr_line = find IRT entry(isi, PCI_SLOT(pcidev), intr_pin)
110** save IRT entry into vector_info later
111** write cfg INTERRUPT_LINE (with intr_line)?
112** else
113** intr_line = pcidev->irq
114** IRT pointer = NULL
115** endif
116** o locate vector_info (needs: isi, intr_line)
117** o allocate processor "irq" and get txn_addr/data
118** o request_irq(processor_irq, iosapic_interrupt, vector_info,...)
119**
120** iosapic_enable_irq:
121** o clear any pending IRQ on that line
122** o enable IRdT - call enable_irq(vector[line]->processor_irq)
123** o write EOI in case line is already asserted.
124**
125** iosapic_disable_irq:
126** o disable IRdT - call disable_irq(vector[line]->processor_irq)
127*/
128
129#include <linux/pci.h>
130
131#include <asm/pdc.h>
132#include <asm/pdcpat.h>
133#ifdef CONFIG_SUPERIO
134#include <asm/superio.h>
135#endif
136
137#include <asm/ropes.h>
138#include "iosapic_private.h"
139
140#define MODULE_NAME "iosapic"
141
142/* "local" compile flags */
143#undef PCI_BRIDGE_FUNCS
144#undef DEBUG_IOSAPIC
145#undef DEBUG_IOSAPIC_IRT
146
147
148#ifdef DEBUG_IOSAPIC
149#define DBG(x...) printk(x)
150#else /* DEBUG_IOSAPIC */
151#define DBG(x...)
152#endif /* DEBUG_IOSAPIC */
153
154#ifdef DEBUG_IOSAPIC_IRT
155#define DBG_IRT(x...) printk(x)
156#else
157#define DBG_IRT(x...)
158#endif
159
160#define COMPARE_IRTE_ADDR(irte, hpa) \
161 ((irte)->dest_iosapic_addr == F_EXTEND(hpa))
162
163#define IOSAPIC_REG_SELECT 0x00
164#define IOSAPIC_REG_WINDOW 0x10
165#define IOSAPIC_REG_EOI 0x40
166
167#define IOSAPIC_REG_VERSION 0x1
168
169#define IOSAPIC_IRDT_ENTRY(idx) (0x10+(idx)*2)
170#define IOSAPIC_IRDT_ENTRY_HI(idx) (0x11+(idx)*2)
171
172static inline unsigned int iosapic_read(void __iomem *iosapic, unsigned int reg)
173{
174 writel(reg, iosapic + IOSAPIC_REG_SELECT);
175 return readl(iosapic + IOSAPIC_REG_WINDOW);
176}
177
178static inline void iosapic_write(void __iomem *iosapic, unsigned int reg, u32 val)
179{
180 writel(reg, iosapic + IOSAPIC_REG_SELECT);
181 writel(val, iosapic + IOSAPIC_REG_WINDOW);
182}
183
184#define IOSAPIC_VERSION_MASK 0x000000ff
185#define IOSAPIC_VERSION(ver) ((int) (ver & IOSAPIC_VERSION_MASK))
186
187#define IOSAPIC_MAX_ENTRY_MASK 0x00ff0000
188#define IOSAPIC_MAX_ENTRY_SHIFT 0x10
189#define IOSAPIC_IRDT_MAX_ENTRY(ver) \
190 (int) (((ver) & IOSAPIC_MAX_ENTRY_MASK) >> IOSAPIC_MAX_ENTRY_SHIFT)
191
192/* bits in the "low" I/O Sapic IRdT entry */
193#define IOSAPIC_IRDT_ENABLE 0x10000
194#define IOSAPIC_IRDT_PO_LOW 0x02000
195#define IOSAPIC_IRDT_LEVEL_TRIG 0x08000
196#define IOSAPIC_IRDT_MODE_LPRI 0x00100
197
198/* bits in the "high" I/O Sapic IRdT entry */
199#define IOSAPIC_IRDT_ID_EID_SHIFT 0x10
200
201
202static DEFINE_SPINLOCK(iosapic_lock);
203
204static inline void iosapic_eoi(void __iomem *addr, unsigned int data)
205{
206 __raw_writel(data, addr);
207}
208
209/*
210** REVISIT: future platforms may have more than one IRT.
211** If so, the following three fields form a structure which
212** then be linked into a list. Names are chosen to make searching
213** for them easy - not necessarily accurate (eg "cell").
214**
215** Alternative: iosapic_info could point to the IRT it's in.
216** iosapic_register() could search a list of IRT's.
217*/
218static struct irt_entry *irt_cell;
219static size_t irt_num_entry;
220
221static struct irt_entry *iosapic_alloc_irt(int num_entries)
222{
223 unsigned long a;
224
225 /* The IRT needs to be 8-byte aligned for the PDC call.
226 * Normally kmalloc would guarantee larger alignment, but
227 * if CONFIG_DEBUG_SLAB is enabled, then we can get only
228 * 4-byte alignment on 32-bit kernels
229 */
230 a = (unsigned long)kmalloc(sizeof(struct irt_entry) * num_entries + 8, GFP_KERNEL);
231 a = (a + 7UL) & ~7UL;
232 return (struct irt_entry *)a;
233}
234
235/**
236 * iosapic_load_irt - Fill in the interrupt routing table
237 * @cell_num: The cell number of the CPU we're currently executing on
238 * @irt: The address to place the new IRT at
239 * @return The number of entries found
240 *
241 * The "Get PCI INT Routing Table Size" option returns the number of
242 * entries in the PCI interrupt routing table for the cell specified
243 * in the cell_number argument. The cell number must be for a cell
244 * within the caller's protection domain.
245 *
246 * The "Get PCI INT Routing Table" option returns, for the cell
247 * specified in the cell_number argument, the PCI interrupt routing
248 * table in the caller allocated memory pointed to by mem_addr.
249 * We assume the IRT only contains entries for I/O SAPIC and
250 * calculate the size based on the size of I/O sapic entries.
251 *
252 * The PCI interrupt routing table entry format is derived from the
253 * IA64 SAL Specification 2.4. The PCI interrupt routing table defines
254 * the routing of PCI interrupt signals between the PCI device output
255 * "pins" and the IO SAPICs' input "lines" (including core I/O PCI
256 * devices). This table does NOT include information for devices/slots
257 * behind PCI to PCI bridges. See PCI to PCI Bridge Architecture Spec.
258 * for the architected method of routing of IRQ's behind PPB's.
259 */
260
261
262static int __init
263iosapic_load_irt(unsigned long cell_num, struct irt_entry **irt)
264{
265 long status; /* PDC return value status */
266 struct irt_entry *table; /* start of interrupt routing tbl */
267 unsigned long num_entries = 0UL;
268
269 BUG_ON(!irt);
270
271 if (is_pdc_pat()) {
272 /* Use pat pdc routine to get interrupt routing table size */
273 DBG("calling get_irt_size (cell %ld)\n", cell_num);
274 status = pdc_pat_get_irt_size(&num_entries, cell_num);
275 DBG("get_irt_size: %ld\n", status);
276
277 BUG_ON(status != PDC_OK);
278 BUG_ON(num_entries == 0);
279
280 /*
281 ** allocate memory for interrupt routing table
282 ** This interface isn't really right. We are assuming
283 ** the contents of the table are exclusively
284 ** for I/O sapic devices.
285 */
286 table = iosapic_alloc_irt(num_entries);
287 if (table == NULL) {
288 printk(KERN_WARNING MODULE_NAME ": read_irt : can "
289 "not alloc mem for IRT\n");
290 return 0;
291 }
292
293 /* get PCI INT routing table */
294 status = pdc_pat_get_irt(table, cell_num);
295 DBG("pdc_pat_get_irt: %ld\n", status);
296 WARN_ON(status != PDC_OK);
297 } else {
298 /*
299 ** C3000/J5000 (and similar) platforms with Sprockets PDC
300 ** will return exactly one IRT for all iosapics.
301 ** So if we have one, don't need to get it again.
302 */
303 if (irt_cell)
304 return 0;
305
306 /* Should be using the Elroy's HPA, but it's ignored anyway */
307 status = pdc_pci_irt_size(&num_entries, 0);
308 DBG("pdc_pci_irt_size: %ld\n", status);
309
310 if (status != PDC_OK) {
311 /* Not a "legacy" system with I/O SAPIC either */
312 return 0;
313 }
314
315 BUG_ON(num_entries == 0);
316
317 table = iosapic_alloc_irt(num_entries);
318 if (!table) {
319 printk(KERN_WARNING MODULE_NAME ": read_irt : can "
320 "not alloc mem for IRT\n");
321 return 0;
322 }
323
324 /* HPA ignored by this call too. */
325 status = pdc_pci_irt(num_entries, 0, table);
326 BUG_ON(status != PDC_OK);
327 }
328
329 /* return interrupt table address */
330 *irt = table;
331
332#ifdef DEBUG_IOSAPIC_IRT
333{
334 struct irt_entry *p = table;
335 int i;
336
337 printk(MODULE_NAME " Interrupt Routing Table (cell %ld)\n", cell_num);
338 printk(MODULE_NAME " start = 0x%p num_entries %ld entry_size %d\n",
339 table,
340 num_entries,
341 (int) sizeof(struct irt_entry));
342
343 for (i = 0 ; i < num_entries ; i++, p++) {
344 printk(MODULE_NAME " %02x %02x %02x %02x %02x %02x %02x %02x %08x%08x\n",
345 p->entry_type, p->entry_length, p->interrupt_type,
346 p->polarity_trigger, p->src_bus_irq_devno, p->src_bus_id,
347 p->src_seg_id, p->dest_iosapic_intin,
348 ((u32 *) p)[2],
349 ((u32 *) p)[3]
350 );
351 }
352}
353#endif /* DEBUG_IOSAPIC_IRT */
354
355 return num_entries;
356}
357
358
359
360void __init iosapic_init(void)
361{
362 unsigned long cell = 0;
363
364 DBG("iosapic_init()\n");
365
366#ifdef __LP64__
367 if (is_pdc_pat()) {
368 int status;
369 struct pdc_pat_cell_num cell_info;
370
371 status = pdc_pat_cell_get_number(&cell_info);
372 if (status == PDC_OK) {
373 cell = cell_info.cell_num;
374 }
375 }
376#endif
377
378 /* get interrupt routing table for this cell */
379 irt_num_entry = iosapic_load_irt(cell, &irt_cell);
380 if (irt_num_entry == 0)
381 irt_cell = NULL; /* old PDC w/o iosapic */
382}
383
384
385/*
386** Return the IRT entry in case we need to look something else up.
387*/
388static struct irt_entry *
389irt_find_irqline(struct iosapic_info *isi, u8 slot, u8 intr_pin)
390{
391 struct irt_entry *i = irt_cell;
392 int cnt; /* track how many entries we've looked at */
393 u8 irq_devno = (slot << IRT_DEV_SHIFT) | (intr_pin-1);
394
395 DBG_IRT("irt_find_irqline() SLOT %d pin %d\n", slot, intr_pin);
396
397 for (cnt=0; cnt < irt_num_entry; cnt++, i++) {
398
399 /*
400 ** Validate: entry_type, entry_length, interrupt_type
401 **
402 ** Difference between validate vs compare is the former
403 ** should print debug info and is not expected to "fail"
404 ** on current platforms.
405 */
406 if (i->entry_type != IRT_IOSAPIC_TYPE) {
407 DBG_IRT(KERN_WARNING MODULE_NAME ":find_irqline(0x%p): skipping entry %d type %d\n", i, cnt, i->entry_type);
408 continue;
409 }
410
411 if (i->entry_length != IRT_IOSAPIC_LENGTH) {
412 DBG_IRT(KERN_WARNING MODULE_NAME ":find_irqline(0x%p): skipping entry %d length %d\n", i, cnt, i->entry_length);
413 continue;
414 }
415
416 if (i->interrupt_type != IRT_VECTORED_INTR) {
417 DBG_IRT(KERN_WARNING MODULE_NAME ":find_irqline(0x%p): skipping entry %d interrupt_type %d\n", i, cnt, i->interrupt_type);
418 continue;
419 }
420
421 if (!COMPARE_IRTE_ADDR(i, isi->isi_hpa))
422 continue;
423
424 if ((i->src_bus_irq_devno & IRT_IRQ_DEVNO_MASK) != irq_devno)
425 continue;
426
427 /*
428 ** Ignore: src_bus_id and rc_seg_id correlate with
429 ** iosapic_info->isi_hpa on HP platforms.
430 ** If needed, pass in "PFA" (aka config space addr)
431 ** instead of slot.
432 */
433
434 /* Found it! */
435 return i;
436 }
437
438 printk(KERN_WARNING MODULE_NAME ": 0x%lx : no IRT entry for slot %d, pin %d\n",
439 isi->isi_hpa, slot, intr_pin);
440 return NULL;
441}
442
443
444/*
445** xlate_pin() supports the skewing of IRQ lines done by subsidiary bridges.
446** Legacy PDC already does this translation for us and stores it in INTR_LINE.
447**
448** PAT PDC needs to basically do what legacy PDC does:
449** o read PIN
450** o adjust PIN in case device is "behind" a PPB
451** (eg 4-port 100BT and SCSI/LAN "Combo Card")
452** o convert slot/pin to I/O SAPIC input line.
453**
454** HP platforms only support:
455** o one level of skewing for any number of PPBs
456** o only support PCI-PCI Bridges.
457*/
458static struct irt_entry *
459iosapic_xlate_pin(struct iosapic_info *isi, struct pci_dev *pcidev)
460{
461 u8 intr_pin, intr_slot;
462
463 pci_read_config_byte(pcidev, PCI_INTERRUPT_PIN, &intr_pin);
464
465 DBG_IRT("iosapic_xlate_pin(%s) SLOT %d pin %d\n",
466 pcidev->slot_name, PCI_SLOT(pcidev->devfn), intr_pin);
467
468 if (intr_pin == 0) {
469 /* The device does NOT support/use IRQ lines. */
470 return NULL;
471 }
472
473 /* Check if pcidev behind a PPB */
474 if (pcidev->bus->parent) {
475 /* Convert pcidev INTR_PIN into something we
476 ** can lookup in the IRT.
477 */
478#ifdef PCI_BRIDGE_FUNCS
479 /*
480 ** Proposal #1:
481 **
482 ** call implementation specific translation function
483 ** This is architecturally "cleaner". HP-UX doesn't
484 ** support other secondary bus types (eg. E/ISA) directly.
485 ** May be needed for other processor (eg IA64) architectures
486 ** or by some ambitous soul who wants to watch TV.
487 */
488 if (pci_bridge_funcs->xlate_intr_line) {
489 intr_pin = pci_bridge_funcs->xlate_intr_line(pcidev);
490 }
491#else /* PCI_BRIDGE_FUNCS */
492 struct pci_bus *p = pcidev->bus;
493 /*
494 ** Proposal #2:
495 ** The "pin" is skewed ((pin + dev - 1) % 4).
496 **
497 ** This isn't very clean since I/O SAPIC must assume:
498 ** - all platforms only have PCI busses.
499 ** - only PCI-PCI bridge (eg not PCI-EISA, PCI-PCMCIA)
500 ** - IRQ routing is only skewed once regardless of
501 ** the number of PPB's between iosapic and device.
502 ** (Bit3 expansion chassis follows this rule)
503 **
504 ** Advantage is it's really easy to implement.
505 */
506 intr_pin = pci_swizzle_interrupt_pin(pcidev, intr_pin);
507#endif /* PCI_BRIDGE_FUNCS */
508
509 /*
510 * Locate the host slot of the PPB.
511 */
512 while (p->parent->parent)
513 p = p->parent;
514
515 intr_slot = PCI_SLOT(p->self->devfn);
516 } else {
517 intr_slot = PCI_SLOT(pcidev->devfn);
518 }
519 DBG_IRT("iosapic_xlate_pin: bus %d slot %d pin %d\n",
520 pcidev->bus->busn_res.start, intr_slot, intr_pin);
521
522 return irt_find_irqline(isi, intr_slot, intr_pin);
523}
524
525static void iosapic_rd_irt_entry(struct vector_info *vi , u32 *dp0, u32 *dp1)
526{
527 struct iosapic_info *isp = vi->iosapic;
528 u8 idx = vi->irqline;
529
530 *dp0 = iosapic_read(isp->addr, IOSAPIC_IRDT_ENTRY(idx));
531 *dp1 = iosapic_read(isp->addr, IOSAPIC_IRDT_ENTRY_HI(idx));
532}
533
534
535static void iosapic_wr_irt_entry(struct vector_info *vi, u32 dp0, u32 dp1)
536{
537 struct iosapic_info *isp = vi->iosapic;
538
539 DBG_IRT("iosapic_wr_irt_entry(): irq %d hpa %lx 0x%x 0x%x\n",
540 vi->irqline, isp->isi_hpa, dp0, dp1);
541
542 iosapic_write(isp->addr, IOSAPIC_IRDT_ENTRY(vi->irqline), dp0);
543
544 /* Read the window register to flush the writes down to HW */
545 dp0 = readl(isp->addr+IOSAPIC_REG_WINDOW);
546
547 iosapic_write(isp->addr, IOSAPIC_IRDT_ENTRY_HI(vi->irqline), dp1);
548
549 /* Read the window register to flush the writes down to HW */
550 dp1 = readl(isp->addr+IOSAPIC_REG_WINDOW);
551}
552
553/*
554** set_irt prepares the data (dp0, dp1) according to the vector_info
555** and target cpu (id_eid). dp0/dp1 are then used to program I/O SAPIC
556** IRdT for the given "vector" (aka IRQ line).
557*/
558static void
559iosapic_set_irt_data( struct vector_info *vi, u32 *dp0, u32 *dp1)
560{
561 u32 mode = 0;
562 struct irt_entry *p = vi->irte;
563
564 if ((p->polarity_trigger & IRT_PO_MASK) == IRT_ACTIVE_LO)
565 mode |= IOSAPIC_IRDT_PO_LOW;
566
567 if (((p->polarity_trigger >> IRT_EL_SHIFT) & IRT_EL_MASK) == IRT_LEVEL_TRIG)
568 mode |= IOSAPIC_IRDT_LEVEL_TRIG;
569
570 /*
571 ** IA64 REVISIT
572 ** PA doesn't support EXTINT or LPRIO bits.
573 */
574
575 *dp0 = mode | (u32) vi->txn_data;
576
577 /*
578 ** Extracting id_eid isn't a real clean way of getting it.
579 ** But the encoding is the same for both PA and IA64 platforms.
580 */
581 if (is_pdc_pat()) {
582 /*
583 ** PAT PDC just hands it to us "right".
584 ** txn_addr comes from cpu_data[x].txn_addr.
585 */
586 *dp1 = (u32) (vi->txn_addr);
587 } else {
588 /*
589 ** eg if base_addr == 0xfffa0000),
590 ** we want to get 0xa0ff0000.
591 **
592 ** eid 0x0ff00000 -> 0x00ff0000
593 ** id 0x000ff000 -> 0xff000000
594 */
595 *dp1 = (((u32)vi->txn_addr & 0x0ff00000) >> 4) |
596 (((u32)vi->txn_addr & 0x000ff000) << 12);
597 }
598 DBG_IRT("iosapic_set_irt_data(): 0x%x 0x%x\n", *dp0, *dp1);
599}
600
601
602static void iosapic_mask_irq(struct irq_data *d)
603{
604 unsigned long flags;
605 struct vector_info *vi = irq_data_get_irq_chip_data(d);
606 u32 d0, d1;
607
608 spin_lock_irqsave(&iosapic_lock, flags);
609 iosapic_rd_irt_entry(vi, &d0, &d1);
610 d0 |= IOSAPIC_IRDT_ENABLE;
611 iosapic_wr_irt_entry(vi, d0, d1);
612 spin_unlock_irqrestore(&iosapic_lock, flags);
613}
614
615static void iosapic_unmask_irq(struct irq_data *d)
616{
617 struct vector_info *vi = irq_data_get_irq_chip_data(d);
618 u32 d0, d1;
619
620 /* data is initialized by fixup_irq */
621 WARN_ON(vi->txn_irq == 0);
622
623 iosapic_set_irt_data(vi, &d0, &d1);
624 iosapic_wr_irt_entry(vi, d0, d1);
625
626#ifdef DEBUG_IOSAPIC_IRT
627{
628 u32 *t = (u32 *) ((ulong) vi->eoi_addr & ~0xffUL);
629 printk("iosapic_enable_irq(): regs %p", vi->eoi_addr);
630 for ( ; t < vi->eoi_addr; t++)
631 printk(" %x", readl(t));
632 printk("\n");
633}
634
635printk("iosapic_enable_irq(): sel ");
636{
637 struct iosapic_info *isp = vi->iosapic;
638
639 for (d0=0x10; d0<0x1e; d0++) {
640 d1 = iosapic_read(isp->addr, d0);
641 printk(" %x", d1);
642 }
643}
644printk("\n");
645#endif
646
647 /*
648 * Issuing I/O SAPIC an EOI causes an interrupt IFF IRQ line is
649 * asserted. IRQ generally should not be asserted when a driver
650 * enables their IRQ. It can lead to "interesting" race conditions
651 * in the driver initialization sequence.
652 */
653 DBG(KERN_DEBUG "enable_irq(%d): eoi(%p, 0x%x)\n", d->irq,
654 vi->eoi_addr, vi->eoi_data);
655 iosapic_eoi(vi->eoi_addr, vi->eoi_data);
656}
657
658static void iosapic_eoi_irq(struct irq_data *d)
659{
660 struct vector_info *vi = irq_data_get_irq_chip_data(d);
661
662 iosapic_eoi(vi->eoi_addr, vi->eoi_data);
663 cpu_eoi_irq(d);
664}
665
666#ifdef CONFIG_SMP
667static int iosapic_set_affinity_irq(struct irq_data *d,
668 const struct cpumask *dest, bool force)
669{
670 struct vector_info *vi = irq_data_get_irq_chip_data(d);
671 u32 d0, d1, dummy_d0;
672 unsigned long flags;
673 int dest_cpu;
674
675 dest_cpu = cpu_check_affinity(d, dest);
676 if (dest_cpu < 0)
677 return -1;
678
679 cpumask_copy(irq_data_get_affinity_mask(d), cpumask_of(dest_cpu));
680 vi->txn_addr = txn_affinity_addr(d->irq, dest_cpu);
681
682 spin_lock_irqsave(&iosapic_lock, flags);
683 /* d1 contains the destination CPU, so only want to set that
684 * entry */
685 iosapic_rd_irt_entry(vi, &d0, &d1);
686 iosapic_set_irt_data(vi, &dummy_d0, &d1);
687 iosapic_wr_irt_entry(vi, d0, d1);
688 spin_unlock_irqrestore(&iosapic_lock, flags);
689
690 return 0;
691}
692#endif
693
694static struct irq_chip iosapic_interrupt_type = {
695 .name = "IO-SAPIC-level",
696 .irq_unmask = iosapic_unmask_irq,
697 .irq_mask = iosapic_mask_irq,
698 .irq_ack = cpu_ack_irq,
699 .irq_eoi = iosapic_eoi_irq,
700#ifdef CONFIG_SMP
701 .irq_set_affinity = iosapic_set_affinity_irq,
702#endif
703};
704
705int iosapic_fixup_irq(void *isi_obj, struct pci_dev *pcidev)
706{
707 struct iosapic_info *isi = isi_obj;
708 struct irt_entry *irte = NULL; /* only used if PAT PDC */
709 struct vector_info *vi;
710 int isi_line; /* line used by device */
711
712 if (!isi) {
713 printk(KERN_WARNING MODULE_NAME ": hpa not registered for %s\n",
714 pci_name(pcidev));
715 return -1;
716 }
717
718#ifdef CONFIG_SUPERIO
719 /*
720 * HACK ALERT! (non-compliant PCI device support)
721 *
722 * All SuckyIO interrupts are routed through the PIC's on function 1.
723 * But SuckyIO OHCI USB controller gets an IRT entry anyway because
724 * it advertises INT D for INT_PIN. Use that IRT entry to get the
725 * SuckyIO interrupt routing for PICs on function 1 (*BLEECCHH*).
726 */
727 if (is_superio_device(pcidev)) {
728 /* We must call superio_fixup_irq() to register the pdev */
729 pcidev->irq = superio_fixup_irq(pcidev);
730
731 /* Don't return if need to program the IOSAPIC's IRT... */
732 if (PCI_FUNC(pcidev->devfn) != SUPERIO_USB_FN)
733 return pcidev->irq;
734 }
735#endif /* CONFIG_SUPERIO */
736
737 /* lookup IRT entry for isi/slot/pin set */
738 irte = iosapic_xlate_pin(isi, pcidev);
739 if (!irte) {
740 printk("iosapic: no IRTE for %s (IRQ not connected?)\n",
741 pci_name(pcidev));
742 return -1;
743 }
744 DBG_IRT("iosapic_fixup_irq(): irte %p %x %x %x %x %x %x %x %x\n",
745 irte,
746 irte->entry_type,
747 irte->entry_length,
748 irte->polarity_trigger,
749 irte->src_bus_irq_devno,
750 irte->src_bus_id,
751 irte->src_seg_id,
752 irte->dest_iosapic_intin,
753 (u32) irte->dest_iosapic_addr);
754 isi_line = irte->dest_iosapic_intin;
755
756 /* get vector info for this input line */
757 vi = isi->isi_vector + isi_line;
758 DBG_IRT("iosapic_fixup_irq: line %d vi 0x%p\n", isi_line, vi);
759
760 /* If this IRQ line has already been setup, skip it */
761 if (vi->irte)
762 goto out;
763
764 vi->irte = irte;
765
766 /*
767 * Allocate processor IRQ
768 *
769 * XXX/FIXME The txn_alloc_irq() code and related code should be
770 * moved to enable_irq(). That way we only allocate processor IRQ
771 * bits for devices that actually have drivers claiming them.
772 * Right now we assign an IRQ to every PCI device present,
773 * regardless of whether it's used or not.
774 */
775 vi->txn_irq = txn_alloc_irq(8);
776
777 if (vi->txn_irq < 0)
778 panic("I/O sapic: couldn't get TXN IRQ\n");
779
780 /* enable_irq() will use txn_* to program IRdT */
781 vi->txn_addr = txn_alloc_addr(vi->txn_irq);
782 vi->txn_data = txn_alloc_data(vi->txn_irq);
783
784 vi->eoi_addr = isi->addr + IOSAPIC_REG_EOI;
785 vi->eoi_data = cpu_to_le32(vi->txn_data);
786
787 cpu_claim_irq(vi->txn_irq, &iosapic_interrupt_type, vi);
788
789 out:
790 pcidev->irq = vi->txn_irq;
791
792 DBG_IRT("iosapic_fixup_irq() %d:%d %x %x line %d irq %d\n",
793 PCI_SLOT(pcidev->devfn), PCI_FUNC(pcidev->devfn),
794 pcidev->vendor, pcidev->device, isi_line, pcidev->irq);
795
796 return pcidev->irq;
797}
798
799static struct iosapic_info *iosapic_list;
800
801#ifdef CONFIG_64BIT
802int iosapic_serial_irq(struct parisc_device *dev)
803{
804 struct iosapic_info *isi;
805 struct irt_entry *irte;
806 struct vector_info *vi;
807 int cnt;
808 int intin;
809
810 intin = (dev->mod_info >> 24) & 15;
811
812 /* lookup IRT entry for isi/slot/pin set */
813 for (cnt = 0; cnt < irt_num_entry; cnt++) {
814 irte = &irt_cell[cnt];
815 if (COMPARE_IRTE_ADDR(irte, dev->mod0) &&
816 irte->dest_iosapic_intin == intin)
817 break;
818 }
819 if (cnt >= irt_num_entry)
820 return 0; /* no irq found, force polling */
821
822 DBG_IRT("iosapic_serial_irq(): irte %p %x %x %x %x %x %x %x %x\n",
823 irte,
824 irte->entry_type,
825 irte->entry_length,
826 irte->polarity_trigger,
827 irte->src_bus_irq_devno,
828 irte->src_bus_id,
829 irte->src_seg_id,
830 irte->dest_iosapic_intin,
831 (u32) irte->dest_iosapic_addr);
832
833 /* search for iosapic */
834 for (isi = iosapic_list; isi; isi = isi->isi_next)
835 if (isi->isi_hpa == dev->mod0)
836 break;
837 if (!isi)
838 return 0; /* no iosapic found, force polling */
839
840 /* get vector info for this input line */
841 vi = isi->isi_vector + intin;
842 DBG_IRT("iosapic_serial_irq: line %d vi 0x%p\n", iosapic_intin, vi);
843
844 /* If this IRQ line has already been setup, skip it */
845 if (vi->irte)
846 goto out;
847
848 vi->irte = irte;
849
850 /*
851 * Allocate processor IRQ
852 *
853 * XXX/FIXME The txn_alloc_irq() code and related code should be
854 * moved to enable_irq(). That way we only allocate processor IRQ
855 * bits for devices that actually have drivers claiming them.
856 * Right now we assign an IRQ to every PCI device present,
857 * regardless of whether it's used or not.
858 */
859 vi->txn_irq = txn_alloc_irq(8);
860
861 if (vi->txn_irq < 0)
862 panic("I/O sapic: couldn't get TXN IRQ\n");
863
864 /* enable_irq() will use txn_* to program IRdT */
865 vi->txn_addr = txn_alloc_addr(vi->txn_irq);
866 vi->txn_data = txn_alloc_data(vi->txn_irq);
867
868 vi->eoi_addr = isi->addr + IOSAPIC_REG_EOI;
869 vi->eoi_data = cpu_to_le32(vi->txn_data);
870
871 cpu_claim_irq(vi->txn_irq, &iosapic_interrupt_type, vi);
872
873 out:
874
875 return vi->txn_irq;
876}
877#endif
878
879
880/*
881** squirrel away the I/O Sapic Version
882*/
883static unsigned int
884iosapic_rd_version(struct iosapic_info *isi)
885{
886 return iosapic_read(isi->addr, IOSAPIC_REG_VERSION);
887}
888
889
890/*
891** iosapic_register() is called by "drivers" with an integrated I/O SAPIC.
892** Caller must be certain they have an I/O SAPIC and know its MMIO address.
893**
894** o allocate iosapic_info and add it to the list
895** o read iosapic version and squirrel that away
896** o read size of IRdT.
897** o allocate and initialize isi_vector[]
898** o allocate irq region
899*/
900void *iosapic_register(unsigned long hpa)
901{
902 struct iosapic_info *isi = NULL;
903 struct irt_entry *irte = irt_cell;
904 struct vector_info *vip;
905 int cnt; /* track how many entries we've looked at */
906
907 /*
908 * Astro based platforms can only support PCI OLARD if they implement
909 * PAT PDC. Legacy PDC omits LBAs with no PCI devices from the IRT.
910 * Search the IRT and ignore iosapic's which aren't in the IRT.
911 */
912 for (cnt=0; cnt < irt_num_entry; cnt++, irte++) {
913 WARN_ON(IRT_IOSAPIC_TYPE != irte->entry_type);
914 if (COMPARE_IRTE_ADDR(irte, hpa))
915 break;
916 }
917
918 if (cnt >= irt_num_entry) {
919 DBG("iosapic_register() ignoring 0x%lx (NOT FOUND)\n", hpa);
920 return NULL;
921 }
922
923 isi = kzalloc(sizeof(struct iosapic_info), GFP_KERNEL);
924 if (!isi) {
925 BUG();
926 return NULL;
927 }
928
929 isi->addr = ioremap_nocache(hpa, 4096);
930 isi->isi_hpa = hpa;
931 isi->isi_version = iosapic_rd_version(isi);
932 isi->isi_num_vectors = IOSAPIC_IRDT_MAX_ENTRY(isi->isi_version) + 1;
933
934 vip = isi->isi_vector = kcalloc(isi->isi_num_vectors,
935 sizeof(struct vector_info), GFP_KERNEL);
936 if (vip == NULL) {
937 kfree(isi);
938 return NULL;
939 }
940
941 for (cnt=0; cnt < isi->isi_num_vectors; cnt++, vip++) {
942 vip->irqline = (unsigned char) cnt;
943 vip->iosapic = isi;
944 }
945 isi->isi_next = iosapic_list;
946 iosapic_list = isi;
947 return isi;
948}
949
950
951#ifdef DEBUG_IOSAPIC
952
953static void
954iosapic_prt_irt(void *irt, long num_entry)
955{
956 unsigned int i, *irp = (unsigned int *) irt;
957
958
959 printk(KERN_DEBUG MODULE_NAME ": Interrupt Routing Table (%lx entries)\n", num_entry);
960
961 for (i=0; i<num_entry; i++, irp += 4) {
962 printk(KERN_DEBUG "%p : %2d %.8x %.8x %.8x %.8x\n",
963 irp, i, irp[0], irp[1], irp[2], irp[3]);
964 }
965}
966
967
968static void
969iosapic_prt_vi(struct vector_info *vi)
970{
971 printk(KERN_DEBUG MODULE_NAME ": vector_info[%d] is at %p\n", vi->irqline, vi);
972 printk(KERN_DEBUG "\t\tstatus: %.4x\n", vi->status);
973 printk(KERN_DEBUG "\t\ttxn_irq: %d\n", vi->txn_irq);
974 printk(KERN_DEBUG "\t\ttxn_addr: %lx\n", vi->txn_addr);
975 printk(KERN_DEBUG "\t\ttxn_data: %lx\n", vi->txn_data);
976 printk(KERN_DEBUG "\t\teoi_addr: %p\n", vi->eoi_addr);
977 printk(KERN_DEBUG "\t\teoi_data: %x\n", vi->eoi_data);
978}
979
980
981static void
982iosapic_prt_isi(struct iosapic_info *isi)
983{
984 printk(KERN_DEBUG MODULE_NAME ": io_sapic_info at %p\n", isi);
985 printk(KERN_DEBUG "\t\tisi_hpa: %lx\n", isi->isi_hpa);
986 printk(KERN_DEBUG "\t\tisi_status: %x\n", isi->isi_status);
987 printk(KERN_DEBUG "\t\tisi_version: %x\n", isi->isi_version);
988 printk(KERN_DEBUG "\t\tisi_vector: %p\n", isi->isi_vector);
989}
990#endif /* DEBUG_IOSAPIC */
991

Warning: That file was not part of the compilation database. It may have many parsing errors.