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1/*
2** System Bus Adapter (SBA) I/O MMU manager
3**
4** (c) Copyright 2000-2004 Grant Grundler <grundler @ parisc-linux x org>
5** (c) Copyright 2004 Naresh Kumar Inna <knaresh at india x hp x com>
6** (c) Copyright 2000-2004 Hewlett-Packard Company
7**
8** Portions (c) 1999 Dave S. Miller (from sparc64 I/O MMU code)
9**
10** This program is free software; you can redistribute it and/or modify
11** it under the terms of the GNU General Public License as published by
12** the Free Software Foundation; either version 2 of the License, or
13** (at your option) any later version.
14**
15**
16** This module initializes the IOC (I/O Controller) found on B1000/C3000/
17** J5000/J7000/N-class/L-class machines and their successors.
18**
19** FIXME: add DMA hint support programming in both sba and lba modules.
20*/
21
22#include <linux/types.h>
23#include <linux/kernel.h>
24#include <linux/spinlock.h>
25#include <linux/slab.h>
26#include <linux/init.h>
27
28#include <linux/mm.h>
29#include <linux/string.h>
30#include <linux/pci.h>
31#include <linux/scatterlist.h>
32#include <linux/iommu-helper.h>
33
34#include <asm/byteorder.h>
35#include <asm/io.h>
36#include <asm/dma.h> /* for DMA_CHUNK_SIZE */
37
38#include <asm/hardware.h> /* for register_parisc_driver() stuff */
39
40#include <linux/proc_fs.h>
41#include <linux/seq_file.h>
42#include <linux/module.h>
43
44#include <asm/ropes.h>
45#include <asm/mckinley.h> /* for proc_mckinley_root */
46#include <asm/runway.h> /* for proc_runway_root */
47#include <asm/page.h> /* for PAGE0 */
48#include <asm/pdc.h> /* for PDC_MODEL_* */
49#include <asm/pdcpat.h> /* for is_pdc_pat() */
50#include <asm/parisc-device.h>
51
52#include "iommu.h"
53
54#define MODULE_NAME "SBA"
55
56/*
57** The number of debug flags is a clue - this code is fragile.
58** Don't even think about messing with it unless you have
59** plenty of 710's to sacrifice to the computer gods. :^)
60*/
61#undef DEBUG_SBA_INIT
62#undef DEBUG_SBA_RUN
63#undef DEBUG_SBA_RUN_SG
64#undef DEBUG_SBA_RESOURCE
65#undef ASSERT_PDIR_SANITY
66#undef DEBUG_LARGE_SG_ENTRIES
67#undef DEBUG_DMB_TRAP
68
69#ifdef DEBUG_SBA_INIT
70#define DBG_INIT(x...) printk(x)
71#else
72#define DBG_INIT(x...)
73#endif
74
75#ifdef DEBUG_SBA_RUN
76#define DBG_RUN(x...) printk(x)
77#else
78#define DBG_RUN(x...)
79#endif
80
81#ifdef DEBUG_SBA_RUN_SG
82#define DBG_RUN_SG(x...) printk(x)
83#else
84#define DBG_RUN_SG(x...)
85#endif
86
87
88#ifdef DEBUG_SBA_RESOURCE
89#define DBG_RES(x...) printk(x)
90#else
91#define DBG_RES(x...)
92#endif
93
94#define SBA_INLINE __inline__
95
96#define DEFAULT_DMA_HINT_REG 0
97
98struct sba_device *sba_list;
99EXPORT_SYMBOL_GPL(sba_list);
100
101static unsigned long ioc_needs_fdc = 0;
102
103/* global count of IOMMUs in the system */
104static unsigned int global_ioc_cnt = 0;
105
106/* PA8700 (Piranha 2.2) bug workaround */
107static unsigned long piranha_bad_128k = 0;
108
109/* Looks nice and keeps the compiler happy */
110#define SBA_DEV(d) ((struct sba_device *) (d))
111
112#ifdef CONFIG_AGP_PARISC
113#define SBA_AGP_SUPPORT
114#endif /*CONFIG_AGP_PARISC*/
115
116#ifdef SBA_AGP_SUPPORT
117static int sba_reserve_agpgart = 1;
118module_param(sba_reserve_agpgart, int, 0444);
119MODULE_PARM_DESC(sba_reserve_agpgart, "Reserve half of IO pdir as AGPGART");
120#endif
121
122
123/************************************
124** SBA register read and write support
125**
126** BE WARNED: register writes are posted.
127** (ie follow writes which must reach HW with a read)
128**
129** Superdome (in particular, REO) allows only 64-bit CSR accesses.
130*/
131#define READ_REG32(addr) readl(addr)
132#define READ_REG64(addr) readq(addr)
133#define WRITE_REG32(val, addr) writel((val), (addr))
134#define WRITE_REG64(val, addr) writeq((val), (addr))
135
136#ifdef CONFIG_64BIT
137#define READ_REG(addr) READ_REG64(addr)
138#define WRITE_REG(value, addr) WRITE_REG64(value, addr)
139#else
140#define READ_REG(addr) READ_REG32(addr)
141#define WRITE_REG(value, addr) WRITE_REG32(value, addr)
142#endif
143
144#ifdef DEBUG_SBA_INIT
145
146/* NOTE: When CONFIG_64BIT isn't defined, READ_REG64() is two 32-bit reads */
147
148/**
149 * sba_dump_ranges - debugging only - print ranges assigned to this IOA
150 * @hpa: base address of the sba
151 *
152 * Print the MMIO and IO Port address ranges forwarded by an Astro/Ike/RIO
153 * IO Adapter (aka Bus Converter).
154 */
155static void
156sba_dump_ranges(void __iomem *hpa)
157{
158 DBG_INIT("SBA at 0x%p\n", hpa);
159 DBG_INIT("IOS_DIST_BASE : %Lx\n", READ_REG64(hpa+IOS_DIST_BASE));
160 DBG_INIT("IOS_DIST_MASK : %Lx\n", READ_REG64(hpa+IOS_DIST_MASK));
161 DBG_INIT("IOS_DIST_ROUTE : %Lx\n", READ_REG64(hpa+IOS_DIST_ROUTE));
162 DBG_INIT("\n");
163 DBG_INIT("IOS_DIRECT_BASE : %Lx\n", READ_REG64(hpa+IOS_DIRECT_BASE));
164 DBG_INIT("IOS_DIRECT_MASK : %Lx\n", READ_REG64(hpa+IOS_DIRECT_MASK));
165 DBG_INIT("IOS_DIRECT_ROUTE: %Lx\n", READ_REG64(hpa+IOS_DIRECT_ROUTE));
166}
167
168/**
169 * sba_dump_tlb - debugging only - print IOMMU operating parameters
170 * @hpa: base address of the IOMMU
171 *
172 * Print the size/location of the IO MMU PDIR.
173 */
174static void sba_dump_tlb(void __iomem *hpa)
175{
176 DBG_INIT("IO TLB at 0x%p\n", hpa);
177 DBG_INIT("IOC_IBASE : 0x%Lx\n", READ_REG64(hpa+IOC_IBASE));
178 DBG_INIT("IOC_IMASK : 0x%Lx\n", READ_REG64(hpa+IOC_IMASK));
179 DBG_INIT("IOC_TCNFG : 0x%Lx\n", READ_REG64(hpa+IOC_TCNFG));
180 DBG_INIT("IOC_PDIR_BASE: 0x%Lx\n", READ_REG64(hpa+IOC_PDIR_BASE));
181 DBG_INIT("\n");
182}
183#else
184#define sba_dump_ranges(x)
185#define sba_dump_tlb(x)
186#endif /* DEBUG_SBA_INIT */
187
188
189#ifdef ASSERT_PDIR_SANITY
190
191/**
192 * sba_dump_pdir_entry - debugging only - print one IOMMU PDIR entry
193 * @ioc: IO MMU structure which owns the pdir we are interested in.
194 * @msg: text to print ont the output line.
195 * @pide: pdir index.
196 *
197 * Print one entry of the IO MMU PDIR in human readable form.
198 */
199static void
200sba_dump_pdir_entry(struct ioc *ioc, char *msg, uint pide)
201{
202 /* start printing from lowest pde in rval */
203 u64 *ptr = &(ioc->pdir_base[pide & (~0U * BITS_PER_LONG)]);
204 unsigned long *rptr = (unsigned long *) &(ioc->res_map[(pide >>3) & ~(sizeof(unsigned long) - 1)]);
205 uint rcnt;
206
207 printk(KERN_DEBUG "SBA: %s rp %p bit %d rval 0x%lx\n",
208 msg,
209 rptr, pide & (BITS_PER_LONG - 1), *rptr);
210
211 rcnt = 0;
212 while (rcnt < BITS_PER_LONG) {
213 printk(KERN_DEBUG "%s %2d %p %016Lx\n",
214 (rcnt == (pide & (BITS_PER_LONG - 1)))
215 ? " -->" : " ",
216 rcnt, ptr, *ptr );
217 rcnt++;
218 ptr++;
219 }
220 printk(KERN_DEBUG "%s", msg);
221}
222
223
224/**
225 * sba_check_pdir - debugging only - consistency checker
226 * @ioc: IO MMU structure which owns the pdir we are interested in.
227 * @msg: text to print ont the output line.
228 *
229 * Verify the resource map and pdir state is consistent
230 */
231static int
232sba_check_pdir(struct ioc *ioc, char *msg)
233{
234 u32 *rptr_end = (u32 *) &(ioc->res_map[ioc->res_size]);
235 u32 *rptr = (u32 *) ioc->res_map; /* resource map ptr */
236 u64 *pptr = ioc->pdir_base; /* pdir ptr */
237 uint pide = 0;
238
239 while (rptr < rptr_end) {
240 u32 rval = *rptr;
241 int rcnt = 32; /* number of bits we might check */
242
243 while (rcnt) {
244 /* Get last byte and highest bit from that */
245 u32 pde = ((u32) (((char *)pptr)[7])) << 24;
246 if ((rval ^ pde) & 0x80000000)
247 {
248 /*
249 ** BUMMER! -- res_map != pdir --
250 ** Dump rval and matching pdir entries
251 */
252 sba_dump_pdir_entry(ioc, msg, pide);
253 return(1);
254 }
255 rcnt--;
256 rval <<= 1; /* try the next bit */
257 pptr++;
258 pide++;
259 }
260 rptr++; /* look at next word of res_map */
261 }
262 /* It'd be nice if we always got here :^) */
263 return 0;
264}
265
266
267/**
268 * sba_dump_sg - debugging only - print Scatter-Gather list
269 * @ioc: IO MMU structure which owns the pdir we are interested in.
270 * @startsg: head of the SG list
271 * @nents: number of entries in SG list
272 *
273 * print the SG list so we can verify it's correct by hand.
274 */
275static void
276sba_dump_sg( struct ioc *ioc, struct scatterlist *startsg, int nents)
277{
278 while (nents-- > 0) {
279 printk(KERN_DEBUG " %d : %08lx/%05x %p/%05x\n",
280 nents,
281 (unsigned long) sg_dma_address(startsg),
282 sg_dma_len(startsg),
283 sg_virt(startsg), startsg->length);
284 startsg++;
285 }
286}
287
288#endif /* ASSERT_PDIR_SANITY */
289
290
291
292
293/**************************************************************
294*
295* I/O Pdir Resource Management
296*
297* Bits set in the resource map are in use.
298* Each bit can represent a number of pages.
299* LSbs represent lower addresses (IOVA's).
300*
301***************************************************************/
302#define PAGES_PER_RANGE 1 /* could increase this to 4 or 8 if needed */
303
304/* Convert from IOVP to IOVA and vice versa. */
305
306#ifdef ZX1_SUPPORT
307/* Pluto (aka ZX1) boxes need to set or clear the ibase bits appropriately */
308#define SBA_IOVA(ioc,iovp,offset,hint_reg) ((ioc->ibase) | (iovp) | (offset))
309#define SBA_IOVP(ioc,iova) ((iova) & (ioc)->iovp_mask)
310#else
311/* only support Astro and ancestors. Saves a few cycles in key places */
312#define SBA_IOVA(ioc,iovp,offset,hint_reg) ((iovp) | (offset))
313#define SBA_IOVP(ioc,iova) (iova)
314#endif
315
316#define PDIR_INDEX(iovp) ((iovp)>>IOVP_SHIFT)
317
318#define RESMAP_MASK(n) (~0UL << (BITS_PER_LONG - (n)))
319#define RESMAP_IDX_MASK (sizeof(unsigned long) - 1)
320
321static unsigned long ptr_to_pide(struct ioc *ioc, unsigned long *res_ptr,
322 unsigned int bitshiftcnt)
323{
324 return (((unsigned long)res_ptr - (unsigned long)ioc->res_map) << 3)
325 + bitshiftcnt;
326}
327
328/**
329 * sba_search_bitmap - find free space in IO PDIR resource bitmap
330 * @ioc: IO MMU structure which owns the pdir we are interested in.
331 * @bits_wanted: number of entries we need.
332 *
333 * Find consecutive free bits in resource bitmap.
334 * Each bit represents one entry in the IO Pdir.
335 * Cool perf optimization: search for log2(size) bits at a time.
336 */
337static SBA_INLINE unsigned long
338sba_search_bitmap(struct ioc *ioc, struct device *dev,
339 unsigned long bits_wanted)
340{
341 unsigned long *res_ptr = ioc->res_hint;
342 unsigned long *res_end = (unsigned long *) &(ioc->res_map[ioc->res_size]);
343 unsigned long pide = ~0UL, tpide;
344 unsigned long boundary_size;
345 unsigned long shift;
346 int ret;
347
348 boundary_size = ALIGN((unsigned long long)dma_get_seg_boundary(dev) + 1,
349 1ULL << IOVP_SHIFT) >> IOVP_SHIFT;
350
351#if defined(ZX1_SUPPORT)
352 BUG_ON(ioc->ibase & ~IOVP_MASK);
353 shift = ioc->ibase >> IOVP_SHIFT;
354#else
355 shift = 0;
356#endif
357
358 if (bits_wanted > (BITS_PER_LONG/2)) {
359 /* Search word at a time - no mask needed */
360 for(; res_ptr < res_end; ++res_ptr) {
361 tpide = ptr_to_pide(ioc, res_ptr, 0);
362 ret = iommu_is_span_boundary(tpide, bits_wanted,
363 shift,
364 boundary_size);
365 if ((*res_ptr == 0) && !ret) {
366 *res_ptr = RESMAP_MASK(bits_wanted);
367 pide = tpide;
368 break;
369 }
370 }
371 /* point to the next word on next pass */
372 res_ptr++;
373 ioc->res_bitshift = 0;
374 } else {
375 /*
376 ** Search the resource bit map on well-aligned values.
377 ** "o" is the alignment.
378 ** We need the alignment to invalidate I/O TLB using
379 ** SBA HW features in the unmap path.
380 */
381 unsigned long o = 1 << get_order(bits_wanted << PAGE_SHIFT);
382 uint bitshiftcnt = ALIGN(ioc->res_bitshift, o);
383 unsigned long mask;
384
385 if (bitshiftcnt >= BITS_PER_LONG) {
386 bitshiftcnt = 0;
387 res_ptr++;
388 }
389 mask = RESMAP_MASK(bits_wanted) >> bitshiftcnt;
390
391 DBG_RES("%s() o %ld %p", __func__, o, res_ptr);
392 while(res_ptr < res_end)
393 {
394 DBG_RES(" %p %lx %lx\n", res_ptr, mask, *res_ptr);
395 WARN_ON(mask == 0);
396 tpide = ptr_to_pide(ioc, res_ptr, bitshiftcnt);
397 ret = iommu_is_span_boundary(tpide, bits_wanted,
398 shift,
399 boundary_size);
400 if ((((*res_ptr) & mask) == 0) && !ret) {
401 *res_ptr |= mask; /* mark resources busy! */
402 pide = tpide;
403 break;
404 }
405 mask >>= o;
406 bitshiftcnt += o;
407 if (mask == 0) {
408 mask = RESMAP_MASK(bits_wanted);
409 bitshiftcnt=0;
410 res_ptr++;
411 }
412 }
413 /* look in the same word on the next pass */
414 ioc->res_bitshift = bitshiftcnt + bits_wanted;
415 }
416
417 /* wrapped ? */
418 if (res_end <= res_ptr) {
419 ioc->res_hint = (unsigned long *) ioc->res_map;
420 ioc->res_bitshift = 0;
421 } else {
422 ioc->res_hint = res_ptr;
423 }
424 return (pide);
425}
426
427
428/**
429 * sba_alloc_range - find free bits and mark them in IO PDIR resource bitmap
430 * @ioc: IO MMU structure which owns the pdir we are interested in.
431 * @size: number of bytes to create a mapping for
432 *
433 * Given a size, find consecutive unmarked and then mark those bits in the
434 * resource bit map.
435 */
436static int
437sba_alloc_range(struct ioc *ioc, struct device *dev, size_t size)
438{
439 unsigned int pages_needed = size >> IOVP_SHIFT;
440#ifdef SBA_COLLECT_STATS
441 unsigned long cr_start = mfctl(16);
442#endif
443 unsigned long pide;
444
445 pide = sba_search_bitmap(ioc, dev, pages_needed);
446 if (pide >= (ioc->res_size << 3)) {
447 pide = sba_search_bitmap(ioc, dev, pages_needed);
448 if (pide >= (ioc->res_size << 3))
449 panic("%s: I/O MMU @ %p is out of mapping resources\n",
450 __FILE__, ioc->ioc_hpa);
451 }
452
453#ifdef ASSERT_PDIR_SANITY
454 /* verify the first enable bit is clear */
455 if(0x00 != ((u8 *) ioc->pdir_base)[pide*sizeof(u64) + 7]) {
456 sba_dump_pdir_entry(ioc, "sba_search_bitmap() botched it?", pide);
457 }
458#endif
459
460 DBG_RES("%s(%x) %d -> %lx hint %x/%x\n",
461 __func__, size, pages_needed, pide,
462 (uint) ((unsigned long) ioc->res_hint - (unsigned long) ioc->res_map),
463 ioc->res_bitshift );
464
465#ifdef SBA_COLLECT_STATS
466 {
467 unsigned long cr_end = mfctl(16);
468 unsigned long tmp = cr_end - cr_start;
469 /* check for roll over */
470 cr_start = (cr_end < cr_start) ? -(tmp) : (tmp);
471 }
472 ioc->avg_search[ioc->avg_idx++] = cr_start;
473 ioc->avg_idx &= SBA_SEARCH_SAMPLE - 1;
474
475 ioc->used_pages += pages_needed;
476#endif
477
478 return (pide);
479}
480
481
482/**
483 * sba_free_range - unmark bits in IO PDIR resource bitmap
484 * @ioc: IO MMU structure which owns the pdir we are interested in.
485 * @iova: IO virtual address which was previously allocated.
486 * @size: number of bytes to create a mapping for
487 *
488 * clear bits in the ioc's resource map
489 */
490static SBA_INLINE void
491sba_free_range(struct ioc *ioc, dma_addr_t iova, size_t size)
492{
493 unsigned long iovp = SBA_IOVP(ioc, iova);
494 unsigned int pide = PDIR_INDEX(iovp);
495 unsigned int ridx = pide >> 3; /* convert bit to byte address */
496 unsigned long *res_ptr = (unsigned long *) &((ioc)->res_map[ridx & ~RESMAP_IDX_MASK]);
497
498 int bits_not_wanted = size >> IOVP_SHIFT;
499
500 /* 3-bits "bit" address plus 2 (or 3) bits for "byte" == bit in word */
501 unsigned long m = RESMAP_MASK(bits_not_wanted) >> (pide & (BITS_PER_LONG - 1));
502
503 DBG_RES("%s( ,%x,%x) %x/%lx %x %p %lx\n",
504 __func__, (uint) iova, size,
505 bits_not_wanted, m, pide, res_ptr, *res_ptr);
506
507#ifdef SBA_COLLECT_STATS
508 ioc->used_pages -= bits_not_wanted;
509#endif
510
511 *res_ptr &= ~m;
512}
513
514
515/**************************************************************
516*
517* "Dynamic DMA Mapping" support (aka "Coherent I/O")
518*
519***************************************************************/
520
521#ifdef SBA_HINT_SUPPORT
522#define SBA_DMA_HINT(ioc, val) ((val) << (ioc)->hint_shift_pdir)
523#endif
524
525typedef unsigned long space_t;
526#define KERNEL_SPACE 0
527
528/**
529 * sba_io_pdir_entry - fill in one IO PDIR entry
530 * @pdir_ptr: pointer to IO PDIR entry
531 * @sid: process Space ID - currently only support KERNEL_SPACE
532 * @vba: Virtual CPU address of buffer to map
533 * @hint: DMA hint set to use for this mapping
534 *
535 * SBA Mapping Routine
536 *
537 * Given a virtual address (vba, arg2) and space id, (sid, arg1)
538 * sba_io_pdir_entry() loads the I/O PDIR entry pointed to by
539 * pdir_ptr (arg0).
540 * Using the bass-ackwards HP bit numbering, Each IO Pdir entry
541 * for Astro/Ike looks like:
542 *
543 *
544 * 0 19 51 55 63
545 * +-+---------------------+----------------------------------+----+--------+
546 * |V| U | PPN[43:12] | U | VI |
547 * +-+---------------------+----------------------------------+----+--------+
548 *
549 * Pluto is basically identical, supports fewer physical address bits:
550 *
551 * 0 23 51 55 63
552 * +-+------------------------+-------------------------------+----+--------+
553 * |V| U | PPN[39:12] | U | VI |
554 * +-+------------------------+-------------------------------+----+--------+
555 *
556 * V == Valid Bit (Most Significant Bit is bit 0)
557 * U == Unused
558 * PPN == Physical Page Number
559 * VI == Virtual Index (aka Coherent Index)
560 *
561 * LPA instruction output is put into PPN field.
562 * LCI (Load Coherence Index) instruction provides the "VI" bits.
563 *
564 * We pre-swap the bytes since PCX-W is Big Endian and the
565 * IOMMU uses little endian for the pdir.
566 */
567
568static void SBA_INLINE
569sba_io_pdir_entry(u64 *pdir_ptr, space_t sid, unsigned long vba,
570 unsigned long hint)
571{
572 u64 pa; /* physical address */
573 register unsigned ci; /* coherent index */
574
575 pa = virt_to_phys(vba);
576 pa &= IOVP_MASK;
577
578 mtsp(sid,1);
579 asm("lci 0(%%sr1, %1), %0" : "=r" (ci) : "r" (vba));
580 pa |= (ci >> PAGE_SHIFT) & 0xff; /* move CI (8 bits) into lowest byte */
581
582 pa |= SBA_PDIR_VALID_BIT; /* set "valid" bit */
583 *pdir_ptr = cpu_to_le64(pa); /* swap and store into I/O Pdir */
584
585 /*
586 * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set
587 * (bit #61, big endian), we have to flush and sync every time
588 * IO-PDIR is changed in Ike/Astro.
589 */
590 asm_io_fdc(pdir_ptr);
591}
592
593
594/**
595 * sba_mark_invalid - invalidate one or more IO PDIR entries
596 * @ioc: IO MMU structure which owns the pdir we are interested in.
597 * @iova: IO Virtual Address mapped earlier
598 * @byte_cnt: number of bytes this mapping covers.
599 *
600 * Marking the IO PDIR entry(ies) as Invalid and invalidate
601 * corresponding IO TLB entry. The Ike PCOM (Purge Command Register)
602 * is to purge stale entries in the IO TLB when unmapping entries.
603 *
604 * The PCOM register supports purging of multiple pages, with a minium
605 * of 1 page and a maximum of 2GB. Hardware requires the address be
606 * aligned to the size of the range being purged. The size of the range
607 * must be a power of 2. The "Cool perf optimization" in the
608 * allocation routine helps keep that true.
609 */
610static SBA_INLINE void
611sba_mark_invalid(struct ioc *ioc, dma_addr_t iova, size_t byte_cnt)
612{
613 u32 iovp = (u32) SBA_IOVP(ioc,iova);
614 u64 *pdir_ptr = &ioc->pdir_base[PDIR_INDEX(iovp)];
615
616#ifdef ASSERT_PDIR_SANITY
617 /* Assert first pdir entry is set.
618 **
619 ** Even though this is a big-endian machine, the entries
620 ** in the iopdir are little endian. That's why we look at
621 ** the byte at +7 instead of at +0.
622 */
623 if (0x80 != (((u8 *) pdir_ptr)[7])) {
624 sba_dump_pdir_entry(ioc,"sba_mark_invalid()", PDIR_INDEX(iovp));
625 }
626#endif
627
628 if (byte_cnt > IOVP_SIZE)
629 {
630#if 0
631 unsigned long entries_per_cacheline = ioc_needs_fdc ?
632 L1_CACHE_ALIGN(((unsigned long) pdir_ptr))
633 - (unsigned long) pdir_ptr;
634 : 262144;
635#endif
636
637 /* set "size" field for PCOM */
638 iovp |= get_order(byte_cnt) + PAGE_SHIFT;
639
640 do {
641 /* clear I/O Pdir entry "valid" bit first */
642 ((u8 *) pdir_ptr)[7] = 0;
643 asm_io_fdc(pdir_ptr);
644 if (ioc_needs_fdc) {
645#if 0
646 entries_per_cacheline = L1_CACHE_SHIFT - 3;
647#endif
648 }
649 pdir_ptr++;
650 byte_cnt -= IOVP_SIZE;
651 } while (byte_cnt > IOVP_SIZE);
652 } else
653 iovp |= IOVP_SHIFT; /* set "size" field for PCOM */
654
655 /*
656 ** clear I/O PDIR entry "valid" bit.
657 ** We have to R/M/W the cacheline regardless how much of the
658 ** pdir entry that we clobber.
659 ** The rest of the entry would be useful for debugging if we
660 ** could dump core on HPMC.
661 */
662 ((u8 *) pdir_ptr)[7] = 0;
663 asm_io_fdc(pdir_ptr);
664
665 WRITE_REG( SBA_IOVA(ioc, iovp, 0, 0), ioc->ioc_hpa+IOC_PCOM);
666}
667
668/**
669 * sba_dma_supported - PCI driver can query DMA support
670 * @dev: instance of PCI owned by the driver that's asking
671 * @mask: number of address bits this PCI device can handle
672 *
673 * See Documentation/DMA-API-HOWTO.txt
674 */
675static int sba_dma_supported( struct device *dev, u64 mask)
676{
677 struct ioc *ioc;
678
679 if (dev == NULL) {
680 printk(KERN_ERR MODULE_NAME ": EISA/ISA/et al not supported\n");
681 BUG();
682 return(0);
683 }
684
685 /* Documentation/DMA-API-HOWTO.txt tells drivers to try 64-bit
686 * first, then fall back to 32-bit if that fails.
687 * We are just "encouraging" 32-bit DMA masks here since we can
688 * never allow IOMMU bypass unless we add special support for ZX1.
689 */
690 if (mask > ~0U)
691 return 0;
692
693 ioc = GET_IOC(dev);
694 if (!ioc)
695 return 0;
696
697 /*
698 * check if mask is >= than the current max IO Virt Address
699 * The max IO Virt address will *always* < 30 bits.
700 */
701 return((int)(mask >= (ioc->ibase - 1 +
702 (ioc->pdir_size / sizeof(u64) * IOVP_SIZE) )));
703}
704
705
706/**
707 * sba_map_single - map one buffer and return IOVA for DMA
708 * @dev: instance of PCI owned by the driver that's asking.
709 * @addr: driver buffer to map.
710 * @size: number of bytes to map in driver buffer.
711 * @direction: R/W or both.
712 *
713 * See Documentation/DMA-API-HOWTO.txt
714 */
715static dma_addr_t
716sba_map_single(struct device *dev, void *addr, size_t size,
717 enum dma_data_direction direction)
718{
719 struct ioc *ioc;
720 unsigned long flags;
721 dma_addr_t iovp;
722 dma_addr_t offset;
723 u64 *pdir_start;
724 int pide;
725
726 ioc = GET_IOC(dev);
727 if (!ioc)
728 return DMA_MAPPING_ERROR;
729
730 /* save offset bits */
731 offset = ((dma_addr_t) (long) addr) & ~IOVP_MASK;
732
733 /* round up to nearest IOVP_SIZE */
734 size = (size + offset + ~IOVP_MASK) & IOVP_MASK;
735
736 spin_lock_irqsave(&ioc->res_lock, flags);
737#ifdef ASSERT_PDIR_SANITY
738 sba_check_pdir(ioc,"Check before sba_map_single()");
739#endif
740
741#ifdef SBA_COLLECT_STATS
742 ioc->msingle_calls++;
743 ioc->msingle_pages += size >> IOVP_SHIFT;
744#endif
745 pide = sba_alloc_range(ioc, dev, size);
746 iovp = (dma_addr_t) pide << IOVP_SHIFT;
747
748 DBG_RUN("%s() 0x%p -> 0x%lx\n",
749 __func__, addr, (long) iovp | offset);
750
751 pdir_start = &(ioc->pdir_base[pide]);
752
753 while (size > 0) {
754 sba_io_pdir_entry(pdir_start, KERNEL_SPACE, (unsigned long) addr, 0);
755
756 DBG_RUN(" pdir 0x%p %02x%02x%02x%02x%02x%02x%02x%02x\n",
757 pdir_start,
758 (u8) (((u8 *) pdir_start)[7]),
759 (u8) (((u8 *) pdir_start)[6]),
760 (u8) (((u8 *) pdir_start)[5]),
761 (u8) (((u8 *) pdir_start)[4]),
762 (u8) (((u8 *) pdir_start)[3]),
763 (u8) (((u8 *) pdir_start)[2]),
764 (u8) (((u8 *) pdir_start)[1]),
765 (u8) (((u8 *) pdir_start)[0])
766 );
767
768 addr += IOVP_SIZE;
769 size -= IOVP_SIZE;
770 pdir_start++;
771 }
772
773 /* force FDC ops in io_pdir_entry() to be visible to IOMMU */
774 asm_io_sync();
775
776#ifdef ASSERT_PDIR_SANITY
777 sba_check_pdir(ioc,"Check after sba_map_single()");
778#endif
779 spin_unlock_irqrestore(&ioc->res_lock, flags);
780
781 /* form complete address */
782 return SBA_IOVA(ioc, iovp, offset, DEFAULT_DMA_HINT_REG);
783}
784
785
786static dma_addr_t
787sba_map_page(struct device *dev, struct page *page, unsigned long offset,
788 size_t size, enum dma_data_direction direction,
789 unsigned long attrs)
790{
791 return sba_map_single(dev, page_address(page) + offset, size,
792 direction);
793}
794
795
796/**
797 * sba_unmap_page - unmap one IOVA and free resources
798 * @dev: instance of PCI owned by the driver that's asking.
799 * @iova: IOVA of driver buffer previously mapped.
800 * @size: number of bytes mapped in driver buffer.
801 * @direction: R/W or both.
802 *
803 * See Documentation/DMA-API-HOWTO.txt
804 */
805static void
806sba_unmap_page(struct device *dev, dma_addr_t iova, size_t size,
807 enum dma_data_direction direction, unsigned long attrs)
808{
809 struct ioc *ioc;
810#if DELAYED_RESOURCE_CNT > 0
811 struct sba_dma_pair *d;
812#endif
813 unsigned long flags;
814 dma_addr_t offset;
815
816 DBG_RUN("%s() iovp 0x%lx/%x\n", __func__, (long) iova, size);
817
818 ioc = GET_IOC(dev);
819 if (!ioc) {
820 WARN_ON(!ioc);
821 return;
822 }
823 offset = iova & ~IOVP_MASK;
824 iova ^= offset; /* clear offset bits */
825 size += offset;
826 size = ALIGN(size, IOVP_SIZE);
827
828 spin_lock_irqsave(&ioc->res_lock, flags);
829
830#ifdef SBA_COLLECT_STATS
831 ioc->usingle_calls++;
832 ioc->usingle_pages += size >> IOVP_SHIFT;
833#endif
834
835 sba_mark_invalid(ioc, iova, size);
836
837#if DELAYED_RESOURCE_CNT > 0
838 /* Delaying when we re-use a IO Pdir entry reduces the number
839 * of MMIO reads needed to flush writes to the PCOM register.
840 */
841 d = &(ioc->saved[ioc->saved_cnt]);
842 d->iova = iova;
843 d->size = size;
844 if (++(ioc->saved_cnt) >= DELAYED_RESOURCE_CNT) {
845 int cnt = ioc->saved_cnt;
846 while (cnt--) {
847 sba_free_range(ioc, d->iova, d->size);
848 d--;
849 }
850 ioc->saved_cnt = 0;
851
852 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */
853 }
854#else /* DELAYED_RESOURCE_CNT == 0 */
855 sba_free_range(ioc, iova, size);
856
857 /* If fdc's were issued, force fdc's to be visible now */
858 asm_io_sync();
859
860 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */
861#endif /* DELAYED_RESOURCE_CNT == 0 */
862
863 spin_unlock_irqrestore(&ioc->res_lock, flags);
864
865 /* XXX REVISIT for 2.5 Linux - need syncdma for zero-copy support.
866 ** For Astro based systems this isn't a big deal WRT performance.
867 ** As long as 2.4 kernels copyin/copyout data from/to userspace,
868 ** we don't need the syncdma. The issue here is I/O MMU cachelines
869 ** are *not* coherent in all cases. May be hwrev dependent.
870 ** Need to investigate more.
871 asm volatile("syncdma");
872 */
873}
874
875
876/**
877 * sba_alloc - allocate/map shared mem for DMA
878 * @hwdev: instance of PCI owned by the driver that's asking.
879 * @size: number of bytes mapped in driver buffer.
880 * @dma_handle: IOVA of new buffer.
881 *
882 * See Documentation/DMA-API-HOWTO.txt
883 */
884static void *sba_alloc(struct device *hwdev, size_t size, dma_addr_t *dma_handle,
885 gfp_t gfp, unsigned long attrs)
886{
887 void *ret;
888
889 if (!hwdev) {
890 /* only support PCI */
891 *dma_handle = 0;
892 return NULL;
893 }
894
895 ret = (void *) __get_free_pages(gfp, get_order(size));
896
897 if (ret) {
898 memset(ret, 0, size);
899 *dma_handle = sba_map_single(hwdev, ret, size, 0);
900 }
901
902 return ret;
903}
904
905
906/**
907 * sba_free - free/unmap shared mem for DMA
908 * @hwdev: instance of PCI owned by the driver that's asking.
909 * @size: number of bytes mapped in driver buffer.
910 * @vaddr: virtual address IOVA of "consistent" buffer.
911 * @dma_handler: IO virtual address of "consistent" buffer.
912 *
913 * See Documentation/DMA-API-HOWTO.txt
914 */
915static void
916sba_free(struct device *hwdev, size_t size, void *vaddr,
917 dma_addr_t dma_handle, unsigned long attrs)
918{
919 sba_unmap_page(hwdev, dma_handle, size, 0, 0);
920 free_pages((unsigned long) vaddr, get_order(size));
921}
922
923
924/*
925** Since 0 is a valid pdir_base index value, can't use that
926** to determine if a value is valid or not. Use a flag to indicate
927** the SG list entry contains a valid pdir index.
928*/
929#define PIDE_FLAG 0x80000000UL
930
931#ifdef SBA_COLLECT_STATS
932#define IOMMU_MAP_STATS
933#endif
934#include "iommu-helpers.h"
935
936#ifdef DEBUG_LARGE_SG_ENTRIES
937int dump_run_sg = 0;
938#endif
939
940
941/**
942 * sba_map_sg - map Scatter/Gather list
943 * @dev: instance of PCI owned by the driver that's asking.
944 * @sglist: array of buffer/length pairs
945 * @nents: number of entries in list
946 * @direction: R/W or both.
947 *
948 * See Documentation/DMA-API-HOWTO.txt
949 */
950static int
951sba_map_sg(struct device *dev, struct scatterlist *sglist, int nents,
952 enum dma_data_direction direction, unsigned long attrs)
953{
954 struct ioc *ioc;
955 int coalesced, filled = 0;
956 unsigned long flags;
957
958 DBG_RUN_SG("%s() START %d entries\n", __func__, nents);
959
960 ioc = GET_IOC(dev);
961 if (!ioc)
962 return 0;
963
964 /* Fast path single entry scatterlists. */
965 if (nents == 1) {
966 sg_dma_address(sglist) = sba_map_single(dev, sg_virt(sglist),
967 sglist->length, direction);
968 sg_dma_len(sglist) = sglist->length;
969 return 1;
970 }
971
972 spin_lock_irqsave(&ioc->res_lock, flags);
973
974#ifdef ASSERT_PDIR_SANITY
975 if (sba_check_pdir(ioc,"Check before sba_map_sg()"))
976 {
977 sba_dump_sg(ioc, sglist, nents);
978 panic("Check before sba_map_sg()");
979 }
980#endif
981
982#ifdef SBA_COLLECT_STATS
983 ioc->msg_calls++;
984#endif
985
986 /*
987 ** First coalesce the chunks and allocate I/O pdir space
988 **
989 ** If this is one DMA stream, we can properly map using the
990 ** correct virtual address associated with each DMA page.
991 ** w/o this association, we wouldn't have coherent DMA!
992 ** Access to the virtual address is what forces a two pass algorithm.
993 */
994 coalesced = iommu_coalesce_chunks(ioc, dev, sglist, nents, sba_alloc_range);
995
996 /*
997 ** Program the I/O Pdir
998 **
999 ** map the virtual addresses to the I/O Pdir
1000 ** o dma_address will contain the pdir index
1001 ** o dma_len will contain the number of bytes to map
1002 ** o address contains the virtual address.
1003 */
1004 filled = iommu_fill_pdir(ioc, sglist, nents, 0, sba_io_pdir_entry);
1005
1006 /* force FDC ops in io_pdir_entry() to be visible to IOMMU */
1007 asm_io_sync();
1008
1009#ifdef ASSERT_PDIR_SANITY
1010 if (sba_check_pdir(ioc,"Check after sba_map_sg()"))
1011 {
1012 sba_dump_sg(ioc, sglist, nents);
1013 panic("Check after sba_map_sg()\n");
1014 }
1015#endif
1016
1017 spin_unlock_irqrestore(&ioc->res_lock, flags);
1018
1019 DBG_RUN_SG("%s() DONE %d mappings\n", __func__, filled);
1020
1021 return filled;
1022}
1023
1024
1025/**
1026 * sba_unmap_sg - unmap Scatter/Gather list
1027 * @dev: instance of PCI owned by the driver that's asking.
1028 * @sglist: array of buffer/length pairs
1029 * @nents: number of entries in list
1030 * @direction: R/W or both.
1031 *
1032 * See Documentation/DMA-API-HOWTO.txt
1033 */
1034static void
1035sba_unmap_sg(struct device *dev, struct scatterlist *sglist, int nents,
1036 enum dma_data_direction direction, unsigned long attrs)
1037{
1038 struct ioc *ioc;
1039#ifdef ASSERT_PDIR_SANITY
1040 unsigned long flags;
1041#endif
1042
1043 DBG_RUN_SG("%s() START %d entries, %p,%x\n",
1044 __func__, nents, sg_virt(sglist), sglist->length);
1045
1046 ioc = GET_IOC(dev);
1047 if (!ioc) {
1048 WARN_ON(!ioc);
1049 return;
1050 }
1051
1052#ifdef SBA_COLLECT_STATS
1053 ioc->usg_calls++;
1054#endif
1055
1056#ifdef ASSERT_PDIR_SANITY
1057 spin_lock_irqsave(&ioc->res_lock, flags);
1058 sba_check_pdir(ioc,"Check before sba_unmap_sg()");
1059 spin_unlock_irqrestore(&ioc->res_lock, flags);
1060#endif
1061
1062 while (sg_dma_len(sglist) && nents--) {
1063
1064 sba_unmap_page(dev, sg_dma_address(sglist), sg_dma_len(sglist),
1065 direction, 0);
1066#ifdef SBA_COLLECT_STATS
1067 ioc->usg_pages += ((sg_dma_address(sglist) & ~IOVP_MASK) + sg_dma_len(sglist) + IOVP_SIZE - 1) >> PAGE_SHIFT;
1068 ioc->usingle_calls--; /* kluge since call is unmap_sg() */
1069#endif
1070 ++sglist;
1071 }
1072
1073 DBG_RUN_SG("%s() DONE (nents %d)\n", __func__, nents);
1074
1075#ifdef ASSERT_PDIR_SANITY
1076 spin_lock_irqsave(&ioc->res_lock, flags);
1077 sba_check_pdir(ioc,"Check after sba_unmap_sg()");
1078 spin_unlock_irqrestore(&ioc->res_lock, flags);
1079#endif
1080
1081}
1082
1083static const struct dma_map_ops sba_ops = {
1084 .dma_supported = sba_dma_supported,
1085 .alloc = sba_alloc,
1086 .free = sba_free,
1087 .map_page = sba_map_page,
1088 .unmap_page = sba_unmap_page,
1089 .map_sg = sba_map_sg,
1090 .unmap_sg = sba_unmap_sg,
1091};
1092
1093
1094/**************************************************************************
1095**
1096** SBA PAT PDC support
1097**
1098** o call pdc_pat_cell_module()
1099** o store ranges in PCI "resource" structures
1100**
1101**************************************************************************/
1102
1103static void
1104sba_get_pat_resources(struct sba_device *sba_dev)
1105{
1106#if 0
1107/*
1108** TODO/REVISIT/FIXME: support for directed ranges requires calls to
1109** PAT PDC to program the SBA/LBA directed range registers...this
1110** burden may fall on the LBA code since it directly supports the
1111** PCI subsystem. It's not clear yet. - ggg
1112*/
1113PAT_MOD(mod)->mod_info.mod_pages = PAT_GET_MOD_PAGES(temp);
1114 FIXME : ???
1115PAT_MOD(mod)->mod_info.dvi = PAT_GET_DVI(temp);
1116 Tells where the dvi bits are located in the address.
1117PAT_MOD(mod)->mod_info.ioc = PAT_GET_IOC(temp);
1118 FIXME : ???
1119#endif
1120}
1121
1122
1123/**************************************************************
1124*
1125* Initialization and claim
1126*
1127***************************************************************/
1128#define PIRANHA_ADDR_MASK 0x00160000UL /* bit 17,18,20 */
1129#define PIRANHA_ADDR_VAL 0x00060000UL /* bit 17,18 on */
1130static void *
1131sba_alloc_pdir(unsigned int pdir_size)
1132{
1133 unsigned long pdir_base;
1134 unsigned long pdir_order = get_order(pdir_size);
1135
1136 pdir_base = __get_free_pages(GFP_KERNEL, pdir_order);
1137 if (NULL == (void *) pdir_base) {
1138 panic("%s() could not allocate I/O Page Table\n",
1139 __func__);
1140 }
1141
1142 /* If this is not PA8700 (PCX-W2)
1143 ** OR newer than ver 2.2
1144 ** OR in a system that doesn't need VINDEX bits from SBA,
1145 **
1146 ** then we aren't exposed to the HW bug.
1147 */
1148 if ( ((boot_cpu_data.pdc.cpuid >> 5) & 0x7f) != 0x13
1149 || (boot_cpu_data.pdc.versions > 0x202)
1150 || (boot_cpu_data.pdc.capabilities & 0x08L) )
1151 return (void *) pdir_base;
1152
1153 /*
1154 * PA8700 (PCX-W2, aka piranha) silent data corruption fix
1155 *
1156 * An interaction between PA8700 CPU (Ver 2.2 or older) and
1157 * Ike/Astro can cause silent data corruption. This is only
1158 * a problem if the I/O PDIR is located in memory such that
1159 * (little-endian) bits 17 and 18 are on and bit 20 is off.
1160 *
1161 * Since the max IO Pdir size is 2MB, by cleverly allocating the
1162 * right physical address, we can either avoid (IOPDIR <= 1MB)
1163 * or minimize (2MB IO Pdir) the problem if we restrict the
1164 * IO Pdir to a maximum size of 2MB-128K (1902K).
1165 *
1166 * Because we always allocate 2^N sized IO pdirs, either of the
1167 * "bad" regions will be the last 128K if at all. That's easy
1168 * to test for.
1169 *
1170 */
1171 if (pdir_order <= (19-12)) {
1172 if (((virt_to_phys(pdir_base)+pdir_size-1) & PIRANHA_ADDR_MASK) == PIRANHA_ADDR_VAL) {
1173 /* allocate a new one on 512k alignment */
1174 unsigned long new_pdir = __get_free_pages(GFP_KERNEL, (19-12));
1175 /* release original */
1176 free_pages(pdir_base, pdir_order);
1177
1178 pdir_base = new_pdir;
1179
1180 /* release excess */
1181 while (pdir_order < (19-12)) {
1182 new_pdir += pdir_size;
1183 free_pages(new_pdir, pdir_order);
1184 pdir_order +=1;
1185 pdir_size <<=1;
1186 }
1187 }
1188 } else {
1189 /*
1190 ** 1MB or 2MB Pdir
1191 ** Needs to be aligned on an "odd" 1MB boundary.
1192 */
1193 unsigned long new_pdir = __get_free_pages(GFP_KERNEL, pdir_order+1); /* 2 or 4MB */
1194
1195 /* release original */
1196 free_pages( pdir_base, pdir_order);
1197
1198 /* release first 1MB */
1199 free_pages(new_pdir, 20-12);
1200
1201 pdir_base = new_pdir + 1024*1024;
1202
1203 if (pdir_order > (20-12)) {
1204 /*
1205 ** 2MB Pdir.
1206 **
1207 ** Flag tells init_bitmap() to mark bad 128k as used
1208 ** and to reduce the size by 128k.
1209 */
1210 piranha_bad_128k = 1;
1211
1212 new_pdir += 3*1024*1024;
1213 /* release last 1MB */
1214 free_pages(new_pdir, 20-12);
1215
1216 /* release unusable 128KB */
1217 free_pages(new_pdir - 128*1024 , 17-12);
1218
1219 pdir_size -= 128*1024;
1220 }
1221 }
1222
1223 memset((void *) pdir_base, 0, pdir_size);
1224 return (void *) pdir_base;
1225}
1226
1227struct ibase_data_struct {
1228 struct ioc *ioc;
1229 int ioc_num;
1230};
1231
1232static int setup_ibase_imask_callback(struct device *dev, void *data)
1233{
1234 /* lba_set_iregs() is in drivers/parisc/lba_pci.c */
1235 extern void lba_set_iregs(struct parisc_device *, u32, u32);
1236 struct parisc_device *lba = to_parisc_device(dev);
1237 struct ibase_data_struct *ibd = data;
1238 int rope_num = (lba->hpa.start >> 13) & 0xf;
1239 if (rope_num >> 3 == ibd->ioc_num)
1240 lba_set_iregs(lba, ibd->ioc->ibase, ibd->ioc->imask);
1241 return 0;
1242}
1243
1244/* setup Mercury or Elroy IBASE/IMASK registers. */
1245static void
1246setup_ibase_imask(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
1247{
1248 struct ibase_data_struct ibase_data = {
1249 .ioc = ioc,
1250 .ioc_num = ioc_num,
1251 };
1252
1253 device_for_each_child(&sba->dev, &ibase_data,
1254 setup_ibase_imask_callback);
1255}
1256
1257#ifdef SBA_AGP_SUPPORT
1258static int
1259sba_ioc_find_quicksilver(struct device *dev, void *data)
1260{
1261 int *agp_found = data;
1262 struct parisc_device *lba = to_parisc_device(dev);
1263
1264 if (IS_QUICKSILVER(lba))
1265 *agp_found = 1;
1266 return 0;
1267}
1268#endif
1269
1270static void
1271sba_ioc_init_pluto(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
1272{
1273 u32 iova_space_mask;
1274 u32 iova_space_size;
1275 int iov_order, tcnfg;
1276#ifdef SBA_AGP_SUPPORT
1277 int agp_found = 0;
1278#endif
1279 /*
1280 ** Firmware programs the base and size of a "safe IOVA space"
1281 ** (one that doesn't overlap memory or LMMIO space) in the
1282 ** IBASE and IMASK registers.
1283 */
1284 ioc->ibase = READ_REG(ioc->ioc_hpa + IOC_IBASE);
1285 iova_space_size = ~(READ_REG(ioc->ioc_hpa + IOC_IMASK) & 0xFFFFFFFFUL) + 1;
1286
1287 if ((ioc->ibase < 0xfed00000UL) && ((ioc->ibase + iova_space_size) > 0xfee00000UL)) {
1288 printk("WARNING: IOV space overlaps local config and interrupt message, truncating\n");
1289 iova_space_size /= 2;
1290 }
1291
1292 /*
1293 ** iov_order is always based on a 1GB IOVA space since we want to
1294 ** turn on the other half for AGP GART.
1295 */
1296 iov_order = get_order(iova_space_size >> (IOVP_SHIFT - PAGE_SHIFT));
1297 ioc->pdir_size = (iova_space_size / IOVP_SIZE) * sizeof(u64);
1298
1299 DBG_INIT("%s() hpa 0x%p IOV %dMB (%d bits)\n",
1300 __func__, ioc->ioc_hpa, iova_space_size >> 20,
1301 iov_order + PAGE_SHIFT);
1302
1303 ioc->pdir_base = (void *) __get_free_pages(GFP_KERNEL,
1304 get_order(ioc->pdir_size));
1305 if (!ioc->pdir_base)
1306 panic("Couldn't allocate I/O Page Table\n");
1307
1308 memset(ioc->pdir_base, 0, ioc->pdir_size);
1309
1310 DBG_INIT("%s() pdir %p size %x\n",
1311 __func__, ioc->pdir_base, ioc->pdir_size);
1312
1313#ifdef SBA_HINT_SUPPORT
1314 ioc->hint_shift_pdir = iov_order + PAGE_SHIFT;
1315 ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT));
1316
1317 DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n",
1318 ioc->hint_shift_pdir, ioc->hint_mask_pdir);
1319#endif
1320
1321 WARN_ON((((unsigned long) ioc->pdir_base) & PAGE_MASK) != (unsigned long) ioc->pdir_base);
1322 WRITE_REG(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE);
1323
1324 /* build IMASK for IOC and Elroy */
1325 iova_space_mask = 0xffffffff;
1326 iova_space_mask <<= (iov_order + PAGE_SHIFT);
1327 ioc->imask = iova_space_mask;
1328#ifdef ZX1_SUPPORT
1329 ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1);
1330#endif
1331 sba_dump_tlb(ioc->ioc_hpa);
1332
1333 setup_ibase_imask(sba, ioc, ioc_num);
1334
1335 WRITE_REG(ioc->imask, ioc->ioc_hpa + IOC_IMASK);
1336
1337#ifdef CONFIG_64BIT
1338 /*
1339 ** Setting the upper bits makes checking for bypass addresses
1340 ** a little faster later on.
1341 */
1342 ioc->imask |= 0xFFFFFFFF00000000UL;
1343#endif
1344
1345 /* Set I/O PDIR Page size to system page size */
1346 switch (PAGE_SHIFT) {
1347 case 12: tcnfg = 0; break; /* 4K */
1348 case 13: tcnfg = 1; break; /* 8K */
1349 case 14: tcnfg = 2; break; /* 16K */
1350 case 16: tcnfg = 3; break; /* 64K */
1351 default:
1352 panic(__FILE__ "Unsupported system page size %d",
1353 1 << PAGE_SHIFT);
1354 break;
1355 }
1356 WRITE_REG(tcnfg, ioc->ioc_hpa + IOC_TCNFG);
1357
1358 /*
1359 ** Program the IOC's ibase and enable IOVA translation
1360 ** Bit zero == enable bit.
1361 */
1362 WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa + IOC_IBASE);
1363
1364 /*
1365 ** Clear I/O TLB of any possible entries.
1366 ** (Yes. This is a bit paranoid...but so what)
1367 */
1368 WRITE_REG(ioc->ibase | 31, ioc->ioc_hpa + IOC_PCOM);
1369
1370#ifdef SBA_AGP_SUPPORT
1371
1372 /*
1373 ** If an AGP device is present, only use half of the IOV space
1374 ** for PCI DMA. Unfortunately we can't know ahead of time
1375 ** whether GART support will actually be used, for now we
1376 ** can just key on any AGP device found in the system.
1377 ** We program the next pdir index after we stop w/ a key for
1378 ** the GART code to handshake on.
1379 */
1380 device_for_each_child(&sba->dev, &agp_found, sba_ioc_find_quicksilver);
1381
1382 if (agp_found && sba_reserve_agpgart) {
1383 printk(KERN_INFO "%s: reserving %dMb of IOVA space for agpgart\n",
1384 __func__, (iova_space_size/2) >> 20);
1385 ioc->pdir_size /= 2;
1386 ioc->pdir_base[PDIR_INDEX(iova_space_size/2)] = SBA_AGPGART_COOKIE;
1387 }
1388#endif /*SBA_AGP_SUPPORT*/
1389}
1390
1391static void
1392sba_ioc_init(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
1393{
1394 u32 iova_space_size, iova_space_mask;
1395 unsigned int pdir_size, iov_order, tcnfg;
1396
1397 /*
1398 ** Determine IOVA Space size from memory size.
1399 **
1400 ** Ideally, PCI drivers would register the maximum number
1401 ** of DMA they can have outstanding for each device they
1402 ** own. Next best thing would be to guess how much DMA
1403 ** can be outstanding based on PCI Class/sub-class. Both
1404 ** methods still require some "extra" to support PCI
1405 ** Hot-Plug/Removal of PCI cards. (aka PCI OLARD).
1406 **
1407 ** While we have 32-bits "IOVA" space, top two 2 bits are used
1408 ** for DMA hints - ergo only 30 bits max.
1409 */
1410
1411 iova_space_size = (u32) (totalram_pages()/global_ioc_cnt);
1412
1413 /* limit IOVA space size to 1MB-1GB */
1414 if (iova_space_size < (1 << (20 - PAGE_SHIFT))) {
1415 iova_space_size = 1 << (20 - PAGE_SHIFT);
1416 }
1417 else if (iova_space_size > (1 << (30 - PAGE_SHIFT))) {
1418 iova_space_size = 1 << (30 - PAGE_SHIFT);
1419 }
1420
1421 /*
1422 ** iova space must be log2() in size.
1423 ** thus, pdir/res_map will also be log2().
1424 ** PIRANHA BUG: Exception is when IO Pdir is 2MB (gets reduced)
1425 */
1426 iov_order = get_order(iova_space_size << PAGE_SHIFT);
1427
1428 /* iova_space_size is now bytes, not pages */
1429 iova_space_size = 1 << (iov_order + PAGE_SHIFT);
1430
1431 ioc->pdir_size = pdir_size = (iova_space_size/IOVP_SIZE) * sizeof(u64);
1432
1433 DBG_INIT("%s() hpa 0x%lx mem %ldMB IOV %dMB (%d bits)\n",
1434 __func__,
1435 ioc->ioc_hpa,
1436 (unsigned long) totalram_pages() >> (20 - PAGE_SHIFT),
1437 iova_space_size>>20,
1438 iov_order + PAGE_SHIFT);
1439
1440 ioc->pdir_base = sba_alloc_pdir(pdir_size);
1441
1442 DBG_INIT("%s() pdir %p size %x\n",
1443 __func__, ioc->pdir_base, pdir_size);
1444
1445#ifdef SBA_HINT_SUPPORT
1446 /* FIXME : DMA HINTs not used */
1447 ioc->hint_shift_pdir = iov_order + PAGE_SHIFT;
1448 ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT));
1449
1450 DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n",
1451 ioc->hint_shift_pdir, ioc->hint_mask_pdir);
1452#endif
1453
1454 WRITE_REG64(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE);
1455
1456 /* build IMASK for IOC and Elroy */
1457 iova_space_mask = 0xffffffff;
1458 iova_space_mask <<= (iov_order + PAGE_SHIFT);
1459
1460 /*
1461 ** On C3000 w/512MB mem, HP-UX 10.20 reports:
1462 ** ibase=0, imask=0xFE000000, size=0x2000000.
1463 */
1464 ioc->ibase = 0;
1465 ioc->imask = iova_space_mask; /* save it */
1466#ifdef ZX1_SUPPORT
1467 ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1);
1468#endif
1469
1470 DBG_INIT("%s() IOV base 0x%lx mask 0x%0lx\n",
1471 __func__, ioc->ibase, ioc->imask);
1472
1473 /*
1474 ** FIXME: Hint registers are programmed with default hint
1475 ** values during boot, so hints should be sane even if we
1476 ** can't reprogram them the way drivers want.
1477 */
1478
1479 setup_ibase_imask(sba, ioc, ioc_num);
1480
1481 /*
1482 ** Program the IOC's ibase and enable IOVA translation
1483 */
1484 WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa+IOC_IBASE);
1485 WRITE_REG(ioc->imask, ioc->ioc_hpa+IOC_IMASK);
1486
1487 /* Set I/O PDIR Page size to system page size */
1488 switch (PAGE_SHIFT) {
1489 case 12: tcnfg = 0; break; /* 4K */
1490 case 13: tcnfg = 1; break; /* 8K */
1491 case 14: tcnfg = 2; break; /* 16K */
1492 case 16: tcnfg = 3; break; /* 64K */
1493 default:
1494 panic(__FILE__ "Unsupported system page size %d",
1495 1 << PAGE_SHIFT);
1496 break;
1497 }
1498 /* Set I/O PDIR Page size to PAGE_SIZE (4k/16k/...) */
1499 WRITE_REG(tcnfg, ioc->ioc_hpa+IOC_TCNFG);
1500
1501 /*
1502 ** Clear I/O TLB of any possible entries.
1503 ** (Yes. This is a bit paranoid...but so what)
1504 */
1505 WRITE_REG(0 | 31, ioc->ioc_hpa+IOC_PCOM);
1506
1507 ioc->ibase = 0; /* used by SBA_IOVA and related macros */
1508
1509 DBG_INIT("%s() DONE\n", __func__);
1510}
1511
1512
1513
1514/**************************************************************************
1515**
1516** SBA initialization code (HW and SW)
1517**
1518** o identify SBA chip itself
1519** o initialize SBA chip modes (HardFail)
1520** o initialize SBA chip modes (HardFail)
1521** o FIXME: initialize DMA hints for reasonable defaults
1522**
1523**************************************************************************/
1524
1525static void __iomem *ioc_remap(struct sba_device *sba_dev, unsigned int offset)
1526{
1527 return ioremap_nocache(sba_dev->dev->hpa.start + offset, SBA_FUNC_SIZE);
1528}
1529
1530static void sba_hw_init(struct sba_device *sba_dev)
1531{
1532 int i;
1533 int num_ioc;
1534 u64 ioc_ctl;
1535
1536 if (!is_pdc_pat()) {
1537 /* Shutdown the USB controller on Astro-based workstations.
1538 ** Once we reprogram the IOMMU, the next DMA performed by
1539 ** USB will HPMC the box. USB is only enabled if a
1540 ** keyboard is present and found.
1541 **
1542 ** With serial console, j6k v5.0 firmware says:
1543 ** mem_kbd hpa 0xfee003f8 sba 0x0 pad 0x0 cl_class 0x7
1544 **
1545 ** FIXME: Using GFX+USB console at power up but direct
1546 ** linux to serial console is still broken.
1547 ** USB could generate DMA so we must reset USB.
1548 ** The proper sequence would be:
1549 ** o block console output
1550 ** o reset USB device
1551 ** o reprogram serial port
1552 ** o unblock console output
1553 */
1554 if (PAGE0->mem_kbd.cl_class == CL_KEYBD) {
1555 pdc_io_reset_devices();
1556 }
1557
1558 }
1559
1560
1561#if 0
1562printk("sba_hw_init(): mem_boot 0x%x 0x%x 0x%x 0x%x\n", PAGE0->mem_boot.hpa,
1563 PAGE0->mem_boot.spa, PAGE0->mem_boot.pad, PAGE0->mem_boot.cl_class);
1564
1565 /*
1566 ** Need to deal with DMA from LAN.
1567 ** Maybe use page zero boot device as a handle to talk
1568 ** to PDC about which device to shutdown.
1569 **
1570 ** Netbooting, j6k v5.0 firmware says:
1571 ** mem_boot hpa 0xf4008000 sba 0x0 pad 0x0 cl_class 0x1002
1572 ** ARGH! invalid class.
1573 */
1574 if ((PAGE0->mem_boot.cl_class != CL_RANDOM)
1575 && (PAGE0->mem_boot.cl_class != CL_SEQU)) {
1576 pdc_io_reset();
1577 }
1578#endif
1579
1580 if (!IS_PLUTO(sba_dev->dev)) {
1581 ioc_ctl = READ_REG(sba_dev->sba_hpa+IOC_CTRL);
1582 DBG_INIT("%s() hpa 0x%lx ioc_ctl 0x%Lx ->",
1583 __func__, sba_dev->sba_hpa, ioc_ctl);
1584 ioc_ctl &= ~(IOC_CTRL_RM | IOC_CTRL_NC | IOC_CTRL_CE);
1585 ioc_ctl |= IOC_CTRL_DD | IOC_CTRL_D4 | IOC_CTRL_TC;
1586 /* j6700 v1.6 firmware sets 0x294f */
1587 /* A500 firmware sets 0x4d */
1588
1589 WRITE_REG(ioc_ctl, sba_dev->sba_hpa+IOC_CTRL);
1590
1591#ifdef DEBUG_SBA_INIT
1592 ioc_ctl = READ_REG64(sba_dev->sba_hpa+IOC_CTRL);
1593 DBG_INIT(" 0x%Lx\n", ioc_ctl);
1594#endif
1595 } /* if !PLUTO */
1596
1597 if (IS_ASTRO(sba_dev->dev)) {
1598 int err;
1599 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, ASTRO_IOC_OFFSET);
1600 num_ioc = 1;
1601
1602 sba_dev->chip_resv.name = "Astro Intr Ack";
1603 sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfef00000UL;
1604 sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff000000UL - 1) ;
1605 err = request_resource(&iomem_resource, &(sba_dev->chip_resv));
1606 BUG_ON(err < 0);
1607
1608 } else if (IS_PLUTO(sba_dev->dev)) {
1609 int err;
1610
1611 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, PLUTO_IOC_OFFSET);
1612 num_ioc = 1;
1613
1614 sba_dev->chip_resv.name = "Pluto Intr/PIOP/VGA";
1615 sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfee00000UL;
1616 sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff200000UL - 1);
1617 err = request_resource(&iomem_resource, &(sba_dev->chip_resv));
1618 WARN_ON(err < 0);
1619
1620 sba_dev->iommu_resv.name = "IOVA Space";
1621 sba_dev->iommu_resv.start = 0x40000000UL;
1622 sba_dev->iommu_resv.end = 0x50000000UL - 1;
1623 err = request_resource(&iomem_resource, &(sba_dev->iommu_resv));
1624 WARN_ON(err < 0);
1625 } else {
1626 /* IKE, REO */
1627 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(0));
1628 sba_dev->ioc[1].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(1));
1629 num_ioc = 2;
1630
1631 /* TODO - LOOKUP Ike/Stretch chipset mem map */
1632 }
1633 /* XXX: What about Reo Grande? */
1634
1635 sba_dev->num_ioc = num_ioc;
1636 for (i = 0; i < num_ioc; i++) {
1637 void __iomem *ioc_hpa = sba_dev->ioc[i].ioc_hpa;
1638 unsigned int j;
1639
1640 for (j=0; j < sizeof(u64) * ROPES_PER_IOC; j+=sizeof(u64)) {
1641
1642 /*
1643 * Clear ROPE(N)_CONFIG AO bit.
1644 * Disables "NT Ordering" (~= !"Relaxed Ordering")
1645 * Overrides bit 1 in DMA Hint Sets.
1646 * Improves netperf UDP_STREAM by ~10% for bcm5701.
1647 */
1648 if (IS_PLUTO(sba_dev->dev)) {
1649 void __iomem *rope_cfg;
1650 unsigned long cfg_val;
1651
1652 rope_cfg = ioc_hpa + IOC_ROPE0_CFG + j;
1653 cfg_val = READ_REG(rope_cfg);
1654 cfg_val &= ~IOC_ROPE_AO;
1655 WRITE_REG(cfg_val, rope_cfg);
1656 }
1657
1658 /*
1659 ** Make sure the box crashes on rope errors.
1660 */
1661 WRITE_REG(HF_ENABLE, ioc_hpa + ROPE0_CTL + j);
1662 }
1663
1664 /* flush out the last writes */
1665 READ_REG(sba_dev->ioc[i].ioc_hpa + ROPE7_CTL);
1666
1667 DBG_INIT(" ioc[%d] ROPE_CFG 0x%Lx ROPE_DBG 0x%Lx\n",
1668 i,
1669 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x40),
1670 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x50)
1671 );
1672 DBG_INIT(" STATUS_CONTROL 0x%Lx FLUSH_CTRL 0x%Lx\n",
1673 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x108),
1674 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x400)
1675 );
1676
1677 if (IS_PLUTO(sba_dev->dev)) {
1678 sba_ioc_init_pluto(sba_dev->dev, &(sba_dev->ioc[i]), i);
1679 } else {
1680 sba_ioc_init(sba_dev->dev, &(sba_dev->ioc[i]), i);
1681 }
1682 }
1683}
1684
1685static void
1686sba_common_init(struct sba_device *sba_dev)
1687{
1688 int i;
1689
1690 /* add this one to the head of the list (order doesn't matter)
1691 ** This will be useful for debugging - especially if we get coredumps
1692 */
1693 sba_dev->next = sba_list;
1694 sba_list = sba_dev;
1695
1696 for(i=0; i< sba_dev->num_ioc; i++) {
1697 int res_size;
1698#ifdef DEBUG_DMB_TRAP
1699 extern void iterate_pages(unsigned long , unsigned long ,
1700 void (*)(pte_t * , unsigned long),
1701 unsigned long );
1702 void set_data_memory_break(pte_t * , unsigned long);
1703#endif
1704 /* resource map size dictated by pdir_size */
1705 res_size = sba_dev->ioc[i].pdir_size/sizeof(u64); /* entries */
1706
1707 /* Second part of PIRANHA BUG */
1708 if (piranha_bad_128k) {
1709 res_size -= (128*1024)/sizeof(u64);
1710 }
1711
1712 res_size >>= 3; /* convert bit count to byte count */
1713 DBG_INIT("%s() res_size 0x%x\n",
1714 __func__, res_size);
1715
1716 sba_dev->ioc[i].res_size = res_size;
1717 sba_dev->ioc[i].res_map = (char *) __get_free_pages(GFP_KERNEL, get_order(res_size));
1718
1719#ifdef DEBUG_DMB_TRAP
1720 iterate_pages( sba_dev->ioc[i].res_map, res_size,
1721 set_data_memory_break, 0);
1722#endif
1723
1724 if (NULL == sba_dev->ioc[i].res_map)
1725 {
1726 panic("%s:%s() could not allocate resource map\n",
1727 __FILE__, __func__ );
1728 }
1729
1730 memset(sba_dev->ioc[i].res_map, 0, res_size);
1731 /* next available IOVP - circular search */
1732 sba_dev->ioc[i].res_hint = (unsigned long *)
1733 &(sba_dev->ioc[i].res_map[L1_CACHE_BYTES]);
1734
1735#ifdef ASSERT_PDIR_SANITY
1736 /* Mark first bit busy - ie no IOVA 0 */
1737 sba_dev->ioc[i].res_map[0] = 0x80;
1738 sba_dev->ioc[i].pdir_base[0] = 0xeeffc0addbba0080ULL;
1739#endif
1740
1741 /* Third (and last) part of PIRANHA BUG */
1742 if (piranha_bad_128k) {
1743 /* region from +1408K to +1536 is un-usable. */
1744
1745 int idx_start = (1408*1024/sizeof(u64)) >> 3;
1746 int idx_end = (1536*1024/sizeof(u64)) >> 3;
1747 long *p_start = (long *) &(sba_dev->ioc[i].res_map[idx_start]);
1748 long *p_end = (long *) &(sba_dev->ioc[i].res_map[idx_end]);
1749
1750 /* mark that part of the io pdir busy */
1751 while (p_start < p_end)
1752 *p_start++ = -1;
1753
1754 }
1755
1756#ifdef DEBUG_DMB_TRAP
1757 iterate_pages( sba_dev->ioc[i].res_map, res_size,
1758 set_data_memory_break, 0);
1759 iterate_pages( sba_dev->ioc[i].pdir_base, sba_dev->ioc[i].pdir_size,
1760 set_data_memory_break, 0);
1761#endif
1762
1763 DBG_INIT("%s() %d res_map %x %p\n",
1764 __func__, i, res_size, sba_dev->ioc[i].res_map);
1765 }
1766
1767 spin_lock_init(&sba_dev->sba_lock);
1768 ioc_needs_fdc = boot_cpu_data.pdc.capabilities & PDC_MODEL_IOPDIR_FDC;
1769
1770#ifdef DEBUG_SBA_INIT
1771 /*
1772 * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set
1773 * (bit #61, big endian), we have to flush and sync every time
1774 * IO-PDIR is changed in Ike/Astro.
1775 */
1776 if (ioc_needs_fdc) {
1777 printk(KERN_INFO MODULE_NAME " FDC/SYNC required.\n");
1778 } else {
1779 printk(KERN_INFO MODULE_NAME " IOC has cache coherent PDIR.\n");
1780 }
1781#endif
1782}
1783
1784#ifdef CONFIG_PROC_FS
1785static int sba_proc_info(struct seq_file *m, void *p)
1786{
1787 struct sba_device *sba_dev = sba_list;
1788 struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Multi-IOC support! */
1789 int total_pages = (int) (ioc->res_size << 3); /* 8 bits per byte */
1790#ifdef SBA_COLLECT_STATS
1791 unsigned long avg = 0, min, max;
1792#endif
1793 int i;
1794
1795 seq_printf(m, "%s rev %d.%d\n",
1796 sba_dev->name,
1797 (sba_dev->hw_rev & 0x7) + 1,
1798 (sba_dev->hw_rev & 0x18) >> 3);
1799 seq_printf(m, "IO PDIR size : %d bytes (%d entries)\n",
1800 (int)((ioc->res_size << 3) * sizeof(u64)), /* 8 bits/byte */
1801 total_pages);
1802
1803 seq_printf(m, "Resource bitmap : %d bytes (%d pages)\n",
1804 ioc->res_size, ioc->res_size << 3); /* 8 bits per byte */
1805
1806 seq_printf(m, "LMMIO_BASE/MASK/ROUTE %08x %08x %08x\n",
1807 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_BASE),
1808 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_MASK),
1809 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_ROUTE));
1810
1811 for (i=0; i<4; i++)
1812 seq_printf(m, "DIR%d_BASE/MASK/ROUTE %08x %08x %08x\n",
1813 i,
1814 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_BASE + i*0x18),
1815 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_MASK + i*0x18),
1816 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_ROUTE + i*0x18));
1817
1818#ifdef SBA_COLLECT_STATS
1819 seq_printf(m, "IO PDIR entries : %ld free %ld used (%d%%)\n",
1820 total_pages - ioc->used_pages, ioc->used_pages,
1821 (int)(ioc->used_pages * 100 / total_pages));
1822
1823 min = max = ioc->avg_search[0];
1824 for (i = 0; i < SBA_SEARCH_SAMPLE; i++) {
1825 avg += ioc->avg_search[i];
1826 if (ioc->avg_search[i] > max) max = ioc->avg_search[i];
1827 if (ioc->avg_search[i] < min) min = ioc->avg_search[i];
1828 }
1829 avg /= SBA_SEARCH_SAMPLE;
1830 seq_printf(m, " Bitmap search : %ld/%ld/%ld (min/avg/max CPU Cycles)\n",
1831 min, avg, max);
1832
1833 seq_printf(m, "pci_map_single(): %12ld calls %12ld pages (avg %d/1000)\n",
1834 ioc->msingle_calls, ioc->msingle_pages,
1835 (int)((ioc->msingle_pages * 1000)/ioc->msingle_calls));
1836
1837 /* KLUGE - unmap_sg calls unmap_single for each mapped page */
1838 min = ioc->usingle_calls;
1839 max = ioc->usingle_pages - ioc->usg_pages;
1840 seq_printf(m, "pci_unmap_single: %12ld calls %12ld pages (avg %d/1000)\n",
1841 min, max, (int)((max * 1000)/min));
1842
1843 seq_printf(m, "pci_map_sg() : %12ld calls %12ld pages (avg %d/1000)\n",
1844 ioc->msg_calls, ioc->msg_pages,
1845 (int)((ioc->msg_pages * 1000)/ioc->msg_calls));
1846
1847 seq_printf(m, "pci_unmap_sg() : %12ld calls %12ld pages (avg %d/1000)\n",
1848 ioc->usg_calls, ioc->usg_pages,
1849 (int)((ioc->usg_pages * 1000)/ioc->usg_calls));
1850#endif
1851
1852 return 0;
1853}
1854
1855static int
1856sba_proc_bitmap_info(struct seq_file *m, void *p)
1857{
1858 struct sba_device *sba_dev = sba_list;
1859 struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Multi-IOC support! */
1860
1861 seq_hex_dump(m, " ", DUMP_PREFIX_NONE, 32, 4, ioc->res_map,
1862 ioc->res_size, false);
1863 seq_putc(m, '\n');
1864
1865 return 0;
1866}
1867#endif /* CONFIG_PROC_FS */
1868
1869static const struct parisc_device_id sba_tbl[] __initconst = {
1870 { HPHW_IOA, HVERSION_REV_ANY_ID, ASTRO_RUNWAY_PORT, 0xb },
1871 { HPHW_BCPORT, HVERSION_REV_ANY_ID, IKE_MERCED_PORT, 0xc },
1872 { HPHW_BCPORT, HVERSION_REV_ANY_ID, REO_MERCED_PORT, 0xc },
1873 { HPHW_BCPORT, HVERSION_REV_ANY_ID, REOG_MERCED_PORT, 0xc },
1874 { HPHW_IOA, HVERSION_REV_ANY_ID, PLUTO_MCKINLEY_PORT, 0xc },
1875 { 0, }
1876};
1877
1878static int sba_driver_callback(struct parisc_device *);
1879
1880static struct parisc_driver sba_driver __refdata = {
1881 .name = MODULE_NAME,
1882 .id_table = sba_tbl,
1883 .probe = sba_driver_callback,
1884};
1885
1886/*
1887** Determine if sba should claim this chip (return 0) or not (return 1).
1888** If so, initialize the chip and tell other partners in crime they
1889** have work to do.
1890*/
1891static int __init sba_driver_callback(struct parisc_device *dev)
1892{
1893 struct sba_device *sba_dev;
1894 u32 func_class;
1895 int i;
1896 char *version;
1897 void __iomem *sba_addr = ioremap_nocache(dev->hpa.start, SBA_FUNC_SIZE);
1898#ifdef CONFIG_PROC_FS
1899 struct proc_dir_entry *root;
1900#endif
1901
1902 sba_dump_ranges(sba_addr);
1903
1904 /* Read HW Rev First */
1905 func_class = READ_REG(sba_addr + SBA_FCLASS);
1906
1907 if (IS_ASTRO(dev)) {
1908 unsigned long fclass;
1909 static char astro_rev[]="Astro ?.?";
1910
1911 /* Astro is broken...Read HW Rev First */
1912 fclass = READ_REG(sba_addr);
1913
1914 astro_rev[6] = '1' + (char) (fclass & 0x7);
1915 astro_rev[8] = '0' + (char) ((fclass & 0x18) >> 3);
1916 version = astro_rev;
1917
1918 } else if (IS_IKE(dev)) {
1919 static char ike_rev[] = "Ike rev ?";
1920 ike_rev[8] = '0' + (char) (func_class & 0xff);
1921 version = ike_rev;
1922 } else if (IS_PLUTO(dev)) {
1923 static char pluto_rev[]="Pluto ?.?";
1924 pluto_rev[6] = '0' + (char) ((func_class & 0xf0) >> 4);
1925 pluto_rev[8] = '0' + (char) (func_class & 0x0f);
1926 version = pluto_rev;
1927 } else {
1928 static char reo_rev[] = "REO rev ?";
1929 reo_rev[8] = '0' + (char) (func_class & 0xff);
1930 version = reo_rev;
1931 }
1932
1933 if (!global_ioc_cnt) {
1934 global_ioc_cnt = count_parisc_driver(&sba_driver);
1935
1936 /* Astro and Pluto have one IOC per SBA */
1937 if ((!IS_ASTRO(dev)) || (!IS_PLUTO(dev)))
1938 global_ioc_cnt *= 2;
1939 }
1940
1941 printk(KERN_INFO "%s found %s at 0x%llx\n",
1942 MODULE_NAME, version, (unsigned long long)dev->hpa.start);
1943
1944 sba_dev = kzalloc(sizeof(struct sba_device), GFP_KERNEL);
1945 if (!sba_dev) {
1946 printk(KERN_ERR MODULE_NAME " - couldn't alloc sba_device\n");
1947 return -ENOMEM;
1948 }
1949
1950 parisc_set_drvdata(dev, sba_dev);
1951
1952 for(i=0; i<MAX_IOC; i++)
1953 spin_lock_init(&(sba_dev->ioc[i].res_lock));
1954
1955 sba_dev->dev = dev;
1956 sba_dev->hw_rev = func_class;
1957 sba_dev->name = dev->name;
1958 sba_dev->sba_hpa = sba_addr;
1959
1960 sba_get_pat_resources(sba_dev);
1961 sba_hw_init(sba_dev);
1962 sba_common_init(sba_dev);
1963
1964 hppa_dma_ops = &sba_ops;
1965
1966#ifdef CONFIG_PROC_FS
1967 switch (dev->id.hversion) {
1968 case PLUTO_MCKINLEY_PORT:
1969 root = proc_mckinley_root;
1970 break;
1971 case ASTRO_RUNWAY_PORT:
1972 case IKE_MERCED_PORT:
1973 default:
1974 root = proc_runway_root;
1975 break;
1976 }
1977
1978 proc_create_single("sba_iommu", 0, root, sba_proc_info);
1979 proc_create_single("sba_iommu-bitmap", 0, root, sba_proc_bitmap_info);
1980#endif
1981 return 0;
1982}
1983
1984/*
1985** One time initialization to let the world know the SBA was found.
1986** This is the only routine which is NOT static.
1987** Must be called exactly once before pci_init().
1988*/
1989void __init sba_init(void)
1990{
1991 register_parisc_driver(&sba_driver);
1992}
1993
1994
1995/**
1996 * sba_get_iommu - Assign the iommu pointer for the pci bus controller.
1997 * @dev: The parisc device.
1998 *
1999 * Returns the appropriate IOMMU data for the given parisc PCI controller.
2000 * This is cached and used later for PCI DMA Mapping.
2001 */
2002void * sba_get_iommu(struct parisc_device *pci_hba)
2003{
2004 struct parisc_device *sba_dev = parisc_parent(pci_hba);
2005 struct sba_device *sba = dev_get_drvdata(&sba_dev->dev);
2006 char t = sba_dev->id.hw_type;
2007 int iocnum = (pci_hba->hw_path >> 3); /* rope # */
2008
2009 WARN_ON((t != HPHW_IOA) && (t != HPHW_BCPORT));
2010
2011 return &(sba->ioc[iocnum]);
2012}
2013
2014
2015/**
2016 * sba_directed_lmmio - return first directed LMMIO range routed to rope
2017 * @pa_dev: The parisc device.
2018 * @r: resource PCI host controller wants start/end fields assigned.
2019 *
2020 * For the given parisc PCI controller, determine if any direct ranges
2021 * are routed down the corresponding rope.
2022 */
2023void sba_directed_lmmio(struct parisc_device *pci_hba, struct resource *r)
2024{
2025 struct parisc_device *sba_dev = parisc_parent(pci_hba);
2026 struct sba_device *sba = dev_get_drvdata(&sba_dev->dev);
2027 char t = sba_dev->id.hw_type;
2028 int i;
2029 int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1)); /* rope # */
2030
2031 BUG_ON((t!=HPHW_IOA) && (t!=HPHW_BCPORT));
2032
2033 r->start = r->end = 0;
2034
2035 /* Astro has 4 directed ranges. Not sure about Ike/Pluto/et al */
2036 for (i=0; i<4; i++) {
2037 int base, size;
2038 void __iomem *reg = sba->sba_hpa + i*0x18;
2039
2040 base = READ_REG32(reg + LMMIO_DIRECT0_BASE);
2041 if ((base & 1) == 0)
2042 continue; /* not enabled */
2043
2044 size = READ_REG32(reg + LMMIO_DIRECT0_ROUTE);
2045
2046 if ((size & (ROPES_PER_IOC-1)) != rope)
2047 continue; /* directed down different rope */
2048
2049 r->start = (base & ~1UL) | PCI_F_EXTEND;
2050 size = ~ READ_REG32(reg + LMMIO_DIRECT0_MASK);
2051 r->end = r->start + size;
2052 r->flags = IORESOURCE_MEM;
2053 }
2054}
2055
2056
2057/**
2058 * sba_distributed_lmmio - return portion of distributed LMMIO range
2059 * @pa_dev: The parisc device.
2060 * @r: resource PCI host controller wants start/end fields assigned.
2061 *
2062 * For the given parisc PCI controller, return portion of distributed LMMIO
2063 * range. The distributed LMMIO is always present and it's just a question
2064 * of the base address and size of the range.
2065 */
2066void sba_distributed_lmmio(struct parisc_device *pci_hba, struct resource *r )
2067{
2068 struct parisc_device *sba_dev = parisc_parent(pci_hba);
2069 struct sba_device *sba = dev_get_drvdata(&sba_dev->dev);
2070 char t = sba_dev->id.hw_type;
2071 int base, size;
2072 int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1)); /* rope # */
2073
2074 BUG_ON((t!=HPHW_IOA) && (t!=HPHW_BCPORT));
2075
2076 r->start = r->end = 0;
2077
2078 base = READ_REG32(sba->sba_hpa + LMMIO_DIST_BASE);
2079 if ((base & 1) == 0) {
2080 BUG(); /* Gah! Distr Range wasn't enabled! */
2081 return;
2082 }
2083
2084 r->start = (base & ~1UL) | PCI_F_EXTEND;
2085
2086 size = (~READ_REG32(sba->sba_hpa + LMMIO_DIST_MASK)) / ROPES_PER_IOC;
2087 r->start += rope * (size + 1); /* adjust base for this rope */
2088 r->end = r->start + size;
2089 r->flags = IORESOURCE_MEM;
2090}
2091

Warning: That file was not part of the compilation database. It may have many parsing errors.