1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | #ifndef DRIVERS_PCI_H |
3 | #define DRIVERS_PCI_H |
4 | |
5 | #include <linux/pci.h> |
6 | |
7 | /* Number of possible devfns: 0.0 to 1f.7 inclusive */ |
8 | #define MAX_NR_DEVFNS 256 |
9 | |
10 | #define PCI_FIND_CAP_TTL 48 |
11 | |
12 | #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */ |
13 | |
14 | #define PCIE_LINK_RETRAIN_TIMEOUT_MS 1000 |
15 | |
16 | /* Power stable to PERST# inactive from PCIe card Electromechanical Spec */ |
17 | #define PCIE_T_PVPERL_MS 100 |
18 | |
19 | /* |
20 | * PCIe r6.0, sec 5.3.3.2.1 <PME Synchronization> |
21 | * Recommends 1ms to 10ms timeout to check L2 ready. |
22 | */ |
23 | #define PCIE_PME_TO_L2_TIMEOUT_US 10000 |
24 | |
25 | extern const unsigned char pcie_link_speed[]; |
26 | extern bool pci_early_dump; |
27 | |
28 | bool pcie_cap_has_lnkctl(const struct pci_dev *dev); |
29 | bool pcie_cap_has_lnkctl2(const struct pci_dev *dev); |
30 | bool pcie_cap_has_rtctl(const struct pci_dev *dev); |
31 | |
32 | /* Functions internal to the PCI core code */ |
33 | |
34 | int pci_create_sysfs_dev_files(struct pci_dev *pdev); |
35 | void pci_remove_sysfs_dev_files(struct pci_dev *pdev); |
36 | void pci_cleanup_rom(struct pci_dev *dev); |
37 | #ifdef CONFIG_DMI |
38 | extern const struct attribute_group pci_dev_smbios_attr_group; |
39 | #endif |
40 | |
41 | enum pci_mmap_api { |
42 | PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */ |
43 | PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */ |
44 | }; |
45 | int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai, |
46 | enum pci_mmap_api mmap_api); |
47 | |
48 | bool pci_reset_supported(struct pci_dev *dev); |
49 | void pci_init_reset_methods(struct pci_dev *dev); |
50 | int pci_bridge_secondary_bus_reset(struct pci_dev *dev); |
51 | int pci_bus_error_reset(struct pci_dev *dev); |
52 | |
53 | struct pci_cap_saved_data { |
54 | u16 cap_nr; |
55 | bool cap_extended; |
56 | unsigned int size; |
57 | u32 data[]; |
58 | }; |
59 | |
60 | struct pci_cap_saved_state { |
61 | struct hlist_node next; |
62 | struct pci_cap_saved_data cap; |
63 | }; |
64 | |
65 | void pci_allocate_cap_save_buffers(struct pci_dev *dev); |
66 | void pci_free_cap_save_buffers(struct pci_dev *dev); |
67 | int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); |
68 | int pci_add_ext_cap_save_buffer(struct pci_dev *dev, |
69 | u16 cap, unsigned int size); |
70 | struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); |
71 | struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, |
72 | u16 cap); |
73 | |
74 | #define PCI_PM_D2_DELAY 200 /* usec; see PCIe r4.0, sec 5.9.1 */ |
75 | #define PCI_PM_D3HOT_WAIT 10 /* msec */ |
76 | #define PCI_PM_D3COLD_WAIT 100 /* msec */ |
77 | |
78 | void pci_update_current_state(struct pci_dev *dev, pci_power_t state); |
79 | void pci_refresh_power_state(struct pci_dev *dev); |
80 | int pci_power_up(struct pci_dev *dev); |
81 | void pci_disable_enabled_device(struct pci_dev *dev); |
82 | int pci_finish_runtime_suspend(struct pci_dev *dev); |
83 | void pcie_clear_device_status(struct pci_dev *dev); |
84 | void pcie_clear_root_pme_status(struct pci_dev *dev); |
85 | bool pci_check_pme_status(struct pci_dev *dev); |
86 | void pci_pme_wakeup_bus(struct pci_bus *bus); |
87 | int __pci_pme_wakeup(struct pci_dev *dev, void *ign); |
88 | void pci_pme_restore(struct pci_dev *dev); |
89 | bool pci_dev_need_resume(struct pci_dev *dev); |
90 | void pci_dev_adjust_pme(struct pci_dev *dev); |
91 | void pci_dev_complete_resume(struct pci_dev *pci_dev); |
92 | void pci_config_pm_runtime_get(struct pci_dev *dev); |
93 | void pci_config_pm_runtime_put(struct pci_dev *dev); |
94 | void pci_pm_init(struct pci_dev *dev); |
95 | void pci_ea_init(struct pci_dev *dev); |
96 | void pci_msi_init(struct pci_dev *dev); |
97 | void pci_msix_init(struct pci_dev *dev); |
98 | bool pci_bridge_d3_possible(struct pci_dev *dev); |
99 | void pci_bridge_d3_update(struct pci_dev *dev); |
100 | void pci_bridge_reconfigure_ltr(struct pci_dev *dev); |
101 | int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type); |
102 | |
103 | static inline void pci_wakeup_event(struct pci_dev *dev) |
104 | { |
105 | /* Wait 100 ms before the system can be put into a sleep state. */ |
106 | pm_wakeup_event(dev: &dev->dev, msec: 100); |
107 | } |
108 | |
109 | static inline bool pci_has_subordinate(struct pci_dev *pci_dev) |
110 | { |
111 | return !!(pci_dev->subordinate); |
112 | } |
113 | |
114 | static inline bool pci_power_manageable(struct pci_dev *pci_dev) |
115 | { |
116 | /* |
117 | * Currently we allow normal PCI devices and PCI bridges transition |
118 | * into D3 if their bridge_d3 is set. |
119 | */ |
120 | return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3; |
121 | } |
122 | |
123 | static inline bool pcie_downstream_port(const struct pci_dev *dev) |
124 | { |
125 | int type = pci_pcie_type(dev); |
126 | |
127 | return type == PCI_EXP_TYPE_ROOT_PORT || |
128 | type == PCI_EXP_TYPE_DOWNSTREAM || |
129 | type == PCI_EXP_TYPE_PCIE_BRIDGE; |
130 | } |
131 | |
132 | void pci_vpd_init(struct pci_dev *dev); |
133 | void pci_vpd_release(struct pci_dev *dev); |
134 | extern const struct attribute_group pci_dev_vpd_attr_group; |
135 | |
136 | /* PCI Virtual Channel */ |
137 | int pci_save_vc_state(struct pci_dev *dev); |
138 | void pci_restore_vc_state(struct pci_dev *dev); |
139 | void pci_allocate_vc_save_buffers(struct pci_dev *dev); |
140 | |
141 | /* PCI /proc functions */ |
142 | #ifdef CONFIG_PROC_FS |
143 | int pci_proc_attach_device(struct pci_dev *dev); |
144 | int pci_proc_detach_device(struct pci_dev *dev); |
145 | int pci_proc_detach_bus(struct pci_bus *bus); |
146 | #else |
147 | static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; } |
148 | static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; } |
149 | static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; } |
150 | #endif |
151 | |
152 | /* Functions for PCI Hotplug drivers to use */ |
153 | int pci_hp_add_bridge(struct pci_dev *dev); |
154 | |
155 | #ifdef HAVE_PCI_LEGACY |
156 | void pci_create_legacy_files(struct pci_bus *bus); |
157 | void pci_remove_legacy_files(struct pci_bus *bus); |
158 | #else |
159 | static inline void pci_create_legacy_files(struct pci_bus *bus) { } |
160 | static inline void pci_remove_legacy_files(struct pci_bus *bus) { } |
161 | #endif |
162 | |
163 | /* Lock for read/write access to pci device and bus lists */ |
164 | extern struct rw_semaphore pci_bus_sem; |
165 | extern struct mutex pci_slot_mutex; |
166 | |
167 | extern raw_spinlock_t pci_lock; |
168 | |
169 | extern unsigned int pci_pm_d3hot_delay; |
170 | |
171 | #ifdef CONFIG_PCI_MSI |
172 | void pci_no_msi(void); |
173 | #else |
174 | static inline void pci_no_msi(void) { } |
175 | #endif |
176 | |
177 | void pci_realloc_get_opt(char *); |
178 | |
179 | static inline int pci_no_d1d2(struct pci_dev *dev) |
180 | { |
181 | unsigned int parent_dstates = 0; |
182 | |
183 | if (dev->bus->self) |
184 | parent_dstates = dev->bus->self->no_d1d2; |
185 | return (dev->no_d1d2 || parent_dstates); |
186 | |
187 | } |
188 | extern const struct attribute_group *pci_dev_groups[]; |
189 | extern const struct attribute_group *pcibus_groups[]; |
190 | extern const struct device_type pci_dev_type; |
191 | extern const struct attribute_group *pci_bus_groups[]; |
192 | |
193 | extern unsigned long pci_hotplug_io_size; |
194 | extern unsigned long pci_hotplug_mmio_size; |
195 | extern unsigned long pci_hotplug_mmio_pref_size; |
196 | extern unsigned long pci_hotplug_bus_size; |
197 | |
198 | /** |
199 | * pci_match_one_device - Tell if a PCI device structure has a matching |
200 | * PCI device id structure |
201 | * @id: single PCI device id structure to match |
202 | * @dev: the PCI device structure to match against |
203 | * |
204 | * Returns the matching pci_device_id structure or %NULL if there is no match. |
205 | */ |
206 | static inline const struct pci_device_id * |
207 | pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev) |
208 | { |
209 | if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) && |
210 | (id->device == PCI_ANY_ID || id->device == dev->device) && |
211 | (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) && |
212 | (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) && |
213 | !((id->class ^ dev->class) & id->class_mask)) |
214 | return id; |
215 | return NULL; |
216 | } |
217 | |
218 | /* PCI slot sysfs helper code */ |
219 | #define to_pci_slot(s) container_of(s, struct pci_slot, kobj) |
220 | |
221 | extern struct kset *pci_slots_kset; |
222 | |
223 | struct pci_slot_attribute { |
224 | struct attribute attr; |
225 | ssize_t (*show)(struct pci_slot *, char *); |
226 | ssize_t (*store)(struct pci_slot *, const char *, size_t); |
227 | }; |
228 | #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr) |
229 | |
230 | enum pci_bar_type { |
231 | pci_bar_unknown, /* Standard PCI BAR probe */ |
232 | pci_bar_io, /* An I/O port BAR */ |
233 | pci_bar_mem32, /* A 32-bit memory BAR */ |
234 | pci_bar_mem64, /* A 64-bit memory BAR */ |
235 | }; |
236 | |
237 | struct device *pci_get_host_bridge_device(struct pci_dev *dev); |
238 | void pci_put_host_bridge_device(struct device *dev); |
239 | |
240 | int pci_configure_extended_tags(struct pci_dev *dev, void *ign); |
241 | bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, |
242 | int crs_timeout); |
243 | bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, |
244 | int crs_timeout); |
245 | int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout); |
246 | |
247 | int pci_setup_device(struct pci_dev *dev); |
248 | int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, |
249 | struct resource *res, unsigned int reg); |
250 | void pci_configure_ari(struct pci_dev *dev); |
251 | void __pci_bus_size_bridges(struct pci_bus *bus, |
252 | struct list_head *realloc_head); |
253 | void __pci_bus_assign_resources(const struct pci_bus *bus, |
254 | struct list_head *realloc_head, |
255 | struct list_head *fail_head); |
256 | bool pci_bus_clip_resource(struct pci_dev *dev, int idx); |
257 | |
258 | void pci_reassigndev_resource_alignment(struct pci_dev *dev); |
259 | void pci_disable_bridge_window(struct pci_dev *dev); |
260 | struct pci_bus *pci_bus_get(struct pci_bus *bus); |
261 | void pci_bus_put(struct pci_bus *bus); |
262 | |
263 | /* PCIe link information from Link Capabilities 2 */ |
264 | #define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \ |
265 | ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \ |
266 | (lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \ |
267 | (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \ |
268 | (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \ |
269 | (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \ |
270 | (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \ |
271 | PCI_SPEED_UNKNOWN) |
272 | |
273 | /* PCIe speed to Mb/s reduced by encoding overhead */ |
274 | #define PCIE_SPEED2MBS_ENC(speed) \ |
275 | ((speed) == PCIE_SPEED_64_0GT ? 64000*128/130 : \ |
276 | (speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \ |
277 | (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \ |
278 | (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \ |
279 | (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \ |
280 | (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \ |
281 | 0) |
282 | |
283 | const char *pci_speed_string(enum pci_bus_speed speed); |
284 | enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); |
285 | enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); |
286 | u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed, |
287 | enum pcie_link_width *width); |
288 | void __pcie_print_link_status(struct pci_dev *dev, bool verbose); |
289 | void pcie_report_downtraining(struct pci_dev *dev); |
290 | void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); |
291 | |
292 | /* Single Root I/O Virtualization */ |
293 | struct pci_sriov { |
294 | int pos; /* Capability position */ |
295 | int nres; /* Number of resources */ |
296 | u32 cap; /* SR-IOV Capabilities */ |
297 | u16 ctrl; /* SR-IOV Control */ |
298 | u16 total_VFs; /* Total VFs associated with the PF */ |
299 | u16 initial_VFs; /* Initial VFs associated with the PF */ |
300 | u16 num_VFs; /* Number of VFs available */ |
301 | u16 offset; /* First VF Routing ID offset */ |
302 | u16 stride; /* Following VF stride */ |
303 | u16 vf_device; /* VF device ID */ |
304 | u32 pgsz; /* Page size for BAR alignment */ |
305 | u8 link; /* Function Dependency Link */ |
306 | u8 max_VF_buses; /* Max buses consumed by VFs */ |
307 | u16 driver_max_VFs; /* Max num VFs driver supports */ |
308 | struct pci_dev *dev; /* Lowest numbered PF */ |
309 | struct pci_dev *self; /* This PF */ |
310 | u32 class; /* VF device */ |
311 | u8 hdr_type; /* VF header type */ |
312 | u16 subsystem_vendor; /* VF subsystem vendor */ |
313 | u16 subsystem_device; /* VF subsystem device */ |
314 | resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */ |
315 | bool drivers_autoprobe; /* Auto probing of VFs by driver */ |
316 | }; |
317 | |
318 | #ifdef CONFIG_PCI_DOE |
319 | void pci_doe_init(struct pci_dev *pdev); |
320 | void pci_doe_destroy(struct pci_dev *pdev); |
321 | void pci_doe_disconnected(struct pci_dev *pdev); |
322 | #else |
323 | static inline void pci_doe_init(struct pci_dev *pdev) { } |
324 | static inline void pci_doe_destroy(struct pci_dev *pdev) { } |
325 | static inline void pci_doe_disconnected(struct pci_dev *pdev) { } |
326 | #endif |
327 | |
328 | /** |
329 | * pci_dev_set_io_state - Set the new error state if possible. |
330 | * |
331 | * @dev: PCI device to set new error_state |
332 | * @new: the state we want dev to be in |
333 | * |
334 | * If the device is experiencing perm_failure, it has to remain in that state. |
335 | * Any other transition is allowed. |
336 | * |
337 | * Returns true if state has been changed to the requested state. |
338 | */ |
339 | static inline bool pci_dev_set_io_state(struct pci_dev *dev, |
340 | pci_channel_state_t new) |
341 | { |
342 | pci_channel_state_t old; |
343 | |
344 | switch (new) { |
345 | case pci_channel_io_perm_failure: |
346 | xchg(&dev->error_state, pci_channel_io_perm_failure); |
347 | return true; |
348 | case pci_channel_io_frozen: |
349 | old = cmpxchg(&dev->error_state, pci_channel_io_normal, |
350 | pci_channel_io_frozen); |
351 | return old != pci_channel_io_perm_failure; |
352 | case pci_channel_io_normal: |
353 | old = cmpxchg(&dev->error_state, pci_channel_io_frozen, |
354 | pci_channel_io_normal); |
355 | return old != pci_channel_io_perm_failure; |
356 | default: |
357 | return false; |
358 | } |
359 | } |
360 | |
361 | static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused) |
362 | { |
363 | pci_dev_set_io_state(dev, new: pci_channel_io_perm_failure); |
364 | pci_doe_disconnected(pdev: dev); |
365 | |
366 | return 0; |
367 | } |
368 | |
369 | static inline bool pci_dev_is_disconnected(const struct pci_dev *dev) |
370 | { |
371 | return dev->error_state == pci_channel_io_perm_failure; |
372 | } |
373 | |
374 | /* pci_dev priv_flags */ |
375 | #define PCI_DEV_ADDED 0 |
376 | #define PCI_DPC_RECOVERED 1 |
377 | #define PCI_DPC_RECOVERING 2 |
378 | |
379 | static inline void pci_dev_assign_added(struct pci_dev *dev, bool added) |
380 | { |
381 | assign_bit(PCI_DEV_ADDED, addr: &dev->priv_flags, value: added); |
382 | } |
383 | |
384 | static inline bool pci_dev_is_added(const struct pci_dev *dev) |
385 | { |
386 | return test_bit(PCI_DEV_ADDED, &dev->priv_flags); |
387 | } |
388 | |
389 | #ifdef CONFIG_PCIEAER |
390 | #include <linux/aer.h> |
391 | |
392 | #define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */ |
393 | |
394 | struct aer_err_info { |
395 | struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES]; |
396 | int error_dev_num; |
397 | |
398 | unsigned int id:16; |
399 | |
400 | unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */ |
401 | unsigned int __pad1:5; |
402 | unsigned int multi_error_valid:1; |
403 | |
404 | unsigned int first_error:5; |
405 | unsigned int __pad2:2; |
406 | unsigned int :1; |
407 | |
408 | unsigned int status; /* COR/UNCOR Error Status */ |
409 | unsigned int mask; /* COR/UNCOR Error Mask */ |
410 | struct aer_header_log_regs tlp; /* TLP Header */ |
411 | }; |
412 | |
413 | int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info); |
414 | void aer_print_error(struct pci_dev *dev, struct aer_err_info *info); |
415 | #endif /* CONFIG_PCIEAER */ |
416 | |
417 | #ifdef CONFIG_PCIEPORTBUS |
418 | /* Cached RCEC Endpoint Association */ |
419 | struct rcec_ea { |
420 | u8 nextbusn; |
421 | u8 lastbusn; |
422 | u32 bitmap; |
423 | }; |
424 | #endif |
425 | |
426 | #ifdef CONFIG_PCIE_DPC |
427 | void pci_save_dpc_state(struct pci_dev *dev); |
428 | void pci_restore_dpc_state(struct pci_dev *dev); |
429 | void pci_dpc_init(struct pci_dev *pdev); |
430 | void dpc_process_error(struct pci_dev *pdev); |
431 | pci_ers_result_t dpc_reset_link(struct pci_dev *pdev); |
432 | bool pci_dpc_recovered(struct pci_dev *pdev); |
433 | #else |
434 | static inline void pci_save_dpc_state(struct pci_dev *dev) { } |
435 | static inline void pci_restore_dpc_state(struct pci_dev *dev) { } |
436 | static inline void pci_dpc_init(struct pci_dev *pdev) { } |
437 | static inline bool pci_dpc_recovered(struct pci_dev *pdev) { return false; } |
438 | #endif |
439 | |
440 | #ifdef CONFIG_PCIEPORTBUS |
441 | void pci_rcec_init(struct pci_dev *dev); |
442 | void pci_rcec_exit(struct pci_dev *dev); |
443 | void pcie_link_rcec(struct pci_dev *rcec); |
444 | void pcie_walk_rcec(struct pci_dev *rcec, |
445 | int (*cb)(struct pci_dev *, void *), |
446 | void *userdata); |
447 | #else |
448 | static inline void pci_rcec_init(struct pci_dev *dev) { } |
449 | static inline void pci_rcec_exit(struct pci_dev *dev) { } |
450 | static inline void pcie_link_rcec(struct pci_dev *rcec) { } |
451 | static inline void pcie_walk_rcec(struct pci_dev *rcec, |
452 | int (*cb)(struct pci_dev *, void *), |
453 | void *userdata) { } |
454 | #endif |
455 | |
456 | #ifdef CONFIG_PCI_ATS |
457 | /* Address Translation Service */ |
458 | void pci_ats_init(struct pci_dev *dev); |
459 | void pci_restore_ats_state(struct pci_dev *dev); |
460 | #else |
461 | static inline void pci_ats_init(struct pci_dev *d) { } |
462 | static inline void pci_restore_ats_state(struct pci_dev *dev) { } |
463 | #endif /* CONFIG_PCI_ATS */ |
464 | |
465 | #ifdef CONFIG_PCI_PRI |
466 | void pci_pri_init(struct pci_dev *dev); |
467 | void pci_restore_pri_state(struct pci_dev *pdev); |
468 | #else |
469 | static inline void pci_pri_init(struct pci_dev *dev) { } |
470 | static inline void pci_restore_pri_state(struct pci_dev *pdev) { } |
471 | #endif |
472 | |
473 | #ifdef CONFIG_PCI_PASID |
474 | void pci_pasid_init(struct pci_dev *dev); |
475 | void pci_restore_pasid_state(struct pci_dev *pdev); |
476 | #else |
477 | static inline void pci_pasid_init(struct pci_dev *dev) { } |
478 | static inline void pci_restore_pasid_state(struct pci_dev *pdev) { } |
479 | #endif |
480 | |
481 | #ifdef CONFIG_PCI_IOV |
482 | int pci_iov_init(struct pci_dev *dev); |
483 | void pci_iov_release(struct pci_dev *dev); |
484 | void pci_iov_remove(struct pci_dev *dev); |
485 | void pci_iov_update_resource(struct pci_dev *dev, int resno); |
486 | resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno); |
487 | void pci_restore_iov_state(struct pci_dev *dev); |
488 | int pci_iov_bus_range(struct pci_bus *bus); |
489 | extern const struct attribute_group sriov_pf_dev_attr_group; |
490 | extern const struct attribute_group sriov_vf_dev_attr_group; |
491 | #else |
492 | static inline int pci_iov_init(struct pci_dev *dev) |
493 | { |
494 | return -ENODEV; |
495 | } |
496 | static inline void pci_iov_release(struct pci_dev *dev) { } |
497 | static inline void pci_iov_remove(struct pci_dev *dev) { } |
498 | static inline void pci_restore_iov_state(struct pci_dev *dev) { } |
499 | static inline int pci_iov_bus_range(struct pci_bus *bus) |
500 | { |
501 | return 0; |
502 | } |
503 | |
504 | #endif /* CONFIG_PCI_IOV */ |
505 | |
506 | #ifdef CONFIG_PCIE_PTM |
507 | void pci_ptm_init(struct pci_dev *dev); |
508 | void pci_save_ptm_state(struct pci_dev *dev); |
509 | void pci_restore_ptm_state(struct pci_dev *dev); |
510 | void pci_suspend_ptm(struct pci_dev *dev); |
511 | void pci_resume_ptm(struct pci_dev *dev); |
512 | #else |
513 | static inline void pci_ptm_init(struct pci_dev *dev) { } |
514 | static inline void pci_save_ptm_state(struct pci_dev *dev) { } |
515 | static inline void pci_restore_ptm_state(struct pci_dev *dev) { } |
516 | static inline void pci_suspend_ptm(struct pci_dev *dev) { } |
517 | static inline void pci_resume_ptm(struct pci_dev *dev) { } |
518 | #endif |
519 | |
520 | unsigned long pci_cardbus_resource_alignment(struct resource *); |
521 | |
522 | static inline resource_size_t pci_resource_alignment(struct pci_dev *dev, |
523 | struct resource *res) |
524 | { |
525 | #ifdef CONFIG_PCI_IOV |
526 | int resno = res - dev->resource; |
527 | |
528 | if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END) |
529 | return pci_sriov_resource_alignment(dev, resno); |
530 | #endif |
531 | if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS) |
532 | return pci_cardbus_resource_alignment(res); |
533 | return resource_alignment(res); |
534 | } |
535 | |
536 | void pci_acs_init(struct pci_dev *dev); |
537 | #ifdef CONFIG_PCI_QUIRKS |
538 | int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); |
539 | int pci_dev_specific_enable_acs(struct pci_dev *dev); |
540 | int pci_dev_specific_disable_acs_redir(struct pci_dev *dev); |
541 | bool pcie_failed_link_retrain(struct pci_dev *dev); |
542 | #else |
543 | static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, |
544 | u16 acs_flags) |
545 | { |
546 | return -ENOTTY; |
547 | } |
548 | static inline int pci_dev_specific_enable_acs(struct pci_dev *dev) |
549 | { |
550 | return -ENOTTY; |
551 | } |
552 | static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev) |
553 | { |
554 | return -ENOTTY; |
555 | } |
556 | static inline bool pcie_failed_link_retrain(struct pci_dev *dev) |
557 | { |
558 | return false; |
559 | } |
560 | #endif |
561 | |
562 | /* PCI error reporting and recovery */ |
563 | pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, |
564 | pci_channel_state_t state, |
565 | pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev)); |
566 | |
567 | bool pcie_wait_for_link(struct pci_dev *pdev, bool active); |
568 | int pcie_retrain_link(struct pci_dev *pdev, bool use_lt); |
569 | #ifdef CONFIG_PCIEASPM |
570 | void pcie_aspm_init_link_state(struct pci_dev *pdev); |
571 | void pcie_aspm_exit_link_state(struct pci_dev *pdev); |
572 | void pcie_aspm_powersave_config_link(struct pci_dev *pdev); |
573 | #else |
574 | static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { } |
575 | static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { } |
576 | static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { } |
577 | #endif |
578 | |
579 | #ifdef CONFIG_PCIE_ECRC |
580 | void pcie_set_ecrc_checking(struct pci_dev *dev); |
581 | void pcie_ecrc_get_policy(char *str); |
582 | #else |
583 | static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } |
584 | static inline void pcie_ecrc_get_policy(char *str) { } |
585 | #endif |
586 | |
587 | struct pci_dev_reset_methods { |
588 | u16 vendor; |
589 | u16 device; |
590 | int (*reset)(struct pci_dev *dev, bool probe); |
591 | }; |
592 | |
593 | struct pci_reset_fn_method { |
594 | int (*reset_fn)(struct pci_dev *pdev, bool probe); |
595 | char *name; |
596 | }; |
597 | |
598 | #ifdef CONFIG_PCI_QUIRKS |
599 | int pci_dev_specific_reset(struct pci_dev *dev, bool probe); |
600 | #else |
601 | static inline int pci_dev_specific_reset(struct pci_dev *dev, bool probe) |
602 | { |
603 | return -ENOTTY; |
604 | } |
605 | #endif |
606 | |
607 | #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64) |
608 | int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment, |
609 | struct resource *res); |
610 | #else |
611 | static inline int acpi_get_rc_resources(struct device *dev, const char *hid, |
612 | u16 segment, struct resource *res) |
613 | { |
614 | return -ENODEV; |
615 | } |
616 | #endif |
617 | |
618 | int pci_rebar_get_current_size(struct pci_dev *pdev, int bar); |
619 | int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size); |
620 | static inline u64 pci_rebar_size_to_bytes(int size) |
621 | { |
622 | return 1ULL << (size + 20); |
623 | } |
624 | |
625 | struct device_node; |
626 | |
627 | #ifdef CONFIG_OF |
628 | int of_pci_parse_bus_range(struct device_node *node, struct resource *res); |
629 | int of_get_pci_domain_nr(struct device_node *node); |
630 | int of_pci_get_max_link_speed(struct device_node *node); |
631 | u32 of_pci_get_slot_power_limit(struct device_node *node, |
632 | u8 *slot_power_limit_value, |
633 | u8 *slot_power_limit_scale); |
634 | int pci_set_of_node(struct pci_dev *dev); |
635 | void pci_release_of_node(struct pci_dev *dev); |
636 | void pci_set_bus_of_node(struct pci_bus *bus); |
637 | void pci_release_bus_of_node(struct pci_bus *bus); |
638 | |
639 | int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge); |
640 | |
641 | #else |
642 | static inline int |
643 | of_pci_parse_bus_range(struct device_node *node, struct resource *res) |
644 | { |
645 | return -EINVAL; |
646 | } |
647 | |
648 | static inline int |
649 | of_get_pci_domain_nr(struct device_node *node) |
650 | { |
651 | return -1; |
652 | } |
653 | |
654 | static inline int |
655 | of_pci_get_max_link_speed(struct device_node *node) |
656 | { |
657 | return -EINVAL; |
658 | } |
659 | |
660 | static inline u32 |
661 | of_pci_get_slot_power_limit(struct device_node *node, |
662 | u8 *slot_power_limit_value, |
663 | u8 *slot_power_limit_scale) |
664 | { |
665 | if (slot_power_limit_value) |
666 | *slot_power_limit_value = 0; |
667 | if (slot_power_limit_scale) |
668 | *slot_power_limit_scale = 0; |
669 | return 0; |
670 | } |
671 | |
672 | static inline int pci_set_of_node(struct pci_dev *dev) { return 0; } |
673 | static inline void pci_release_of_node(struct pci_dev *dev) { } |
674 | static inline void pci_set_bus_of_node(struct pci_bus *bus) { } |
675 | static inline void pci_release_bus_of_node(struct pci_bus *bus) { } |
676 | |
677 | static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge) |
678 | { |
679 | return 0; |
680 | } |
681 | |
682 | #endif /* CONFIG_OF */ |
683 | |
684 | struct of_changeset; |
685 | |
686 | #ifdef CONFIG_PCI_DYNAMIC_OF_NODES |
687 | void of_pci_make_dev_node(struct pci_dev *pdev); |
688 | void of_pci_remove_node(struct pci_dev *pdev); |
689 | int of_pci_add_properties(struct pci_dev *pdev, struct of_changeset *ocs, |
690 | struct device_node *np); |
691 | #else |
692 | static inline void of_pci_make_dev_node(struct pci_dev *pdev) { } |
693 | static inline void of_pci_remove_node(struct pci_dev *pdev) { } |
694 | #endif |
695 | |
696 | #ifdef CONFIG_PCIEAER |
697 | void pci_no_aer(void); |
698 | void pci_aer_init(struct pci_dev *dev); |
699 | void pci_aer_exit(struct pci_dev *dev); |
700 | extern const struct attribute_group aer_stats_attr_group; |
701 | void pci_aer_clear_fatal_status(struct pci_dev *dev); |
702 | int pci_aer_clear_status(struct pci_dev *dev); |
703 | int pci_aer_raw_clear_status(struct pci_dev *dev); |
704 | void pci_save_aer_state(struct pci_dev *dev); |
705 | void pci_restore_aer_state(struct pci_dev *dev); |
706 | #else |
707 | static inline void pci_no_aer(void) { } |
708 | static inline void pci_aer_init(struct pci_dev *d) { } |
709 | static inline void pci_aer_exit(struct pci_dev *d) { } |
710 | static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { } |
711 | static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; } |
712 | static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; } |
713 | static inline void pci_save_aer_state(struct pci_dev *dev) { } |
714 | static inline void pci_restore_aer_state(struct pci_dev *dev) { } |
715 | #endif |
716 | |
717 | #ifdef CONFIG_ACPI |
718 | int pci_acpi_program_hp_params(struct pci_dev *dev); |
719 | extern const struct attribute_group pci_dev_acpi_attr_group; |
720 | void pci_set_acpi_fwnode(struct pci_dev *dev); |
721 | int pci_dev_acpi_reset(struct pci_dev *dev, bool probe); |
722 | bool acpi_pci_power_manageable(struct pci_dev *dev); |
723 | bool acpi_pci_bridge_d3(struct pci_dev *dev); |
724 | int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state); |
725 | pci_power_t acpi_pci_get_power_state(struct pci_dev *dev); |
726 | void acpi_pci_refresh_power_state(struct pci_dev *dev); |
727 | int acpi_pci_wakeup(struct pci_dev *dev, bool enable); |
728 | bool acpi_pci_need_resume(struct pci_dev *dev); |
729 | pci_power_t acpi_pci_choose_state(struct pci_dev *pdev); |
730 | #else |
731 | static inline int pci_dev_acpi_reset(struct pci_dev *dev, bool probe) |
732 | { |
733 | return -ENOTTY; |
734 | } |
735 | static inline void pci_set_acpi_fwnode(struct pci_dev *dev) { } |
736 | static inline int pci_acpi_program_hp_params(struct pci_dev *dev) |
737 | { |
738 | return -ENODEV; |
739 | } |
740 | static inline bool acpi_pci_power_manageable(struct pci_dev *dev) |
741 | { |
742 | return false; |
743 | } |
744 | static inline bool acpi_pci_bridge_d3(struct pci_dev *dev) |
745 | { |
746 | return false; |
747 | } |
748 | static inline int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state) |
749 | { |
750 | return -ENODEV; |
751 | } |
752 | static inline pci_power_t acpi_pci_get_power_state(struct pci_dev *dev) |
753 | { |
754 | return PCI_UNKNOWN; |
755 | } |
756 | static inline void acpi_pci_refresh_power_state(struct pci_dev *dev) { } |
757 | static inline int acpi_pci_wakeup(struct pci_dev *dev, bool enable) |
758 | { |
759 | return -ENODEV; |
760 | } |
761 | static inline bool acpi_pci_need_resume(struct pci_dev *dev) |
762 | { |
763 | return false; |
764 | } |
765 | static inline pci_power_t acpi_pci_choose_state(struct pci_dev *pdev) |
766 | { |
767 | return PCI_POWER_ERROR; |
768 | } |
769 | #endif |
770 | |
771 | #ifdef CONFIG_PCIEASPM |
772 | extern const struct attribute_group aspm_ctrl_attr_group; |
773 | #endif |
774 | |
775 | extern const struct attribute_group pci_dev_reset_method_attr_group; |
776 | |
777 | #ifdef CONFIG_X86_INTEL_MID |
778 | bool pci_use_mid_pm(void); |
779 | int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state); |
780 | pci_power_t mid_pci_get_power_state(struct pci_dev *pdev); |
781 | #else |
782 | static inline bool pci_use_mid_pm(void) |
783 | { |
784 | return false; |
785 | } |
786 | static inline int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state) |
787 | { |
788 | return -ENODEV; |
789 | } |
790 | static inline pci_power_t mid_pci_get_power_state(struct pci_dev *pdev) |
791 | { |
792 | return PCI_UNKNOWN; |
793 | } |
794 | #endif |
795 | |
796 | /* |
797 | * Config Address for PCI Configuration Mechanism #1 |
798 | * |
799 | * See PCI Local Bus Specification, Revision 3.0, |
800 | * Section 3.2.2.3.2, Figure 3-2, p. 50. |
801 | */ |
802 | |
803 | #define PCI_CONF1_BUS_SHIFT 16 /* Bus number */ |
804 | #define PCI_CONF1_DEV_SHIFT 11 /* Device number */ |
805 | #define PCI_CONF1_FUNC_SHIFT 8 /* Function number */ |
806 | |
807 | #define PCI_CONF1_BUS_MASK 0xff |
808 | #define PCI_CONF1_DEV_MASK 0x1f |
809 | #define PCI_CONF1_FUNC_MASK 0x7 |
810 | #define PCI_CONF1_REG_MASK 0xfc /* Limit aligned offset to a maximum of 256B */ |
811 | |
812 | #define PCI_CONF1_ENABLE BIT(31) |
813 | #define PCI_CONF1_BUS(x) (((x) & PCI_CONF1_BUS_MASK) << PCI_CONF1_BUS_SHIFT) |
814 | #define PCI_CONF1_DEV(x) (((x) & PCI_CONF1_DEV_MASK) << PCI_CONF1_DEV_SHIFT) |
815 | #define PCI_CONF1_FUNC(x) (((x) & PCI_CONF1_FUNC_MASK) << PCI_CONF1_FUNC_SHIFT) |
816 | #define PCI_CONF1_REG(x) ((x) & PCI_CONF1_REG_MASK) |
817 | |
818 | #define PCI_CONF1_ADDRESS(bus, dev, func, reg) \ |
819 | (PCI_CONF1_ENABLE | \ |
820 | PCI_CONF1_BUS(bus) | \ |
821 | PCI_CONF1_DEV(dev) | \ |
822 | PCI_CONF1_FUNC(func) | \ |
823 | PCI_CONF1_REG(reg)) |
824 | |
825 | /* |
826 | * Extension of PCI Config Address for accessing extended PCIe registers |
827 | * |
828 | * No standardized specification, but used on lot of non-ECAM-compliant ARM SoCs |
829 | * or on AMD Barcelona and new CPUs. Reserved bits [27:24] of PCI Config Address |
830 | * are used for specifying additional 4 high bits of PCI Express register. |
831 | */ |
832 | |
833 | #define PCI_CONF1_EXT_REG_SHIFT 16 |
834 | #define PCI_CONF1_EXT_REG_MASK 0xf00 |
835 | #define PCI_CONF1_EXT_REG(x) (((x) & PCI_CONF1_EXT_REG_MASK) << PCI_CONF1_EXT_REG_SHIFT) |
836 | |
837 | #define PCI_CONF1_EXT_ADDRESS(bus, dev, func, reg) \ |
838 | (PCI_CONF1_ADDRESS(bus, dev, func, reg) | \ |
839 | PCI_CONF1_EXT_REG(reg)) |
840 | |
841 | #endif /* DRIVERS_PCI_H */ |
842 | |