1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * AXP20x pinctrl and GPIO driver
4 *
5 * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
6 * Copyright (C) 2017 Quentin Schulz <quentin.schulz@free-electrons.com>
7 */
8
9#include <linux/bitops.h>
10#include <linux/device.h>
11#include <linux/gpio/driver.h>
12#include <linux/init.h>
13#include <linux/interrupt.h>
14#include <linux/kernel.h>
15#include <linux/mfd/axp20x.h>
16#include <linux/module.h>
17#include <linux/of.h>
18#include <linux/platform_device.h>
19#include <linux/regmap.h>
20#include <linux/slab.h>
21
22#include <linux/pinctrl/consumer.h>
23#include <linux/pinctrl/pinconf-generic.h>
24#include <linux/pinctrl/pinctrl.h>
25#include <linux/pinctrl/pinmux.h>
26
27#define AXP20X_GPIO_FUNCTIONS 0x7
28#define AXP20X_GPIO_FUNCTION_OUT_LOW 0
29#define AXP20X_GPIO_FUNCTION_OUT_HIGH 1
30#define AXP20X_GPIO_FUNCTION_INPUT 2
31
32#define AXP20X_GPIO3_FUNCTIONS GENMASK(2, 1)
33#define AXP20X_GPIO3_FUNCTION_OUT_LOW 0
34#define AXP20X_GPIO3_FUNCTION_OUT_HIGH 2
35#define AXP20X_GPIO3_FUNCTION_INPUT 4
36
37#define AXP20X_FUNC_GPIO_OUT 0
38#define AXP20X_FUNC_GPIO_IN 1
39#define AXP20X_FUNC_LDO 2
40#define AXP20X_FUNC_ADC 3
41#define AXP20X_FUNCS_NB 4
42
43#define AXP20X_MUX_GPIO_OUT 0
44#define AXP20X_MUX_GPIO_IN BIT(1)
45#define AXP20X_MUX_ADC BIT(2)
46
47#define AXP813_MUX_ADC (BIT(2) | BIT(0))
48
49struct axp20x_pctrl_desc {
50 const struct pinctrl_pin_desc *pins;
51 unsigned int npins;
52 /* Stores the pins supporting LDO function. Bit offset is pin number. */
53 u8 ldo_mask;
54 /* Stores the pins supporting ADC function. Bit offset is pin number. */
55 u8 adc_mask;
56 u8 gpio_status_offset;
57 u8 adc_mux;
58};
59
60struct axp20x_pinctrl_function {
61 const char *name;
62 unsigned int muxval;
63 const char **groups;
64 unsigned int ngroups;
65};
66
67struct axp20x_pctl {
68 struct gpio_chip chip;
69 struct regmap *regmap;
70 struct pinctrl_dev *pctl_dev;
71 struct device *dev;
72 const struct axp20x_pctrl_desc *desc;
73 struct axp20x_pinctrl_function funcs[AXP20X_FUNCS_NB];
74};
75
76static const struct pinctrl_pin_desc axp209_pins[] = {
77 PINCTRL_PIN(0, "GPIO0"),
78 PINCTRL_PIN(1, "GPIO1"),
79 PINCTRL_PIN(2, "GPIO2"),
80 PINCTRL_PIN(3, "GPIO3"),
81};
82
83static const struct pinctrl_pin_desc axp22x_pins[] = {
84 PINCTRL_PIN(0, "GPIO0"),
85 PINCTRL_PIN(1, "GPIO1"),
86};
87
88static const struct axp20x_pctrl_desc axp20x_data = {
89 .pins = axp209_pins,
90 .npins = ARRAY_SIZE(axp209_pins),
91 .ldo_mask = BIT(0) | BIT(1),
92 .adc_mask = BIT(0) | BIT(1),
93 .gpio_status_offset = 4,
94 .adc_mux = AXP20X_MUX_ADC,
95};
96
97static const struct axp20x_pctrl_desc axp22x_data = {
98 .pins = axp22x_pins,
99 .npins = ARRAY_SIZE(axp22x_pins),
100 .ldo_mask = BIT(0) | BIT(1),
101 .gpio_status_offset = 0,
102};
103
104static const struct axp20x_pctrl_desc axp813_data = {
105 .pins = axp22x_pins,
106 .npins = ARRAY_SIZE(axp22x_pins),
107 .ldo_mask = BIT(0) | BIT(1),
108 .adc_mask = BIT(0),
109 .gpio_status_offset = 0,
110 .adc_mux = AXP813_MUX_ADC,
111};
112
113static int axp20x_gpio_get_reg(unsigned int offset)
114{
115 switch (offset) {
116 case 0:
117 return AXP20X_GPIO0_CTRL;
118 case 1:
119 return AXP20X_GPIO1_CTRL;
120 case 2:
121 return AXP20X_GPIO2_CTRL;
122 }
123
124 return -EINVAL;
125}
126
127static int axp20x_gpio_get(struct gpio_chip *chip, unsigned int offset)
128{
129 struct axp20x_pctl *pctl = gpiochip_get_data(gc: chip);
130 unsigned int val;
131 int ret;
132
133 /* AXP209 has GPIO3 status sharing the settings register */
134 if (offset == 3) {
135 ret = regmap_read(map: pctl->regmap, AXP20X_GPIO3_CTRL, val: &val);
136 if (ret)
137 return ret;
138 return !!(val & BIT(0));
139 }
140
141 ret = regmap_read(map: pctl->regmap, AXP20X_GPIO20_SS, val: &val);
142 if (ret)
143 return ret;
144
145 return !!(val & BIT(offset + pctl->desc->gpio_status_offset));
146}
147
148static int axp20x_gpio_get_direction(struct gpio_chip *chip,
149 unsigned int offset)
150{
151 struct axp20x_pctl *pctl = gpiochip_get_data(gc: chip);
152 unsigned int val;
153 int reg, ret;
154
155 /* AXP209 GPIO3 settings have a different layout */
156 if (offset == 3) {
157 ret = regmap_read(map: pctl->regmap, AXP20X_GPIO3_CTRL, val: &val);
158 if (ret)
159 return ret;
160 if (val & AXP20X_GPIO3_FUNCTION_INPUT)
161 return GPIO_LINE_DIRECTION_IN;
162
163 return GPIO_LINE_DIRECTION_OUT;
164 }
165
166 reg = axp20x_gpio_get_reg(offset);
167 if (reg < 0)
168 return reg;
169
170 ret = regmap_read(map: pctl->regmap, reg, val: &val);
171 if (ret)
172 return ret;
173
174 /*
175 * This shouldn't really happen if the pin is in use already,
176 * or if it's not in use yet, it doesn't matter since we're
177 * going to change the value soon anyway. Default to output.
178 */
179 if ((val & AXP20X_GPIO_FUNCTIONS) > 2)
180 return GPIO_LINE_DIRECTION_OUT;
181
182 /*
183 * The GPIO directions are the three lowest values.
184 * 2 is input, 0 and 1 are output
185 */
186 if (val & 2)
187 return GPIO_LINE_DIRECTION_IN;
188
189 return GPIO_LINE_DIRECTION_OUT;
190}
191
192static int axp20x_gpio_output(struct gpio_chip *chip, unsigned int offset,
193 int value)
194{
195 chip->set(chip, offset, value);
196
197 return 0;
198}
199
200static void axp20x_gpio_set(struct gpio_chip *chip, unsigned int offset,
201 int value)
202{
203 struct axp20x_pctl *pctl = gpiochip_get_data(gc: chip);
204 int reg;
205
206 /* AXP209 has GPIO3 status sharing the settings register */
207 if (offset == 3) {
208 regmap_update_bits(map: pctl->regmap, AXP20X_GPIO3_CTRL,
209 AXP20X_GPIO3_FUNCTIONS,
210 val: value ? AXP20X_GPIO3_FUNCTION_OUT_HIGH :
211 AXP20X_GPIO3_FUNCTION_OUT_LOW);
212 return;
213 }
214
215 reg = axp20x_gpio_get_reg(offset);
216 if (reg < 0)
217 return;
218
219 regmap_update_bits(map: pctl->regmap, reg,
220 AXP20X_GPIO_FUNCTIONS,
221 val: value ? AXP20X_GPIO_FUNCTION_OUT_HIGH :
222 AXP20X_GPIO_FUNCTION_OUT_LOW);
223}
224
225static int axp20x_pmx_set(struct pinctrl_dev *pctldev, unsigned int offset,
226 u8 config)
227{
228 struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
229 int reg;
230
231 /* AXP209 GPIO3 settings have a different layout */
232 if (offset == 3) {
233 return regmap_update_bits(map: pctl->regmap, AXP20X_GPIO3_CTRL,
234 AXP20X_GPIO3_FUNCTIONS,
235 val: config == AXP20X_MUX_GPIO_OUT ? AXP20X_GPIO3_FUNCTION_OUT_LOW :
236 AXP20X_GPIO3_FUNCTION_INPUT);
237 }
238
239 reg = axp20x_gpio_get_reg(offset);
240 if (reg < 0)
241 return reg;
242
243 return regmap_update_bits(map: pctl->regmap, reg, AXP20X_GPIO_FUNCTIONS,
244 val: config);
245}
246
247static int axp20x_pmx_func_cnt(struct pinctrl_dev *pctldev)
248{
249 struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
250
251 return ARRAY_SIZE(pctl->funcs);
252}
253
254static const char *axp20x_pmx_func_name(struct pinctrl_dev *pctldev,
255 unsigned int selector)
256{
257 struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
258
259 return pctl->funcs[selector].name;
260}
261
262static int axp20x_pmx_func_groups(struct pinctrl_dev *pctldev,
263 unsigned int selector,
264 const char * const **groups,
265 unsigned int *num_groups)
266{
267 struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
268
269 *groups = pctl->funcs[selector].groups;
270 *num_groups = pctl->funcs[selector].ngroups;
271
272 return 0;
273}
274
275static int axp20x_pmx_set_mux(struct pinctrl_dev *pctldev,
276 unsigned int function, unsigned int group)
277{
278 struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
279 unsigned int mask;
280
281 /* Every pin supports GPIO_OUT and GPIO_IN functions */
282 if (function <= AXP20X_FUNC_GPIO_IN)
283 return axp20x_pmx_set(pctldev, offset: group,
284 config: pctl->funcs[function].muxval);
285
286 if (function == AXP20X_FUNC_LDO)
287 mask = pctl->desc->ldo_mask;
288 else
289 mask = pctl->desc->adc_mask;
290
291 if (!(BIT(group) & mask))
292 return -EINVAL;
293
294 /*
295 * We let the regulator framework handle the LDO muxing as muxing bits
296 * are basically also regulators on/off bits. It's better not to enforce
297 * any state of the regulator when selecting LDO mux so that we don't
298 * interfere with the regulator driver.
299 */
300 if (function == AXP20X_FUNC_LDO)
301 return 0;
302
303 return axp20x_pmx_set(pctldev, offset: group, config: pctl->funcs[function].muxval);
304}
305
306static int axp20x_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
307 struct pinctrl_gpio_range *range,
308 unsigned int offset, bool input)
309{
310 struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
311
312 if (input)
313 return axp20x_pmx_set(pctldev, offset,
314 config: pctl->funcs[AXP20X_FUNC_GPIO_IN].muxval);
315
316 return axp20x_pmx_set(pctldev, offset,
317 config: pctl->funcs[AXP20X_FUNC_GPIO_OUT].muxval);
318}
319
320static const struct pinmux_ops axp20x_pmx_ops = {
321 .get_functions_count = axp20x_pmx_func_cnt,
322 .get_function_name = axp20x_pmx_func_name,
323 .get_function_groups = axp20x_pmx_func_groups,
324 .set_mux = axp20x_pmx_set_mux,
325 .gpio_set_direction = axp20x_pmx_gpio_set_direction,
326 .strict = true,
327};
328
329static int axp20x_groups_cnt(struct pinctrl_dev *pctldev)
330{
331 struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
332
333 return pctl->desc->npins;
334}
335
336static int axp20x_group_pins(struct pinctrl_dev *pctldev, unsigned int selector,
337 const unsigned int **pins, unsigned int *num_pins)
338{
339 struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
340
341 *pins = (unsigned int *)&pctl->desc->pins[selector];
342 *num_pins = 1;
343
344 return 0;
345}
346
347static const char *axp20x_group_name(struct pinctrl_dev *pctldev,
348 unsigned int selector)
349{
350 struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
351
352 return pctl->desc->pins[selector].name;
353}
354
355static const struct pinctrl_ops axp20x_pctrl_ops = {
356 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
357 .dt_free_map = pinconf_generic_dt_free_map,
358 .get_groups_count = axp20x_groups_cnt,
359 .get_group_name = axp20x_group_name,
360 .get_group_pins = axp20x_group_pins,
361};
362
363static int axp20x_funcs_groups_from_mask(struct device *dev, unsigned int mask,
364 unsigned int mask_len,
365 struct axp20x_pinctrl_function *func,
366 const struct pinctrl_pin_desc *pins)
367{
368 unsigned long int mask_cpy = mask;
369 const char **group;
370 unsigned int ngroups = hweight8(mask);
371 int bit;
372
373 func->ngroups = ngroups;
374 if (func->ngroups > 0) {
375 func->groups = devm_kcalloc(dev,
376 n: ngroups, size: sizeof(const char *),
377 GFP_KERNEL);
378 if (!func->groups)
379 return -ENOMEM;
380 group = func->groups;
381 for_each_set_bit(bit, &mask_cpy, mask_len) {
382 *group = pins[bit].name;
383 group++;
384 }
385 }
386
387 return 0;
388}
389
390static int axp20x_build_funcs_groups(struct platform_device *pdev)
391{
392 struct axp20x_pctl *pctl = platform_get_drvdata(pdev);
393 int i, ret, pin, npins = pctl->desc->npins;
394
395 pctl->funcs[AXP20X_FUNC_GPIO_OUT].name = "gpio_out";
396 pctl->funcs[AXP20X_FUNC_GPIO_OUT].muxval = AXP20X_MUX_GPIO_OUT;
397 pctl->funcs[AXP20X_FUNC_GPIO_IN].name = "gpio_in";
398 pctl->funcs[AXP20X_FUNC_GPIO_IN].muxval = AXP20X_MUX_GPIO_IN;
399 pctl->funcs[AXP20X_FUNC_LDO].name = "ldo";
400 /*
401 * Muxval for LDO is useless as we won't use it.
402 * See comment in axp20x_pmx_set_mux.
403 */
404 pctl->funcs[AXP20X_FUNC_ADC].name = "adc";
405 pctl->funcs[AXP20X_FUNC_ADC].muxval = pctl->desc->adc_mux;
406
407 /* Every pin supports GPIO_OUT and GPIO_IN functions */
408 for (i = 0; i <= AXP20X_FUNC_GPIO_IN; i++) {
409 pctl->funcs[i].ngroups = npins;
410 pctl->funcs[i].groups = devm_kcalloc(dev: &pdev->dev,
411 n: npins, size: sizeof(char *),
412 GFP_KERNEL);
413 if (!pctl->funcs[i].groups)
414 return -ENOMEM;
415 for (pin = 0; pin < npins; pin++)
416 pctl->funcs[i].groups[pin] = pctl->desc->pins[pin].name;
417 }
418
419 ret = axp20x_funcs_groups_from_mask(dev: &pdev->dev, mask: pctl->desc->ldo_mask,
420 mask_len: npins, func: &pctl->funcs[AXP20X_FUNC_LDO],
421 pins: pctl->desc->pins);
422 if (ret)
423 return ret;
424
425 ret = axp20x_funcs_groups_from_mask(dev: &pdev->dev, mask: pctl->desc->adc_mask,
426 mask_len: npins, func: &pctl->funcs[AXP20X_FUNC_ADC],
427 pins: pctl->desc->pins);
428 if (ret)
429 return ret;
430
431 return 0;
432}
433
434static const struct of_device_id axp20x_pctl_match[] = {
435 { .compatible = "x-powers,axp209-gpio", .data = &axp20x_data, },
436 { .compatible = "x-powers,axp221-gpio", .data = &axp22x_data, },
437 { .compatible = "x-powers,axp813-gpio", .data = &axp813_data, },
438 { }
439};
440MODULE_DEVICE_TABLE(of, axp20x_pctl_match);
441
442static int axp20x_pctl_probe(struct platform_device *pdev)
443{
444 struct axp20x_dev *axp20x = dev_get_drvdata(dev: pdev->dev.parent);
445 struct axp20x_pctl *pctl;
446 struct device *dev = &pdev->dev;
447 struct pinctrl_desc *pctrl_desc;
448 int ret;
449
450 if (!of_device_is_available(device: pdev->dev.of_node))
451 return -ENODEV;
452
453 if (!axp20x) {
454 dev_err(&pdev->dev, "Parent drvdata not set\n");
455 return -EINVAL;
456 }
457
458 pctl = devm_kzalloc(dev: &pdev->dev, size: sizeof(*pctl), GFP_KERNEL);
459 if (!pctl)
460 return -ENOMEM;
461
462 pctl->chip.base = -1;
463 pctl->chip.can_sleep = true;
464 pctl->chip.request = gpiochip_generic_request;
465 pctl->chip.free = gpiochip_generic_free;
466 pctl->chip.parent = &pdev->dev;
467 pctl->chip.label = dev_name(dev: &pdev->dev);
468 pctl->chip.owner = THIS_MODULE;
469 pctl->chip.get = axp20x_gpio_get;
470 pctl->chip.get_direction = axp20x_gpio_get_direction;
471 pctl->chip.set = axp20x_gpio_set;
472 pctl->chip.direction_input = pinctrl_gpio_direction_input;
473 pctl->chip.direction_output = axp20x_gpio_output;
474
475 pctl->desc = of_device_get_match_data(dev);
476
477 pctl->chip.ngpio = pctl->desc->npins;
478
479 pctl->regmap = axp20x->regmap;
480 pctl->dev = &pdev->dev;
481
482 platform_set_drvdata(pdev, data: pctl);
483
484 ret = axp20x_build_funcs_groups(pdev);
485 if (ret) {
486 dev_err(&pdev->dev, "failed to build groups\n");
487 return ret;
488 }
489
490 pctrl_desc = devm_kzalloc(dev: &pdev->dev, size: sizeof(*pctrl_desc), GFP_KERNEL);
491 if (!pctrl_desc)
492 return -ENOMEM;
493
494 pctrl_desc->name = dev_name(dev: &pdev->dev);
495 pctrl_desc->owner = THIS_MODULE;
496 pctrl_desc->pins = pctl->desc->pins;
497 pctrl_desc->npins = pctl->desc->npins;
498 pctrl_desc->pctlops = &axp20x_pctrl_ops;
499 pctrl_desc->pmxops = &axp20x_pmx_ops;
500
501 pctl->pctl_dev = devm_pinctrl_register(dev: &pdev->dev, pctldesc: pctrl_desc, driver_data: pctl);
502 if (IS_ERR(ptr: pctl->pctl_dev)) {
503 dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
504 return PTR_ERR(ptr: pctl->pctl_dev);
505 }
506
507 ret = devm_gpiochip_add_data(&pdev->dev, &pctl->chip, pctl);
508 if (ret) {
509 dev_err(&pdev->dev, "Failed to register GPIO chip\n");
510 return ret;
511 }
512
513 ret = gpiochip_add_pin_range(gc: &pctl->chip, pinctl_name: dev_name(dev: &pdev->dev),
514 gpio_offset: pctl->desc->pins->number,
515 pin_offset: pctl->desc->pins->number,
516 npins: pctl->desc->npins);
517 if (ret) {
518 dev_err(&pdev->dev, "failed to add pin range\n");
519 return ret;
520 }
521
522 dev_info(&pdev->dev, "AXP209 pinctrl and GPIO driver loaded\n");
523
524 return 0;
525}
526
527static struct platform_driver axp20x_pctl_driver = {
528 .probe = axp20x_pctl_probe,
529 .driver = {
530 .name = "axp20x-gpio",
531 .of_match_table = axp20x_pctl_match,
532 },
533};
534
535module_platform_driver(axp20x_pctl_driver);
536
537MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
538MODULE_AUTHOR("Quentin Schulz <quentin.schulz@free-electrons.com>");
539MODULE_DESCRIPTION("AXP20x PMIC pinctrl and GPIO driver");
540MODULE_LICENSE("GPL");
541

source code of linux/drivers/pinctrl/pinctrl-axp209.c