1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Pistachio SoC pinctrl driver |
4 | * |
5 | * Copyright (C) 2014 Imagination Technologies Ltd. |
6 | * Copyright (C) 2014 Google, Inc. |
7 | */ |
8 | |
9 | #include <linux/gpio/driver.h> |
10 | #include <linux/interrupt.h> |
11 | #include <linux/io.h> |
12 | #include <linux/irq.h> |
13 | #include <linux/mod_devicetable.h> |
14 | #include <linux/pinctrl/pinconf.h> |
15 | #include <linux/pinctrl/pinconf-generic.h> |
16 | #include <linux/pinctrl/pinctrl.h> |
17 | #include <linux/pinctrl/pinmux.h> |
18 | #include <linux/platform_device.h> |
19 | #include <linux/property.h> |
20 | #include <linux/seq_file.h> |
21 | #include <linux/slab.h> |
22 | #include <linux/spinlock.h> |
23 | |
24 | #include "pinctrl-utils.h" |
25 | |
26 | #define PADS_SCHMITT_EN0 0x000 |
27 | #define PADS_SCHMITT_EN_REG(pin) (PADS_SCHMITT_EN0 + 0x4 * ((pin) / 32)) |
28 | #define PADS_SCHMITT_EN_BIT(pin) BIT((pin) % 32) |
29 | |
30 | #define PADS_PU_PD0 0x040 |
31 | #define PADS_PU_PD_REG(pin) (PADS_PU_PD0 + 0x4 * ((pin) / 16)) |
32 | #define PADS_PU_PD_SHIFT(pin) (2 * ((pin) % 16)) |
33 | #define PADS_PU_PD_MASK 0x3 |
34 | #define PADS_PU_PD_HIGHZ 0x0 |
35 | #define PADS_PU_PD_UP 0x1 |
36 | #define PADS_PU_PD_DOWN 0x2 |
37 | #define PADS_PU_PD_BUS 0x3 |
38 | |
39 | #define PADS_FUNCTION_SELECT0 0x0c0 |
40 | #define PADS_FUNCTION_SELECT1 0x0c4 |
41 | #define PADS_FUNCTION_SELECT2 0x0c8 |
42 | #define PADS_SCENARIO_SELECT 0x0f8 |
43 | |
44 | #define PADS_SLEW_RATE0 0x100 |
45 | #define PADS_SLEW_RATE_REG(pin) (PADS_SLEW_RATE0 + 0x4 * ((pin) / 32)) |
46 | #define PADS_SLEW_RATE_BIT(pin) BIT((pin) % 32) |
47 | |
48 | #define PADS_DRIVE_STRENGTH0 0x120 |
49 | #define PADS_DRIVE_STRENGTH_REG(pin) \ |
50 | (PADS_DRIVE_STRENGTH0 + 0x4 * ((pin) / 16)) |
51 | #define PADS_DRIVE_STRENGTH_SHIFT(pin) (2 * ((pin) % 16)) |
52 | #define PADS_DRIVE_STRENGTH_MASK 0x3 |
53 | #define PADS_DRIVE_STRENGTH_2MA 0x0 |
54 | #define PADS_DRIVE_STRENGTH_4MA 0x1 |
55 | #define PADS_DRIVE_STRENGTH_8MA 0x2 |
56 | #define PADS_DRIVE_STRENGTH_12MA 0x3 |
57 | |
58 | #define GPIO_BANK_BASE(bank) (0x200 + 0x24 * (bank)) |
59 | |
60 | #define GPIO_BIT_EN 0x00 |
61 | #define GPIO_OUTPUT_EN 0x04 |
62 | #define GPIO_OUTPUT 0x08 |
63 | #define GPIO_INPUT 0x0c |
64 | #define GPIO_INPUT_POLARITY 0x10 |
65 | #define GPIO_INTERRUPT_TYPE 0x14 |
66 | #define GPIO_INTERRUPT_TYPE_LEVEL 0x0 |
67 | #define GPIO_INTERRUPT_TYPE_EDGE 0x1 |
68 | #define GPIO_INTERRUPT_EDGE 0x18 |
69 | #define GPIO_INTERRUPT_EDGE_SINGLE 0x0 |
70 | #define GPIO_INTERRUPT_EDGE_DUAL 0x1 |
71 | #define GPIO_INTERRUPT_EN 0x1c |
72 | #define GPIO_INTERRUPT_STATUS 0x20 |
73 | |
74 | struct pistachio_function { |
75 | const char *name; |
76 | const char * const *groups; |
77 | unsigned int ngroups; |
78 | const int *scenarios; |
79 | unsigned int nscenarios; |
80 | unsigned int scenario_reg; |
81 | unsigned int scenario_shift; |
82 | unsigned int scenario_mask; |
83 | }; |
84 | |
85 | struct pistachio_pin_group { |
86 | const char *name; |
87 | unsigned int pin; |
88 | int mux_option[3]; |
89 | int mux_reg; |
90 | int mux_shift; |
91 | int mux_mask; |
92 | }; |
93 | |
94 | struct pistachio_gpio_bank { |
95 | struct pistachio_pinctrl *pctl; |
96 | void __iomem *base; |
97 | int instance; |
98 | unsigned int pin_base; |
99 | unsigned int npins; |
100 | struct gpio_chip gpio_chip; |
101 | }; |
102 | |
103 | struct pistachio_pinctrl { |
104 | struct device *dev; |
105 | void __iomem *base; |
106 | struct pinctrl_dev *pctldev; |
107 | const struct pinctrl_pin_desc *pins; |
108 | unsigned int npins; |
109 | const struct pistachio_function *functions; |
110 | unsigned int nfunctions; |
111 | const struct pistachio_pin_group *groups; |
112 | unsigned int ngroups; |
113 | struct pistachio_gpio_bank *gpio_banks; |
114 | unsigned int nbanks; |
115 | }; |
116 | |
117 | #define PISTACHIO_PIN_MFIO(p) (p) |
118 | #define PISTACHIO_PIN_TCK 90 |
119 | #define PISTACHIO_PIN_TRSTN 91 |
120 | #define PISTACHIO_PIN_TDI 92 |
121 | #define PISTACHIO_PIN_TMS 93 |
122 | #define PISTACHIO_PIN_TDO 94 |
123 | #define PISTACHIO_PIN_JTAG_COMPLY 95 |
124 | #define PISTACHIO_PIN_SAFE_MODE 96 |
125 | #define PISTACHIO_PIN_POR_DISABLE 97 |
126 | #define PISTACHIO_PIN_RESETN 98 |
127 | |
128 | #define MFIO_PIN_DESC(p) PINCTRL_PIN(PISTACHIO_PIN_MFIO(p), "mfio" #p) |
129 | |
130 | static const struct pinctrl_pin_desc pistachio_pins[] = { |
131 | MFIO_PIN_DESC(0), |
132 | MFIO_PIN_DESC(1), |
133 | MFIO_PIN_DESC(2), |
134 | MFIO_PIN_DESC(3), |
135 | MFIO_PIN_DESC(4), |
136 | MFIO_PIN_DESC(5), |
137 | MFIO_PIN_DESC(6), |
138 | MFIO_PIN_DESC(7), |
139 | MFIO_PIN_DESC(8), |
140 | MFIO_PIN_DESC(9), |
141 | MFIO_PIN_DESC(10), |
142 | MFIO_PIN_DESC(11), |
143 | MFIO_PIN_DESC(12), |
144 | MFIO_PIN_DESC(13), |
145 | MFIO_PIN_DESC(14), |
146 | MFIO_PIN_DESC(15), |
147 | MFIO_PIN_DESC(16), |
148 | MFIO_PIN_DESC(17), |
149 | MFIO_PIN_DESC(18), |
150 | MFIO_PIN_DESC(19), |
151 | MFIO_PIN_DESC(20), |
152 | MFIO_PIN_DESC(21), |
153 | MFIO_PIN_DESC(22), |
154 | MFIO_PIN_DESC(23), |
155 | MFIO_PIN_DESC(24), |
156 | MFIO_PIN_DESC(25), |
157 | MFIO_PIN_DESC(26), |
158 | MFIO_PIN_DESC(27), |
159 | MFIO_PIN_DESC(28), |
160 | MFIO_PIN_DESC(29), |
161 | MFIO_PIN_DESC(30), |
162 | MFIO_PIN_DESC(31), |
163 | MFIO_PIN_DESC(32), |
164 | MFIO_PIN_DESC(33), |
165 | MFIO_PIN_DESC(34), |
166 | MFIO_PIN_DESC(35), |
167 | MFIO_PIN_DESC(36), |
168 | MFIO_PIN_DESC(37), |
169 | MFIO_PIN_DESC(38), |
170 | MFIO_PIN_DESC(39), |
171 | MFIO_PIN_DESC(40), |
172 | MFIO_PIN_DESC(41), |
173 | MFIO_PIN_DESC(42), |
174 | MFIO_PIN_DESC(43), |
175 | MFIO_PIN_DESC(44), |
176 | MFIO_PIN_DESC(45), |
177 | MFIO_PIN_DESC(46), |
178 | MFIO_PIN_DESC(47), |
179 | MFIO_PIN_DESC(48), |
180 | MFIO_PIN_DESC(49), |
181 | MFIO_PIN_DESC(50), |
182 | MFIO_PIN_DESC(51), |
183 | MFIO_PIN_DESC(52), |
184 | MFIO_PIN_DESC(53), |
185 | MFIO_PIN_DESC(54), |
186 | MFIO_PIN_DESC(55), |
187 | MFIO_PIN_DESC(56), |
188 | MFIO_PIN_DESC(57), |
189 | MFIO_PIN_DESC(58), |
190 | MFIO_PIN_DESC(59), |
191 | MFIO_PIN_DESC(60), |
192 | MFIO_PIN_DESC(61), |
193 | MFIO_PIN_DESC(62), |
194 | MFIO_PIN_DESC(63), |
195 | MFIO_PIN_DESC(64), |
196 | MFIO_PIN_DESC(65), |
197 | MFIO_PIN_DESC(66), |
198 | MFIO_PIN_DESC(67), |
199 | MFIO_PIN_DESC(68), |
200 | MFIO_PIN_DESC(69), |
201 | MFIO_PIN_DESC(70), |
202 | MFIO_PIN_DESC(71), |
203 | MFIO_PIN_DESC(72), |
204 | MFIO_PIN_DESC(73), |
205 | MFIO_PIN_DESC(74), |
206 | MFIO_PIN_DESC(75), |
207 | MFIO_PIN_DESC(76), |
208 | MFIO_PIN_DESC(77), |
209 | MFIO_PIN_DESC(78), |
210 | MFIO_PIN_DESC(79), |
211 | MFIO_PIN_DESC(80), |
212 | MFIO_PIN_DESC(81), |
213 | MFIO_PIN_DESC(82), |
214 | MFIO_PIN_DESC(83), |
215 | MFIO_PIN_DESC(84), |
216 | MFIO_PIN_DESC(85), |
217 | MFIO_PIN_DESC(86), |
218 | MFIO_PIN_DESC(87), |
219 | MFIO_PIN_DESC(88), |
220 | MFIO_PIN_DESC(89), |
221 | PINCTRL_PIN(PISTACHIO_PIN_TCK, "tck" ), |
222 | PINCTRL_PIN(PISTACHIO_PIN_TRSTN, "trstn" ), |
223 | PINCTRL_PIN(PISTACHIO_PIN_TDI, "tdi" ), |
224 | PINCTRL_PIN(PISTACHIO_PIN_TMS, "tms" ), |
225 | PINCTRL_PIN(PISTACHIO_PIN_TDO, "tdo" ), |
226 | PINCTRL_PIN(PISTACHIO_PIN_JTAG_COMPLY, "jtag_comply" ), |
227 | PINCTRL_PIN(PISTACHIO_PIN_SAFE_MODE, "safe_mode" ), |
228 | PINCTRL_PIN(PISTACHIO_PIN_POR_DISABLE, "por_disable" ), |
229 | PINCTRL_PIN(PISTACHIO_PIN_RESETN, "resetn" ), |
230 | }; |
231 | |
232 | static const char * const pistachio_spim0_groups[] = { |
233 | "mfio1" , "mfio2" , "mfio8" , "mfio9" , "mfio10" , "mfio28" , "mfio29" , |
234 | "mfio30" , "mfio55" , "mfio56" , "mfio57" , |
235 | }; |
236 | |
237 | static const char * const pistachio_spim1_groups[] = { |
238 | "mfio0" , "mfio1" , "mfio2" , "mfio3" , "mfio4" , "mfio5" , "mfio6" , |
239 | "mfio7" , "mfio31" , "mfio55" , "mfio56" , "mfio57" , "mfio58" , |
240 | }; |
241 | |
242 | static const char * const pistachio_spis_groups[] = { |
243 | "mfio11" , "mfio12" , "mfio13" , "mfio14" , |
244 | }; |
245 | |
246 | static const char *const pistachio_sdhost_groups[] = { |
247 | "mfio15" , "mfio16" , "mfio17" , "mfio18" , "mfio19" , "mfio20" , |
248 | "mfio21" , "mfio22" , "mfio23" , "mfio24" , "mfio25" , "mfio26" , |
249 | "mfio27" , |
250 | }; |
251 | |
252 | static const char * const pistachio_i2c0_groups[] = { |
253 | "mfio28" , "mfio29" , |
254 | }; |
255 | |
256 | static const char * const pistachio_i2c1_groups[] = { |
257 | "mfio30" , "mfio31" , |
258 | }; |
259 | |
260 | static const char * const pistachio_i2c2_groups[] = { |
261 | "mfio32" , "mfio33" , |
262 | }; |
263 | |
264 | static const char * const pistachio_i2c3_groups[] = { |
265 | "mfio34" , "mfio35" , |
266 | }; |
267 | |
268 | static const char * const pistachio_audio_clk_in_groups[] = { |
269 | "mfio36" , |
270 | }; |
271 | |
272 | static const char * const pistachio_i2s_out_groups[] = { |
273 | "mfio36" , "mfio37" , "mfio38" , "mfio39" , "mfio40" , "mfio41" , |
274 | "mfio42" , "mfio43" , "mfio44" , |
275 | }; |
276 | |
277 | static const char * const pistachio_debug_raw_cca_ind_groups[] = { |
278 | "mfio37" , |
279 | }; |
280 | |
281 | static const char * const pistachio_debug_ed_sec20_cca_ind_groups[] = { |
282 | "mfio38" , |
283 | }; |
284 | |
285 | static const char * const pistachio_debug_ed_sec40_cca_ind_groups[] = { |
286 | "mfio39" , |
287 | }; |
288 | |
289 | static const char * const pistachio_debug_agc_done_0_groups[] = { |
290 | "mfio40" , |
291 | }; |
292 | |
293 | static const char * const pistachio_debug_agc_done_1_groups[] = { |
294 | "mfio41" , |
295 | }; |
296 | |
297 | static const char * const pistachio_debug_ed_cca_ind_groups[] = { |
298 | "mfio42" , |
299 | }; |
300 | |
301 | static const char * const pistachio_debug_s2l_done_groups[] = { |
302 | "mfio43" , |
303 | }; |
304 | |
305 | static const char * const pistachio_i2s_dac_clk_groups[] = { |
306 | "mfio45" , |
307 | }; |
308 | |
309 | static const char * const pistachio_audio_sync_groups[] = { |
310 | "mfio45" , |
311 | }; |
312 | |
313 | static const char * const pistachio_audio_trigger_groups[] = { |
314 | "mfio46" , |
315 | }; |
316 | |
317 | static const char * const pistachio_i2s_in_groups[] = { |
318 | "mfio47" , "mfio48" , "mfio49" , "mfio50" , "mfio51" , "mfio52" , |
319 | "mfio53" , "mfio54" , |
320 | }; |
321 | |
322 | static const char * const pistachio_uart0_groups[] = { |
323 | "mfio55" , "mfio56" , "mfio57" , "mfio58" , |
324 | }; |
325 | |
326 | static const char * const pistachio_uart1_groups[] = { |
327 | "mfio59" , "mfio60" , "mfio1" , "mfio2" , |
328 | }; |
329 | |
330 | static const char * const pistachio_spdif_out_groups[] = { |
331 | "mfio61" , |
332 | }; |
333 | |
334 | static const char * const pistachio_spdif_in_groups[] = { |
335 | "mfio62" , "mfio54" , |
336 | }; |
337 | static const int pistachio_spdif_in_scenarios[] = { |
338 | PISTACHIO_PIN_MFIO(62), |
339 | PISTACHIO_PIN_MFIO(54), |
340 | }; |
341 | |
342 | static const char * const pistachio_eth_groups[] = { |
343 | "mfio63" , "mfio64" , "mfio65" , "mfio66" , "mfio67" , "mfio68" , |
344 | "mfio69" , "mfio70" , "mfio71" , |
345 | }; |
346 | |
347 | static const char * const pistachio_ir_groups[] = { |
348 | "mfio72" , |
349 | }; |
350 | |
351 | static const char * const pistachio_pwmpdm_groups[] = { |
352 | "mfio73" , "mfio74" , "mfio75" , "mfio76" , |
353 | }; |
354 | |
355 | static const char * const pistachio_mips_trace_clk_groups[] = { |
356 | "mfio15" , "mfio63" , "mfio73" , |
357 | }; |
358 | |
359 | static const char * const pistachio_mips_trace_dint_groups[] = { |
360 | "mfio16" , "mfio64" , "mfio74" , |
361 | }; |
362 | static const int pistachio_mips_trace_dint_scenarios[] = { |
363 | PISTACHIO_PIN_MFIO(16), |
364 | PISTACHIO_PIN_MFIO(64), |
365 | PISTACHIO_PIN_MFIO(74), |
366 | }; |
367 | |
368 | static const char * const pistachio_mips_trace_trigout_groups[] = { |
369 | "mfio17" , "mfio65" , "mfio75" , |
370 | }; |
371 | |
372 | static const char * const pistachio_mips_trace_trigin_groups[] = { |
373 | "mfio18" , "mfio66" , "mfio76" , |
374 | }; |
375 | static const int pistachio_mips_trace_trigin_scenarios[] = { |
376 | PISTACHIO_PIN_MFIO(18), |
377 | PISTACHIO_PIN_MFIO(66), |
378 | PISTACHIO_PIN_MFIO(76), |
379 | }; |
380 | |
381 | static const char * const pistachio_mips_trace_dm_groups[] = { |
382 | "mfio19" , "mfio67" , "mfio77" , |
383 | }; |
384 | |
385 | static const char * const pistachio_mips_probe_n_groups[] = { |
386 | "mfio20" , "mfio68" , "mfio78" , |
387 | }; |
388 | static const int pistachio_mips_probe_n_scenarios[] = { |
389 | PISTACHIO_PIN_MFIO(20), |
390 | PISTACHIO_PIN_MFIO(68), |
391 | PISTACHIO_PIN_MFIO(78), |
392 | }; |
393 | |
394 | static const char * const pistachio_mips_trace_data_groups[] = { |
395 | "mfio15" , "mfio16" , "mfio17" , "mfio18" , "mfio19" , "mfio20" , |
396 | "mfio21" , "mfio22" , "mfio63" , "mfio64" , "mfio65" , "mfio66" , |
397 | "mfio67" , "mfio68" , "mfio69" , "mfio70" , "mfio79" , "mfio80" , |
398 | "mfio81" , "mfio82" , "mfio83" , "mfio84" , "mfio85" , "mfio86" , |
399 | }; |
400 | |
401 | static const char * const pistachio_sram_debug_groups[] = { |
402 | "mfio73" , "mfio74" , |
403 | }; |
404 | |
405 | static const char * const pistachio_rom_debug_groups[] = { |
406 | "mfio75" , "mfio76" , |
407 | }; |
408 | |
409 | static const char * const pistachio_rpu_debug_groups[] = { |
410 | "mfio77" , "mfio78" , |
411 | }; |
412 | |
413 | static const char * const pistachio_mips_debug_groups[] = { |
414 | "mfio79" , "mfio80" , |
415 | }; |
416 | |
417 | static const char * const pistachio_eth_debug_groups[] = { |
418 | "mfio81" , "mfio82" , |
419 | }; |
420 | |
421 | static const char * const pistachio_usb_debug_groups[] = { |
422 | "mfio83" , "mfio84" , |
423 | }; |
424 | |
425 | static const char * const pistachio_sdhost_debug_groups[] = { |
426 | "mfio85" , "mfio86" , |
427 | }; |
428 | |
429 | static const char * const pistachio_socif_debug_groups[] = { |
430 | "mfio87" , "mfio88" , |
431 | }; |
432 | |
433 | static const char * const pistachio_mdc_debug_groups[] = { |
434 | "mfio77" , "mfio78" , |
435 | }; |
436 | |
437 | static const char * const pistachio_ddr_debug_groups[] = { |
438 | "mfio79" , "mfio80" , |
439 | }; |
440 | |
441 | static const char * const pistachio_dreq0_groups[] = { |
442 | "mfio81" , |
443 | }; |
444 | |
445 | static const char * const pistachio_dreq1_groups[] = { |
446 | "mfio82" , |
447 | }; |
448 | |
449 | static const char * const pistachio_dreq2_groups[] = { |
450 | "mfio87" , |
451 | }; |
452 | |
453 | static const char * const pistachio_dreq3_groups[] = { |
454 | "mfio88" , |
455 | }; |
456 | |
457 | static const char * const pistachio_dreq4_groups[] = { |
458 | "mfio89" , |
459 | }; |
460 | |
461 | static const char * const pistachio_dreq5_groups[] = { |
462 | "mfio89" , |
463 | }; |
464 | |
465 | static const char * const pistachio_mips_pll_lock_groups[] = { |
466 | "mfio83" , |
467 | }; |
468 | |
469 | static const char * const pistachio_audio_pll_lock_groups[] = { |
470 | "mfio84" , |
471 | }; |
472 | |
473 | static const char * const pistachio_rpu_v_pll_lock_groups[] = { |
474 | "mfio85" , |
475 | }; |
476 | |
477 | static const char * const pistachio_rpu_l_pll_lock_groups[] = { |
478 | "mfio86" , |
479 | }; |
480 | |
481 | static const char * const pistachio_sys_pll_lock_groups[] = { |
482 | "mfio87" , |
483 | }; |
484 | |
485 | static const char * const pistachio_wifi_pll_lock_groups[] = { |
486 | "mfio88" , |
487 | }; |
488 | |
489 | static const char * const pistachio_bt_pll_lock_groups[] = { |
490 | "mfio89" , |
491 | }; |
492 | |
493 | #define FUNCTION(_name) \ |
494 | { \ |
495 | .name = #_name, \ |
496 | .groups = pistachio_##_name##_groups, \ |
497 | .ngroups = ARRAY_SIZE(pistachio_##_name##_groups), \ |
498 | } |
499 | |
500 | #define FUNCTION_SCENARIO(_name, _reg, _shift, _mask) \ |
501 | { \ |
502 | .name = #_name, \ |
503 | .groups = pistachio_##_name##_groups, \ |
504 | .ngroups = ARRAY_SIZE(pistachio_##_name##_groups), \ |
505 | .scenarios = pistachio_##_name##_scenarios, \ |
506 | .nscenarios = ARRAY_SIZE(pistachio_##_name##_scenarios),\ |
507 | .scenario_reg = _reg, \ |
508 | .scenario_shift = _shift, \ |
509 | .scenario_mask = _mask, \ |
510 | } |
511 | |
512 | enum pistachio_mux_option { |
513 | PISTACHIO_FUNCTION_NONE = -1, |
514 | PISTACHIO_FUNCTION_SPIM0, |
515 | PISTACHIO_FUNCTION_SPIM1, |
516 | PISTACHIO_FUNCTION_SPIS, |
517 | PISTACHIO_FUNCTION_SDHOST, |
518 | PISTACHIO_FUNCTION_I2C0, |
519 | PISTACHIO_FUNCTION_I2C1, |
520 | PISTACHIO_FUNCTION_I2C2, |
521 | PISTACHIO_FUNCTION_I2C3, |
522 | PISTACHIO_FUNCTION_AUDIO_CLK_IN, |
523 | PISTACHIO_FUNCTION_I2S_OUT, |
524 | PISTACHIO_FUNCTION_I2S_DAC_CLK, |
525 | PISTACHIO_FUNCTION_AUDIO_SYNC, |
526 | PISTACHIO_FUNCTION_AUDIO_TRIGGER, |
527 | PISTACHIO_FUNCTION_I2S_IN, |
528 | PISTACHIO_FUNCTION_UART0, |
529 | PISTACHIO_FUNCTION_UART1, |
530 | PISTACHIO_FUNCTION_SPDIF_OUT, |
531 | PISTACHIO_FUNCTION_SPDIF_IN, |
532 | PISTACHIO_FUNCTION_ETH, |
533 | PISTACHIO_FUNCTION_IR, |
534 | PISTACHIO_FUNCTION_PWMPDM, |
535 | PISTACHIO_FUNCTION_MIPS_TRACE_CLK, |
536 | PISTACHIO_FUNCTION_MIPS_TRACE_DINT, |
537 | PISTACHIO_FUNCTION_MIPS_TRACE_TRIGOUT, |
538 | PISTACHIO_FUNCTION_MIPS_TRACE_TRIGIN, |
539 | PISTACHIO_FUNCTION_MIPS_TRACE_DM, |
540 | PISTACHIO_FUNCTION_MIPS_TRACE_PROBE_N, |
541 | PISTACHIO_FUNCTION_MIPS_TRACE_DATA, |
542 | PISTACHIO_FUNCTION_SRAM_DEBUG, |
543 | PISTACHIO_FUNCTION_ROM_DEBUG, |
544 | PISTACHIO_FUNCTION_RPU_DEBUG, |
545 | PISTACHIO_FUNCTION_MIPS_DEBUG, |
546 | PISTACHIO_FUNCTION_ETH_DEBUG, |
547 | PISTACHIO_FUNCTION_USB_DEBUG, |
548 | PISTACHIO_FUNCTION_SDHOST_DEBUG, |
549 | PISTACHIO_FUNCTION_SOCIF_DEBUG, |
550 | PISTACHIO_FUNCTION_MDC_DEBUG, |
551 | PISTACHIO_FUNCTION_DDR_DEBUG, |
552 | PISTACHIO_FUNCTION_DREQ0, |
553 | PISTACHIO_FUNCTION_DREQ1, |
554 | PISTACHIO_FUNCTION_DREQ2, |
555 | PISTACHIO_FUNCTION_DREQ3, |
556 | PISTACHIO_FUNCTION_DREQ4, |
557 | PISTACHIO_FUNCTION_DREQ5, |
558 | PISTACHIO_FUNCTION_MIPS_PLL_LOCK, |
559 | PISTACHIO_FUNCTION_AUDIO_PLL_LOCK, |
560 | PISTACHIO_FUNCTION_RPU_V_PLL_LOCK, |
561 | PISTACHIO_FUNCTION_RPU_L_PLL_LOCK, |
562 | PISTACHIO_FUNCTION_SYS_PLL_LOCK, |
563 | PISTACHIO_FUNCTION_WIFI_PLL_LOCK, |
564 | PISTACHIO_FUNCTION_BT_PLL_LOCK, |
565 | PISTACHIO_FUNCTION_DEBUG_RAW_CCA_IND, |
566 | PISTACHIO_FUNCTION_DEBUG_ED_SEC20_CCA_IND, |
567 | PISTACHIO_FUNCTION_DEBUG_ED_SEC40_CCA_IND, |
568 | PISTACHIO_FUNCTION_DEBUG_AGC_DONE_0, |
569 | PISTACHIO_FUNCTION_DEBUG_AGC_DONE_1, |
570 | PISTACHIO_FUNCTION_DEBUG_ED_CCA_IND, |
571 | PISTACHIO_FUNCTION_DEBUG_S2L_DONE, |
572 | }; |
573 | |
574 | static const struct pistachio_function pistachio_functions[] = { |
575 | FUNCTION(spim0), |
576 | FUNCTION(spim1), |
577 | FUNCTION(spis), |
578 | FUNCTION(sdhost), |
579 | FUNCTION(i2c0), |
580 | FUNCTION(i2c1), |
581 | FUNCTION(i2c2), |
582 | FUNCTION(i2c3), |
583 | FUNCTION(audio_clk_in), |
584 | FUNCTION(i2s_out), |
585 | FUNCTION(i2s_dac_clk), |
586 | FUNCTION(audio_sync), |
587 | FUNCTION(audio_trigger), |
588 | FUNCTION(i2s_in), |
589 | FUNCTION(uart0), |
590 | FUNCTION(uart1), |
591 | FUNCTION(spdif_out), |
592 | FUNCTION_SCENARIO(spdif_in, PADS_SCENARIO_SELECT, 0, 0x1), |
593 | FUNCTION(eth), |
594 | FUNCTION(ir), |
595 | FUNCTION(pwmpdm), |
596 | FUNCTION(mips_trace_clk), |
597 | FUNCTION_SCENARIO(mips_trace_dint, PADS_SCENARIO_SELECT, 1, 0x3), |
598 | FUNCTION(mips_trace_trigout), |
599 | FUNCTION_SCENARIO(mips_trace_trigin, PADS_SCENARIO_SELECT, 3, 0x3), |
600 | FUNCTION(mips_trace_dm), |
601 | FUNCTION_SCENARIO(mips_probe_n, PADS_SCENARIO_SELECT, 5, 0x3), |
602 | FUNCTION(mips_trace_data), |
603 | FUNCTION(sram_debug), |
604 | FUNCTION(rom_debug), |
605 | FUNCTION(rpu_debug), |
606 | FUNCTION(mips_debug), |
607 | FUNCTION(eth_debug), |
608 | FUNCTION(usb_debug), |
609 | FUNCTION(sdhost_debug), |
610 | FUNCTION(socif_debug), |
611 | FUNCTION(mdc_debug), |
612 | FUNCTION(ddr_debug), |
613 | FUNCTION(dreq0), |
614 | FUNCTION(dreq1), |
615 | FUNCTION(dreq2), |
616 | FUNCTION(dreq3), |
617 | FUNCTION(dreq4), |
618 | FUNCTION(dreq5), |
619 | FUNCTION(mips_pll_lock), |
620 | FUNCTION(audio_pll_lock), |
621 | FUNCTION(rpu_v_pll_lock), |
622 | FUNCTION(rpu_l_pll_lock), |
623 | FUNCTION(sys_pll_lock), |
624 | FUNCTION(wifi_pll_lock), |
625 | FUNCTION(bt_pll_lock), |
626 | FUNCTION(debug_raw_cca_ind), |
627 | FUNCTION(debug_ed_sec20_cca_ind), |
628 | FUNCTION(debug_ed_sec40_cca_ind), |
629 | FUNCTION(debug_agc_done_0), |
630 | FUNCTION(debug_agc_done_1), |
631 | FUNCTION(debug_ed_cca_ind), |
632 | FUNCTION(debug_s2l_done), |
633 | }; |
634 | |
635 | #define PIN_GROUP(_pin, _name) \ |
636 | { \ |
637 | .name = #_name, \ |
638 | .pin = PISTACHIO_PIN_##_pin, \ |
639 | .mux_option = { \ |
640 | PISTACHIO_FUNCTION_NONE, \ |
641 | PISTACHIO_FUNCTION_NONE, \ |
642 | PISTACHIO_FUNCTION_NONE, \ |
643 | }, \ |
644 | .mux_reg = -1, \ |
645 | .mux_shift = -1, \ |
646 | .mux_mask = -1, \ |
647 | } |
648 | |
649 | #define MFIO_PIN_GROUP(_pin, _func) \ |
650 | { \ |
651 | .name = "mfio" #_pin, \ |
652 | .pin = PISTACHIO_PIN_MFIO(_pin), \ |
653 | .mux_option = { \ |
654 | PISTACHIO_FUNCTION_##_func, \ |
655 | PISTACHIO_FUNCTION_NONE, \ |
656 | PISTACHIO_FUNCTION_NONE, \ |
657 | }, \ |
658 | .mux_reg = -1, \ |
659 | .mux_shift = -1, \ |
660 | .mux_mask = -1, \ |
661 | } |
662 | |
663 | #define MFIO_MUX_PIN_GROUP(_pin, _f0, _f1, _f2, _reg, _shift, _mask) \ |
664 | { \ |
665 | .name = "mfio" #_pin, \ |
666 | .pin = PISTACHIO_PIN_MFIO(_pin), \ |
667 | .mux_option = { \ |
668 | PISTACHIO_FUNCTION_##_f0, \ |
669 | PISTACHIO_FUNCTION_##_f1, \ |
670 | PISTACHIO_FUNCTION_##_f2, \ |
671 | }, \ |
672 | .mux_reg = _reg, \ |
673 | .mux_shift = _shift, \ |
674 | .mux_mask = _mask, \ |
675 | } |
676 | |
677 | static const struct pistachio_pin_group pistachio_groups[] = { |
678 | MFIO_PIN_GROUP(0, SPIM1), |
679 | MFIO_MUX_PIN_GROUP(1, SPIM1, SPIM0, UART1, |
680 | PADS_FUNCTION_SELECT0, 0, 0x3), |
681 | MFIO_MUX_PIN_GROUP(2, SPIM1, SPIM0, UART1, |
682 | PADS_FUNCTION_SELECT0, 2, 0x3), |
683 | MFIO_PIN_GROUP(3, SPIM1), |
684 | MFIO_PIN_GROUP(4, SPIM1), |
685 | MFIO_PIN_GROUP(5, SPIM1), |
686 | MFIO_PIN_GROUP(6, SPIM1), |
687 | MFIO_PIN_GROUP(7, SPIM1), |
688 | MFIO_PIN_GROUP(8, SPIM0), |
689 | MFIO_PIN_GROUP(9, SPIM0), |
690 | MFIO_PIN_GROUP(10, SPIM0), |
691 | MFIO_PIN_GROUP(11, SPIS), |
692 | MFIO_PIN_GROUP(12, SPIS), |
693 | MFIO_PIN_GROUP(13, SPIS), |
694 | MFIO_PIN_GROUP(14, SPIS), |
695 | MFIO_MUX_PIN_GROUP(15, SDHOST, MIPS_TRACE_CLK, MIPS_TRACE_DATA, |
696 | PADS_FUNCTION_SELECT0, 4, 0x3), |
697 | MFIO_MUX_PIN_GROUP(16, SDHOST, MIPS_TRACE_DINT, MIPS_TRACE_DATA, |
698 | PADS_FUNCTION_SELECT0, 6, 0x3), |
699 | MFIO_MUX_PIN_GROUP(17, SDHOST, MIPS_TRACE_TRIGOUT, MIPS_TRACE_DATA, |
700 | PADS_FUNCTION_SELECT0, 8, 0x3), |
701 | MFIO_MUX_PIN_GROUP(18, SDHOST, MIPS_TRACE_TRIGIN, MIPS_TRACE_DATA, |
702 | PADS_FUNCTION_SELECT0, 10, 0x3), |
703 | MFIO_MUX_PIN_GROUP(19, SDHOST, MIPS_TRACE_DM, MIPS_TRACE_DATA, |
704 | PADS_FUNCTION_SELECT0, 12, 0x3), |
705 | MFIO_MUX_PIN_GROUP(20, SDHOST, MIPS_TRACE_PROBE_N, MIPS_TRACE_DATA, |
706 | PADS_FUNCTION_SELECT0, 14, 0x3), |
707 | MFIO_MUX_PIN_GROUP(21, SDHOST, NONE, MIPS_TRACE_DATA, |
708 | PADS_FUNCTION_SELECT0, 16, 0x3), |
709 | MFIO_MUX_PIN_GROUP(22, SDHOST, NONE, MIPS_TRACE_DATA, |
710 | PADS_FUNCTION_SELECT0, 18, 0x3), |
711 | MFIO_PIN_GROUP(23, SDHOST), |
712 | MFIO_PIN_GROUP(24, SDHOST), |
713 | MFIO_PIN_GROUP(25, SDHOST), |
714 | MFIO_PIN_GROUP(26, SDHOST), |
715 | MFIO_PIN_GROUP(27, SDHOST), |
716 | MFIO_MUX_PIN_GROUP(28, I2C0, SPIM0, NONE, |
717 | PADS_FUNCTION_SELECT0, 20, 0x1), |
718 | MFIO_MUX_PIN_GROUP(29, I2C0, SPIM0, NONE, |
719 | PADS_FUNCTION_SELECT0, 21, 0x1), |
720 | MFIO_MUX_PIN_GROUP(30, I2C1, SPIM0, NONE, |
721 | PADS_FUNCTION_SELECT0, 22, 0x1), |
722 | MFIO_MUX_PIN_GROUP(31, I2C1, SPIM1, NONE, |
723 | PADS_FUNCTION_SELECT0, 23, 0x1), |
724 | MFIO_PIN_GROUP(32, I2C2), |
725 | MFIO_PIN_GROUP(33, I2C2), |
726 | MFIO_PIN_GROUP(34, I2C3), |
727 | MFIO_PIN_GROUP(35, I2C3), |
728 | MFIO_MUX_PIN_GROUP(36, I2S_OUT, AUDIO_CLK_IN, NONE, |
729 | PADS_FUNCTION_SELECT0, 24, 0x1), |
730 | MFIO_MUX_PIN_GROUP(37, I2S_OUT, DEBUG_RAW_CCA_IND, NONE, |
731 | PADS_FUNCTION_SELECT0, 25, 0x1), |
732 | MFIO_MUX_PIN_GROUP(38, I2S_OUT, DEBUG_ED_SEC20_CCA_IND, NONE, |
733 | PADS_FUNCTION_SELECT0, 26, 0x1), |
734 | MFIO_MUX_PIN_GROUP(39, I2S_OUT, DEBUG_ED_SEC40_CCA_IND, NONE, |
735 | PADS_FUNCTION_SELECT0, 27, 0x1), |
736 | MFIO_MUX_PIN_GROUP(40, I2S_OUT, DEBUG_AGC_DONE_0, NONE, |
737 | PADS_FUNCTION_SELECT0, 28, 0x1), |
738 | MFIO_MUX_PIN_GROUP(41, I2S_OUT, DEBUG_AGC_DONE_1, NONE, |
739 | PADS_FUNCTION_SELECT0, 29, 0x1), |
740 | MFIO_MUX_PIN_GROUP(42, I2S_OUT, DEBUG_ED_CCA_IND, NONE, |
741 | PADS_FUNCTION_SELECT0, 30, 0x1), |
742 | MFIO_MUX_PIN_GROUP(43, I2S_OUT, DEBUG_S2L_DONE, NONE, |
743 | PADS_FUNCTION_SELECT0, 31, 0x1), |
744 | MFIO_PIN_GROUP(44, I2S_OUT), |
745 | MFIO_MUX_PIN_GROUP(45, I2S_DAC_CLK, AUDIO_SYNC, NONE, |
746 | PADS_FUNCTION_SELECT1, 0, 0x1), |
747 | MFIO_PIN_GROUP(46, AUDIO_TRIGGER), |
748 | MFIO_PIN_GROUP(47, I2S_IN), |
749 | MFIO_PIN_GROUP(48, I2S_IN), |
750 | MFIO_PIN_GROUP(49, I2S_IN), |
751 | MFIO_PIN_GROUP(50, I2S_IN), |
752 | MFIO_PIN_GROUP(51, I2S_IN), |
753 | MFIO_PIN_GROUP(52, I2S_IN), |
754 | MFIO_PIN_GROUP(53, I2S_IN), |
755 | MFIO_MUX_PIN_GROUP(54, I2S_IN, NONE, SPDIF_IN, |
756 | PADS_FUNCTION_SELECT1, 1, 0x3), |
757 | MFIO_MUX_PIN_GROUP(55, UART0, SPIM0, SPIM1, |
758 | PADS_FUNCTION_SELECT1, 3, 0x3), |
759 | MFIO_MUX_PIN_GROUP(56, UART0, SPIM0, SPIM1, |
760 | PADS_FUNCTION_SELECT1, 5, 0x3), |
761 | MFIO_MUX_PIN_GROUP(57, UART0, SPIM0, SPIM1, |
762 | PADS_FUNCTION_SELECT1, 7, 0x3), |
763 | MFIO_MUX_PIN_GROUP(58, UART0, SPIM1, NONE, |
764 | PADS_FUNCTION_SELECT1, 9, 0x1), |
765 | MFIO_PIN_GROUP(59, UART1), |
766 | MFIO_PIN_GROUP(60, UART1), |
767 | MFIO_PIN_GROUP(61, SPDIF_OUT), |
768 | MFIO_PIN_GROUP(62, SPDIF_IN), |
769 | MFIO_MUX_PIN_GROUP(63, ETH, MIPS_TRACE_CLK, MIPS_TRACE_DATA, |
770 | PADS_FUNCTION_SELECT1, 10, 0x3), |
771 | MFIO_MUX_PIN_GROUP(64, ETH, MIPS_TRACE_DINT, MIPS_TRACE_DATA, |
772 | PADS_FUNCTION_SELECT1, 12, 0x3), |
773 | MFIO_MUX_PIN_GROUP(65, ETH, MIPS_TRACE_TRIGOUT, MIPS_TRACE_DATA, |
774 | PADS_FUNCTION_SELECT1, 14, 0x3), |
775 | MFIO_MUX_PIN_GROUP(66, ETH, MIPS_TRACE_TRIGIN, MIPS_TRACE_DATA, |
776 | PADS_FUNCTION_SELECT1, 16, 0x3), |
777 | MFIO_MUX_PIN_GROUP(67, ETH, MIPS_TRACE_DM, MIPS_TRACE_DATA, |
778 | PADS_FUNCTION_SELECT1, 18, 0x3), |
779 | MFIO_MUX_PIN_GROUP(68, ETH, MIPS_TRACE_PROBE_N, MIPS_TRACE_DATA, |
780 | PADS_FUNCTION_SELECT1, 20, 0x3), |
781 | MFIO_MUX_PIN_GROUP(69, ETH, NONE, MIPS_TRACE_DATA, |
782 | PADS_FUNCTION_SELECT1, 22, 0x3), |
783 | MFIO_MUX_PIN_GROUP(70, ETH, NONE, MIPS_TRACE_DATA, |
784 | PADS_FUNCTION_SELECT1, 24, 0x3), |
785 | MFIO_PIN_GROUP(71, ETH), |
786 | MFIO_PIN_GROUP(72, IR), |
787 | MFIO_MUX_PIN_GROUP(73, PWMPDM, MIPS_TRACE_CLK, SRAM_DEBUG, |
788 | PADS_FUNCTION_SELECT1, 26, 0x3), |
789 | MFIO_MUX_PIN_GROUP(74, PWMPDM, MIPS_TRACE_DINT, SRAM_DEBUG, |
790 | PADS_FUNCTION_SELECT1, 28, 0x3), |
791 | MFIO_MUX_PIN_GROUP(75, PWMPDM, MIPS_TRACE_TRIGOUT, ROM_DEBUG, |
792 | PADS_FUNCTION_SELECT1, 30, 0x3), |
793 | MFIO_MUX_PIN_GROUP(76, PWMPDM, MIPS_TRACE_TRIGIN, ROM_DEBUG, |
794 | PADS_FUNCTION_SELECT2, 0, 0x3), |
795 | MFIO_MUX_PIN_GROUP(77, MDC_DEBUG, MIPS_TRACE_DM, RPU_DEBUG, |
796 | PADS_FUNCTION_SELECT2, 2, 0x3), |
797 | MFIO_MUX_PIN_GROUP(78, MDC_DEBUG, MIPS_TRACE_PROBE_N, RPU_DEBUG, |
798 | PADS_FUNCTION_SELECT2, 4, 0x3), |
799 | MFIO_MUX_PIN_GROUP(79, DDR_DEBUG, MIPS_TRACE_DATA, MIPS_DEBUG, |
800 | PADS_FUNCTION_SELECT2, 6, 0x3), |
801 | MFIO_MUX_PIN_GROUP(80, DDR_DEBUG, MIPS_TRACE_DATA, MIPS_DEBUG, |
802 | PADS_FUNCTION_SELECT2, 8, 0x3), |
803 | MFIO_MUX_PIN_GROUP(81, DREQ0, MIPS_TRACE_DATA, ETH_DEBUG, |
804 | PADS_FUNCTION_SELECT2, 10, 0x3), |
805 | MFIO_MUX_PIN_GROUP(82, DREQ1, MIPS_TRACE_DATA, ETH_DEBUG, |
806 | PADS_FUNCTION_SELECT2, 12, 0x3), |
807 | MFIO_MUX_PIN_GROUP(83, MIPS_PLL_LOCK, MIPS_TRACE_DATA, USB_DEBUG, |
808 | PADS_FUNCTION_SELECT2, 14, 0x3), |
809 | MFIO_MUX_PIN_GROUP(84, AUDIO_PLL_LOCK, MIPS_TRACE_DATA, USB_DEBUG, |
810 | PADS_FUNCTION_SELECT2, 16, 0x3), |
811 | MFIO_MUX_PIN_GROUP(85, RPU_V_PLL_LOCK, MIPS_TRACE_DATA, SDHOST_DEBUG, |
812 | PADS_FUNCTION_SELECT2, 18, 0x3), |
813 | MFIO_MUX_PIN_GROUP(86, RPU_L_PLL_LOCK, MIPS_TRACE_DATA, SDHOST_DEBUG, |
814 | PADS_FUNCTION_SELECT2, 20, 0x3), |
815 | MFIO_MUX_PIN_GROUP(87, SYS_PLL_LOCK, DREQ2, SOCIF_DEBUG, |
816 | PADS_FUNCTION_SELECT2, 22, 0x3), |
817 | MFIO_MUX_PIN_GROUP(88, WIFI_PLL_LOCK, DREQ3, SOCIF_DEBUG, |
818 | PADS_FUNCTION_SELECT2, 24, 0x3), |
819 | MFIO_MUX_PIN_GROUP(89, BT_PLL_LOCK, DREQ4, DREQ5, |
820 | PADS_FUNCTION_SELECT2, 26, 0x3), |
821 | PIN_GROUP(TCK, "tck" ), |
822 | PIN_GROUP(TRSTN, "trstn" ), |
823 | PIN_GROUP(TDI, "tdi" ), |
824 | PIN_GROUP(TMS, "tms" ), |
825 | PIN_GROUP(TDO, "tdo" ), |
826 | PIN_GROUP(JTAG_COMPLY, "jtag_comply" ), |
827 | PIN_GROUP(SAFE_MODE, "safe_mode" ), |
828 | PIN_GROUP(POR_DISABLE, "por_disable" ), |
829 | PIN_GROUP(RESETN, "resetn" ), |
830 | }; |
831 | |
832 | static inline u32 pctl_readl(struct pistachio_pinctrl *pctl, u32 reg) |
833 | { |
834 | return readl(addr: pctl->base + reg); |
835 | } |
836 | |
837 | static inline void pctl_writel(struct pistachio_pinctrl *pctl, u32 val, u32 reg) |
838 | { |
839 | writel(val, addr: pctl->base + reg); |
840 | } |
841 | |
842 | static inline struct pistachio_gpio_bank *irqd_to_bank(struct irq_data *d) |
843 | { |
844 | return gpiochip_get_data(gc: irq_data_get_irq_chip_data(d)); |
845 | } |
846 | |
847 | static inline u32 gpio_readl(struct pistachio_gpio_bank *bank, u32 reg) |
848 | { |
849 | return readl(addr: bank->base + reg); |
850 | } |
851 | |
852 | static inline void gpio_writel(struct pistachio_gpio_bank *bank, u32 val, |
853 | u32 reg) |
854 | { |
855 | writel(val, addr: bank->base + reg); |
856 | } |
857 | |
858 | static inline void gpio_mask_writel(struct pistachio_gpio_bank *bank, |
859 | u32 reg, unsigned int bit, u32 val) |
860 | { |
861 | /* |
862 | * For most of the GPIO registers, bit 16 + X must be set in order to |
863 | * write bit X. |
864 | */ |
865 | gpio_writel(bank, val: (0x10000 | val) << bit, reg); |
866 | } |
867 | |
868 | static inline void gpio_enable(struct pistachio_gpio_bank *bank, |
869 | unsigned offset) |
870 | { |
871 | gpio_mask_writel(bank, GPIO_BIT_EN, bit: offset, val: 1); |
872 | } |
873 | |
874 | static inline void gpio_disable(struct pistachio_gpio_bank *bank, |
875 | unsigned offset) |
876 | { |
877 | gpio_mask_writel(bank, GPIO_BIT_EN, bit: offset, val: 0); |
878 | } |
879 | |
880 | static int pistachio_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) |
881 | { |
882 | struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
883 | |
884 | return pctl->ngroups; |
885 | } |
886 | |
887 | static const char *pistachio_pinctrl_get_group_name(struct pinctrl_dev *pctldev, |
888 | unsigned group) |
889 | { |
890 | struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
891 | |
892 | return pctl->groups[group].name; |
893 | } |
894 | |
895 | static int pistachio_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, |
896 | unsigned group, |
897 | const unsigned **pins, |
898 | unsigned *num_pins) |
899 | { |
900 | struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
901 | |
902 | *pins = &pctl->groups[group].pin; |
903 | *num_pins = 1; |
904 | |
905 | return 0; |
906 | } |
907 | |
908 | static const struct pinctrl_ops pistachio_pinctrl_ops = { |
909 | .get_groups_count = pistachio_pinctrl_get_groups_count, |
910 | .get_group_name = pistachio_pinctrl_get_group_name, |
911 | .get_group_pins = pistachio_pinctrl_get_group_pins, |
912 | .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, |
913 | .dt_free_map = pinctrl_utils_free_map, |
914 | }; |
915 | |
916 | static int pistachio_pinmux_get_functions_count(struct pinctrl_dev *pctldev) |
917 | { |
918 | struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
919 | |
920 | return pctl->nfunctions; |
921 | } |
922 | |
923 | static const char * |
924 | pistachio_pinmux_get_function_name(struct pinctrl_dev *pctldev, unsigned func) |
925 | { |
926 | struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
927 | |
928 | return pctl->functions[func].name; |
929 | } |
930 | |
931 | static int pistachio_pinmux_get_function_groups(struct pinctrl_dev *pctldev, |
932 | unsigned func, |
933 | const char * const **groups, |
934 | unsigned * const num_groups) |
935 | { |
936 | struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
937 | |
938 | *groups = pctl->functions[func].groups; |
939 | *num_groups = pctl->functions[func].ngroups; |
940 | |
941 | return 0; |
942 | } |
943 | |
944 | static int pistachio_pinmux_enable(struct pinctrl_dev *pctldev, |
945 | unsigned func, unsigned group) |
946 | { |
947 | struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
948 | const struct pistachio_pin_group *pg = &pctl->groups[group]; |
949 | const struct pistachio_function *pf = &pctl->functions[func]; |
950 | struct pinctrl_gpio_range *range; |
951 | unsigned int i; |
952 | u32 val; |
953 | |
954 | if (pg->mux_reg > 0) { |
955 | for (i = 0; i < ARRAY_SIZE(pg->mux_option); i++) { |
956 | if (pg->mux_option[i] == func) |
957 | break; |
958 | } |
959 | if (i == ARRAY_SIZE(pg->mux_option)) { |
960 | dev_err(pctl->dev, "Cannot mux pin %u to function %u\n" , |
961 | group, func); |
962 | return -EINVAL; |
963 | } |
964 | |
965 | val = pctl_readl(pctl, reg: pg->mux_reg); |
966 | val &= ~(pg->mux_mask << pg->mux_shift); |
967 | val |= i << pg->mux_shift; |
968 | pctl_writel(pctl, val, reg: pg->mux_reg); |
969 | |
970 | if (pf->scenarios) { |
971 | for (i = 0; i < pf->nscenarios; i++) { |
972 | if (pf->scenarios[i] == group) |
973 | break; |
974 | } |
975 | if (WARN_ON(i == pf->nscenarios)) |
976 | return -EINVAL; |
977 | |
978 | val = pctl_readl(pctl, reg: pf->scenario_reg); |
979 | val &= ~(pf->scenario_mask << pf->scenario_shift); |
980 | val |= i << pf->scenario_shift; |
981 | pctl_writel(pctl, val, reg: pf->scenario_reg); |
982 | } |
983 | } |
984 | |
985 | range = pinctrl_find_gpio_range_from_pin(pctldev: pctl->pctldev, pin: pg->pin); |
986 | if (range) |
987 | gpio_disable(bank: gpiochip_get_data(gc: range->gc), offset: pg->pin - range->pin_base); |
988 | |
989 | return 0; |
990 | } |
991 | |
992 | static const struct pinmux_ops pistachio_pinmux_ops = { |
993 | .get_functions_count = pistachio_pinmux_get_functions_count, |
994 | .get_function_name = pistachio_pinmux_get_function_name, |
995 | .get_function_groups = pistachio_pinmux_get_function_groups, |
996 | .set_mux = pistachio_pinmux_enable, |
997 | }; |
998 | |
999 | static int pistachio_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin, |
1000 | unsigned long *config) |
1001 | { |
1002 | struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
1003 | enum pin_config_param param = pinconf_to_config_param(config: *config); |
1004 | u32 val, arg; |
1005 | |
1006 | switch (param) { |
1007 | case PIN_CONFIG_INPUT_SCHMITT_ENABLE: |
1008 | val = pctl_readl(pctl, PADS_SCHMITT_EN_REG(pin)); |
1009 | arg = !!(val & PADS_SCHMITT_EN_BIT(pin)); |
1010 | break; |
1011 | case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: |
1012 | val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >> |
1013 | PADS_PU_PD_SHIFT(pin); |
1014 | arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_HIGHZ; |
1015 | break; |
1016 | case PIN_CONFIG_BIAS_PULL_UP: |
1017 | val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >> |
1018 | PADS_PU_PD_SHIFT(pin); |
1019 | arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_UP; |
1020 | break; |
1021 | case PIN_CONFIG_BIAS_PULL_DOWN: |
1022 | val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >> |
1023 | PADS_PU_PD_SHIFT(pin); |
1024 | arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_DOWN; |
1025 | break; |
1026 | case PIN_CONFIG_BIAS_BUS_HOLD: |
1027 | val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >> |
1028 | PADS_PU_PD_SHIFT(pin); |
1029 | arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_BUS; |
1030 | break; |
1031 | case PIN_CONFIG_SLEW_RATE: |
1032 | val = pctl_readl(pctl, PADS_SLEW_RATE_REG(pin)); |
1033 | arg = !!(val & PADS_SLEW_RATE_BIT(pin)); |
1034 | break; |
1035 | case PIN_CONFIG_DRIVE_STRENGTH: |
1036 | val = pctl_readl(pctl, PADS_DRIVE_STRENGTH_REG(pin)) >> |
1037 | PADS_DRIVE_STRENGTH_SHIFT(pin); |
1038 | switch (val & PADS_DRIVE_STRENGTH_MASK) { |
1039 | case PADS_DRIVE_STRENGTH_2MA: |
1040 | arg = 2; |
1041 | break; |
1042 | case PADS_DRIVE_STRENGTH_4MA: |
1043 | arg = 4; |
1044 | break; |
1045 | case PADS_DRIVE_STRENGTH_8MA: |
1046 | arg = 8; |
1047 | break; |
1048 | case PADS_DRIVE_STRENGTH_12MA: |
1049 | default: |
1050 | arg = 12; |
1051 | break; |
1052 | } |
1053 | break; |
1054 | default: |
1055 | dev_dbg(pctl->dev, "Property %u not supported\n" , param); |
1056 | return -ENOTSUPP; |
1057 | } |
1058 | |
1059 | *config = pinconf_to_config_packed(param, argument: arg); |
1060 | |
1061 | return 0; |
1062 | } |
1063 | |
1064 | static int pistachio_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin, |
1065 | unsigned long *configs, unsigned num_configs) |
1066 | { |
1067 | struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
1068 | enum pin_config_param param; |
1069 | u32 drv, val, arg; |
1070 | unsigned int i; |
1071 | |
1072 | for (i = 0; i < num_configs; i++) { |
1073 | param = pinconf_to_config_param(config: configs[i]); |
1074 | arg = pinconf_to_config_argument(config: configs[i]); |
1075 | |
1076 | switch (param) { |
1077 | case PIN_CONFIG_INPUT_SCHMITT_ENABLE: |
1078 | val = pctl_readl(pctl, PADS_SCHMITT_EN_REG(pin)); |
1079 | if (arg) |
1080 | val |= PADS_SCHMITT_EN_BIT(pin); |
1081 | else |
1082 | val &= ~PADS_SCHMITT_EN_BIT(pin); |
1083 | pctl_writel(pctl, val, PADS_SCHMITT_EN_REG(pin)); |
1084 | break; |
1085 | case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: |
1086 | val = pctl_readl(pctl, PADS_PU_PD_REG(pin)); |
1087 | val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin)); |
1088 | val |= PADS_PU_PD_HIGHZ << PADS_PU_PD_SHIFT(pin); |
1089 | pctl_writel(pctl, val, PADS_PU_PD_REG(pin)); |
1090 | break; |
1091 | case PIN_CONFIG_BIAS_PULL_UP: |
1092 | val = pctl_readl(pctl, PADS_PU_PD_REG(pin)); |
1093 | val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin)); |
1094 | val |= PADS_PU_PD_UP << PADS_PU_PD_SHIFT(pin); |
1095 | pctl_writel(pctl, val, PADS_PU_PD_REG(pin)); |
1096 | break; |
1097 | case PIN_CONFIG_BIAS_PULL_DOWN: |
1098 | val = pctl_readl(pctl, PADS_PU_PD_REG(pin)); |
1099 | val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin)); |
1100 | val |= PADS_PU_PD_DOWN << PADS_PU_PD_SHIFT(pin); |
1101 | pctl_writel(pctl, val, PADS_PU_PD_REG(pin)); |
1102 | break; |
1103 | case PIN_CONFIG_BIAS_BUS_HOLD: |
1104 | val = pctl_readl(pctl, PADS_PU_PD_REG(pin)); |
1105 | val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin)); |
1106 | val |= PADS_PU_PD_BUS << PADS_PU_PD_SHIFT(pin); |
1107 | pctl_writel(pctl, val, PADS_PU_PD_REG(pin)); |
1108 | break; |
1109 | case PIN_CONFIG_SLEW_RATE: |
1110 | val = pctl_readl(pctl, PADS_SLEW_RATE_REG(pin)); |
1111 | if (arg) |
1112 | val |= PADS_SLEW_RATE_BIT(pin); |
1113 | else |
1114 | val &= ~PADS_SLEW_RATE_BIT(pin); |
1115 | pctl_writel(pctl, val, PADS_SLEW_RATE_REG(pin)); |
1116 | break; |
1117 | case PIN_CONFIG_DRIVE_STRENGTH: |
1118 | val = pctl_readl(pctl, PADS_DRIVE_STRENGTH_REG(pin)); |
1119 | val &= ~(PADS_DRIVE_STRENGTH_MASK << |
1120 | PADS_DRIVE_STRENGTH_SHIFT(pin)); |
1121 | switch (arg) { |
1122 | case 2: |
1123 | drv = PADS_DRIVE_STRENGTH_2MA; |
1124 | break; |
1125 | case 4: |
1126 | drv = PADS_DRIVE_STRENGTH_4MA; |
1127 | break; |
1128 | case 8: |
1129 | drv = PADS_DRIVE_STRENGTH_8MA; |
1130 | break; |
1131 | case 12: |
1132 | drv = PADS_DRIVE_STRENGTH_12MA; |
1133 | break; |
1134 | default: |
1135 | dev_err(pctl->dev, |
1136 | "Drive strength %umA not supported\n" , |
1137 | arg); |
1138 | return -EINVAL; |
1139 | } |
1140 | val |= drv << PADS_DRIVE_STRENGTH_SHIFT(pin); |
1141 | pctl_writel(pctl, val, PADS_DRIVE_STRENGTH_REG(pin)); |
1142 | break; |
1143 | default: |
1144 | dev_err(pctl->dev, "Property %u not supported\n" , |
1145 | param); |
1146 | return -ENOTSUPP; |
1147 | } |
1148 | } |
1149 | |
1150 | return 0; |
1151 | } |
1152 | |
1153 | static const struct pinconf_ops pistachio_pinconf_ops = { |
1154 | .pin_config_get = pistachio_pinconf_get, |
1155 | .pin_config_set = pistachio_pinconf_set, |
1156 | .is_generic = true, |
1157 | }; |
1158 | |
1159 | static struct pinctrl_desc pistachio_pinctrl_desc = { |
1160 | .name = "pistachio-pinctrl" , |
1161 | .pctlops = &pistachio_pinctrl_ops, |
1162 | .pmxops = &pistachio_pinmux_ops, |
1163 | .confops = &pistachio_pinconf_ops, |
1164 | }; |
1165 | |
1166 | static int pistachio_gpio_get_direction(struct gpio_chip *chip, unsigned offset) |
1167 | { |
1168 | struct pistachio_gpio_bank *bank = gpiochip_get_data(gc: chip); |
1169 | |
1170 | if (gpio_readl(bank, GPIO_OUTPUT_EN) & BIT(offset)) |
1171 | return GPIO_LINE_DIRECTION_OUT; |
1172 | |
1173 | return GPIO_LINE_DIRECTION_IN; |
1174 | } |
1175 | |
1176 | static int pistachio_gpio_get(struct gpio_chip *chip, unsigned offset) |
1177 | { |
1178 | struct pistachio_gpio_bank *bank = gpiochip_get_data(gc: chip); |
1179 | u32 reg; |
1180 | |
1181 | if (gpio_readl(bank, GPIO_OUTPUT_EN) & BIT(offset)) |
1182 | reg = GPIO_OUTPUT; |
1183 | else |
1184 | reg = GPIO_INPUT; |
1185 | |
1186 | return !!(gpio_readl(bank, reg) & BIT(offset)); |
1187 | } |
1188 | |
1189 | static void pistachio_gpio_set(struct gpio_chip *chip, unsigned offset, |
1190 | int value) |
1191 | { |
1192 | struct pistachio_gpio_bank *bank = gpiochip_get_data(gc: chip); |
1193 | |
1194 | gpio_mask_writel(bank, GPIO_OUTPUT, bit: offset, val: !!value); |
1195 | } |
1196 | |
1197 | static int pistachio_gpio_direction_input(struct gpio_chip *chip, |
1198 | unsigned offset) |
1199 | { |
1200 | struct pistachio_gpio_bank *bank = gpiochip_get_data(gc: chip); |
1201 | |
1202 | gpio_mask_writel(bank, GPIO_OUTPUT_EN, bit: offset, val: 0); |
1203 | gpio_enable(bank, offset); |
1204 | |
1205 | return 0; |
1206 | } |
1207 | |
1208 | static int pistachio_gpio_direction_output(struct gpio_chip *chip, |
1209 | unsigned offset, int value) |
1210 | { |
1211 | struct pistachio_gpio_bank *bank = gpiochip_get_data(gc: chip); |
1212 | |
1213 | pistachio_gpio_set(chip, offset, value); |
1214 | gpio_mask_writel(bank, GPIO_OUTPUT_EN, bit: offset, val: 1); |
1215 | gpio_enable(bank, offset); |
1216 | |
1217 | return 0; |
1218 | } |
1219 | |
1220 | static void pistachio_gpio_irq_ack(struct irq_data *data) |
1221 | { |
1222 | struct pistachio_gpio_bank *bank = irqd_to_bank(d: data); |
1223 | |
1224 | gpio_mask_writel(bank, GPIO_INTERRUPT_STATUS, bit: data->hwirq, val: 0); |
1225 | } |
1226 | |
1227 | static void pistachio_gpio_irq_mask(struct irq_data *data) |
1228 | { |
1229 | struct pistachio_gpio_bank *bank = irqd_to_bank(d: data); |
1230 | |
1231 | gpio_mask_writel(bank, GPIO_INTERRUPT_EN, bit: data->hwirq, val: 0); |
1232 | gpiochip_disable_irq(gc: &bank->gpio_chip, offset: irqd_to_hwirq(d: data)); |
1233 | } |
1234 | |
1235 | static void pistachio_gpio_irq_unmask(struct irq_data *data) |
1236 | { |
1237 | struct pistachio_gpio_bank *bank = irqd_to_bank(d: data); |
1238 | |
1239 | gpiochip_enable_irq(gc: &bank->gpio_chip, offset: irqd_to_hwirq(d: data)); |
1240 | gpio_mask_writel(bank, GPIO_INTERRUPT_EN, bit: data->hwirq, val: 1); |
1241 | } |
1242 | |
1243 | static unsigned int pistachio_gpio_irq_startup(struct irq_data *data) |
1244 | { |
1245 | struct gpio_chip *chip = irq_data_get_irq_chip_data(d: data); |
1246 | |
1247 | pistachio_gpio_direction_input(chip, offset: data->hwirq); |
1248 | pistachio_gpio_irq_unmask(data); |
1249 | |
1250 | return 0; |
1251 | } |
1252 | |
1253 | static int pistachio_gpio_irq_set_type(struct irq_data *data, unsigned int type) |
1254 | { |
1255 | struct pistachio_gpio_bank *bank = irqd_to_bank(d: data); |
1256 | |
1257 | switch (type & IRQ_TYPE_SENSE_MASK) { |
1258 | case IRQ_TYPE_EDGE_RISING: |
1259 | gpio_mask_writel(bank, GPIO_INPUT_POLARITY, bit: data->hwirq, val: 1); |
1260 | gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, bit: data->hwirq, |
1261 | GPIO_INTERRUPT_TYPE_EDGE); |
1262 | gpio_mask_writel(bank, GPIO_INTERRUPT_EDGE, bit: data->hwirq, |
1263 | GPIO_INTERRUPT_EDGE_SINGLE); |
1264 | break; |
1265 | case IRQ_TYPE_EDGE_FALLING: |
1266 | gpio_mask_writel(bank, GPIO_INPUT_POLARITY, bit: data->hwirq, val: 0); |
1267 | gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, bit: data->hwirq, |
1268 | GPIO_INTERRUPT_TYPE_EDGE); |
1269 | gpio_mask_writel(bank, GPIO_INTERRUPT_EDGE, bit: data->hwirq, |
1270 | GPIO_INTERRUPT_EDGE_SINGLE); |
1271 | break; |
1272 | case IRQ_TYPE_EDGE_BOTH: |
1273 | gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, bit: data->hwirq, |
1274 | GPIO_INTERRUPT_TYPE_EDGE); |
1275 | gpio_mask_writel(bank, GPIO_INTERRUPT_EDGE, bit: data->hwirq, |
1276 | GPIO_INTERRUPT_EDGE_DUAL); |
1277 | break; |
1278 | case IRQ_TYPE_LEVEL_HIGH: |
1279 | gpio_mask_writel(bank, GPIO_INPUT_POLARITY, bit: data->hwirq, val: 1); |
1280 | gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, bit: data->hwirq, |
1281 | GPIO_INTERRUPT_TYPE_LEVEL); |
1282 | break; |
1283 | case IRQ_TYPE_LEVEL_LOW: |
1284 | gpio_mask_writel(bank, GPIO_INPUT_POLARITY, bit: data->hwirq, val: 0); |
1285 | gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, bit: data->hwirq, |
1286 | GPIO_INTERRUPT_TYPE_LEVEL); |
1287 | break; |
1288 | default: |
1289 | return -EINVAL; |
1290 | } |
1291 | |
1292 | if (type & IRQ_TYPE_LEVEL_MASK) |
1293 | irq_set_handler_locked(data, handler: handle_level_irq); |
1294 | else |
1295 | irq_set_handler_locked(data, handler: handle_edge_irq); |
1296 | |
1297 | return 0; |
1298 | } |
1299 | |
1300 | static void pistachio_gpio_irq_handler(struct irq_desc *desc) |
1301 | { |
1302 | struct gpio_chip *gc = irq_desc_get_handler_data(desc); |
1303 | struct pistachio_gpio_bank *bank = gpiochip_get_data(gc); |
1304 | struct irq_chip *chip = irq_desc_get_chip(desc); |
1305 | unsigned long pending; |
1306 | unsigned int pin; |
1307 | |
1308 | chained_irq_enter(chip, desc); |
1309 | pending = gpio_readl(bank, GPIO_INTERRUPT_STATUS) & |
1310 | gpio_readl(bank, GPIO_INTERRUPT_EN); |
1311 | for_each_set_bit(pin, &pending, 16) |
1312 | generic_handle_domain_irq(domain: gc->irq.domain, hwirq: pin); |
1313 | chained_irq_exit(chip, desc); |
1314 | } |
1315 | |
1316 | #define GPIO_BANK(_bank, _pin_base, _npins) \ |
1317 | { \ |
1318 | .instance = (_bank), \ |
1319 | .pin_base = _pin_base, \ |
1320 | .npins = _npins, \ |
1321 | .gpio_chip = { \ |
1322 | .label = "GPIO" #_bank, \ |
1323 | .request = gpiochip_generic_request, \ |
1324 | .free = gpiochip_generic_free, \ |
1325 | .get_direction = pistachio_gpio_get_direction, \ |
1326 | .direction_input = pistachio_gpio_direction_input, \ |
1327 | .direction_output = pistachio_gpio_direction_output, \ |
1328 | .get = pistachio_gpio_get, \ |
1329 | .set = pistachio_gpio_set, \ |
1330 | .base = _pin_base, \ |
1331 | .ngpio = _npins, \ |
1332 | }, \ |
1333 | } |
1334 | |
1335 | static struct pistachio_gpio_bank pistachio_gpio_banks[] = { |
1336 | GPIO_BANK(0, PISTACHIO_PIN_MFIO(0), 16), |
1337 | GPIO_BANK(1, PISTACHIO_PIN_MFIO(16), 16), |
1338 | GPIO_BANK(2, PISTACHIO_PIN_MFIO(32), 16), |
1339 | GPIO_BANK(3, PISTACHIO_PIN_MFIO(48), 16), |
1340 | GPIO_BANK(4, PISTACHIO_PIN_MFIO(64), 16), |
1341 | GPIO_BANK(5, PISTACHIO_PIN_MFIO(80), 10), |
1342 | }; |
1343 | |
1344 | static void pistachio_gpio_irq_print_chip(struct irq_data *data, |
1345 | struct seq_file *p) |
1346 | { |
1347 | struct pistachio_gpio_bank *bank = irqd_to_bank(d: data); |
1348 | |
1349 | seq_printf(m: p, fmt: "GPIO%d" , bank->instance); |
1350 | } |
1351 | |
1352 | static const struct irq_chip pistachio_gpio_irq_chip = { |
1353 | .irq_startup = pistachio_gpio_irq_startup, |
1354 | .irq_ack = pistachio_gpio_irq_ack, |
1355 | .irq_mask = pistachio_gpio_irq_mask, |
1356 | .irq_unmask = pistachio_gpio_irq_unmask, |
1357 | .irq_set_type = pistachio_gpio_irq_set_type, |
1358 | .irq_print_chip = pistachio_gpio_irq_print_chip, |
1359 | .flags = IRQCHIP_IMMUTABLE, |
1360 | GPIOCHIP_IRQ_RESOURCE_HELPERS, |
1361 | }; |
1362 | |
1363 | static int pistachio_gpio_register(struct pistachio_pinctrl *pctl) |
1364 | { |
1365 | struct pistachio_gpio_bank *bank; |
1366 | unsigned int i; |
1367 | int irq, ret = 0; |
1368 | |
1369 | for (i = 0; i < pctl->nbanks; i++) { |
1370 | char child_name[sizeof("gpioXX" )]; |
1371 | struct fwnode_handle *child; |
1372 | struct gpio_irq_chip *girq; |
1373 | |
1374 | snprintf(buf: child_name, size: sizeof(child_name), fmt: "gpio%d" , i); |
1375 | child = device_get_named_child_node(dev: pctl->dev, childname: child_name); |
1376 | if (!child) { |
1377 | dev_err(pctl->dev, "No node for bank %u\n" , i); |
1378 | ret = -ENODEV; |
1379 | goto err; |
1380 | } |
1381 | |
1382 | if (!fwnode_property_present(fwnode: child, propname: "gpio-controller" )) { |
1383 | fwnode_handle_put(fwnode: child); |
1384 | dev_err(pctl->dev, |
1385 | "No gpio-controller property for bank %u\n" , i); |
1386 | ret = -ENODEV; |
1387 | goto err; |
1388 | } |
1389 | |
1390 | ret = fwnode_irq_get(fwnode: child, index: 0); |
1391 | if (ret < 0) { |
1392 | fwnode_handle_put(fwnode: child); |
1393 | dev_err(pctl->dev, "Failed to retrieve IRQ for bank %u\n" , i); |
1394 | goto err; |
1395 | } |
1396 | if (!ret) { |
1397 | fwnode_handle_put(fwnode: child); |
1398 | dev_err(pctl->dev, "No IRQ for bank %u\n" , i); |
1399 | ret = -EINVAL; |
1400 | goto err; |
1401 | } |
1402 | irq = ret; |
1403 | |
1404 | bank = &pctl->gpio_banks[i]; |
1405 | bank->pctl = pctl; |
1406 | bank->base = pctl->base + GPIO_BANK_BASE(i); |
1407 | |
1408 | bank->gpio_chip.parent = pctl->dev; |
1409 | bank->gpio_chip.fwnode = child; |
1410 | |
1411 | girq = &bank->gpio_chip.irq; |
1412 | gpio_irq_chip_set_chip(girq, chip: &pistachio_gpio_irq_chip); |
1413 | girq->parent_handler = pistachio_gpio_irq_handler; |
1414 | girq->num_parents = 1; |
1415 | girq->parents = devm_kcalloc(dev: pctl->dev, n: 1, |
1416 | size: sizeof(*girq->parents), |
1417 | GFP_KERNEL); |
1418 | if (!girq->parents) { |
1419 | ret = -ENOMEM; |
1420 | goto err; |
1421 | } |
1422 | girq->parents[0] = irq; |
1423 | girq->default_type = IRQ_TYPE_NONE; |
1424 | girq->handler = handle_level_irq; |
1425 | |
1426 | ret = gpiochip_add_data(&bank->gpio_chip, bank); |
1427 | if (ret < 0) { |
1428 | dev_err(pctl->dev, "Failed to add GPIO chip %u: %d\n" , |
1429 | i, ret); |
1430 | goto err; |
1431 | } |
1432 | |
1433 | ret = gpiochip_add_pin_range(gc: &bank->gpio_chip, |
1434 | pinctl_name: dev_name(dev: pctl->dev), gpio_offset: 0, |
1435 | pin_offset: bank->pin_base, npins: bank->npins); |
1436 | if (ret < 0) { |
1437 | dev_err(pctl->dev, "Failed to add GPIO range %u: %d\n" , |
1438 | i, ret); |
1439 | gpiochip_remove(gc: &bank->gpio_chip); |
1440 | goto err; |
1441 | } |
1442 | } |
1443 | |
1444 | return 0; |
1445 | err: |
1446 | for (; i > 0; i--) { |
1447 | bank = &pctl->gpio_banks[i - 1]; |
1448 | gpiochip_remove(gc: &bank->gpio_chip); |
1449 | } |
1450 | return ret; |
1451 | } |
1452 | |
1453 | static const struct of_device_id pistachio_pinctrl_of_match[] = { |
1454 | { .compatible = "img,pistachio-system-pinctrl" , }, |
1455 | { }, |
1456 | }; |
1457 | |
1458 | static int pistachio_pinctrl_probe(struct platform_device *pdev) |
1459 | { |
1460 | struct pistachio_pinctrl *pctl; |
1461 | |
1462 | pctl = devm_kzalloc(dev: &pdev->dev, size: sizeof(*pctl), GFP_KERNEL); |
1463 | if (!pctl) |
1464 | return -ENOMEM; |
1465 | pctl->dev = &pdev->dev; |
1466 | dev_set_drvdata(dev: &pdev->dev, data: pctl); |
1467 | |
1468 | pctl->base = devm_platform_ioremap_resource(pdev, index: 0); |
1469 | if (IS_ERR(ptr: pctl->base)) |
1470 | return PTR_ERR(ptr: pctl->base); |
1471 | |
1472 | pctl->pins = pistachio_pins; |
1473 | pctl->npins = ARRAY_SIZE(pistachio_pins); |
1474 | pctl->functions = pistachio_functions; |
1475 | pctl->nfunctions = ARRAY_SIZE(pistachio_functions); |
1476 | pctl->groups = pistachio_groups; |
1477 | pctl->ngroups = ARRAY_SIZE(pistachio_groups); |
1478 | pctl->gpio_banks = pistachio_gpio_banks; |
1479 | pctl->nbanks = ARRAY_SIZE(pistachio_gpio_banks); |
1480 | |
1481 | pistachio_pinctrl_desc.pins = pctl->pins; |
1482 | pistachio_pinctrl_desc.npins = pctl->npins; |
1483 | |
1484 | pctl->pctldev = devm_pinctrl_register(dev: &pdev->dev, pctldesc: &pistachio_pinctrl_desc, |
1485 | driver_data: pctl); |
1486 | if (IS_ERR(ptr: pctl->pctldev)) { |
1487 | dev_err(&pdev->dev, "Failed to register pinctrl device\n" ); |
1488 | return PTR_ERR(ptr: pctl->pctldev); |
1489 | } |
1490 | |
1491 | return pistachio_gpio_register(pctl); |
1492 | } |
1493 | |
1494 | static struct platform_driver pistachio_pinctrl_driver = { |
1495 | .driver = { |
1496 | .name = "pistachio-pinctrl" , |
1497 | .of_match_table = pistachio_pinctrl_of_match, |
1498 | .suppress_bind_attrs = true, |
1499 | }, |
1500 | .probe = pistachio_pinctrl_probe, |
1501 | }; |
1502 | |
1503 | static int __init pistachio_pinctrl_register(void) |
1504 | { |
1505 | return platform_driver_register(&pistachio_pinctrl_driver); |
1506 | } |
1507 | arch_initcall(pistachio_pinctrl_register); |
1508 | |