1	/*
2	* Generic device tree based pinctrl driver for one register per pin
3	* type pinmux controllers
4	*
5	* Copyright (C) 2012 Texas Instruments, Inc.
6	*
7	* This file is licensed under the terms of the GNU General Public
8	* License version 2. This program is licensed "as is" without any
9	* warranty of any kind, whether express or implied.
10	*/
11
12	#include <linux/init.h>
13	#include <linux/module.h>
14	#include <linux/io.h>
15	#include <linux/platform_device.h>
16	#include <linux/slab.h>
17	#include <linux/err.h>
18	#include <linux/list.h>
19	#include <linux/interrupt.h>
20	#include <linux/irqchip/chained_irq.h>
21	#include <linux/of.h>
22	#include <linux/of_irq.h>
23	#include <linux/seq_file.h>
24
25	#include <linux/pinctrl/pinconf-generic.h>
26	#include <linux/pinctrl/pinconf.h>
27	#include <linux/pinctrl/pinctrl.h>
28	#include <linux/pinctrl/pinmux.h>
29
30	#include <linux/platform_data/pinctrl-single.h>
31
32	#include "core.h"
33	#include "devicetree.h"
34	#include "pinconf.h"
35	#include "pinmux.h"
36
37	#define DRIVER_NAME "pinctrl-single"
38	#define PCS_OFF_DISABLED ~0U
39
40	/**
41	* struct pcs_func_vals - mux function register offset and value pair
42	* @reg: register virtual address
43	* @val: register value
44	* @mask: mask
45	*/
46	struct pcs_func_vals {
47	void __iomem *reg;
48	unsigned val;
49	unsigned mask;
50	};
51
52	/**
53	* struct pcs_conf_vals - pinconf parameter, pinconf register offset
54	* and value, enable, disable, mask
55	* @param: config parameter
56	* @val: user input bits in the pinconf register
57	* @enable: enable bits in the pinconf register
58	* @disable: disable bits in the pinconf register
59	* @mask: mask bits in the register value
60	*/
61	struct pcs_conf_vals {
62	enum pin_config_param param;
63	unsigned val;
64	unsigned enable;
65	unsigned disable;
66	unsigned mask;
67	};
68
69	/**
70	* struct pcs_conf_type - pinconf property name, pinconf param pair
71	* @name: property name in DTS file
72	* @param: config parameter
73	*/
74	struct pcs_conf_type {
75	const char *name;
76	enum pin_config_param param;
77	};
78
79	/**
80	* struct pcs_function - pinctrl function
81	* @name: pinctrl function name
82	* @vals: register and vals array
83	* @nvals: number of entries in vals array
84	* @pgnames: array of pingroup names the function uses
85	* @npgnames: number of pingroup names the function uses
86	* @conf: array of pin configurations
87	* @nconfs: number of pin configurations available
88	* @node: list node
89	*/
90	struct pcs_function {
91	const char *name;
92	struct pcs_func_vals *vals;
93	unsigned nvals;
94	const char **pgnames;
95	int npgnames;
96	struct pcs_conf_vals *conf;
97	int nconfs;
98	struct list_head node;
99	};
100
101	/**
102	* struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function
103	* @offset: offset base of pins
104	* @npins: number pins with the same mux value of gpio function
105	* @gpiofunc: mux value of gpio function
106	* @node: list node
107	*/
108	struct pcs_gpiofunc_range {
109	unsigned offset;
110	unsigned npins;
111	unsigned gpiofunc;
112	struct list_head node;
113	};
114
115	/**
116	* struct pcs_data - wrapper for data needed by pinctrl framework
117	* @pa: pindesc array
118	* @cur: index to current element
119	*
120	* REVISIT: We should be able to drop this eventually by adding
121	* support for registering pins individually in the pinctrl
122	* framework for those drivers that don't need a static array.
123	*/
124	struct pcs_data {
125	struct pinctrl_pin_desc *pa;
126	int cur;
127	};
128
129	/**
130	* struct pcs_soc_data - SoC specific settings
131	* @flags: initial SoC specific PCS_FEAT_xxx values
132	* @irq: optional interrupt for the controller
133	* @irq_enable_mask: optional SoC specific interrupt enable mask
134	* @irq_status_mask: optional SoC specific interrupt status mask
135	* @rearm: optional SoC specific wake-up rearm function
136	*/
137	struct pcs_soc_data {
138	unsigned flags;
139	int irq;
140	unsigned irq_enable_mask;
141	unsigned irq_status_mask;
142	void (*rearm)(void);
143	};
144
145	/**
146	* struct pcs_device - pinctrl device instance
147	* @res: resources
148	* @base: virtual address of the controller
149	* @saved_vals: saved values for the controller
150	* @size: size of the ioremapped area
151	* @dev: device entry
152	* @np: device tree node
153	* @pctl: pin controller device
154	* @flags: mask of PCS_FEAT_xxx values
155	* @missing_nr_pinctrl_cells: for legacy binding, may go away
156	* @socdata: soc specific data
157	* @lock: spinlock for register access
158	* @mutex: mutex protecting the lists
159	* @width: bits per mux register
160	* @fmask: function register mask
161	* @fshift: function register shift
162	* @foff: value to turn mux off
163	* @fmax: max number of functions in fmask
164	* @bits_per_mux: number of bits per mux
165	* @bits_per_pin: number of bits per pin
166	* @pins: physical pins on the SoC
167	* @gpiofuncs: list of gpio functions
168	* @irqs: list of interrupt registers
169	* @chip: chip container for this instance
170	* @domain: IRQ domain for this instance
171	* @desc: pin controller descriptor
172	* @read: register read function to use
173	* @write: register write function to use
174	*/
175	struct pcs_device {
176	struct resource *res;
177	void __iomem *base;
178	void *saved_vals;
179	unsigned size;
180	struct device *dev;
181	struct device_node *np;
182	struct pinctrl_dev *pctl;
183	unsigned flags;
184	#define PCS_CONTEXT_LOSS_OFF (1 << 3)
185	#define PCS_QUIRK_SHARED_IRQ (1 << 2)
186	#define PCS_FEAT_IRQ (1 << 1)
187	#define PCS_FEAT_PINCONF (1 << 0)
188	struct property *missing_nr_pinctrl_cells;
189	struct pcs_soc_data socdata;
190	raw_spinlock_t lock;
191	struct mutex mutex;
192	unsigned width;
193	unsigned fmask;
194	unsigned fshift;
195	unsigned foff;
196	unsigned fmax;
197	bool bits_per_mux;
198	unsigned bits_per_pin;
199	struct pcs_data pins;
200	struct list_head gpiofuncs;
201	struct list_head irqs;
202	struct irq_chip chip;
203	struct irq_domain *domain;
204	struct pinctrl_desc desc;
205	unsigned (*read)(void __iomem *reg);
206	void (*write)(unsigned val, void __iomem *reg);
207	};
208
209	#define PCS_QUIRK_HAS_SHARED_IRQ (pcs->flags & PCS_QUIRK_SHARED_IRQ)
210	#define PCS_HAS_IRQ (pcs->flags & PCS_FEAT_IRQ)
211	#define PCS_HAS_PINCONF (pcs->flags & PCS_FEAT_PINCONF)
212
213	static int pcs_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
214	unsigned long *config);
215	static int pcs_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
216	unsigned long *configs, unsigned num_configs);
217
218	static enum pin_config_param pcs_bias[] = {
219	PIN_CONFIG_BIAS_PULL_DOWN,
220	PIN_CONFIG_BIAS_PULL_UP,
221	};
222
223	/*
224	* This lock class tells lockdep that irqchip core that this single
225	* pinctrl can be in a different category than its parents, so it won't
226	* report false recursion.
227	*/
228	static struct lock_class_key pcs_lock_class;
229
230	/* Class for the IRQ request mutex */
231	static struct lock_class_key pcs_request_class;
232
233	/*
234	* REVISIT: Reads and writes could eventually use regmap or something
235	* generic. But at least on omaps, some mux registers are performance
236	* critical as they may need to be remuxed every time before and after
237	* idle. Adding tests for register access width for every read and
238	* write like regmap is doing is not desired, and caching the registers
239	* does not help in this case.
240	*/
241
242	static unsigned int pcs_readb(void __iomem *reg)
243	{
244	return readb(addr: reg);
245	}
246
247	static unsigned int pcs_readw(void __iomem *reg)
248	{
249	return readw(addr: reg);
250	}
251
252	static unsigned int pcs_readl(void __iomem *reg)
253	{
254	return readl(addr: reg);
255	}
256
257	static void pcs_writeb(unsigned int val, void __iomem *reg)
258	{
259	writeb(val, addr: reg);
260	}
261
262	static void pcs_writew(unsigned int val, void __iomem *reg)
263	{
264	writew(val, addr: reg);
265	}
266
267	static void pcs_writel(unsigned int val, void __iomem *reg)
268	{
269	writel(val, addr: reg);
270	}
271
272	static unsigned int pcs_pin_reg_offset_get(struct pcs_device *pcs,
273	unsigned int pin)
274	{
275	unsigned int mux_bytes = pcs->width / BITS_PER_BYTE;
276
277	if (pcs->bits_per_mux) {
278	unsigned int pin_offset_bytes;
279
280	pin_offset_bytes = (pcs->bits_per_pin * pin) / BITS_PER_BYTE;
281	return (pin_offset_bytes / mux_bytes) * mux_bytes;
282	}
283
284	return pin * mux_bytes;
285	}
286
287	static unsigned int pcs_pin_shift_reg_get(struct pcs_device *pcs,
288	unsigned int pin)
289	{
290	return (pin % (pcs->width / pcs->bits_per_pin)) * pcs->bits_per_pin;
291	}
292
293	static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev,
294	struct seq_file *s,
295	unsigned pin)
296	{
297	struct pcs_device *pcs;
298	unsigned int val;
299	unsigned long offset;
300	size_t pa;
301
302	pcs = pinctrl_dev_get_drvdata(pctldev);
303
304	offset = pcs_pin_reg_offset_get(pcs, pin);
305	val = pcs->read(pcs->base + offset);
306
307	if (pcs->bits_per_mux)
308	val &= pcs->fmask << pcs_pin_shift_reg_get(pcs, pin);
309
310	pa = pcs->res->start + offset;
311
312	seq_printf(m: s, fmt: "%zx %08x %s ", pa, val, DRIVER_NAME);
313	}
314
315	static void pcs_dt_free_map(struct pinctrl_dev *pctldev,
316	struct pinctrl_map *map, unsigned num_maps)
317	{
318	struct pcs_device *pcs;
319
320	pcs = pinctrl_dev_get_drvdata(pctldev);
321	devm_kfree(dev: pcs->dev, p: map);
322	}
323
324	static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
325	struct device_node *np_config,
326	struct pinctrl_map **map, unsigned *num_maps);
327
328	static const struct pinctrl_ops pcs_pinctrl_ops = {
329	.get_groups_count = pinctrl_generic_get_group_count,
330	.get_group_name = pinctrl_generic_get_group_name,
331	.get_group_pins = pinctrl_generic_get_group_pins,
332	.pin_dbg_show = pcs_pin_dbg_show,
333	.dt_node_to_map = pcs_dt_node_to_map,
334	.dt_free_map = pcs_dt_free_map,
335	};
336
337	static int pcs_get_function(struct pinctrl_dev *pctldev, unsigned pin,
338	struct pcs_function **func)
339	{
340	struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
341	struct pin_desc *pdesc = pin_desc_get(pctldev, pin);
342	const struct pinctrl_setting_mux *setting;
343	struct function_desc *function;
344	unsigned fselector;
345
346	/* If pin is not described in DTS & enabled, mux_setting is NULL. */
347	setting = pdesc->mux_setting;
348	if (!setting)
349	return -ENOTSUPP;
350	fselector = setting->func;
351	function = pinmux_generic_get_function(pctldev, selector: fselector);
352	*func = function->data;
353	if (!(*func)) {
354	dev_err(pcs->dev, "%s could not find function%i\n",
355	__func__, fselector);
356	return -ENOTSUPP;
357	}
358	return 0;
359	}
360
361	static int pcs_set_mux(struct pinctrl_dev *pctldev, unsigned fselector,
362	unsigned group)
363	{
364	struct pcs_device *pcs;
365	struct function_desc *function;
366	struct pcs_function *func;
367	int i;
368
369	pcs = pinctrl_dev_get_drvdata(pctldev);
370	/* If function mask is null, needn't enable it. */
371	if (!pcs->fmask)
372	return 0;
373	function = pinmux_generic_get_function(pctldev, selector: fselector);
374	if (!function)
375	return -EINVAL;
376	func = function->data;
377	if (!func)
378	return -EINVAL;
379
380	dev_dbg(pcs->dev, "enabling %s function%i\n",
381	func->name, fselector);
382
383	for (i = 0; i < func->nvals; i++) {
384	struct pcs_func_vals *vals;
385	unsigned long flags;
386	unsigned val, mask;
387
388	vals = &func->vals[i];
389	raw_spin_lock_irqsave(&pcs->lock, flags);
390	val = pcs->read(vals->reg);
391
392	if (pcs->bits_per_mux)
393	mask = vals->mask;
394	else
395	mask = pcs->fmask;
396
397	val &= ~mask;
398	val |= (vals->val & mask);
399	pcs->write(val, vals->reg);
400	raw_spin_unlock_irqrestore(&pcs->lock, flags);
401	}
402
403	return 0;
404	}
405
406	static int pcs_request_gpio(struct pinctrl_dev *pctldev,
407	struct pinctrl_gpio_range *range, unsigned pin)
408	{
409	struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
410	struct pcs_gpiofunc_range *frange = NULL;
411	struct list_head *pos, *tmp;
412	unsigned data;
413
414	/* If function mask is null, return directly. */
415	if (!pcs->fmask)
416	return -ENOTSUPP;
417
418	list_for_each_safe(pos, tmp, &pcs->gpiofuncs) {
419	u32 offset;
420
421	frange = list_entry(pos, struct pcs_gpiofunc_range, node);
422	if (pin >= frange->offset + frange->npins
423	|| pin < frange->offset)
424	continue;
425
426	offset = pcs_pin_reg_offset_get(pcs, pin);
427
428	if (pcs->bits_per_mux) {
429	int pin_shift = pcs_pin_shift_reg_get(pcs, pin);
430
431	data = pcs->read(pcs->base + offset);
432	data &= ~(pcs->fmask << pin_shift);
433	data |= frange->gpiofunc << pin_shift;
434	pcs->write(data, pcs->base + offset);
435	} else {
436	data = pcs->read(pcs->base + offset);
437	data &= ~pcs->fmask;
438	data |= frange->gpiofunc;
439	pcs->write(data, pcs->base + offset);
440	}
441	break;
442	}
443	return 0;
444	}
445
446	static const struct pinmux_ops pcs_pinmux_ops = {
447	.get_functions_count = pinmux_generic_get_function_count,
448	.get_function_name = pinmux_generic_get_function_name,
449	.get_function_groups = pinmux_generic_get_function_groups,
450	.set_mux = pcs_set_mux,
451	.gpio_request_enable = pcs_request_gpio,
452	};
453
454	/* Clear BIAS value */
455	static void pcs_pinconf_clear_bias(struct pinctrl_dev *pctldev, unsigned pin)
456	{
457	unsigned long config;
458	int i;
459	for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
460	config = pinconf_to_config_packed(param: pcs_bias[i], argument: 0);
461	pcs_pinconf_set(pctldev, pin, configs: &config, num_configs: 1);
462	}
463	}
464
465	/*
466	* Check whether PIN_CONFIG_BIAS_DISABLE is valid.
467	* It's depend on that PULL_DOWN & PULL_UP configs are all invalid.
468	*/
469	static bool pcs_pinconf_bias_disable(struct pinctrl_dev *pctldev, unsigned pin)
470	{
471	unsigned long config;
472	int i;
473
474	for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
475	config = pinconf_to_config_packed(param: pcs_bias[i], argument: 0);
476	if (!pcs_pinconf_get(pctldev, pin, config: &config))
477	goto out;
478	}
479	return true;
480	out:
481	return false;
482	}
483
484	static int pcs_pinconf_get(struct pinctrl_dev *pctldev,
485	unsigned pin, unsigned long *config)
486	{
487	struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
488	struct pcs_function *func;
489	enum pin_config_param param;
490	unsigned offset = 0, data = 0, i, j, ret;
491
492	ret = pcs_get_function(pctldev, pin, func: &func);
493	if (ret)
494	return ret;
495
496	for (i = 0; i < func->nconfs; i++) {
497	param = pinconf_to_config_param(config: *config);
498	if (param == PIN_CONFIG_BIAS_DISABLE) {
499	if (pcs_pinconf_bias_disable(pctldev, pin)) {
500	*config = 0;
501	return 0;
502	} else {
503	return -ENOTSUPP;
504	}
505	} else if (param != func->conf[i].param) {
506	continue;
507	}
508
509	offset = pin * (pcs->width / BITS_PER_BYTE);
510	data = pcs->read(pcs->base + offset) & func->conf[i].mask;
511	switch (func->conf[i].param) {
512	/* 4 parameters */
513	case PIN_CONFIG_BIAS_PULL_DOWN:
514	case PIN_CONFIG_BIAS_PULL_UP:
515	case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
516	if ((data != func->conf[i].enable) ||
517	(data == func->conf[i].disable))
518	return -ENOTSUPP;
519	*config = 0;
520	break;
521	/* 2 parameters */
522	case PIN_CONFIG_INPUT_SCHMITT:
523	for (j = 0; j < func->nconfs; j++) {
524	switch (func->conf[j].param) {
525	case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
526	if (data != func->conf[j].enable)
527	return -ENOTSUPP;
528	break;
529	default:
530	break;
531	}
532	}
533	*config = data;
534	break;
535	case PIN_CONFIG_DRIVE_STRENGTH:
536	case PIN_CONFIG_SLEW_RATE:
537	case PIN_CONFIG_MODE_LOW_POWER:
538	case PIN_CONFIG_INPUT_ENABLE:
539	default:
540	*config = data;
541	break;
542	}
543	return 0;
544	}
545	return -ENOTSUPP;
546	}
547
548	static int pcs_pinconf_set(struct pinctrl_dev *pctldev,
549	unsigned pin, unsigned long *configs,
550	unsigned num_configs)
551	{
552	struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
553	struct pcs_function *func;
554	unsigned offset = 0, shift = 0, i, data, ret;
555	u32 arg;
556	int j;
557
558	ret = pcs_get_function(pctldev, pin, func: &func);
559	if (ret)
560	return ret;
561
562	for (j = 0; j < num_configs; j++) {
563	for (i = 0; i < func->nconfs; i++) {
564	if (pinconf_to_config_param(config: configs[j])
565	!= func->conf[i].param)
566	continue;
567
568	offset = pin * (pcs->width / BITS_PER_BYTE);
569	data = pcs->read(pcs->base + offset);
570	arg = pinconf_to_config_argument(config: configs[j]);
571	switch (func->conf[i].param) {
572	/* 2 parameters */
573	case PIN_CONFIG_INPUT_SCHMITT:
574	case PIN_CONFIG_DRIVE_STRENGTH:
575	case PIN_CONFIG_SLEW_RATE:
576	case PIN_CONFIG_MODE_LOW_POWER:
577	case PIN_CONFIG_INPUT_ENABLE:
578	shift = ffs(func->conf[i].mask) - 1;
579	data &= ~func->conf[i].mask;
580	data |= (arg << shift) & func->conf[i].mask;
581	break;
582	/* 4 parameters */
583	case PIN_CONFIG_BIAS_DISABLE:
584	pcs_pinconf_clear_bias(pctldev, pin);
585	break;
586	case PIN_CONFIG_BIAS_PULL_DOWN:
587	case PIN_CONFIG_BIAS_PULL_UP:
588	if (arg)
589	pcs_pinconf_clear_bias(pctldev, pin);
590	fallthrough;
591	case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
592	data &= ~func->conf[i].mask;
593	if (arg)
594	data |= func->conf[i].enable;
595	else
596	data |= func->conf[i].disable;
597	break;
598	default:
599	return -ENOTSUPP;
600	}
601	pcs->write(data, pcs->base + offset);
602
603	break;
604	}
605	if (i >= func->nconfs)
606	return -ENOTSUPP;
607	} /* for each config */
608
609	return 0;
610	}
611
612	static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev,
613	unsigned group, unsigned long *config)
614	{
615	const unsigned *pins;
616	unsigned npins, old = 0;
617	int i, ret;
618
619	ret = pinctrl_generic_get_group_pins(pctldev, group_selector: group, pins: &pins, npins: &npins);
620	if (ret)
621	return ret;
622	for (i = 0; i < npins; i++) {
623	if (pcs_pinconf_get(pctldev, pin: pins[i], config))
624	return -ENOTSUPP;
625	/* configs do not match between two pins */
626	if (i && (old != *config))
627	return -ENOTSUPP;
628	old = *config;
629	}
630	return 0;
631	}
632
633	static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev,
634	unsigned group, unsigned long *configs,
635	unsigned num_configs)
636	{
637	const unsigned *pins;
638	unsigned npins;
639	int i, ret;
640
641	ret = pinctrl_generic_get_group_pins(pctldev, group_selector: group, pins: &pins, npins: &npins);
642	if (ret)
643	return ret;
644	for (i = 0; i < npins; i++) {
645	if (pcs_pinconf_set(pctldev, pin: pins[i], configs, num_configs))
646	return -ENOTSUPP;
647	}
648	return 0;
649	}
650
651	static void pcs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
652	struct seq_file *s, unsigned pin)
653	{
654	}
655
656	static void pcs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
657	struct seq_file *s, unsigned selector)
658	{
659	}
660
661	static void pcs_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
662	struct seq_file *s,
663	unsigned long config)
664	{
665	pinconf_generic_dump_config(pctldev, s, config);
666	}
667
668	static const struct pinconf_ops pcs_pinconf_ops = {
669	.pin_config_get = pcs_pinconf_get,
670	.pin_config_set = pcs_pinconf_set,
671	.pin_config_group_get = pcs_pinconf_group_get,
672	.pin_config_group_set = pcs_pinconf_group_set,
673	.pin_config_dbg_show = pcs_pinconf_dbg_show,
674	.pin_config_group_dbg_show = pcs_pinconf_group_dbg_show,
675	.pin_config_config_dbg_show = pcs_pinconf_config_dbg_show,
676	.is_generic = true,
677	};
678
679	/**
680	* pcs_add_pin() - add a pin to the static per controller pin array
681	* @pcs: pcs driver instance
682	* @offset: register offset from base
683	*/
684	static int pcs_add_pin(struct pcs_device *pcs, unsigned int offset)
685	{
686	struct pcs_soc_data *pcs_soc = &pcs->socdata;
687	struct pinctrl_pin_desc *pin;
688	int i;
689
690	i = pcs->pins.cur;
691	if (i >= pcs->desc.npins) {
692	dev_err(pcs->dev, "too many pins, max %i\n",
693	pcs->desc.npins);
694	return -ENOMEM;
695	}
696
697	if (pcs_soc->irq_enable_mask) {
698	unsigned val;
699
700	val = pcs->read(pcs->base + offset);
701	if (val & pcs_soc->irq_enable_mask) {
702	dev_dbg(pcs->dev, "irq enabled at boot for pin at %lx (%x), clearing\n",
703	(unsigned long)pcs->res->start + offset, val);
704	val &= ~pcs_soc->irq_enable_mask;
705	pcs->write(val, pcs->base + offset);
706	}
707	}
708
709	pin = &pcs->pins.pa[i];
710	pin->number = i;
711	pcs->pins.cur++;
712
713	return i;
714	}
715
716	/**
717	* pcs_allocate_pin_table() - adds all the pins for the pinctrl driver
718	* @pcs: pcs driver instance
719	*
720	* In case of errors, resources are freed in pcs_free_resources.
721	*
722	* If your hardware needs holes in the address space, then just set
723	* up multiple driver instances.
724	*/
725	static int pcs_allocate_pin_table(struct pcs_device *pcs)
726	{
727	int mux_bytes, nr_pins, i;
728
729	mux_bytes = pcs->width / BITS_PER_BYTE;
730
731	if (pcs->bits_per_mux && pcs->fmask) {
732	pcs->bits_per_pin = fls(x: pcs->fmask);
733	nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin;
734	} else {
735	nr_pins = pcs->size / mux_bytes;
736	}
737
738	dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins);
739	pcs->pins.pa = devm_kcalloc(dev: pcs->dev,
740	n: nr_pins, size: sizeof(*pcs->pins.pa),
741	GFP_KERNEL);
742	if (!pcs->pins.pa)
743	return -ENOMEM;
744
745	pcs->desc.pins = pcs->pins.pa;
746	pcs->desc.npins = nr_pins;
747
748	for (i = 0; i < pcs->desc.npins; i++) {
749	unsigned offset;
750	int res;
751
752	offset = pcs_pin_reg_offset_get(pcs, pin: i);
753	res = pcs_add_pin(pcs, offset);
754	if (res < 0) {
755	dev_err(pcs->dev, "error adding pins: %i\n", res);
756	return res;
757	}
758	}
759
760	return 0;
761	}
762
763	/**
764	* pcs_add_function() - adds a new function to the function list
765	* @pcs: pcs driver instance
766	* @fcn: new function allocated
767	* @name: name of the function
768	* @vals: array of mux register value pairs used by the function
769	* @nvals: number of mux register value pairs
770	* @pgnames: array of pingroup names for the function
771	* @npgnames: number of pingroup names
772	*
773	* Caller must take care of locking.
774	*/
775	static int pcs_add_function(struct pcs_device *pcs,
776	struct pcs_function **fcn,
777	const char *name,
778	struct pcs_func_vals *vals,
779	unsigned int nvals,
780	const char **pgnames,
781	unsigned int npgnames)
782	{
783	struct pcs_function *function;
784	int selector;
785
786	function = devm_kzalloc(dev: pcs->dev, size: sizeof(*function), GFP_KERNEL);
787	if (!function)
788	return -ENOMEM;
789
790	function->vals = vals;
791	function->nvals = nvals;
792	function->name = name;
793
794	selector = pinmux_generic_add_function(pctldev: pcs->pctl, name,
795	groups: pgnames, num_groups: npgnames,
796	data: function);
797	if (selector < 0) {
798	devm_kfree(dev: pcs->dev, p: function);
799	*fcn = NULL;
800	} else {
801	*fcn = function;
802	}
803
804	return selector;
805	}
806
807	/**
808	* pcs_get_pin_by_offset() - get a pin index based on the register offset
809	* @pcs: pcs driver instance
810	* @offset: register offset from the base
811	*
812	* Note that this is OK as long as the pins are in a static array.
813	*/
814	static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset)
815	{
816	unsigned index;
817
818	if (offset >= pcs->size) {
819	dev_err(pcs->dev, "mux offset out of range: 0x%x (0x%x)\n",
820	offset, pcs->size);
821	return -EINVAL;
822	}
823
824	if (pcs->bits_per_mux)
825	index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin;
826	else
827	index = offset / (pcs->width / BITS_PER_BYTE);
828
829	return index;
830	}
831
832	/*
833	* check whether data matches enable bits or disable bits
834	* Return value: 1 for matching enable bits, 0 for matching disable bits,
835	* and negative value for matching failure.
836	*/
837	static int pcs_config_match(unsigned data, unsigned enable, unsigned disable)
838	{
839	int ret = -EINVAL;
840
841	if (data == enable)
842	ret = 1;
843	else if (data == disable)
844	ret = 0;
845	return ret;
846	}
847
848	static void add_config(struct pcs_conf_vals **conf, enum pin_config_param param,
849	unsigned value, unsigned enable, unsigned disable,
850	unsigned mask)
851	{
852	(*conf)->param = param;
853	(*conf)->val = value;
854	(*conf)->enable = enable;
855	(*conf)->disable = disable;
856	(*conf)->mask = mask;
857	(*conf)++;
858	}
859
860	static void add_setting(unsigned long **setting, enum pin_config_param param,
861	unsigned arg)
862	{
863	**setting = pinconf_to_config_packed(param, argument: arg);
864	(*setting)++;
865	}
866
867	/* add pinconf setting with 2 parameters */
868	static void pcs_add_conf2(struct pcs_device *pcs, struct device_node *np,
869	const char *name, enum pin_config_param param,
870	struct pcs_conf_vals **conf, unsigned long **settings)
871	{
872	unsigned value[2], shift;
873	int ret;
874
875	ret = of_property_read_u32_array(np, propname: name, out_values: value, sz: 2);
876	if (ret)
877	return;
878	/* set value & mask */
879	value[0] &= value[1];
880	shift = ffs(value[1]) - 1;
881	/* skip enable & disable */
882	add_config(conf, param, value: value[0], enable: 0, disable: 0, mask: value[1]);
883	add_setting(setting: settings, param, arg: value[0] >> shift);
884	}
885
886	/* add pinconf setting with 4 parameters */
887	static void pcs_add_conf4(struct pcs_device *pcs, struct device_node *np,
888	const char *name, enum pin_config_param param,
889	struct pcs_conf_vals **conf, unsigned long **settings)
890	{
891	unsigned value[4];
892	int ret;
893
894	/* value to set, enable, disable, mask */
895	ret = of_property_read_u32_array(np, propname: name, out_values: value, sz: 4);
896	if (ret)
897	return;
898	if (!value[3]) {
899	dev_err(pcs->dev, "mask field of the property can't be 0\n");
900	return;
901	}
902	value[0] &= value[3];
903	value[1] &= value[3];
904	value[2] &= value[3];
905	ret = pcs_config_match(data: value[0], enable: value[1], disable: value[2]);
906	if (ret < 0)
907	dev_dbg(pcs->dev, "failed to match enable or disable bits\n");
908	add_config(conf, param, value: value[0], enable: value[1], disable: value[2], mask: value[3]);
909	add_setting(setting: settings, param, arg: ret);
910	}
911
912	static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np,
913	struct pcs_function *func,
914	struct pinctrl_map **map)
915
916	{
917	struct pinctrl_map *m = *map;
918	int i = 0, nconfs = 0;
919	unsigned long *settings = NULL, *s = NULL;
920	struct pcs_conf_vals *conf = NULL;
921	static const struct pcs_conf_type prop2[] = {
922	{ "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, },
923	{ "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, },
924	{ "pinctrl-single,input-enable", PIN_CONFIG_INPUT_ENABLE, },
925	{ "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, },
926	{ "pinctrl-single,low-power-mode", PIN_CONFIG_MODE_LOW_POWER, },
927	};
928	static const struct pcs_conf_type prop4[] = {
929	{ "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, },
930	{ "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, },
931	{ "pinctrl-single,input-schmitt-enable",
932	PIN_CONFIG_INPUT_SCHMITT_ENABLE, },
933	};
934
935	/* If pinconf isn't supported, don't parse properties in below. */
936	if (!PCS_HAS_PINCONF)
937	return -ENOTSUPP;
938
939	/* cacluate how much properties are supported in current node */
940	for (i = 0; i < ARRAY_SIZE(prop2); i++) {
941	if (of_property_present(np, propname: prop2[i].name))
942	nconfs++;
943	}
944	for (i = 0; i < ARRAY_SIZE(prop4); i++) {
945	if (of_property_present(np, propname: prop4[i].name))
946	nconfs++;
947	}
948	if (!nconfs)
949	return -ENOTSUPP;
950
951	func->conf = devm_kcalloc(dev: pcs->dev,
952	n: nconfs, size: sizeof(struct pcs_conf_vals),
953	GFP_KERNEL);
954	if (!func->conf)
955	return -ENOMEM;
956	func->nconfs = nconfs;
957	conf = &(func->conf[0]);
958	m++;
959	settings = devm_kcalloc(dev: pcs->dev, n: nconfs, size: sizeof(unsigned long),
960	GFP_KERNEL);
961	if (!settings)
962	return -ENOMEM;
963	s = &settings[0];
964
965	for (i = 0; i < ARRAY_SIZE(prop2); i++)
966	pcs_add_conf2(pcs, np, name: prop2[i].name, param: prop2[i].param,
967	conf: &conf, settings: &s);
968	for (i = 0; i < ARRAY_SIZE(prop4); i++)
969	pcs_add_conf4(pcs, np, name: prop4[i].name, param: prop4[i].param,
970	conf: &conf, settings: &s);
971	m->type = PIN_MAP_TYPE_CONFIGS_GROUP;
972	m->data.configs.group_or_pin = np->name;
973	m->data.configs.configs = settings;
974	m->data.configs.num_configs = nconfs;
975	return 0;
976	}
977
978	/**
979	* pcs_parse_one_pinctrl_entry() - parses a device tree mux entry
980	* @pcs: pinctrl driver instance
981	* @np: device node of the mux entry
982	* @map: map entry
983	* @num_maps: number of map
984	* @pgnames: pingroup names
985	*
986	* Note that this binding currently supports only sets of one register + value.
987	*
988	* Also note that this driver tries to avoid understanding pin and function
989	* names because of the extra bloat they would cause especially in the case of
990	* a large number of pins. This driver just sets what is specified for the board
991	* in the .dts file. Further user space debugging tools can be developed to
992	* decipher the pin and function names using debugfs.
993	*
994	* If you are concerned about the boot time, set up the static pins in
995	* the bootloader, and only set up selected pins as device tree entries.
996	*/
997	static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
998	struct device_node *np,
999	struct pinctrl_map **map,
1000	unsigned *num_maps,
1001	const char **pgnames)
1002	{
1003	const char *name = "pinctrl-single,pins";
1004	struct pcs_func_vals *vals;
1005	int rows, *pins, found = 0, res = -ENOMEM, i, fsel, gsel;
1006	struct pcs_function *function = NULL;
1007
1008	rows = pinctrl_count_index_with_args(np, list_name: name);
1009	if (rows <= 0) {
1010	dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);
1011	return -EINVAL;
1012	}
1013
1014	vals = devm_kcalloc(dev: pcs->dev, n: rows, size: sizeof(*vals), GFP_KERNEL);
1015	if (!vals)
1016	return -ENOMEM;
1017
1018	pins = devm_kcalloc(dev: pcs->dev, n: rows, size: sizeof(*pins), GFP_KERNEL);
1019	if (!pins)
1020	goto free_vals;
1021
1022	for (i = 0; i < rows; i++) {
1023	struct of_phandle_args pinctrl_spec;
1024	unsigned int offset;
1025	int pin;
1026
1027	res = pinctrl_parse_index_with_args(np, list_name: name, index: i, out_args: &pinctrl_spec);
1028	if (res)
1029	return res;
1030
1031	if (pinctrl_spec.args_count < 2 || pinctrl_spec.args_count > 3) {
1032	dev_err(pcs->dev, "invalid args_count for spec: %i\n",
1033	pinctrl_spec.args_count);
1034	break;
1035	}
1036
1037	offset = pinctrl_spec.args[0];
1038	vals[found].reg = pcs->base + offset;
1039
1040	switch (pinctrl_spec.args_count) {
1041	case 2:
1042	vals[found].val = pinctrl_spec.args[1];
1043	break;
1044	case 3:
1045	vals[found].val = (pinctrl_spec.args[1] | pinctrl_spec.args[2]);
1046	break;
1047	}
1048
1049	dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x\n",
1050	pinctrl_spec.np, offset, vals[found].val);
1051
1052	pin = pcs_get_pin_by_offset(pcs, offset);
1053	if (pin < 0) {
1054	dev_err(pcs->dev,
1055	"could not add functions for %pOFn %ux\n",
1056	np, offset);
1057	break;
1058	}
1059	pins[found++] = pin;
1060	}
1061
1062	pgnames[0] = np->name;
1063	mutex_lock(&pcs->mutex);
1064	fsel = pcs_add_function(pcs, fcn: &function, name: np->name, vals, nvals: found,
1065	pgnames, npgnames: 1);
1066	if (fsel < 0) {
1067	res = fsel;
1068	goto free_pins;
1069	}
1070
1071	gsel = pinctrl_generic_add_group(pctldev: pcs->pctl, name: np->name, gpins: pins, ngpins: found, data: pcs);
1072	if (gsel < 0) {
1073	res = gsel;
1074	goto free_function;
1075	}
1076
1077	(*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1078	(*map)->data.mux.group = np->name;
1079	(*map)->data.mux.function = np->name;
1080
1081	if (PCS_HAS_PINCONF && function) {
1082	res = pcs_parse_pinconf(pcs, np, func: function, map);
1083	if (res == 0)
1084	*num_maps = 2;
1085	else if (res == -ENOTSUPP)
1086	*num_maps = 1;
1087	else
1088	goto free_pingroups;
1089	} else {
1090	*num_maps = 1;
1091	}
1092	mutex_unlock(lock: &pcs->mutex);
1093
1094	return 0;
1095
1096	free_pingroups:
1097	pinctrl_generic_remove_group(pctldev: pcs->pctl, group_selector: gsel);
1098	*num_maps = 1;
1099	free_function:
1100	pinmux_generic_remove_function(pctldev: pcs->pctl, selector: fsel);
1101	free_pins:
1102	mutex_unlock(lock: &pcs->mutex);
1103	devm_kfree(dev: pcs->dev, p: pins);
1104
1105	free_vals:
1106	devm_kfree(dev: pcs->dev, p: vals);
1107
1108	return res;
1109	}
1110
1111	static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs,
1112	struct device_node *np,
1113	struct pinctrl_map **map,
1114	unsigned *num_maps,
1115	const char **pgnames)
1116	{
1117	const char *name = "pinctrl-single,bits";
1118	struct pcs_func_vals *vals;
1119	int rows, *pins, found = 0, res = -ENOMEM, i, fsel;
1120	int npins_in_row;
1121	struct pcs_function *function = NULL;
1122
1123	rows = pinctrl_count_index_with_args(np, list_name: name);
1124	if (rows <= 0) {
1125	dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);
1126	return -EINVAL;
1127	}
1128
1129	if (PCS_HAS_PINCONF) {
1130	dev_err(pcs->dev, "pinconf not supported\n");
1131	return -ENOTSUPP;
1132	}
1133
1134	npins_in_row = pcs->width / pcs->bits_per_pin;
1135
1136	vals = devm_kzalloc(dev: pcs->dev,
1137	array3_size(rows, npins_in_row, sizeof(*vals)),
1138	GFP_KERNEL);
1139	if (!vals)
1140	return -ENOMEM;
1141
1142	pins = devm_kzalloc(dev: pcs->dev,
1143	array3_size(rows, npins_in_row, sizeof(*pins)),
1144	GFP_KERNEL);
1145	if (!pins)
1146	goto free_vals;
1147
1148	for (i = 0; i < rows; i++) {
1149	struct of_phandle_args pinctrl_spec;
1150	unsigned offset, val;
1151	unsigned mask, bit_pos, val_pos, mask_pos, submask;
1152	unsigned pin_num_from_lsb;
1153	int pin;
1154
1155	res = pinctrl_parse_index_with_args(np, list_name: name, index: i, out_args: &pinctrl_spec);
1156	if (res)
1157	return res;
1158
1159	if (pinctrl_spec.args_count < 3) {
1160	dev_err(pcs->dev, "invalid args_count for spec: %i\n",
1161	pinctrl_spec.args_count);
1162	break;
1163	}
1164
1165	/* Index plus two value cells */
1166	offset = pinctrl_spec.args[0];
1167	val = pinctrl_spec.args[1];
1168	mask = pinctrl_spec.args[2];
1169
1170	dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x mask: 0x%x\n",
1171	pinctrl_spec.np, offset, val, mask);
1172
1173	/* Parse pins in each row from LSB */
1174	while (mask) {
1175	bit_pos = __ffs(mask);
1176	pin_num_from_lsb = bit_pos / pcs->bits_per_pin;
1177	mask_pos = ((pcs->fmask) << bit_pos);
1178	val_pos = val & mask_pos;
1179	submask = mask & mask_pos;
1180
1181	if ((mask & mask_pos) == 0) {
1182	dev_err(pcs->dev,
1183	"Invalid mask for %pOFn at 0x%x\n",
1184	np, offset);
1185	break;
1186	}
1187
1188	mask &= ~mask_pos;
1189
1190	if (submask != mask_pos) {
1191	dev_warn(pcs->dev,
1192	"Invalid submask 0x%x for %pOFn at 0x%x\n",
1193	submask, np, offset);
1194	continue;
1195	}
1196
1197	vals[found].mask = submask;
1198	vals[found].reg = pcs->base + offset;
1199	vals[found].val = val_pos;
1200
1201	pin = pcs_get_pin_by_offset(pcs, offset);
1202	if (pin < 0) {
1203	dev_err(pcs->dev,
1204	"could not add functions for %pOFn %ux\n",
1205	np, offset);
1206	break;
1207	}
1208	pins[found++] = pin + pin_num_from_lsb;
1209	}
1210	}
1211
1212	pgnames[0] = np->name;
1213	mutex_lock(&pcs->mutex);
1214	fsel = pcs_add_function(pcs, fcn: &function, name: np->name, vals, nvals: found,
1215	pgnames, npgnames: 1);
1216	if (fsel < 0) {
1217	res = fsel;
1218	goto free_pins;
1219	}
1220
1221	res = pinctrl_generic_add_group(pctldev: pcs->pctl, name: np->name, gpins: pins, ngpins: found, data: pcs);
1222	if (res < 0)
1223	goto free_function;
1224
1225	(*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1226	(*map)->data.mux.group = np->name;
1227	(*map)->data.mux.function = np->name;
1228
1229	*num_maps = 1;
1230	mutex_unlock(lock: &pcs->mutex);
1231
1232	return 0;
1233
1234	free_function:
1235	pinmux_generic_remove_function(pctldev: pcs->pctl, selector: fsel);
1236	free_pins:
1237	mutex_unlock(lock: &pcs->mutex);
1238	devm_kfree(dev: pcs->dev, p: pins);
1239
1240	free_vals:
1241	devm_kfree(dev: pcs->dev, p: vals);
1242
1243	return res;
1244	}
1245	/**
1246	* pcs_dt_node_to_map() - allocates and parses pinctrl maps
1247	* @pctldev: pinctrl instance
1248	* @np_config: device tree pinmux entry
1249	* @map: array of map entries
1250	* @num_maps: number of maps
1251	*/
1252	static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
1253	struct device_node *np_config,
1254	struct pinctrl_map **map, unsigned *num_maps)
1255	{
1256	struct pcs_device *pcs;
1257	const char **pgnames;
1258	int ret;
1259
1260	pcs = pinctrl_dev_get_drvdata(pctldev);
1261
1262	/* create 2 maps. One is for pinmux, and the other is for pinconf. */
1263	*map = devm_kcalloc(dev: pcs->dev, n: 2, size: sizeof(**map), GFP_KERNEL);
1264	if (!*map)
1265	return -ENOMEM;
1266
1267	*num_maps = 0;
1268
1269	pgnames = devm_kzalloc(dev: pcs->dev, size: sizeof(*pgnames), GFP_KERNEL);
1270	if (!pgnames) {
1271	ret = -ENOMEM;
1272	goto free_map;
1273	}
1274
1275	if (pcs->bits_per_mux) {
1276	ret = pcs_parse_bits_in_pinctrl_entry(pcs, np: np_config, map,
1277	num_maps, pgnames);
1278	if (ret < 0) {
1279	dev_err(pcs->dev, "no pins entries for %pOFn\n",
1280	np_config);
1281	goto free_pgnames;
1282	}
1283	} else {
1284	ret = pcs_parse_one_pinctrl_entry(pcs, np: np_config, map,
1285	num_maps, pgnames);
1286	if (ret < 0) {
1287	dev_err(pcs->dev, "no pins entries for %pOFn\n",
1288	np_config);
1289	goto free_pgnames;
1290	}
1291	}
1292
1293	return 0;
1294
1295	free_pgnames:
1296	devm_kfree(dev: pcs->dev, p: pgnames);
1297	free_map:
1298	devm_kfree(dev: pcs->dev, p: *map);
1299
1300	return ret;
1301	}
1302
1303	/**
1304	* pcs_irq_free() - free interrupt
1305	* @pcs: pcs driver instance
1306	*/
1307	static void pcs_irq_free(struct pcs_device *pcs)
1308	{
1309	struct pcs_soc_data *pcs_soc = &pcs->socdata;
1310
1311	if (pcs_soc->irq < 0)
1312	return;
1313
1314	if (pcs->domain)
1315	irq_domain_remove(host: pcs->domain);
1316
1317	if (PCS_QUIRK_HAS_SHARED_IRQ)
1318	free_irq(pcs_soc->irq, pcs_soc);
1319	else
1320	irq_set_chained_handler(irq: pcs_soc->irq, NULL);
1321	}
1322
1323	/**
1324	* pcs_free_resources() - free memory used by this driver
1325	* @pcs: pcs driver instance
1326	*/
1327	static void pcs_free_resources(struct pcs_device *pcs)
1328	{
1329	pcs_irq_free(pcs);
1330	pinctrl_unregister(pctldev: pcs->pctl);
1331
1332	#if IS_BUILTIN(CONFIG_PINCTRL_SINGLE)
1333	if (pcs->missing_nr_pinctrl_cells)
1334	of_remove_property(np: pcs->np, prop: pcs->missing_nr_pinctrl_cells);
1335	#endif
1336	}
1337
1338	static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs)
1339	{
1340	const char *propname = "pinctrl-single,gpio-range";
1341	const char *cellname = "#pinctrl-single,gpio-range-cells";
1342	struct of_phandle_args gpiospec;
1343	struct pcs_gpiofunc_range *range;
1344	int ret, i;
1345
1346	for (i = 0; ; i++) {
1347	ret = of_parse_phandle_with_args(np: node, list_name: propname, cells_name: cellname,
1348	index: i, out_args: &gpiospec);
1349	/* Do not treat it as error. Only treat it as end condition. */
1350	if (ret) {
1351	ret = 0;
1352	break;
1353	}
1354	range = devm_kzalloc(dev: pcs->dev, size: sizeof(*range), GFP_KERNEL);
1355	if (!range) {
1356	ret = -ENOMEM;
1357	break;
1358	}
1359	range->offset = gpiospec.args[0];
1360	range->npins = gpiospec.args[1];
1361	range->gpiofunc = gpiospec.args[2];
1362	mutex_lock(&pcs->mutex);
1363	list_add_tail(new: &range->node, head: &pcs->gpiofuncs);
1364	mutex_unlock(lock: &pcs->mutex);
1365	}
1366	return ret;
1367	}
1368
1369	/**
1370	* struct pcs_interrupt
1371	* @reg: virtual address of interrupt register
1372	* @hwirq: hardware irq number
1373	* @irq: virtual irq number
1374	* @node: list node
1375	*/
1376	struct pcs_interrupt {
1377	void __iomem *reg;
1378	irq_hw_number_t hwirq;
1379	unsigned int irq;
1380	struct list_head node;
1381	};
1382
1383	/**
1384	* pcs_irq_set() - enables or disables an interrupt
1385	* @pcs_soc: SoC specific settings
1386	* @irq: interrupt
1387	* @enable: enable or disable the interrupt
1388	*
1389	* Note that this currently assumes one interrupt per pinctrl
1390	* register that is typically used for wake-up events.
1391	*/
1392	static inline void pcs_irq_set(struct pcs_soc_data *pcs_soc,
1393	int irq, const bool enable)
1394	{
1395	struct pcs_device *pcs;
1396	struct list_head *pos;
1397	unsigned mask;
1398
1399	pcs = container_of(pcs_soc, struct pcs_device, socdata);
1400	list_for_each(pos, &pcs->irqs) {
1401	struct pcs_interrupt *pcswi;
1402	unsigned soc_mask;
1403
1404	pcswi = list_entry(pos, struct pcs_interrupt, node);
1405	if (irq != pcswi->irq)
1406	continue;
1407
1408	soc_mask = pcs_soc->irq_enable_mask;
1409	raw_spin_lock(&pcs->lock);
1410	mask = pcs->read(pcswi->reg);
1411	if (enable)
1412	mask |= soc_mask;
1413	else
1414	mask &= ~soc_mask;
1415	pcs->write(mask, pcswi->reg);
1416
1417	/* flush posted write */
1418	mask = pcs->read(pcswi->reg);
1419	raw_spin_unlock(&pcs->lock);
1420	}
1421
1422	if (pcs_soc->rearm)
1423	pcs_soc->rearm();
1424	}
1425
1426	/**
1427	* pcs_irq_mask() - mask pinctrl interrupt
1428	* @d: interrupt data
1429	*/
1430	static void pcs_irq_mask(struct irq_data *d)
1431	{
1432	struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1433
1434	pcs_irq_set(pcs_soc, irq: d->irq, enable: false);
1435	}
1436
1437	/**
1438	* pcs_irq_unmask() - unmask pinctrl interrupt
1439	* @d: interrupt data
1440	*/
1441	static void pcs_irq_unmask(struct irq_data *d)
1442	{
1443	struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1444
1445	pcs_irq_set(pcs_soc, irq: d->irq, enable: true);
1446	}
1447
1448	/**
1449	* pcs_irq_set_wake() - toggle the suspend and resume wake up
1450	* @d: interrupt data
1451	* @state: wake-up state
1452	*
1453	* Note that this should be called only for suspend and resume.
1454	* For runtime PM, the wake-up events should be enabled by default.
1455	*/
1456	static int pcs_irq_set_wake(struct irq_data *d, unsigned int state)
1457	{
1458	if (state)
1459	pcs_irq_unmask(d);
1460	else
1461	pcs_irq_mask(d);
1462
1463	return 0;
1464	}
1465
1466	/**
1467	* pcs_irq_handle() - common interrupt handler
1468	* @pcs_soc: SoC specific settings
1469	*
1470	* Note that this currently assumes we have one interrupt bit per
1471	* mux register. This interrupt is typically used for wake-up events.
1472	* For more complex interrupts different handlers can be specified.
1473	*/
1474	static int pcs_irq_handle(struct pcs_soc_data *pcs_soc)
1475	{
1476	struct pcs_device *pcs;
1477	struct list_head *pos;
1478	int count = 0;
1479
1480	pcs = container_of(pcs_soc, struct pcs_device, socdata);
1481	list_for_each(pos, &pcs->irqs) {
1482	struct pcs_interrupt *pcswi;
1483	unsigned mask;
1484
1485	pcswi = list_entry(pos, struct pcs_interrupt, node);
1486	raw_spin_lock(&pcs->lock);
1487	mask = pcs->read(pcswi->reg);
1488	raw_spin_unlock(&pcs->lock);
1489	if (mask & pcs_soc->irq_status_mask) {
1490	generic_handle_domain_irq(domain: pcs->domain,
1491	hwirq: pcswi->hwirq);
1492	count++;
1493	}
1494	}
1495
1496	return count;
1497	}
1498
1499	/**
1500	* pcs_irq_handler() - handler for the shared interrupt case
1501	* @irq: interrupt
1502	* @d: data
1503	*
1504	* Use this for cases where multiple instances of
1505	* pinctrl-single share a single interrupt like on omaps.
1506	*/
1507	static irqreturn_t pcs_irq_handler(int irq, void *d)
1508	{
1509	struct pcs_soc_data *pcs_soc = d;
1510
1511	return pcs_irq_handle(pcs_soc) ? IRQ_HANDLED : IRQ_NONE;
1512	}
1513
1514	/**
1515	* pcs_irq_chain_handler() - handler for the dedicated chained interrupt case
1516	* @desc: interrupt descriptor
1517	*
1518	* Use this if you have a separate interrupt for each
1519	* pinctrl-single instance.
1520	*/
1521	static void pcs_irq_chain_handler(struct irq_desc *desc)
1522	{
1523	struct pcs_soc_data *pcs_soc = irq_desc_get_handler_data(desc);
1524	struct irq_chip *chip;
1525
1526	chip = irq_desc_get_chip(desc);
1527	chained_irq_enter(chip, desc);
1528	pcs_irq_handle(pcs_soc);
1529	/* REVISIT: export and add handle_bad_irq(irq, desc)? */
1530	chained_irq_exit(chip, desc);
1531	}
1532
1533	static int pcs_irqdomain_map(struct irq_domain *d, unsigned int irq,
1534	irq_hw_number_t hwirq)
1535	{
1536	struct pcs_soc_data *pcs_soc = d->host_data;
1537	struct pcs_device *pcs;
1538	struct pcs_interrupt *pcswi;
1539
1540	pcs = container_of(pcs_soc, struct pcs_device, socdata);
1541	pcswi = devm_kzalloc(dev: pcs->dev, size: sizeof(*pcswi), GFP_KERNEL);
1542	if (!pcswi)
1543	return -ENOMEM;
1544
1545	pcswi->reg = pcs->base + hwirq;
1546	pcswi->hwirq = hwirq;
1547	pcswi->irq = irq;
1548
1549	mutex_lock(&pcs->mutex);
1550	list_add_tail(new: &pcswi->node, head: &pcs->irqs);
1551	mutex_unlock(lock: &pcs->mutex);
1552
1553	irq_set_chip_data(irq, data: pcs_soc);
1554	irq_set_chip_and_handler(irq, chip: &pcs->chip,
1555	handle: handle_level_irq);
1556	irq_set_lockdep_class(irq, lock_class: &pcs_lock_class, request_class: &pcs_request_class);
1557	irq_set_noprobe(irq);
1558
1559	return 0;
1560	}
1561
1562	static const struct irq_domain_ops pcs_irqdomain_ops = {
1563	.map = pcs_irqdomain_map,
1564	.xlate = irq_domain_xlate_onecell,
1565	};
1566
1567	/**
1568	* pcs_irq_init_chained_handler() - set up a chained interrupt handler
1569	* @pcs: pcs driver instance
1570	* @np: device node pointer
1571	*/
1572	static int pcs_irq_init_chained_handler(struct pcs_device *pcs,
1573	struct device_node *np)
1574	{
1575	struct pcs_soc_data *pcs_soc = &pcs->socdata;
1576	const char *name = "pinctrl";
1577	int num_irqs;
1578
1579	if (!pcs_soc->irq_enable_mask ||
1580	!pcs_soc->irq_status_mask) {
1581	pcs_soc->irq = -1;
1582	return -EINVAL;
1583	}
1584
1585	INIT_LIST_HEAD(list: &pcs->irqs);
1586	pcs->chip.name = name;
1587	pcs->chip.irq_ack = pcs_irq_mask;
1588	pcs->chip.irq_mask = pcs_irq_mask;
1589	pcs->chip.irq_unmask = pcs_irq_unmask;
1590	pcs->chip.irq_set_wake = pcs_irq_set_wake;
1591
1592	if (PCS_QUIRK_HAS_SHARED_IRQ) {
1593	int res;
1594
1595	res = request_irq(irq: pcs_soc->irq, handler: pcs_irq_handler,
1596	IRQF_SHARED | IRQF_NO_SUSPEND |
1597	IRQF_NO_THREAD,
1598	name, dev: pcs_soc);
1599	if (res) {
1600	pcs_soc->irq = -1;
1601	return res;
1602	}
1603	} else {
1604	irq_set_chained_handler_and_data(irq: pcs_soc->irq,
1605	handle: pcs_irq_chain_handler,
1606	data: pcs_soc);
1607	}
1608
1609	/*
1610	* We can use the register offset as the hardirq
1611	* number as irq_domain_add_simple maps them lazily.
1612	* This way we can easily support more than one
1613	* interrupt per function if needed.
1614	*/
1615	num_irqs = pcs->size;
1616
1617	pcs->domain = irq_domain_add_simple(of_node: np, size: num_irqs, first_irq: 0,
1618	ops: &pcs_irqdomain_ops,
1619	host_data: pcs_soc);
1620	if (!pcs->domain) {
1621	irq_set_chained_handler(irq: pcs_soc->irq, NULL);
1622	return -EINVAL;
1623	}
1624
1625	return 0;
1626	}
1627
1628	#ifdef CONFIG_PM
1629	static int pcs_save_context(struct pcs_device *pcs)
1630	{
1631	int i, mux_bytes;
1632	u64 *regsl;
1633	u32 *regsw;
1634	u16 *regshw;
1635
1636	mux_bytes = pcs->width / BITS_PER_BYTE;
1637
1638	if (!pcs->saved_vals) {
1639	pcs->saved_vals = devm_kzalloc(dev: pcs->dev, size: pcs->size, GFP_ATOMIC);
1640	if (!pcs->saved_vals)
1641	return -ENOMEM;
1642	}
1643
1644	switch (pcs->width) {
1645	case 64:
1646	regsl = pcs->saved_vals;
1647	for (i = 0; i < pcs->size; i += mux_bytes)
1648	*regsl++ = pcs->read(pcs->base + i);
1649	break;
1650	case 32:
1651	regsw = pcs->saved_vals;
1652	for (i = 0; i < pcs->size; i += mux_bytes)
1653	*regsw++ = pcs->read(pcs->base + i);
1654	break;
1655	case 16:
1656	regshw = pcs->saved_vals;
1657	for (i = 0; i < pcs->size; i += mux_bytes)
1658	*regshw++ = pcs->read(pcs->base + i);
1659	break;
1660	}
1661
1662	return 0;
1663	}
1664
1665	static void pcs_restore_context(struct pcs_device *pcs)
1666	{
1667	int i, mux_bytes;
1668	u64 *regsl;
1669	u32 *regsw;
1670	u16 *regshw;
1671
1672	mux_bytes = pcs->width / BITS_PER_BYTE;
1673
1674	switch (pcs->width) {
1675	case 64:
1676	regsl = pcs->saved_vals;
1677	for (i = 0; i < pcs->size; i += mux_bytes)
1678	pcs->write(*regsl++, pcs->base + i);
1679	break;
1680	case 32:
1681	regsw = pcs->saved_vals;
1682	for (i = 0; i < pcs->size; i += mux_bytes)
1683	pcs->write(*regsw++, pcs->base + i);
1684	break;
1685	case 16:
1686	regshw = pcs->saved_vals;
1687	for (i = 0; i < pcs->size; i += mux_bytes)
1688	pcs->write(*regshw++, pcs->base + i);
1689	break;
1690	}
1691	}
1692
1693	static int pinctrl_single_suspend(struct platform_device *pdev,
1694	pm_message_t state)
1695	{
1696	struct pcs_device *pcs;
1697
1698	pcs = platform_get_drvdata(pdev);
1699	if (!pcs)
1700	return -EINVAL;
1701
1702	if (pcs->flags & PCS_CONTEXT_LOSS_OFF) {
1703	int ret;
1704
1705	ret = pcs_save_context(pcs);
1706	if (ret < 0)
1707	return ret;
1708	}
1709
1710	return pinctrl_force_sleep(pctldev: pcs->pctl);
1711	}
1712
1713	static int pinctrl_single_resume(struct platform_device *pdev)
1714	{
1715	struct pcs_device *pcs;
1716
1717	pcs = platform_get_drvdata(pdev);
1718	if (!pcs)
1719	return -EINVAL;
1720
1721	if (pcs->flags & PCS_CONTEXT_LOSS_OFF)
1722	pcs_restore_context(pcs);
1723
1724	return pinctrl_force_default(pctldev: pcs->pctl);
1725	}
1726	#endif
1727
1728	/**
1729	* pcs_quirk_missing_pinctrl_cells - handle legacy binding
1730	* @pcs: pinctrl driver instance
1731	* @np: device tree node
1732	* @cells: number of cells
1733	*
1734	* Handle legacy binding with no #pinctrl-cells. This should be
1735	* always two pinctrl-single,bit-per-mux and one for others.
1736	* At some point we may want to consider removing this.
1737	*/
1738	static int pcs_quirk_missing_pinctrl_cells(struct pcs_device *pcs,
1739	struct device_node *np,
1740	int cells)
1741	{
1742	struct property *p;
1743	const char *name = "#pinctrl-cells";
1744	int error;
1745	u32 val;
1746
1747	error = of_property_read_u32(np, propname: name, out_value: &val);
1748	if (!error)
1749	return 0;
1750
1751	dev_warn(pcs->dev, "please update dts to use %s = <%i>\n",
1752	name, cells);
1753
1754	p = devm_kzalloc(dev: pcs->dev, size: sizeof(*p), GFP_KERNEL);
1755	if (!p)
1756	return -ENOMEM;
1757
1758	p->length = sizeof(__be32);
1759	p->value = devm_kzalloc(dev: pcs->dev, size: sizeof(__be32), GFP_KERNEL);
1760	if (!p->value)
1761	return -ENOMEM;
1762	*(__be32 *)p->value = cpu_to_be32(cells);
1763
1764	p->name = devm_kstrdup(dev: pcs->dev, s: name, GFP_KERNEL);
1765	if (!p->name)
1766	return -ENOMEM;
1767
1768	pcs->missing_nr_pinctrl_cells = p;
1769
1770	#if IS_BUILTIN(CONFIG_PINCTRL_SINGLE)
1771	error = of_add_property(np, prop: pcs->missing_nr_pinctrl_cells);
1772	#endif
1773
1774	return error;
1775	}
1776
1777	static int pcs_probe(struct platform_device *pdev)
1778	{
1779	struct device_node *np = pdev->dev.of_node;
1780	struct pcs_pdata *pdata;
1781	struct resource *res;
1782	struct pcs_device *pcs;
1783	const struct pcs_soc_data *soc;
1784	int ret;
1785
1786	soc = of_device_get_match_data(dev: &pdev->dev);
1787	if (WARN_ON(!soc))
1788	return -EINVAL;
1789
1790	pcs = devm_kzalloc(dev: &pdev->dev, size: sizeof(*pcs), GFP_KERNEL);
1791	if (!pcs)
1792	return -ENOMEM;
1793
1794	pcs->dev = &pdev->dev;
1795	pcs->np = np;
1796	raw_spin_lock_init(&pcs->lock);
1797	mutex_init(&pcs->mutex);
1798	INIT_LIST_HEAD(list: &pcs->gpiofuncs);
1799	pcs->flags = soc->flags;
1800	memcpy(&pcs->socdata, soc, sizeof(*soc));
1801
1802	ret = of_property_read_u32(np, propname: "pinctrl-single,register-width",
1803	out_value: &pcs->width);
1804	if (ret) {
1805	dev_err(pcs->dev, "register width not specified\n");
1806
1807	return ret;
1808	}
1809
1810	ret = of_property_read_u32(np, propname: "pinctrl-single,function-mask",
1811	out_value: &pcs->fmask);
1812	if (!ret) {
1813	pcs->fshift = __ffs(pcs->fmask);
1814	pcs->fmax = pcs->fmask >> pcs->fshift;
1815	} else {
1816	/* If mask property doesn't exist, function mux is invalid. */
1817	pcs->fmask = 0;
1818	pcs->fshift = 0;
1819	pcs->fmax = 0;
1820	}
1821
1822	ret = of_property_read_u32(np, propname: "pinctrl-single,function-off",
1823	out_value: &pcs->foff);
1824	if (ret)
1825	pcs->foff = PCS_OFF_DISABLED;
1826
1827	pcs->bits_per_mux = of_property_read_bool(np,
1828	propname: "pinctrl-single,bit-per-mux");
1829	ret = pcs_quirk_missing_pinctrl_cells(pcs, np,
1830	cells: pcs->bits_per_mux ? 2 : 1);
1831	if (ret) {
1832	dev_err(&pdev->dev, "unable to patch #pinctrl-cells\n");
1833
1834	return ret;
1835	}
1836
1837	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1838	if (!res) {
1839	dev_err(pcs->dev, "could not get resource\n");
1840	return -ENODEV;
1841	}
1842
1843	pcs->res = devm_request_mem_region(pcs->dev, res->start,
1844	resource_size(res), DRIVER_NAME);
1845	if (!pcs->res) {
1846	dev_err(pcs->dev, "could not get mem_region\n");
1847	return -EBUSY;
1848	}
1849
1850	pcs->size = resource_size(res: pcs->res);
1851	pcs->base = devm_ioremap(dev: pcs->dev, offset: pcs->res->start, size: pcs->size);
1852	if (!pcs->base) {
1853	dev_err(pcs->dev, "could not ioremap\n");
1854	return -ENODEV;
1855	}
1856
1857	platform_set_drvdata(pdev, data: pcs);
1858
1859	switch (pcs->width) {
1860	case 8:
1861	pcs->read = pcs_readb;
1862	pcs->write = pcs_writeb;
1863	break;
1864	case 16:
1865	pcs->read = pcs_readw;
1866	pcs->write = pcs_writew;
1867	break;
1868	case 32:
1869	pcs->read = pcs_readl;
1870	pcs->write = pcs_writel;
1871	break;
1872	default:
1873	break;
1874	}
1875
1876	pcs->desc.name = DRIVER_NAME;
1877	pcs->desc.pctlops = &pcs_pinctrl_ops;
1878	pcs->desc.pmxops = &pcs_pinmux_ops;
1879	if (PCS_HAS_PINCONF)
1880	pcs->desc.confops = &pcs_pinconf_ops;
1881	pcs->desc.owner = THIS_MODULE;
1882
1883	ret = pcs_allocate_pin_table(pcs);
1884	if (ret < 0)
1885	goto free;
1886
1887	ret = pinctrl_register_and_init(pctldesc: &pcs->desc, dev: pcs->dev, driver_data: pcs, pctldev: &pcs->pctl);
1888	if (ret) {
1889	dev_err(pcs->dev, "could not register single pinctrl driver\n");
1890	goto free;
1891	}
1892
1893	ret = pcs_add_gpio_func(node: np, pcs);
1894	if (ret < 0)
1895	goto free;
1896
1897	pcs->socdata.irq = irq_of_parse_and_map(node: np, index: 0);
1898	if (pcs->socdata.irq)
1899	pcs->flags |= PCS_FEAT_IRQ;
1900
1901	/* We still need auxdata for some omaps for PRM interrupts */
1902	pdata = dev_get_platdata(dev: &pdev->dev);
1903	if (pdata) {
1904	if (pdata->rearm)
1905	pcs->socdata.rearm = pdata->rearm;
1906	if (pdata->irq) {
1907	pcs->socdata.irq = pdata->irq;
1908	pcs->flags |= PCS_FEAT_IRQ;
1909	}
1910	}
1911
1912	if (PCS_HAS_IRQ) {
1913	ret = pcs_irq_init_chained_handler(pcs, np);
1914	if (ret < 0)
1915	dev_warn(pcs->dev, "initialized with no interrupts\n");
1916	}
1917
1918	dev_info(pcs->dev, "%i pins, size %u\n", pcs->desc.npins, pcs->size);
1919
1920	return pinctrl_enable(pctldev: pcs->pctl);
1921
1922	free:
1923	pcs_free_resources(pcs);
1924
1925	return ret;
1926	}
1927
1928	static void pcs_remove(struct platform_device *pdev)
1929	{
1930	struct pcs_device *pcs = platform_get_drvdata(pdev);
1931
1932	pcs_free_resources(pcs);
1933	}
1934
1935	static const struct pcs_soc_data pinctrl_single_omap_wkup = {
1936	.flags = PCS_QUIRK_SHARED_IRQ,
1937	.irq_enable_mask = (1 << 14), /* OMAP_WAKEUP_EN */
1938	.irq_status_mask = (1 << 15), /* OMAP_WAKEUP_EVENT */
1939	};
1940
1941	static const struct pcs_soc_data pinctrl_single_dra7 = {
1942	.irq_enable_mask = (1 << 24), /* WAKEUPENABLE */
1943	.irq_status_mask = (1 << 25), /* WAKEUPEVENT */
1944	};
1945
1946	static const struct pcs_soc_data pinctrl_single_am437x = {
1947	.flags = PCS_QUIRK_SHARED_IRQ | PCS_CONTEXT_LOSS_OFF,
1948	.irq_enable_mask = (1 << 29), /* OMAP_WAKEUP_EN */
1949	.irq_status_mask = (1 << 30), /* OMAP_WAKEUP_EVENT */
1950	};
1951
1952	static const struct pcs_soc_data pinctrl_single_am654 = {
1953	.flags = PCS_QUIRK_SHARED_IRQ | PCS_CONTEXT_LOSS_OFF,
1954	.irq_enable_mask = (1 << 29), /* WKUP_EN */
1955	.irq_status_mask = (1 << 30), /* WKUP_EVT */
1956	};
1957
1958	static const struct pcs_soc_data pinctrl_single = {
1959	};
1960
1961	static const struct pcs_soc_data pinconf_single = {
1962	.flags = PCS_FEAT_PINCONF,
1963	};
1964
1965	static const struct of_device_id pcs_of_match[] = {
1966	{ .compatible = "ti,am437-padconf", .data = &pinctrl_single_am437x },
1967	{ .compatible = "ti,am654-padconf", .data = &pinctrl_single_am654 },
1968	{ .compatible = "ti,dra7-padconf", .data = &pinctrl_single_dra7 },
1969	{ .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup },
1970	{ .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup },
1971	{ .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup },
1972	{ .compatible = "pinctrl-single", .data = &pinctrl_single },
1973	{ .compatible = "pinconf-single", .data = &pinconf_single },
1974	{ },
1975	};
1976	MODULE_DEVICE_TABLE(of, pcs_of_match);
1977
1978	static struct platform_driver pcs_driver = {
1979	.probe = pcs_probe,
1980	.remove_new = pcs_remove,
1981	.driver = {
1982	.name = DRIVER_NAME,
1983	.of_match_table = pcs_of_match,
1984	},
1985	#ifdef CONFIG_PM
1986	.suspend = pinctrl_single_suspend,
1987	.resume = pinctrl_single_resume,
1988	#endif
1989	};
1990
1991	module_platform_driver(pcs_driver);
1992
1993	MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>");
1994	MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver");
1995	MODULE_LICENSE("GPL v2");
1996