1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* |
3 | * LPC variant I/O for Microchip EC |
4 | * |
5 | * Copyright (C) 2016 Google, Inc |
6 | */ |
7 | |
8 | #ifndef __CROS_EC_LPC_MEC_H |
9 | #define __CROS_EC_LPC_MEC_H |
10 | |
11 | enum cros_ec_lpc_mec_emi_access_mode { |
12 | /* 8-bit access */ |
13 | ACCESS_TYPE_BYTE = 0x0, |
14 | /* 16-bit access */ |
15 | ACCESS_TYPE_WORD = 0x1, |
16 | /* 32-bit access */ |
17 | ACCESS_TYPE_LONG = 0x2, |
18 | /* |
19 | * 32-bit access, read or write of MEC_EMI_EC_DATA_B3 causes the |
20 | * EC data register to be incremented. |
21 | */ |
22 | ACCESS_TYPE_LONG_AUTO_INCREMENT = 0x3, |
23 | }; |
24 | |
25 | enum cros_ec_lpc_mec_io_type { |
26 | MEC_IO_READ, |
27 | MEC_IO_WRITE, |
28 | }; |
29 | |
30 | /* EMI registers are relative to base */ |
31 | #define MEC_EMI_HOST_TO_EC(MEC_EMI_BASE) ((MEC_EMI_BASE) + 0) |
32 | #define MEC_EMI_EC_TO_HOST(MEC_EMI_BASE) ((MEC_EMI_BASE) + 1) |
33 | #define MEC_EMI_EC_ADDRESS_B0(MEC_EMI_BASE) ((MEC_EMI_BASE) + 2) |
34 | #define MEC_EMI_EC_ADDRESS_B1(MEC_EMI_BASE) ((MEC_EMI_BASE) + 3) |
35 | #define MEC_EMI_EC_DATA_B0(MEC_EMI_BASE) ((MEC_EMI_BASE) + 4) |
36 | #define MEC_EMI_EC_DATA_B1(MEC_EMI_BASE) ((MEC_EMI_BASE) + 5) |
37 | #define MEC_EMI_EC_DATA_B2(MEC_EMI_BASE) ((MEC_EMI_BASE) + 6) |
38 | #define MEC_EMI_EC_DATA_B3(MEC_EMI_BASE) ((MEC_EMI_BASE) + 7) |
39 | |
40 | /** |
41 | * cros_ec_lpc_mec_init() - Initialize MEC I/O. |
42 | * |
43 | * @base: MEC EMI Base address |
44 | * @end: MEC EMI End address |
45 | */ |
46 | void cros_ec_lpc_mec_init(unsigned int base, unsigned int end); |
47 | |
48 | /** |
49 | * cros_ec_lpc_mec_in_range() - Determine if addresses are in MEC EMI range. |
50 | * |
51 | * @offset: Address offset |
52 | * @length: Number of bytes to check |
53 | * |
54 | * Return: 1 if in range, 0 if not, and -EINVAL on failure |
55 | * such as the mec range not being initialized |
56 | */ |
57 | int cros_ec_lpc_mec_in_range(unsigned int offset, unsigned int length); |
58 | |
59 | /** |
60 | * cros_ec_lpc_io_bytes_mec - Read / write bytes to MEC EMI port |
61 | * |
62 | * @io_type: MEC_IO_READ or MEC_IO_WRITE, depending on request |
63 | * @offset: Base read / write address |
64 | * @length: Number of bytes to read / write |
65 | * @buf: Destination / source buffer |
66 | * |
67 | * @return 8-bit checksum of all bytes read / written |
68 | */ |
69 | u8 cros_ec_lpc_io_bytes_mec(enum cros_ec_lpc_mec_io_type io_type, |
70 | unsigned int offset, unsigned int length, u8 *buf); |
71 | |
72 | #endif /* __CROS_EC_LPC_MEC_H */ |
73 | |