1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Copyright (C) Overkiz SAS 2012 |
4 | * |
5 | * Author: Boris BREZILLON <b.brezillon@overkiz.com> |
6 | */ |
7 | |
8 | #include <linux/module.h> |
9 | #include <linux/init.h> |
10 | #include <linux/clocksource.h> |
11 | #include <linux/clockchips.h> |
12 | #include <linux/interrupt.h> |
13 | #include <linux/irq.h> |
14 | |
15 | #include <linux/clk.h> |
16 | #include <linux/err.h> |
17 | #include <linux/ioport.h> |
18 | #include <linux/io.h> |
19 | #include <linux/mfd/syscon.h> |
20 | #include <linux/platform_device.h> |
21 | #include <linux/pwm.h> |
22 | #include <linux/of.h> |
23 | #include <linux/regmap.h> |
24 | #include <linux/slab.h> |
25 | #include <soc/at91/atmel_tcb.h> |
26 | |
27 | #define NPWM 2 |
28 | |
29 | #define ATMEL_TC_ACMR_MASK (ATMEL_TC_ACPA | ATMEL_TC_ACPC | \ |
30 | ATMEL_TC_AEEVT | ATMEL_TC_ASWTRG) |
31 | |
32 | #define ATMEL_TC_BCMR_MASK (ATMEL_TC_BCPB | ATMEL_TC_BCPC | \ |
33 | ATMEL_TC_BEEVT | ATMEL_TC_BSWTRG) |
34 | |
35 | struct atmel_tcb_pwm_device { |
36 | unsigned div; /* PWM clock divider */ |
37 | unsigned duty; /* PWM duty expressed in clk cycles */ |
38 | unsigned period; /* PWM period expressed in clk cycles */ |
39 | }; |
40 | |
41 | struct atmel_tcb_channel { |
42 | u32 enabled; |
43 | u32 cmr; |
44 | u32 ra; |
45 | u32 rb; |
46 | u32 rc; |
47 | }; |
48 | |
49 | struct atmel_tcb_pwm_chip { |
50 | struct pwm_chip chip; |
51 | spinlock_t lock; |
52 | u8 channel; |
53 | u8 width; |
54 | struct regmap *regmap; |
55 | struct clk *clk; |
56 | struct clk *gclk; |
57 | struct clk *slow_clk; |
58 | struct atmel_tcb_pwm_device pwms[NPWM]; |
59 | struct atmel_tcb_channel bkup; |
60 | }; |
61 | |
62 | static const u8 atmel_tcb_divisors[] = { 2, 8, 32, 128, 0, }; |
63 | |
64 | static inline struct atmel_tcb_pwm_chip *to_tcb_chip(struct pwm_chip *chip) |
65 | { |
66 | return container_of(chip, struct atmel_tcb_pwm_chip, chip); |
67 | } |
68 | |
69 | static int atmel_tcb_pwm_request(struct pwm_chip *chip, |
70 | struct pwm_device *pwm) |
71 | { |
72 | struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip); |
73 | struct atmel_tcb_pwm_device *tcbpwm = &tcbpwmc->pwms[pwm->hwpwm]; |
74 | unsigned cmr; |
75 | int ret; |
76 | |
77 | ret = clk_prepare_enable(clk: tcbpwmc->clk); |
78 | if (ret) |
79 | return ret; |
80 | |
81 | tcbpwm->duty = 0; |
82 | tcbpwm->period = 0; |
83 | tcbpwm->div = 0; |
84 | |
85 | spin_lock(lock: &tcbpwmc->lock); |
86 | regmap_read(map: tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), val: &cmr); |
87 | /* |
88 | * Get init config from Timer Counter registers if |
89 | * Timer Counter is already configured as a PWM generator. |
90 | */ |
91 | if (cmr & ATMEL_TC_WAVE) { |
92 | if (pwm->hwpwm == 0) |
93 | regmap_read(map: tcbpwmc->regmap, |
94 | ATMEL_TC_REG(tcbpwmc->channel, RA), |
95 | val: &tcbpwm->duty); |
96 | else |
97 | regmap_read(map: tcbpwmc->regmap, |
98 | ATMEL_TC_REG(tcbpwmc->channel, RB), |
99 | val: &tcbpwm->duty); |
100 | |
101 | tcbpwm->div = cmr & ATMEL_TC_TCCLKS; |
102 | regmap_read(map: tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, RC), |
103 | val: &tcbpwm->period); |
104 | cmr &= (ATMEL_TC_TCCLKS | ATMEL_TC_ACMR_MASK | |
105 | ATMEL_TC_BCMR_MASK); |
106 | } else |
107 | cmr = 0; |
108 | |
109 | cmr |= ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO | ATMEL_TC_EEVT_XC0; |
110 | regmap_write(map: tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), val: cmr); |
111 | spin_unlock(lock: &tcbpwmc->lock); |
112 | |
113 | return 0; |
114 | } |
115 | |
116 | static void atmel_tcb_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) |
117 | { |
118 | struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip); |
119 | |
120 | clk_disable_unprepare(clk: tcbpwmc->clk); |
121 | } |
122 | |
123 | static void atmel_tcb_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm, |
124 | enum pwm_polarity polarity) |
125 | { |
126 | struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip); |
127 | struct atmel_tcb_pwm_device *tcbpwm = &tcbpwmc->pwms[pwm->hwpwm]; |
128 | unsigned cmr; |
129 | |
130 | /* |
131 | * If duty is 0 the timer will be stopped and we have to |
132 | * configure the output correctly on software trigger: |
133 | * - set output to high if PWM_POLARITY_INVERSED |
134 | * - set output to low if PWM_POLARITY_NORMAL |
135 | * |
136 | * This is why we're reverting polarity in this case. |
137 | */ |
138 | if (tcbpwm->duty == 0) |
139 | polarity = !polarity; |
140 | |
141 | spin_lock(lock: &tcbpwmc->lock); |
142 | regmap_read(map: tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), val: &cmr); |
143 | |
144 | /* flush old setting and set the new one */ |
145 | if (pwm->hwpwm == 0) { |
146 | cmr &= ~ATMEL_TC_ACMR_MASK; |
147 | if (polarity == PWM_POLARITY_INVERSED) |
148 | cmr |= ATMEL_TC_ASWTRG_CLEAR; |
149 | else |
150 | cmr |= ATMEL_TC_ASWTRG_SET; |
151 | } else { |
152 | cmr &= ~ATMEL_TC_BCMR_MASK; |
153 | if (polarity == PWM_POLARITY_INVERSED) |
154 | cmr |= ATMEL_TC_BSWTRG_CLEAR; |
155 | else |
156 | cmr |= ATMEL_TC_BSWTRG_SET; |
157 | } |
158 | |
159 | regmap_write(map: tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), val: cmr); |
160 | |
161 | /* |
162 | * Use software trigger to apply the new setting. |
163 | * If both PWM devices in this group are disabled we stop the clock. |
164 | */ |
165 | if (!(cmr & (ATMEL_TC_ACPC | ATMEL_TC_BCPC))) { |
166 | regmap_write(map: tcbpwmc->regmap, |
167 | ATMEL_TC_REG(tcbpwmc->channel, CCR), |
168 | ATMEL_TC_SWTRG | ATMEL_TC_CLKDIS); |
169 | tcbpwmc->bkup.enabled = 1; |
170 | } else { |
171 | regmap_write(map: tcbpwmc->regmap, |
172 | ATMEL_TC_REG(tcbpwmc->channel, CCR), |
173 | ATMEL_TC_SWTRG); |
174 | tcbpwmc->bkup.enabled = 0; |
175 | } |
176 | |
177 | spin_unlock(lock: &tcbpwmc->lock); |
178 | } |
179 | |
180 | static int atmel_tcb_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm, |
181 | enum pwm_polarity polarity) |
182 | { |
183 | struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip); |
184 | struct atmel_tcb_pwm_device *tcbpwm = &tcbpwmc->pwms[pwm->hwpwm]; |
185 | u32 cmr; |
186 | |
187 | /* |
188 | * If duty is 0 the timer will be stopped and we have to |
189 | * configure the output correctly on software trigger: |
190 | * - set output to high if PWM_POLARITY_INVERSED |
191 | * - set output to low if PWM_POLARITY_NORMAL |
192 | * |
193 | * This is why we're reverting polarity in this case. |
194 | */ |
195 | if (tcbpwm->duty == 0) |
196 | polarity = !polarity; |
197 | |
198 | spin_lock(lock: &tcbpwmc->lock); |
199 | regmap_read(map: tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), val: &cmr); |
200 | |
201 | /* flush old setting and set the new one */ |
202 | cmr &= ~ATMEL_TC_TCCLKS; |
203 | |
204 | if (pwm->hwpwm == 0) { |
205 | cmr &= ~ATMEL_TC_ACMR_MASK; |
206 | |
207 | /* Set CMR flags according to given polarity */ |
208 | if (polarity == PWM_POLARITY_INVERSED) |
209 | cmr |= ATMEL_TC_ASWTRG_CLEAR; |
210 | else |
211 | cmr |= ATMEL_TC_ASWTRG_SET; |
212 | } else { |
213 | cmr &= ~ATMEL_TC_BCMR_MASK; |
214 | if (polarity == PWM_POLARITY_INVERSED) |
215 | cmr |= ATMEL_TC_BSWTRG_CLEAR; |
216 | else |
217 | cmr |= ATMEL_TC_BSWTRG_SET; |
218 | } |
219 | |
220 | /* |
221 | * If duty is 0 or equal to period there's no need to register |
222 | * a specific action on RA/RB and RC compare. |
223 | * The output will be configured on software trigger and keep |
224 | * this config till next config call. |
225 | */ |
226 | if (tcbpwm->duty != tcbpwm->period && tcbpwm->duty > 0) { |
227 | if (pwm->hwpwm == 0) { |
228 | if (polarity == PWM_POLARITY_INVERSED) |
229 | cmr |= ATMEL_TC_ACPA_SET | ATMEL_TC_ACPC_CLEAR; |
230 | else |
231 | cmr |= ATMEL_TC_ACPA_CLEAR | ATMEL_TC_ACPC_SET; |
232 | } else { |
233 | if (polarity == PWM_POLARITY_INVERSED) |
234 | cmr |= ATMEL_TC_BCPB_SET | ATMEL_TC_BCPC_CLEAR; |
235 | else |
236 | cmr |= ATMEL_TC_BCPB_CLEAR | ATMEL_TC_BCPC_SET; |
237 | } |
238 | } |
239 | |
240 | cmr |= (tcbpwm->div & ATMEL_TC_TCCLKS); |
241 | |
242 | regmap_write(map: tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), val: cmr); |
243 | |
244 | if (pwm->hwpwm == 0) |
245 | regmap_write(map: tcbpwmc->regmap, |
246 | ATMEL_TC_REG(tcbpwmc->channel, RA), |
247 | val: tcbpwm->duty); |
248 | else |
249 | regmap_write(map: tcbpwmc->regmap, |
250 | ATMEL_TC_REG(tcbpwmc->channel, RB), |
251 | val: tcbpwm->duty); |
252 | |
253 | regmap_write(map: tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, RC), |
254 | val: tcbpwm->period); |
255 | |
256 | /* Use software trigger to apply the new setting */ |
257 | regmap_write(map: tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CCR), |
258 | ATMEL_TC_SWTRG | ATMEL_TC_CLKEN); |
259 | tcbpwmc->bkup.enabled = 1; |
260 | spin_unlock(lock: &tcbpwmc->lock); |
261 | return 0; |
262 | } |
263 | |
264 | static int atmel_tcb_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, |
265 | int duty_ns, int period_ns) |
266 | { |
267 | struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip); |
268 | struct atmel_tcb_pwm_device *tcbpwm = &tcbpwmc->pwms[pwm->hwpwm]; |
269 | struct atmel_tcb_pwm_device *atcbpwm = NULL; |
270 | int i = 0; |
271 | int slowclk = 0; |
272 | unsigned period; |
273 | unsigned duty; |
274 | unsigned rate = clk_get_rate(clk: tcbpwmc->clk); |
275 | unsigned long long min; |
276 | unsigned long long max; |
277 | |
278 | /* |
279 | * Find best clk divisor: |
280 | * the smallest divisor which can fulfill the period_ns requirements. |
281 | * If there is a gclk, the first divisor is actually the gclk selector |
282 | */ |
283 | if (tcbpwmc->gclk) |
284 | i = 1; |
285 | for (; i < ARRAY_SIZE(atmel_tcb_divisors); ++i) { |
286 | if (atmel_tcb_divisors[i] == 0) { |
287 | slowclk = i; |
288 | continue; |
289 | } |
290 | min = div_u64(dividend: (u64)NSEC_PER_SEC * atmel_tcb_divisors[i], divisor: rate); |
291 | max = min << tcbpwmc->width; |
292 | if (max >= period_ns) |
293 | break; |
294 | } |
295 | |
296 | /* |
297 | * If none of the divisor are small enough to represent period_ns |
298 | * take slow clock (32KHz). |
299 | */ |
300 | if (i == ARRAY_SIZE(atmel_tcb_divisors)) { |
301 | i = slowclk; |
302 | rate = clk_get_rate(clk: tcbpwmc->slow_clk); |
303 | min = div_u64(NSEC_PER_SEC, divisor: rate); |
304 | max = min << tcbpwmc->width; |
305 | |
306 | /* If period is too big return ERANGE error */ |
307 | if (max < period_ns) |
308 | return -ERANGE; |
309 | } |
310 | |
311 | duty = div_u64(dividend: duty_ns, divisor: min); |
312 | period = div_u64(dividend: period_ns, divisor: min); |
313 | |
314 | if (pwm->hwpwm == 0) |
315 | atcbpwm = &tcbpwmc->pwms[1]; |
316 | else |
317 | atcbpwm = &tcbpwmc->pwms[0]; |
318 | |
319 | /* |
320 | * PWM devices provided by the TCB driver are grouped by 2. |
321 | * PWM devices in a given group must be configured with the |
322 | * same period_ns. |
323 | * |
324 | * We're checking the period value of the second PWM device |
325 | * in this group before applying the new config. |
326 | */ |
327 | if ((atcbpwm && atcbpwm->duty > 0 && |
328 | atcbpwm->duty != atcbpwm->period) && |
329 | (atcbpwm->div != i || atcbpwm->period != period)) { |
330 | dev_err(chip->dev, |
331 | "failed to configure period_ns: PWM group already configured with a different value\n" ); |
332 | return -EINVAL; |
333 | } |
334 | |
335 | tcbpwm->period = period; |
336 | tcbpwm->div = i; |
337 | tcbpwm->duty = duty; |
338 | |
339 | return 0; |
340 | } |
341 | |
342 | static int atmel_tcb_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, |
343 | const struct pwm_state *state) |
344 | { |
345 | int duty_cycle, period; |
346 | int ret; |
347 | |
348 | if (!state->enabled) { |
349 | atmel_tcb_pwm_disable(chip, pwm, polarity: state->polarity); |
350 | return 0; |
351 | } |
352 | |
353 | period = state->period < INT_MAX ? state->period : INT_MAX; |
354 | duty_cycle = state->duty_cycle < INT_MAX ? state->duty_cycle : INT_MAX; |
355 | |
356 | ret = atmel_tcb_pwm_config(chip, pwm, duty_ns: duty_cycle, period_ns: period); |
357 | if (ret) |
358 | return ret; |
359 | |
360 | return atmel_tcb_pwm_enable(chip, pwm, polarity: state->polarity); |
361 | } |
362 | |
363 | static const struct pwm_ops atmel_tcb_pwm_ops = { |
364 | .request = atmel_tcb_pwm_request, |
365 | .free = atmel_tcb_pwm_free, |
366 | .apply = atmel_tcb_pwm_apply, |
367 | .owner = THIS_MODULE, |
368 | }; |
369 | |
370 | static struct atmel_tcb_config tcb_rm9200_config = { |
371 | .counter_width = 16, |
372 | }; |
373 | |
374 | static struct atmel_tcb_config tcb_sam9x5_config = { |
375 | .counter_width = 32, |
376 | }; |
377 | |
378 | static struct atmel_tcb_config tcb_sama5d2_config = { |
379 | .counter_width = 32, |
380 | .has_gclk = 1, |
381 | }; |
382 | |
383 | static const struct of_device_id atmel_tcb_of_match[] = { |
384 | { .compatible = "atmel,at91rm9200-tcb" , .data = &tcb_rm9200_config, }, |
385 | { .compatible = "atmel,at91sam9x5-tcb" , .data = &tcb_sam9x5_config, }, |
386 | { .compatible = "atmel,sama5d2-tcb" , .data = &tcb_sama5d2_config, }, |
387 | { /* sentinel */ } |
388 | }; |
389 | |
390 | static int atmel_tcb_pwm_probe(struct platform_device *pdev) |
391 | { |
392 | const struct of_device_id *match; |
393 | struct atmel_tcb_pwm_chip *tcbpwm; |
394 | const struct atmel_tcb_config *config; |
395 | struct device_node *np = pdev->dev.of_node; |
396 | char clk_name[] = "t0_clk" ; |
397 | int err; |
398 | int channel; |
399 | |
400 | tcbpwm = devm_kzalloc(dev: &pdev->dev, size: sizeof(*tcbpwm), GFP_KERNEL); |
401 | if (tcbpwm == NULL) |
402 | return -ENOMEM; |
403 | |
404 | err = of_property_read_u32(np, propname: "reg" , out_value: &channel); |
405 | if (err < 0) { |
406 | dev_err(&pdev->dev, |
407 | "failed to get Timer Counter Block channel from device tree (error: %d)\n" , |
408 | err); |
409 | return err; |
410 | } |
411 | |
412 | tcbpwm->regmap = syscon_node_to_regmap(np: np->parent); |
413 | if (IS_ERR(ptr: tcbpwm->regmap)) |
414 | return PTR_ERR(ptr: tcbpwm->regmap); |
415 | |
416 | tcbpwm->slow_clk = of_clk_get_by_name(np: np->parent, name: "slow_clk" ); |
417 | if (IS_ERR(ptr: tcbpwm->slow_clk)) |
418 | return PTR_ERR(ptr: tcbpwm->slow_clk); |
419 | |
420 | clk_name[1] += channel; |
421 | tcbpwm->clk = of_clk_get_by_name(np: np->parent, name: clk_name); |
422 | if (IS_ERR(ptr: tcbpwm->clk)) |
423 | tcbpwm->clk = of_clk_get_by_name(np: np->parent, name: "t0_clk" ); |
424 | if (IS_ERR(ptr: tcbpwm->clk)) { |
425 | err = PTR_ERR(ptr: tcbpwm->clk); |
426 | goto err_slow_clk; |
427 | } |
428 | |
429 | match = of_match_node(matches: atmel_tcb_of_match, node: np->parent); |
430 | config = match->data; |
431 | |
432 | if (config->has_gclk) { |
433 | tcbpwm->gclk = of_clk_get_by_name(np: np->parent, name: "gclk" ); |
434 | if (IS_ERR(ptr: tcbpwm->gclk)) { |
435 | err = PTR_ERR(ptr: tcbpwm->gclk); |
436 | goto err_clk; |
437 | } |
438 | } |
439 | |
440 | tcbpwm->chip.dev = &pdev->dev; |
441 | tcbpwm->chip.ops = &atmel_tcb_pwm_ops; |
442 | tcbpwm->chip.npwm = NPWM; |
443 | tcbpwm->channel = channel; |
444 | tcbpwm->width = config->counter_width; |
445 | |
446 | err = clk_prepare_enable(clk: tcbpwm->slow_clk); |
447 | if (err) |
448 | goto err_gclk; |
449 | |
450 | spin_lock_init(&tcbpwm->lock); |
451 | |
452 | err = pwmchip_add(chip: &tcbpwm->chip); |
453 | if (err < 0) |
454 | goto err_disable_clk; |
455 | |
456 | platform_set_drvdata(pdev, data: tcbpwm); |
457 | |
458 | return 0; |
459 | |
460 | err_disable_clk: |
461 | clk_disable_unprepare(clk: tcbpwm->slow_clk); |
462 | |
463 | err_gclk: |
464 | clk_put(clk: tcbpwm->gclk); |
465 | |
466 | err_clk: |
467 | clk_put(clk: tcbpwm->clk); |
468 | |
469 | err_slow_clk: |
470 | clk_put(clk: tcbpwm->slow_clk); |
471 | |
472 | return err; |
473 | } |
474 | |
475 | static void atmel_tcb_pwm_remove(struct platform_device *pdev) |
476 | { |
477 | struct atmel_tcb_pwm_chip *tcbpwm = platform_get_drvdata(pdev); |
478 | |
479 | pwmchip_remove(chip: &tcbpwm->chip); |
480 | |
481 | clk_disable_unprepare(clk: tcbpwm->slow_clk); |
482 | clk_put(clk: tcbpwm->gclk); |
483 | clk_put(clk: tcbpwm->clk); |
484 | clk_put(clk: tcbpwm->slow_clk); |
485 | } |
486 | |
487 | static const struct of_device_id atmel_tcb_pwm_dt_ids[] = { |
488 | { .compatible = "atmel,tcb-pwm" , }, |
489 | { /* sentinel */ } |
490 | }; |
491 | MODULE_DEVICE_TABLE(of, atmel_tcb_pwm_dt_ids); |
492 | |
493 | #ifdef CONFIG_PM_SLEEP |
494 | static int atmel_tcb_pwm_suspend(struct device *dev) |
495 | { |
496 | struct atmel_tcb_pwm_chip *tcbpwm = dev_get_drvdata(dev); |
497 | struct atmel_tcb_channel *chan = &tcbpwm->bkup; |
498 | unsigned int channel = tcbpwm->channel; |
499 | |
500 | regmap_read(map: tcbpwm->regmap, ATMEL_TC_REG(channel, CMR), val: &chan->cmr); |
501 | regmap_read(map: tcbpwm->regmap, ATMEL_TC_REG(channel, RA), val: &chan->ra); |
502 | regmap_read(map: tcbpwm->regmap, ATMEL_TC_REG(channel, RB), val: &chan->rb); |
503 | regmap_read(map: tcbpwm->regmap, ATMEL_TC_REG(channel, RC), val: &chan->rc); |
504 | |
505 | return 0; |
506 | } |
507 | |
508 | static int atmel_tcb_pwm_resume(struct device *dev) |
509 | { |
510 | struct atmel_tcb_pwm_chip *tcbpwm = dev_get_drvdata(dev); |
511 | struct atmel_tcb_channel *chan = &tcbpwm->bkup; |
512 | unsigned int channel = tcbpwm->channel; |
513 | |
514 | regmap_write(map: tcbpwm->regmap, ATMEL_TC_REG(channel, CMR), val: chan->cmr); |
515 | regmap_write(map: tcbpwm->regmap, ATMEL_TC_REG(channel, RA), val: chan->ra); |
516 | regmap_write(map: tcbpwm->regmap, ATMEL_TC_REG(channel, RB), val: chan->rb); |
517 | regmap_write(map: tcbpwm->regmap, ATMEL_TC_REG(channel, RC), val: chan->rc); |
518 | |
519 | if (chan->enabled) |
520 | regmap_write(map: tcbpwm->regmap, |
521 | ATMEL_TC_CLKEN | ATMEL_TC_SWTRG, |
522 | ATMEL_TC_REG(channel, CCR)); |
523 | |
524 | return 0; |
525 | } |
526 | #endif |
527 | |
528 | static SIMPLE_DEV_PM_OPS(atmel_tcb_pwm_pm_ops, atmel_tcb_pwm_suspend, |
529 | atmel_tcb_pwm_resume); |
530 | |
531 | static struct platform_driver atmel_tcb_pwm_driver = { |
532 | .driver = { |
533 | .name = "atmel-tcb-pwm" , |
534 | .of_match_table = atmel_tcb_pwm_dt_ids, |
535 | .pm = &atmel_tcb_pwm_pm_ops, |
536 | }, |
537 | .probe = atmel_tcb_pwm_probe, |
538 | .remove_new = atmel_tcb_pwm_remove, |
539 | }; |
540 | module_platform_driver(atmel_tcb_pwm_driver); |
541 | |
542 | MODULE_AUTHOR("Boris BREZILLON <b.brezillon@overkiz.com>" ); |
543 | MODULE_DESCRIPTION("Atmel Timer Counter Pulse Width Modulation Driver" ); |
544 | MODULE_LICENSE("GPL v2" ); |
545 | |