1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Driver for Atmel Pulse Width Modulation Controller
4 *
5 * Copyright (C) 2013 Atmel Corporation
6 * Bo Shen <voice.shen@atmel.com>
7 *
8 * Links to reference manuals for the supported PWM chips can be found in
9 * Documentation/arch/arm/microchip.rst.
10 *
11 * Limitations:
12 * - Periods start with the inactive level.
13 * - Hardware has to be stopped in general to update settings.
14 *
15 * Software bugs/possible improvements:
16 * - When atmel_pwm_apply() is called with state->enabled=false a change in
17 * state->polarity isn't honored.
18 * - Instead of sleeping to wait for a completed period, the interrupt
19 * functionality could be used.
20 */
21
22#include <linux/clk.h>
23#include <linux/delay.h>
24#include <linux/err.h>
25#include <linux/io.h>
26#include <linux/module.h>
27#include <linux/of.h>
28#include <linux/platform_device.h>
29#include <linux/pwm.h>
30#include <linux/slab.h>
31
32/* The following is global registers for PWM controller */
33#define PWM_ENA 0x04
34#define PWM_DIS 0x08
35#define PWM_SR 0x0C
36#define PWM_ISR 0x1C
37/* Bit field in SR */
38#define PWM_SR_ALL_CH_MASK 0x0F
39
40/* The following register is PWM channel related registers */
41#define PWM_CH_REG_OFFSET 0x200
42#define PWM_CH_REG_SIZE 0x20
43
44#define PWM_CMR 0x0
45/* Bit field in CMR */
46#define PWM_CMR_CPOL (1 << 9)
47#define PWM_CMR_UPD_CDTY (1 << 10)
48#define PWM_CMR_CPRE_MSK 0xF
49
50/* The following registers for PWM v1 */
51#define PWMV1_CDTY 0x04
52#define PWMV1_CPRD 0x08
53#define PWMV1_CUPD 0x10
54
55/* The following registers for PWM v2 */
56#define PWMV2_CDTY 0x04
57#define PWMV2_CDTYUPD 0x08
58#define PWMV2_CPRD 0x0C
59#define PWMV2_CPRDUPD 0x10
60
61#define PWM_MAX_PRES 10
62
63struct atmel_pwm_registers {
64 u8 period;
65 u8 period_upd;
66 u8 duty;
67 u8 duty_upd;
68};
69
70struct atmel_pwm_config {
71 u32 period_bits;
72};
73
74struct atmel_pwm_data {
75 struct atmel_pwm_registers regs;
76 struct atmel_pwm_config cfg;
77};
78
79struct atmel_pwm_chip {
80 struct pwm_chip chip;
81 struct clk *clk;
82 void __iomem *base;
83 const struct atmel_pwm_data *data;
84
85 /*
86 * The hardware supports a mechanism to update a channel's duty cycle at
87 * the end of the currently running period. When such an update is
88 * pending we delay disabling the PWM until the new configuration is
89 * active because otherwise pmw_config(duty_cycle=0); pwm_disable();
90 * might not result in an inactive output.
91 * This bitmask tracks for which channels an update is pending in
92 * hardware.
93 */
94 u32 update_pending;
95
96 /* Protects .update_pending */
97 spinlock_t lock;
98};
99
100static inline struct atmel_pwm_chip *to_atmel_pwm_chip(struct pwm_chip *chip)
101{
102 return container_of(chip, struct atmel_pwm_chip, chip);
103}
104
105static inline u32 atmel_pwm_readl(struct atmel_pwm_chip *chip,
106 unsigned long offset)
107{
108 return readl_relaxed(chip->base + offset);
109}
110
111static inline void atmel_pwm_writel(struct atmel_pwm_chip *chip,
112 unsigned long offset, unsigned long val)
113{
114 writel_relaxed(val, chip->base + offset);
115}
116
117static inline u32 atmel_pwm_ch_readl(struct atmel_pwm_chip *chip,
118 unsigned int ch, unsigned long offset)
119{
120 unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
121
122 return atmel_pwm_readl(chip, offset: base + offset);
123}
124
125static inline void atmel_pwm_ch_writel(struct atmel_pwm_chip *chip,
126 unsigned int ch, unsigned long offset,
127 unsigned long val)
128{
129 unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
130
131 atmel_pwm_writel(chip, offset: base + offset, val);
132}
133
134static void atmel_pwm_update_pending(struct atmel_pwm_chip *chip)
135{
136 /*
137 * Each channel that has its bit in ISR set started a new period since
138 * ISR was cleared and so there is no more update pending. Note that
139 * reading ISR clears it, so this needs to handle all channels to not
140 * loose information.
141 */
142 u32 isr = atmel_pwm_readl(chip, PWM_ISR);
143
144 chip->update_pending &= ~isr;
145}
146
147static void atmel_pwm_set_pending(struct atmel_pwm_chip *chip, unsigned int ch)
148{
149 spin_lock(lock: &chip->lock);
150
151 /*
152 * Clear pending flags in hardware because otherwise there might still
153 * be a stale flag in ISR.
154 */
155 atmel_pwm_update_pending(chip);
156
157 chip->update_pending |= (1 << ch);
158
159 spin_unlock(lock: &chip->lock);
160}
161
162static int atmel_pwm_test_pending(struct atmel_pwm_chip *chip, unsigned int ch)
163{
164 int ret = 0;
165
166 spin_lock(lock: &chip->lock);
167
168 if (chip->update_pending & (1 << ch)) {
169 atmel_pwm_update_pending(chip);
170
171 if (chip->update_pending & (1 << ch))
172 ret = 1;
173 }
174
175 spin_unlock(lock: &chip->lock);
176
177 return ret;
178}
179
180static int atmel_pwm_wait_nonpending(struct atmel_pwm_chip *chip, unsigned int ch)
181{
182 unsigned long timeout = jiffies + 2 * HZ;
183 int ret;
184
185 while ((ret = atmel_pwm_test_pending(chip, ch)) &&
186 time_before(jiffies, timeout))
187 usleep_range(min: 10, max: 100);
188
189 return ret ? -ETIMEDOUT : 0;
190}
191
192static int atmel_pwm_calculate_cprd_and_pres(struct pwm_chip *chip,
193 unsigned long clkrate,
194 const struct pwm_state *state,
195 unsigned long *cprd, u32 *pres)
196{
197 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
198 unsigned long long cycles = state->period;
199 int shift;
200
201 /* Calculate the period cycles and prescale value */
202 cycles *= clkrate;
203 do_div(cycles, NSEC_PER_SEC);
204
205 /*
206 * The register for the period length is cfg.period_bits bits wide.
207 * So for each bit the number of clock cycles is wider divide the input
208 * clock frequency by two using pres and shift cprd accordingly.
209 */
210 shift = fls(x: cycles) - atmel_pwm->data->cfg.period_bits;
211
212 if (shift > PWM_MAX_PRES) {
213 dev_err(chip->dev, "pres exceeds the maximum value\n");
214 return -EINVAL;
215 } else if (shift > 0) {
216 *pres = shift;
217 cycles >>= *pres;
218 } else {
219 *pres = 0;
220 }
221
222 *cprd = cycles;
223
224 return 0;
225}
226
227static void atmel_pwm_calculate_cdty(const struct pwm_state *state,
228 unsigned long clkrate, unsigned long cprd,
229 u32 pres, unsigned long *cdty)
230{
231 unsigned long long cycles = state->duty_cycle;
232
233 cycles *= clkrate;
234 do_div(cycles, NSEC_PER_SEC);
235 cycles >>= pres;
236 *cdty = cprd - cycles;
237}
238
239static void atmel_pwm_update_cdty(struct pwm_chip *chip, struct pwm_device *pwm,
240 unsigned long cdty)
241{
242 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
243 u32 val;
244
245 if (atmel_pwm->data->regs.duty_upd ==
246 atmel_pwm->data->regs.period_upd) {
247 val = atmel_pwm_ch_readl(chip: atmel_pwm, ch: pwm->hwpwm, PWM_CMR);
248 val &= ~PWM_CMR_UPD_CDTY;
249 atmel_pwm_ch_writel(chip: atmel_pwm, ch: pwm->hwpwm, PWM_CMR, val);
250 }
251
252 atmel_pwm_ch_writel(chip: atmel_pwm, ch: pwm->hwpwm,
253 offset: atmel_pwm->data->regs.duty_upd, val: cdty);
254 atmel_pwm_set_pending(chip: atmel_pwm, ch: pwm->hwpwm);
255}
256
257static void atmel_pwm_set_cprd_cdty(struct pwm_chip *chip,
258 struct pwm_device *pwm,
259 unsigned long cprd, unsigned long cdty)
260{
261 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
262
263 atmel_pwm_ch_writel(chip: atmel_pwm, ch: pwm->hwpwm,
264 offset: atmel_pwm->data->regs.duty, val: cdty);
265 atmel_pwm_ch_writel(chip: atmel_pwm, ch: pwm->hwpwm,
266 offset: atmel_pwm->data->regs.period, val: cprd);
267}
268
269static void atmel_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm,
270 bool disable_clk)
271{
272 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
273 unsigned long timeout;
274
275 atmel_pwm_wait_nonpending(chip: atmel_pwm, ch: pwm->hwpwm);
276
277 atmel_pwm_writel(chip: atmel_pwm, PWM_DIS, val: 1 << pwm->hwpwm);
278
279 /*
280 * Wait for the PWM channel disable operation to be effective before
281 * stopping the clock.
282 */
283 timeout = jiffies + 2 * HZ;
284
285 while ((atmel_pwm_readl(chip: atmel_pwm, PWM_SR) & (1 << pwm->hwpwm)) &&
286 time_before(jiffies, timeout))
287 usleep_range(min: 10, max: 100);
288
289 if (disable_clk)
290 clk_disable(clk: atmel_pwm->clk);
291}
292
293static int atmel_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
294 const struct pwm_state *state)
295{
296 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
297 struct pwm_state cstate;
298 unsigned long cprd, cdty;
299 u32 pres, val;
300 int ret;
301
302 pwm_get_state(pwm, state: &cstate);
303
304 if (state->enabled) {
305 unsigned long clkrate = clk_get_rate(clk: atmel_pwm->clk);
306
307 if (cstate.enabled &&
308 cstate.polarity == state->polarity &&
309 cstate.period == state->period) {
310 u32 cmr = atmel_pwm_ch_readl(chip: atmel_pwm, ch: pwm->hwpwm, PWM_CMR);
311
312 cprd = atmel_pwm_ch_readl(chip: atmel_pwm, ch: pwm->hwpwm,
313 offset: atmel_pwm->data->regs.period);
314 pres = cmr & PWM_CMR_CPRE_MSK;
315
316 atmel_pwm_calculate_cdty(state, clkrate, cprd, pres, cdty: &cdty);
317 atmel_pwm_update_cdty(chip, pwm, cdty);
318 return 0;
319 }
320
321 ret = atmel_pwm_calculate_cprd_and_pres(chip, clkrate, state, cprd: &cprd,
322 pres: &pres);
323 if (ret) {
324 dev_err(chip->dev,
325 "failed to calculate cprd and prescaler\n");
326 return ret;
327 }
328
329 atmel_pwm_calculate_cdty(state, clkrate, cprd, pres, cdty: &cdty);
330
331 if (cstate.enabled) {
332 atmel_pwm_disable(chip, pwm, disable_clk: false);
333 } else {
334 ret = clk_enable(clk: atmel_pwm->clk);
335 if (ret) {
336 dev_err(chip->dev, "failed to enable clock\n");
337 return ret;
338 }
339 }
340
341 /* It is necessary to preserve CPOL, inside CMR */
342 val = atmel_pwm_ch_readl(chip: atmel_pwm, ch: pwm->hwpwm, PWM_CMR);
343 val = (val & ~PWM_CMR_CPRE_MSK) | (pres & PWM_CMR_CPRE_MSK);
344 if (state->polarity == PWM_POLARITY_NORMAL)
345 val &= ~PWM_CMR_CPOL;
346 else
347 val |= PWM_CMR_CPOL;
348 atmel_pwm_ch_writel(chip: atmel_pwm, ch: pwm->hwpwm, PWM_CMR, val);
349 atmel_pwm_set_cprd_cdty(chip, pwm, cprd, cdty);
350 atmel_pwm_writel(chip: atmel_pwm, PWM_ENA, val: 1 << pwm->hwpwm);
351 } else if (cstate.enabled) {
352 atmel_pwm_disable(chip, pwm, disable_clk: true);
353 }
354
355 return 0;
356}
357
358static int atmel_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
359 struct pwm_state *state)
360{
361 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
362 u32 sr, cmr;
363
364 sr = atmel_pwm_readl(chip: atmel_pwm, PWM_SR);
365 cmr = atmel_pwm_ch_readl(chip: atmel_pwm, ch: pwm->hwpwm, PWM_CMR);
366
367 if (sr & (1 << pwm->hwpwm)) {
368 unsigned long rate = clk_get_rate(clk: atmel_pwm->clk);
369 u32 cdty, cprd, pres;
370 u64 tmp;
371
372 pres = cmr & PWM_CMR_CPRE_MSK;
373
374 cprd = atmel_pwm_ch_readl(chip: atmel_pwm, ch: pwm->hwpwm,
375 offset: atmel_pwm->data->regs.period);
376 tmp = (u64)cprd * NSEC_PER_SEC;
377 tmp <<= pres;
378 state->period = DIV64_U64_ROUND_UP(tmp, rate);
379
380 /* Wait for an updated duty_cycle queued in hardware */
381 atmel_pwm_wait_nonpending(chip: atmel_pwm, ch: pwm->hwpwm);
382
383 cdty = atmel_pwm_ch_readl(chip: atmel_pwm, ch: pwm->hwpwm,
384 offset: atmel_pwm->data->regs.duty);
385 tmp = (u64)(cprd - cdty) * NSEC_PER_SEC;
386 tmp <<= pres;
387 state->duty_cycle = DIV64_U64_ROUND_UP(tmp, rate);
388
389 state->enabled = true;
390 } else {
391 state->enabled = false;
392 }
393
394 if (cmr & PWM_CMR_CPOL)
395 state->polarity = PWM_POLARITY_INVERSED;
396 else
397 state->polarity = PWM_POLARITY_NORMAL;
398
399 return 0;
400}
401
402static const struct pwm_ops atmel_pwm_ops = {
403 .apply = atmel_pwm_apply,
404 .get_state = atmel_pwm_get_state,
405 .owner = THIS_MODULE,
406};
407
408static const struct atmel_pwm_data atmel_sam9rl_pwm_data = {
409 .regs = {
410 .period = PWMV1_CPRD,
411 .period_upd = PWMV1_CUPD,
412 .duty = PWMV1_CDTY,
413 .duty_upd = PWMV1_CUPD,
414 },
415 .cfg = {
416 /* 16 bits to keep period and duty. */
417 .period_bits = 16,
418 },
419};
420
421static const struct atmel_pwm_data atmel_sama5_pwm_data = {
422 .regs = {
423 .period = PWMV2_CPRD,
424 .period_upd = PWMV2_CPRDUPD,
425 .duty = PWMV2_CDTY,
426 .duty_upd = PWMV2_CDTYUPD,
427 },
428 .cfg = {
429 /* 16 bits to keep period and duty. */
430 .period_bits = 16,
431 },
432};
433
434static const struct atmel_pwm_data mchp_sam9x60_pwm_data = {
435 .regs = {
436 .period = PWMV1_CPRD,
437 .period_upd = PWMV1_CUPD,
438 .duty = PWMV1_CDTY,
439 .duty_upd = PWMV1_CUPD,
440 },
441 .cfg = {
442 /* 32 bits to keep period and duty. */
443 .period_bits = 32,
444 },
445};
446
447static const struct of_device_id atmel_pwm_dt_ids[] = {
448 {
449 .compatible = "atmel,at91sam9rl-pwm",
450 .data = &atmel_sam9rl_pwm_data,
451 }, {
452 .compatible = "atmel,sama5d3-pwm",
453 .data = &atmel_sama5_pwm_data,
454 }, {
455 .compatible = "atmel,sama5d2-pwm",
456 .data = &atmel_sama5_pwm_data,
457 }, {
458 .compatible = "microchip,sam9x60-pwm",
459 .data = &mchp_sam9x60_pwm_data,
460 }, {
461 /* sentinel */
462 },
463};
464MODULE_DEVICE_TABLE(of, atmel_pwm_dt_ids);
465
466static int atmel_pwm_enable_clk_if_on(struct atmel_pwm_chip *atmel_pwm, bool on)
467{
468 unsigned int i, cnt = 0;
469 unsigned long sr;
470 int ret = 0;
471
472 sr = atmel_pwm_readl(chip: atmel_pwm, PWM_SR) & PWM_SR_ALL_CH_MASK;
473 if (!sr)
474 return 0;
475
476 cnt = bitmap_weight(src: &sr, nbits: atmel_pwm->chip.npwm);
477
478 if (!on)
479 goto disable_clk;
480
481 for (i = 0; i < cnt; i++) {
482 ret = clk_enable(clk: atmel_pwm->clk);
483 if (ret) {
484 dev_err(atmel_pwm->chip.dev,
485 "failed to enable clock for pwm %pe\n",
486 ERR_PTR(ret));
487
488 cnt = i;
489 goto disable_clk;
490 }
491 }
492
493 return 0;
494
495disable_clk:
496 while (cnt--)
497 clk_disable(clk: atmel_pwm->clk);
498
499 return ret;
500}
501
502static int atmel_pwm_probe(struct platform_device *pdev)
503{
504 struct atmel_pwm_chip *atmel_pwm;
505 int ret;
506
507 atmel_pwm = devm_kzalloc(dev: &pdev->dev, size: sizeof(*atmel_pwm), GFP_KERNEL);
508 if (!atmel_pwm)
509 return -ENOMEM;
510
511 atmel_pwm->data = of_device_get_match_data(dev: &pdev->dev);
512
513 atmel_pwm->update_pending = 0;
514 spin_lock_init(&atmel_pwm->lock);
515
516 atmel_pwm->base = devm_platform_ioremap_resource(pdev, index: 0);
517 if (IS_ERR(ptr: atmel_pwm->base))
518 return PTR_ERR(ptr: atmel_pwm->base);
519
520 atmel_pwm->clk = devm_clk_get_prepared(dev: &pdev->dev, NULL);
521 if (IS_ERR(ptr: atmel_pwm->clk))
522 return dev_err_probe(dev: &pdev->dev, err: PTR_ERR(ptr: atmel_pwm->clk),
523 fmt: "failed to get prepared PWM clock\n");
524
525 atmel_pwm->chip.dev = &pdev->dev;
526 atmel_pwm->chip.ops = &atmel_pwm_ops;
527 atmel_pwm->chip.npwm = 4;
528
529 ret = atmel_pwm_enable_clk_if_on(atmel_pwm, on: true);
530 if (ret < 0)
531 return ret;
532
533 ret = devm_pwmchip_add(dev: &pdev->dev, chip: &atmel_pwm->chip);
534 if (ret < 0) {
535 dev_err_probe(dev: &pdev->dev, err: ret, fmt: "failed to add PWM chip\n");
536 goto disable_clk;
537 }
538
539 return 0;
540
541disable_clk:
542 atmel_pwm_enable_clk_if_on(atmel_pwm, on: false);
543
544 return ret;
545}
546
547static struct platform_driver atmel_pwm_driver = {
548 .driver = {
549 .name = "atmel-pwm",
550 .of_match_table = of_match_ptr(atmel_pwm_dt_ids),
551 },
552 .probe = atmel_pwm_probe,
553};
554module_platform_driver(atmel_pwm_driver);
555
556MODULE_ALIAS("platform:atmel-pwm");
557MODULE_AUTHOR("Bo Shen <voice.shen@atmel.com>");
558MODULE_DESCRIPTION("Atmel PWM driver");
559MODULE_LICENSE("GPL v2");
560

source code of linux/drivers/pwm/pwm-atmel.c