1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * STM32 Low-Power Timer PWM driver |
4 | * |
5 | * Copyright (C) STMicroelectronics 2017 |
6 | * |
7 | * Author: Gerald Baeza <gerald.baeza@st.com> |
8 | * |
9 | * Inspired by Gerald Baeza's pwm-stm32 driver |
10 | */ |
11 | |
12 | #include <linux/bitfield.h> |
13 | #include <linux/mfd/stm32-lptimer.h> |
14 | #include <linux/module.h> |
15 | #include <linux/of.h> |
16 | #include <linux/pinctrl/consumer.h> |
17 | #include <linux/platform_device.h> |
18 | #include <linux/pwm.h> |
19 | |
20 | struct stm32_pwm_lp { |
21 | struct pwm_chip chip; |
22 | struct clk *clk; |
23 | struct regmap *regmap; |
24 | }; |
25 | |
26 | static inline struct stm32_pwm_lp *to_stm32_pwm_lp(struct pwm_chip *chip) |
27 | { |
28 | return container_of(chip, struct stm32_pwm_lp, chip); |
29 | } |
30 | |
31 | /* STM32 Low-Power Timer is preceded by a configurable power-of-2 prescaler */ |
32 | #define STM32_LPTIM_MAX_PRESCALER 128 |
33 | |
34 | static int stm32_pwm_lp_apply(struct pwm_chip *chip, struct pwm_device *pwm, |
35 | const struct pwm_state *state) |
36 | { |
37 | struct stm32_pwm_lp *priv = to_stm32_pwm_lp(chip); |
38 | unsigned long long prd, div, dty; |
39 | struct pwm_state cstate; |
40 | u32 val, mask, cfgr, presc = 0; |
41 | bool reenable; |
42 | int ret; |
43 | |
44 | pwm_get_state(pwm, state: &cstate); |
45 | reenable = !cstate.enabled; |
46 | |
47 | if (!state->enabled) { |
48 | if (cstate.enabled) { |
49 | /* Disable LP timer */ |
50 | ret = regmap_write(map: priv->regmap, STM32_LPTIM_CR, val: 0); |
51 | if (ret) |
52 | return ret; |
53 | /* disable clock to PWM counter */ |
54 | clk_disable(clk: priv->clk); |
55 | } |
56 | return 0; |
57 | } |
58 | |
59 | /* Calculate the period and prescaler value */ |
60 | div = (unsigned long long)clk_get_rate(clk: priv->clk) * state->period; |
61 | do_div(div, NSEC_PER_SEC); |
62 | if (!div) { |
63 | /* Clock is too slow to achieve requested period. */ |
64 | dev_dbg(priv->chip.dev, "Can't reach %llu ns\n" , state->period); |
65 | return -EINVAL; |
66 | } |
67 | |
68 | prd = div; |
69 | while (div > STM32_LPTIM_MAX_ARR) { |
70 | presc++; |
71 | if ((1 << presc) > STM32_LPTIM_MAX_PRESCALER) { |
72 | dev_err(priv->chip.dev, "max prescaler exceeded\n" ); |
73 | return -EINVAL; |
74 | } |
75 | div = prd >> presc; |
76 | } |
77 | prd = div; |
78 | |
79 | /* Calculate the duty cycle */ |
80 | dty = prd * state->duty_cycle; |
81 | do_div(dty, state->period); |
82 | |
83 | if (!cstate.enabled) { |
84 | /* enable clock to drive PWM counter */ |
85 | ret = clk_enable(clk: priv->clk); |
86 | if (ret) |
87 | return ret; |
88 | } |
89 | |
90 | ret = regmap_read(map: priv->regmap, STM32_LPTIM_CFGR, val: &cfgr); |
91 | if (ret) |
92 | goto err; |
93 | |
94 | if ((FIELD_GET(STM32_LPTIM_PRESC, cfgr) != presc) || |
95 | (FIELD_GET(STM32_LPTIM_WAVPOL, cfgr) != state->polarity)) { |
96 | val = FIELD_PREP(STM32_LPTIM_PRESC, presc); |
97 | val |= FIELD_PREP(STM32_LPTIM_WAVPOL, state->polarity); |
98 | mask = STM32_LPTIM_PRESC | STM32_LPTIM_WAVPOL; |
99 | |
100 | /* Must disable LP timer to modify CFGR */ |
101 | reenable = true; |
102 | ret = regmap_write(map: priv->regmap, STM32_LPTIM_CR, val: 0); |
103 | if (ret) |
104 | goto err; |
105 | |
106 | ret = regmap_update_bits(map: priv->regmap, STM32_LPTIM_CFGR, mask, |
107 | val); |
108 | if (ret) |
109 | goto err; |
110 | } |
111 | |
112 | if (reenable) { |
113 | /* Must (re)enable LP timer to modify CMP & ARR */ |
114 | ret = regmap_write(map: priv->regmap, STM32_LPTIM_CR, |
115 | STM32_LPTIM_ENABLE); |
116 | if (ret) |
117 | goto err; |
118 | } |
119 | |
120 | ret = regmap_write(map: priv->regmap, STM32_LPTIM_ARR, val: prd - 1); |
121 | if (ret) |
122 | goto err; |
123 | |
124 | ret = regmap_write(map: priv->regmap, STM32_LPTIM_CMP, val: prd - (1 + dty)); |
125 | if (ret) |
126 | goto err; |
127 | |
128 | /* ensure CMP & ARR registers are properly written */ |
129 | ret = regmap_read_poll_timeout(priv->regmap, STM32_LPTIM_ISR, val, |
130 | (val & STM32_LPTIM_CMPOK_ARROK) == STM32_LPTIM_CMPOK_ARROK, |
131 | 100, 1000); |
132 | if (ret) { |
133 | dev_err(priv->chip.dev, "ARR/CMP registers write issue\n" ); |
134 | goto err; |
135 | } |
136 | ret = regmap_write(map: priv->regmap, STM32_LPTIM_ICR, |
137 | STM32_LPTIM_CMPOKCF_ARROKCF); |
138 | if (ret) |
139 | goto err; |
140 | |
141 | if (reenable) { |
142 | /* Start LP timer in continuous mode */ |
143 | ret = regmap_set_bits(map: priv->regmap, STM32_LPTIM_CR, |
144 | STM32_LPTIM_CNTSTRT); |
145 | if (ret) { |
146 | regmap_write(map: priv->regmap, STM32_LPTIM_CR, val: 0); |
147 | goto err; |
148 | } |
149 | } |
150 | |
151 | return 0; |
152 | err: |
153 | if (!cstate.enabled) |
154 | clk_disable(clk: priv->clk); |
155 | |
156 | return ret; |
157 | } |
158 | |
159 | static int stm32_pwm_lp_get_state(struct pwm_chip *chip, |
160 | struct pwm_device *pwm, |
161 | struct pwm_state *state) |
162 | { |
163 | struct stm32_pwm_lp *priv = to_stm32_pwm_lp(chip); |
164 | unsigned long rate = clk_get_rate(clk: priv->clk); |
165 | u32 val, presc, prd; |
166 | u64 tmp; |
167 | |
168 | regmap_read(map: priv->regmap, STM32_LPTIM_CR, val: &val); |
169 | state->enabled = !!FIELD_GET(STM32_LPTIM_ENABLE, val); |
170 | /* Keep PWM counter clock refcount in sync with PWM initial state */ |
171 | if (state->enabled) |
172 | clk_enable(clk: priv->clk); |
173 | |
174 | regmap_read(map: priv->regmap, STM32_LPTIM_CFGR, val: &val); |
175 | presc = FIELD_GET(STM32_LPTIM_PRESC, val); |
176 | state->polarity = FIELD_GET(STM32_LPTIM_WAVPOL, val); |
177 | |
178 | regmap_read(map: priv->regmap, STM32_LPTIM_ARR, val: &prd); |
179 | tmp = prd + 1; |
180 | tmp = (tmp << presc) * NSEC_PER_SEC; |
181 | state->period = DIV_ROUND_CLOSEST_ULL(tmp, rate); |
182 | |
183 | regmap_read(map: priv->regmap, STM32_LPTIM_CMP, val: &val); |
184 | tmp = prd - val; |
185 | tmp = (tmp << presc) * NSEC_PER_SEC; |
186 | state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, rate); |
187 | |
188 | return 0; |
189 | } |
190 | |
191 | static const struct pwm_ops stm32_pwm_lp_ops = { |
192 | .owner = THIS_MODULE, |
193 | .apply = stm32_pwm_lp_apply, |
194 | .get_state = stm32_pwm_lp_get_state, |
195 | }; |
196 | |
197 | static int stm32_pwm_lp_probe(struct platform_device *pdev) |
198 | { |
199 | struct stm32_lptimer *ddata = dev_get_drvdata(dev: pdev->dev.parent); |
200 | struct stm32_pwm_lp *priv; |
201 | int ret; |
202 | |
203 | priv = devm_kzalloc(dev: &pdev->dev, size: sizeof(*priv), GFP_KERNEL); |
204 | if (!priv) |
205 | return -ENOMEM; |
206 | |
207 | priv->regmap = ddata->regmap; |
208 | priv->clk = ddata->clk; |
209 | priv->chip.dev = &pdev->dev; |
210 | priv->chip.ops = &stm32_pwm_lp_ops; |
211 | priv->chip.npwm = 1; |
212 | |
213 | ret = devm_pwmchip_add(dev: &pdev->dev, chip: &priv->chip); |
214 | if (ret < 0) |
215 | return ret; |
216 | |
217 | platform_set_drvdata(pdev, data: priv); |
218 | |
219 | return 0; |
220 | } |
221 | |
222 | static int __maybe_unused stm32_pwm_lp_suspend(struct device *dev) |
223 | { |
224 | struct stm32_pwm_lp *priv = dev_get_drvdata(dev); |
225 | struct pwm_state state; |
226 | |
227 | pwm_get_state(pwm: &priv->chip.pwms[0], state: &state); |
228 | if (state.enabled) { |
229 | dev_err(dev, "The consumer didn't stop us (%s)\n" , |
230 | priv->chip.pwms[0].label); |
231 | return -EBUSY; |
232 | } |
233 | |
234 | return pinctrl_pm_select_sleep_state(dev); |
235 | } |
236 | |
237 | static int __maybe_unused stm32_pwm_lp_resume(struct device *dev) |
238 | { |
239 | return pinctrl_pm_select_default_state(dev); |
240 | } |
241 | |
242 | static SIMPLE_DEV_PM_OPS(stm32_pwm_lp_pm_ops, stm32_pwm_lp_suspend, |
243 | stm32_pwm_lp_resume); |
244 | |
245 | static const struct of_device_id stm32_pwm_lp_of_match[] = { |
246 | { .compatible = "st,stm32-pwm-lp" , }, |
247 | {}, |
248 | }; |
249 | MODULE_DEVICE_TABLE(of, stm32_pwm_lp_of_match); |
250 | |
251 | static struct platform_driver stm32_pwm_lp_driver = { |
252 | .probe = stm32_pwm_lp_probe, |
253 | .driver = { |
254 | .name = "stm32-pwm-lp" , |
255 | .of_match_table = stm32_pwm_lp_of_match, |
256 | .pm = &stm32_pwm_lp_pm_ops, |
257 | }, |
258 | }; |
259 | module_platform_driver(stm32_pwm_lp_driver); |
260 | |
261 | MODULE_ALIAS("platform:stm32-pwm-lp" ); |
262 | MODULE_DESCRIPTION("STMicroelectronics STM32 PWM LP driver" ); |
263 | MODULE_LICENSE("GPL v2" ); |
264 | |