1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Copyright (C) 2016 Linaro Ltd. |
4 | * |
5 | * Author: Linus Walleij <linus.walleij@linaro.org> |
6 | */ |
7 | |
8 | #include <linux/bitops.h> |
9 | #include <linux/delay.h> |
10 | #include <linux/err.h> |
11 | #include <linux/mfd/stmpe.h> |
12 | #include <linux/module.h> |
13 | #include <linux/of.h> |
14 | #include <linux/platform_device.h> |
15 | #include <linux/pwm.h> |
16 | #include <linux/slab.h> |
17 | |
18 | #define STMPE24XX_PWMCS 0x30 |
19 | #define PWMCS_EN_PWM0 BIT(0) |
20 | #define PWMCS_EN_PWM1 BIT(1) |
21 | #define PWMCS_EN_PWM2 BIT(2) |
22 | #define STMPE24XX_PWMIC0 0x38 |
23 | #define STMPE24XX_PWMIC1 0x39 |
24 | #define STMPE24XX_PWMIC2 0x3a |
25 | |
26 | #define STMPE_PWM_24XX_PINBASE 21 |
27 | |
28 | struct stmpe_pwm { |
29 | struct stmpe *stmpe; |
30 | struct pwm_chip chip; |
31 | u8 last_duty; |
32 | }; |
33 | |
34 | static inline struct stmpe_pwm *to_stmpe_pwm(struct pwm_chip *chip) |
35 | { |
36 | return container_of(chip, struct stmpe_pwm, chip); |
37 | } |
38 | |
39 | static int stmpe_24xx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) |
40 | { |
41 | struct stmpe_pwm *stmpe_pwm = to_stmpe_pwm(chip); |
42 | u8 value; |
43 | int ret; |
44 | |
45 | ret = stmpe_reg_read(stmpe: stmpe_pwm->stmpe, STMPE24XX_PWMCS); |
46 | if (ret < 0) { |
47 | dev_err(chip->dev, "error reading PWM#%u control\n" , |
48 | pwm->hwpwm); |
49 | return ret; |
50 | } |
51 | |
52 | value = ret | BIT(pwm->hwpwm); |
53 | |
54 | ret = stmpe_reg_write(stmpe: stmpe_pwm->stmpe, STMPE24XX_PWMCS, data: value); |
55 | if (ret) { |
56 | dev_err(chip->dev, "error writing PWM#%u control\n" , |
57 | pwm->hwpwm); |
58 | return ret; |
59 | } |
60 | |
61 | return 0; |
62 | } |
63 | |
64 | static int stmpe_24xx_pwm_disable(struct pwm_chip *chip, |
65 | struct pwm_device *pwm) |
66 | { |
67 | struct stmpe_pwm *stmpe_pwm = to_stmpe_pwm(chip); |
68 | u8 value; |
69 | int ret; |
70 | |
71 | ret = stmpe_reg_read(stmpe: stmpe_pwm->stmpe, STMPE24XX_PWMCS); |
72 | if (ret < 0) { |
73 | dev_err(chip->dev, "error reading PWM#%u control\n" , |
74 | pwm->hwpwm); |
75 | return ret; |
76 | } |
77 | |
78 | value = ret & ~BIT(pwm->hwpwm); |
79 | |
80 | ret = stmpe_reg_write(stmpe: stmpe_pwm->stmpe, STMPE24XX_PWMCS, data: value); |
81 | if (ret) |
82 | dev_err(chip->dev, "error writing PWM#%u control\n" , |
83 | pwm->hwpwm); |
84 | return ret; |
85 | } |
86 | |
87 | /* STMPE 24xx PWM instructions */ |
88 | #define SMAX 0x007f |
89 | #define SMIN 0x00ff |
90 | #define GTS 0x0000 |
91 | #define LOAD BIT(14) /* Only available on 2403 */ |
92 | #define RAMPUP 0x0000 |
93 | #define RAMPDOWN BIT(7) |
94 | #define PRESCALE_512 BIT(14) |
95 | #define STEPTIME_1 BIT(8) |
96 | #define BRANCH (BIT(15) | BIT(13)) |
97 | |
98 | static int stmpe_24xx_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, |
99 | int duty_ns, int period_ns) |
100 | { |
101 | struct stmpe_pwm *stmpe_pwm = to_stmpe_pwm(chip); |
102 | unsigned int i, pin; |
103 | u16 program[3] = { |
104 | SMAX, |
105 | GTS, |
106 | GTS, |
107 | }; |
108 | u8 offset; |
109 | int ret; |
110 | |
111 | /* Make sure we are disabled */ |
112 | if (pwm_is_enabled(pwm)) { |
113 | ret = stmpe_24xx_pwm_disable(chip, pwm); |
114 | if (ret) |
115 | return ret; |
116 | } else { |
117 | /* Connect the PWM to the pin */ |
118 | pin = pwm->hwpwm; |
119 | |
120 | /* On STMPE2401 and 2403 pins 21,22,23 are used */ |
121 | if (stmpe_pwm->stmpe->partnum == STMPE2401 || |
122 | stmpe_pwm->stmpe->partnum == STMPE2403) |
123 | pin += STMPE_PWM_24XX_PINBASE; |
124 | |
125 | ret = stmpe_set_altfunc(stmpe: stmpe_pwm->stmpe, BIT(pin), |
126 | block: STMPE_BLOCK_PWM); |
127 | if (ret) { |
128 | dev_err(chip->dev, "unable to connect PWM#%u to pin\n" , |
129 | pwm->hwpwm); |
130 | return ret; |
131 | } |
132 | } |
133 | |
134 | /* STMPE24XX */ |
135 | switch (pwm->hwpwm) { |
136 | case 0: |
137 | offset = STMPE24XX_PWMIC0; |
138 | break; |
139 | |
140 | case 1: |
141 | offset = STMPE24XX_PWMIC1; |
142 | break; |
143 | |
144 | case 2: |
145 | offset = STMPE24XX_PWMIC2; |
146 | break; |
147 | |
148 | default: |
149 | /* Should not happen as npwm is 3 */ |
150 | return -ENODEV; |
151 | } |
152 | |
153 | dev_dbg(chip->dev, "PWM#%u: config duty %d ns, period %d ns\n" , |
154 | pwm->hwpwm, duty_ns, period_ns); |
155 | |
156 | if (duty_ns == 0) { |
157 | if (stmpe_pwm->stmpe->partnum == STMPE2401) |
158 | program[0] = SMAX; /* off all the time */ |
159 | |
160 | if (stmpe_pwm->stmpe->partnum == STMPE2403) |
161 | program[0] = LOAD | 0xff; /* LOAD 0xff */ |
162 | |
163 | stmpe_pwm->last_duty = 0x00; |
164 | } else if (duty_ns == period_ns) { |
165 | if (stmpe_pwm->stmpe->partnum == STMPE2401) |
166 | program[0] = SMIN; /* on all the time */ |
167 | |
168 | if (stmpe_pwm->stmpe->partnum == STMPE2403) |
169 | program[0] = LOAD | 0x00; /* LOAD 0x00 */ |
170 | |
171 | stmpe_pwm->last_duty = 0xff; |
172 | } else { |
173 | u8 value, last = stmpe_pwm->last_duty; |
174 | unsigned long duty; |
175 | |
176 | /* |
177 | * Counter goes from 0x00 to 0xff repeatedly at 32768 Hz, |
178 | * (means a period of 30517 ns) then this is compared to the |
179 | * counter from the ramp, if this is >= PWM counter the output |
180 | * is high. With LOAD we can define how much of the cycle it |
181 | * is on. |
182 | * |
183 | * Prescale = 0 -> 2 kHz -> T = 1/f = 488281.25 ns |
184 | */ |
185 | |
186 | /* Scale to 0..0xff */ |
187 | duty = duty_ns * 256; |
188 | duty = DIV_ROUND_CLOSEST(duty, period_ns); |
189 | value = duty; |
190 | |
191 | if (value == last) { |
192 | /* Run the old program */ |
193 | if (pwm_is_enabled(pwm)) |
194 | stmpe_24xx_pwm_enable(chip, pwm); |
195 | |
196 | return 0; |
197 | } else if (stmpe_pwm->stmpe->partnum == STMPE2403) { |
198 | /* STMPE2403 can simply set the right PWM value */ |
199 | program[0] = LOAD | value; |
200 | program[1] = 0x0000; |
201 | } else if (stmpe_pwm->stmpe->partnum == STMPE2401) { |
202 | /* STMPE2401 need a complex program */ |
203 | u16 incdec = 0x0000; |
204 | |
205 | if (last < value) |
206 | /* Count up */ |
207 | incdec = RAMPUP | (value - last); |
208 | else |
209 | /* Count down */ |
210 | incdec = RAMPDOWN | (last - value); |
211 | |
212 | /* Step to desired value, smoothly */ |
213 | program[0] = PRESCALE_512 | STEPTIME_1 | incdec; |
214 | |
215 | /* Loop eternally to 0x00 */ |
216 | program[1] = BRANCH; |
217 | } |
218 | |
219 | dev_dbg(chip->dev, |
220 | "PWM#%u: value = %02x, last_duty = %02x, program=%04x,%04x,%04x\n" , |
221 | pwm->hwpwm, value, last, program[0], program[1], |
222 | program[2]); |
223 | stmpe_pwm->last_duty = value; |
224 | } |
225 | |
226 | /* |
227 | * We can write programs of up to 64 16-bit words into this channel. |
228 | */ |
229 | for (i = 0; i < ARRAY_SIZE(program); i++) { |
230 | u8 value; |
231 | |
232 | value = (program[i] >> 8) & 0xff; |
233 | |
234 | ret = stmpe_reg_write(stmpe: stmpe_pwm->stmpe, reg: offset, data: value); |
235 | if (ret) { |
236 | dev_err(chip->dev, "error writing register %02x: %d\n" , |
237 | offset, ret); |
238 | return ret; |
239 | } |
240 | |
241 | value = program[i] & 0xff; |
242 | |
243 | ret = stmpe_reg_write(stmpe: stmpe_pwm->stmpe, reg: offset, data: value); |
244 | if (ret) { |
245 | dev_err(chip->dev, "error writing register %02x: %d\n" , |
246 | offset, ret); |
247 | return ret; |
248 | } |
249 | } |
250 | |
251 | /* If we were enabled, re-enable this PWM */ |
252 | if (pwm_is_enabled(pwm)) |
253 | stmpe_24xx_pwm_enable(chip, pwm); |
254 | |
255 | /* Sleep for 200ms so we're sure it will take effect */ |
256 | msleep(msecs: 200); |
257 | |
258 | dev_dbg(chip->dev, "programmed PWM#%u, %u bytes\n" , pwm->hwpwm, i); |
259 | |
260 | return 0; |
261 | } |
262 | |
263 | static int stmpe_24xx_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, |
264 | const struct pwm_state *state) |
265 | { |
266 | int err; |
267 | |
268 | if (state->polarity != PWM_POLARITY_NORMAL) |
269 | return -EINVAL; |
270 | |
271 | if (!state->enabled) { |
272 | if (pwm->state.enabled) |
273 | return stmpe_24xx_pwm_disable(chip, pwm); |
274 | |
275 | return 0; |
276 | } |
277 | |
278 | err = stmpe_24xx_pwm_config(chip: pwm->chip, pwm, duty_ns: state->duty_cycle, period_ns: state->period); |
279 | if (err) |
280 | return err; |
281 | |
282 | if (!pwm->state.enabled) |
283 | err = stmpe_24xx_pwm_enable(chip, pwm); |
284 | |
285 | return err; |
286 | } |
287 | |
288 | static const struct pwm_ops stmpe_24xx_pwm_ops = { |
289 | .apply = stmpe_24xx_pwm_apply, |
290 | .owner = THIS_MODULE, |
291 | }; |
292 | |
293 | static int __init stmpe_pwm_probe(struct platform_device *pdev) |
294 | { |
295 | struct stmpe *stmpe = dev_get_drvdata(dev: pdev->dev.parent); |
296 | struct stmpe_pwm *stmpe_pwm; |
297 | int ret; |
298 | |
299 | stmpe_pwm = devm_kzalloc(dev: &pdev->dev, size: sizeof(*stmpe_pwm), GFP_KERNEL); |
300 | if (!stmpe_pwm) |
301 | return -ENOMEM; |
302 | |
303 | stmpe_pwm->stmpe = stmpe; |
304 | stmpe_pwm->chip.dev = &pdev->dev; |
305 | |
306 | if (stmpe->partnum == STMPE2401 || stmpe->partnum == STMPE2403) { |
307 | stmpe_pwm->chip.ops = &stmpe_24xx_pwm_ops; |
308 | stmpe_pwm->chip.npwm = 3; |
309 | } else { |
310 | if (stmpe->partnum == STMPE1601) |
311 | dev_err(&pdev->dev, "STMPE1601 not yet supported\n" ); |
312 | else |
313 | dev_err(&pdev->dev, "Unknown STMPE PWM\n" ); |
314 | |
315 | return -ENODEV; |
316 | } |
317 | |
318 | ret = stmpe_enable(stmpe, blocks: STMPE_BLOCK_PWM); |
319 | if (ret) |
320 | return ret; |
321 | |
322 | ret = pwmchip_add(chip: &stmpe_pwm->chip); |
323 | if (ret) { |
324 | stmpe_disable(stmpe, blocks: STMPE_BLOCK_PWM); |
325 | return ret; |
326 | } |
327 | |
328 | return 0; |
329 | } |
330 | |
331 | static struct platform_driver stmpe_pwm_driver = { |
332 | .driver = { |
333 | .name = "stmpe-pwm" , |
334 | }, |
335 | }; |
336 | builtin_platform_driver_probe(stmpe_pwm_driver, stmpe_pwm_probe); |
337 | |