| 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
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| 2 | /* |
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| 3 | * da9211-regulator.h - Regulator definitions for DA9211/DA9212 |
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| 4 | * /DA9213/DA9223/DA9214/DA9224/DA9215/DA9225 |
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| 5 | * Copyright (C) 2015 Dialog Semiconductor Ltd. |
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| 6 | */ |
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| 7 | |
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| 8 | #ifndef __DA9211_REGISTERS_H__ |
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| 9 | #define __DA9211_REGISTERS_H__ |
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| 10 | |
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| 11 | /* Page selection */ |
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| 12 | #define DA9211_REG_PAGE_CON 0x00 |
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| 13 | |
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| 14 | /* System Control and Event Registers */ |
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| 15 | #define DA9211_REG_STATUS_A 0x50 |
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| 16 | #define DA9211_REG_STATUS_B 0x51 |
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| 17 | #define DA9211_REG_EVENT_A 0x52 |
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| 18 | #define DA9211_REG_EVENT_B 0x53 |
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| 19 | #define DA9211_REG_MASK_A 0x54 |
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| 20 | #define DA9211_REG_MASK_B 0x55 |
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| 21 | #define DA9211_REG_CONTROL_A 0x56 |
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| 22 | |
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| 23 | /* GPIO Control Registers */ |
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| 24 | #define DA9211_REG_GPIO_0_1 0x58 |
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| 25 | #define DA9211_REG_GPIO_2_3 0x59 |
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| 26 | #define DA9211_REG_GPIO_4 0x5A |
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| 27 | |
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| 28 | /* Regulator Registers */ |
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| 29 | #define DA9211_REG_BUCKA_CONT 0x5D |
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| 30 | #define DA9211_REG_BUCKB_CONT 0x5E |
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| 31 | #define DA9211_REG_BUCK_ILIM 0xD0 |
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| 32 | #define DA9211_REG_BUCKA_CONF 0xD1 |
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| 33 | #define DA9211_REG_BUCKB_CONF 0xD2 |
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| 34 | #define DA9211_REG_BUCK_CONF 0xD3 |
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| 35 | #define DA9211_REG_VBACKA_MAX 0xD5 |
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| 36 | #define DA9211_REG_VBACKB_MAX 0xD6 |
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| 37 | #define DA9211_REG_VBUCKA_A 0xD7 |
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| 38 | #define DA9211_REG_VBUCKA_B 0xD8 |
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| 39 | #define DA9211_REG_VBUCKB_A 0xD9 |
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| 40 | #define DA9211_REG_VBUCKB_B 0xDA |
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| 41 | |
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| 42 | /* I2C Interface Settings */ |
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| 43 | #define DA9211_REG_INTERFACE 0x105 |
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| 44 | |
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| 45 | /* BUCK Phase Selection*/ |
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| 46 | #define DA9211_REG_CONFIG_E 0x147 |
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| 47 | |
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| 48 | /* Device ID */ |
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| 49 | #define DA9211_REG_DEVICE_ID 0x201 |
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| 50 | |
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| 51 | /* |
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| 52 | * Registers bits |
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| 53 | */ |
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| 54 | /* DA9211_REG_PAGE_CON (addr=0x00) */ |
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| 55 | #define DA9211_REG_PAGE_SHIFT 1 |
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| 56 | #define DA9211_REG_PAGE_MASK 0x06 |
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| 57 | /* On I2C registers 0x00 - 0xFF */ |
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| 58 | #define DA9211_REG_PAGE0 0 |
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| 59 | /* On I2C registers 0x100 - 0x1FF */ |
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| 60 | #define DA9211_REG_PAGE2 2 |
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| 61 | #define DA9211_PAGE_WRITE_MODE 0x00 |
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| 62 | #define DA9211_REPEAT_WRITE_MODE 0x40 |
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| 63 | #define DA9211_PAGE_REVERT 0x80 |
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| 64 | |
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| 65 | /* DA9211_REG_STATUS_A (addr=0x50) */ |
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| 66 | #define DA9211_GPI0 0x01 |
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| 67 | #define DA9211_GPI1 0x02 |
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| 68 | #define DA9211_GPI2 0x04 |
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| 69 | #define DA9211_GPI3 0x08 |
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| 70 | #define DA9211_GPI4 0x10 |
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| 71 | |
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| 72 | /* DA9211_REG_EVENT_A (addr=0x52) */ |
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| 73 | #define DA9211_E_GPI0 0x01 |
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| 74 | #define DA9211_E_GPI1 0x02 |
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| 75 | #define DA9211_E_GPI2 0x04 |
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| 76 | #define DA9211_E_GPI3 0x08 |
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| 77 | #define DA9211_E_GPI4 0x10 |
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| 78 | #define DA9211_E_UVLO_IO 0x40 |
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| 79 | |
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| 80 | /* DA9211_REG_EVENT_B (addr=0x53) */ |
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| 81 | #define DA9211_E_PWRGOOD_A 0x01 |
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| 82 | #define DA9211_E_PWRGOOD_B 0x02 |
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| 83 | #define DA9211_E_TEMP_WARN 0x04 |
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| 84 | #define DA9211_E_TEMP_CRIT 0x08 |
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| 85 | #define DA9211_E_OV_CURR_A 0x10 |
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| 86 | #define DA9211_E_OV_CURR_B 0x20 |
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| 87 | |
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| 88 | /* DA9211_REG_MASK_A (addr=0x54) */ |
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| 89 | #define DA9211_M_GPI0 0x01 |
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| 90 | #define DA9211_M_GPI1 0x02 |
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| 91 | #define DA9211_M_GPI2 0x04 |
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| 92 | #define DA9211_M_GPI3 0x08 |
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| 93 | #define DA9211_M_GPI4 0x10 |
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| 94 | #define DA9211_M_UVLO_IO 0x40 |
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| 95 | |
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| 96 | /* DA9211_REG_MASK_B (addr=0x55) */ |
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| 97 | #define DA9211_M_PWRGOOD_A 0x01 |
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| 98 | #define DA9211_M_PWRGOOD_B 0x02 |
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| 99 | #define DA9211_M_TEMP_WARN 0x04 |
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| 100 | #define DA9211_M_TEMP_CRIT 0x08 |
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| 101 | #define DA9211_M_OV_CURR_A 0x10 |
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| 102 | #define DA9211_M_OV_CURR_B 0x20 |
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| 103 | |
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| 104 | /* DA9211_REG_CONTROL_A (addr=0x56) */ |
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| 105 | #define DA9211_DEBOUNCING_SHIFT 0 |
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| 106 | #define DA9211_DEBOUNCING_MASK 0x07 |
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| 107 | #define DA9211_SLEW_RATE_SHIFT 3 |
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| 108 | #define DA9211_SLEW_RATE_A_MASK 0x18 |
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| 109 | #define DA9211_SLEW_RATE_B_SHIFT 5 |
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| 110 | #define DA9211_SLEW_RATE_B_MASK 0x60 |
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| 111 | #define DA9211_V_LOCK 0x80 |
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| 112 | |
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| 113 | /* DA9211_REG_GPIO_0_1 (addr=0x58) */ |
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| 114 | #define DA9211_GPIO0_PIN_SHIFT 0 |
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| 115 | #define DA9211_GPIO0_PIN_MASK 0x03 |
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| 116 | #define DA9211_GPIO0_PIN_GPI 0x00 |
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| 117 | #define DA9211_GPIO0_PIN_GPO_OD 0x02 |
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| 118 | #define DA9211_GPIO0_PIN_GPO 0x03 |
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| 119 | #define DA9211_GPIO0_TYPE 0x04 |
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| 120 | #define DA9211_GPIO0_TYPE_GPI 0x00 |
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| 121 | #define DA9211_GPIO0_TYPE_GPO 0x04 |
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| 122 | #define DA9211_GPIO0_MODE 0x08 |
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| 123 | #define DA9211_GPIO1_PIN_SHIFT 4 |
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| 124 | #define DA9211_GPIO1_PIN_MASK 0x30 |
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| 125 | #define DA9211_GPIO1_PIN_GPI 0x00 |
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| 126 | #define DA9211_GPIO1_PIN_VERROR 0x10 |
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| 127 | #define DA9211_GPIO1_PIN_GPO_OD 0x20 |
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| 128 | #define DA9211_GPIO1_PIN_GPO 0x30 |
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| 129 | #define DA9211_GPIO1_TYPE_SHIFT 0x40 |
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| 130 | #define DA9211_GPIO1_TYPE_GPI 0x00 |
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| 131 | #define DA9211_GPIO1_TYPE_GPO 0x40 |
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| 132 | #define DA9211_GPIO1_MODE 0x80 |
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| 133 | |
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| 134 | /* DA9211_REG_GPIO_2_3 (addr=0x59) */ |
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| 135 | #define DA9211_GPIO2_PIN_SHIFT 0 |
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| 136 | #define DA9211_GPIO2_PIN_MASK 0x03 |
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| 137 | #define DA9211_GPIO2_PIN_GPI 0x00 |
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| 138 | #define DA9211_GPIO5_PIN_BUCK_CLK 0x10 |
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| 139 | #define DA9211_GPIO2_PIN_GPO_OD 0x02 |
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| 140 | #define DA9211_GPIO2_PIN_GPO 0x03 |
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| 141 | #define DA9211_GPIO2_TYPE 0x04 |
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| 142 | #define DA9211_GPIO2_TYPE_GPI 0x00 |
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| 143 | #define DA9211_GPIO2_TYPE_GPO 0x04 |
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| 144 | #define DA9211_GPIO2_MODE 0x08 |
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| 145 | #define DA9211_GPIO3_PIN_SHIFT 4 |
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| 146 | #define DA9211_GPIO3_PIN_MASK 0x30 |
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| 147 | #define DA9211_GPIO3_PIN_GPI 0x00 |
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| 148 | #define DA9211_GPIO3_PIN_IERROR 0x10 |
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| 149 | #define DA9211_GPIO3_PIN_GPO_OD 0x20 |
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| 150 | #define DA9211_GPIO3_PIN_GPO 0x30 |
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| 151 | #define DA9211_GPIO3_TYPE_SHIFT 0x40 |
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| 152 | #define DA9211_GPIO3_TYPE_GPI 0x00 |
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| 153 | #define DA9211_GPIO3_TYPE_GPO 0x40 |
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| 154 | #define DA9211_GPIO3_MODE 0x80 |
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| 155 | |
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| 156 | /* DA9211_REG_GPIO_4 (addr=0x5A) */ |
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| 157 | #define DA9211_GPIO4_PIN_SHIFT 0 |
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| 158 | #define DA9211_GPIO4_PIN_MASK 0x03 |
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| 159 | #define DA9211_GPIO4_PIN_GPI 0x00 |
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| 160 | #define DA9211_GPIO4_PIN_GPO_OD 0x02 |
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| 161 | #define DA9211_GPIO4_PIN_GPO 0x03 |
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| 162 | #define DA9211_GPIO4_TYPE 0x04 |
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| 163 | #define DA9211_GPIO4_TYPE_GPI 0x00 |
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| 164 | #define DA9211_GPIO4_TYPE_GPO 0x04 |
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| 165 | #define DA9211_GPIO4_MODE 0x08 |
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| 166 | |
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| 167 | /* DA9211_REG_BUCKA_CONT (addr=0x5D) */ |
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| 168 | #define DA9211_BUCKA_EN 0x01 |
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| 169 | #define DA9211_BUCKA_GPI_SHIFT 1 |
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| 170 | #define DA9211_BUCKA_GPI_MASK 0x06 |
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| 171 | #define DA9211_BUCKA_GPI_OFF 0x00 |
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| 172 | #define DA9211_BUCKA_GPI_GPIO0 0x02 |
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| 173 | #define DA9211_BUCKA_GPI_GPIO1 0x04 |
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| 174 | #define DA9211_BUCKA_GPI_GPIO3 0x06 |
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| 175 | #define DA9211_BUCKA_PD_DIS 0x08 |
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| 176 | #define DA9211_VBUCKA_SEL 0x10 |
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| 177 | #define DA9211_VBUCKA_SEL_A 0x00 |
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| 178 | #define DA9211_VBUCKA_SEL_B 0x10 |
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| 179 | #define DA9211_VBUCKA_GPI_SHIFT 5 |
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| 180 | #define DA9211_VBUCKA_GPI_MASK 0x60 |
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| 181 | #define DA9211_VBUCKA_GPI_OFF 0x00 |
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| 182 | #define DA9211_VBUCKA_GPI_GPIO1 0x20 |
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| 183 | #define DA9211_VBUCKA_GPI_GPIO2 0x40 |
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| 184 | #define DA9211_VBUCKA_GPI_GPIO4 0x60 |
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| 185 | |
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| 186 | /* DA9211_REG_BUCKB_CONT (addr=0x5E) */ |
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| 187 | #define DA9211_BUCKB_EN 0x01 |
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| 188 | #define DA9211_BUCKB_GPI_SHIFT 1 |
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| 189 | #define DA9211_BUCKB_GPI_MASK 0x06 |
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| 190 | #define DA9211_BUCKB_GPI_OFF 0x00 |
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| 191 | #define DA9211_BUCKB_GPI_GPIO0 0x02 |
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| 192 | #define DA9211_BUCKB_GPI_GPIO1 0x04 |
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| 193 | #define DA9211_BUCKB_GPI_GPIO3 0x06 |
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| 194 | #define DA9211_BUCKB_PD_DIS 0x08 |
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| 195 | #define DA9211_VBUCKB_SEL 0x10 |
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| 196 | #define DA9211_VBUCKB_SEL_A 0x00 |
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| 197 | #define DA9211_VBUCKB_SEL_B 0x10 |
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| 198 | #define DA9211_VBUCKB_GPI_SHIFT 5 |
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| 199 | #define DA9211_VBUCKB_GPI_MASK 0x60 |
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| 200 | #define DA9211_VBUCKB_GPI_OFF 0x00 |
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| 201 | #define DA9211_VBUCKB_GPI_GPIO1 0x20 |
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| 202 | #define DA9211_VBUCKB_GPI_GPIO2 0x40 |
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| 203 | #define DA9211_VBUCKB_GPI_GPIO4 0x60 |
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| 204 | |
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| 205 | /* DA9211_REG_BUCK_ILIM (addr=0xD0) */ |
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| 206 | #define DA9211_BUCKA_ILIM_SHIFT 0 |
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| 207 | #define DA9211_BUCKA_ILIM_MASK 0x0F |
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| 208 | #define DA9211_BUCKB_ILIM_SHIFT 4 |
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| 209 | #define DA9211_BUCKB_ILIM_MASK 0xF0 |
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| 210 | |
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| 211 | /* DA9211_REG_BUCKA_CONF (addr=0xD1) */ |
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| 212 | #define DA9211_BUCKA_MODE_SHIFT 0 |
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| 213 | #define DA9211_BUCKA_MODE_MASK 0x03 |
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| 214 | #define DA9211_BUCKA_MODE_MANUAL 0x00 |
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| 215 | #define DA9211_BUCKA_MODE_SLEEP 0x01 |
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| 216 | #define DA9211_BUCKA_MODE_SYNC 0x02 |
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| 217 | #define DA9211_BUCKA_MODE_AUTO 0x03 |
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| 218 | #define DA9211_BUCKA_UP_CTRL_SHIFT 2 |
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| 219 | #define DA9211_BUCKA_UP_CTRL_MASK 0x1C |
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| 220 | #define DA9211_BUCKA_DOWN_CTRL_SHIFT 5 |
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| 221 | #define DA9211_BUCKA_DOWN_CTRL_MASK 0xE0 |
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| 222 | |
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| 223 | /* DA9211_REG_BUCKB_CONF (addr=0xD2) */ |
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| 224 | #define DA9211_BUCKB_MODE_SHIFT 0 |
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| 225 | #define DA9211_BUCKB_MODE_MASK 0x03 |
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| 226 | #define DA9211_BUCKB_MODE_MANUAL 0x00 |
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| 227 | #define DA9211_BUCKB_MODE_SLEEP 0x01 |
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| 228 | #define DA9211_BUCKB_MODE_SYNC 0x02 |
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| 229 | #define DA9211_BUCKB_MODE_AUTO 0x03 |
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| 230 | #define DA9211_BUCKB_UP_CTRL_SHIFT 2 |
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| 231 | #define DA9211_BUCKB_UP_CTRL_MASK 0x1C |
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| 232 | #define DA9211_BUCKB_DOWN_CTRL_SHIFT 5 |
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| 233 | #define DA9211_BUCKB_DOWN_CTRL_MASK 0xE0 |
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| 234 | |
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| 235 | /* DA9211_REG_BUCK_CONF (addr=0xD3) */ |
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| 236 | #define DA9211_PHASE_SEL_A_SHIFT 0 |
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| 237 | #define DA9211_PHASE_SEL_A_MASK 0x03 |
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| 238 | #define DA9211_PHASE_SEL_B_SHIFT 2 |
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| 239 | #define DA9211_PHASE_SEL_B_MASK 0x04 |
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| 240 | #define DA9211_PH_SH_EN_A_SHIFT 3 |
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| 241 | #define DA9211_PH_SH_EN_A_MASK 0x08 |
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| 242 | #define DA9211_PH_SH_EN_B_SHIFT 4 |
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| 243 | #define DA9211_PH_SH_EN_B_MASK 0x10 |
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| 244 | |
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| 245 | /* DA9211_REG_VBUCKA_MAX (addr=0xD5) */ |
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| 246 | #define DA9211_VBUCKA_BASE_SHIFT 0 |
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| 247 | #define DA9211_VBUCKA_BASE_MASK 0x7F |
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| 248 | |
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| 249 | /* DA9211_REG_VBUCKB_MAX (addr=0xD6) */ |
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| 250 | #define DA9211_VBUCKB_BASE_SHIFT 0 |
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| 251 | #define DA9211_VBUCKB_BASE_MASK 0x7F |
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| 252 | |
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| 253 | /* DA9211_REG_VBUCKA/B_A/B (addr=0xD7/0xD8/0xD9/0xDA) */ |
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| 254 | #define DA9211_VBUCK_SHIFT 0 |
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| 255 | #define DA9211_VBUCK_MASK 0x7F |
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| 256 | #define DA9211_VBUCK_BIAS 0 |
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| 257 | #define DA9211_BUCK_SL 0x80 |
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| 258 | |
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| 259 | /* DA9211_REG_INTERFACE (addr=0x105) */ |
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| 260 | #define DA9211_IF_BASE_ADDR_SHIFT 4 |
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| 261 | #define DA9211_IF_BASE_ADDR_MASK 0xF0 |
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| 262 | |
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| 263 | /* DA9211_REG_CONFIG_E (addr=0x147) */ |
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| 264 | #define DA9211_SLAVE_SEL 0x40 |
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| 265 | |
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| 266 | #endif /* __DA9211_REGISTERS_H__ */ |
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| 267 | |
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