1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2 | /* |
3 | * Simple Reset Controller Driver |
4 | * |
5 | * Copyright (C) 2017 Pengutronix, Philipp Zabel <kernel@pengutronix.de> |
6 | * |
7 | * Based on Allwinner SoCs Reset Controller driver |
8 | * |
9 | * Copyright 2013 Maxime Ripard |
10 | * |
11 | * Maxime Ripard <maxime.ripard@free-electrons.com> |
12 | */ |
13 | |
14 | #include <linux/delay.h> |
15 | #include <linux/device.h> |
16 | #include <linux/err.h> |
17 | #include <linux/io.h> |
18 | #include <linux/of.h> |
19 | #include <linux/platform_device.h> |
20 | #include <linux/reset-controller.h> |
21 | #include <linux/reset/reset-simple.h> |
22 | #include <linux/spinlock.h> |
23 | |
24 | static inline struct reset_simple_data * |
25 | to_reset_simple_data(struct reset_controller_dev *rcdev) |
26 | { |
27 | return container_of(rcdev, struct reset_simple_data, rcdev); |
28 | } |
29 | |
30 | static int reset_simple_update(struct reset_controller_dev *rcdev, |
31 | unsigned long id, bool assert) |
32 | { |
33 | struct reset_simple_data *data = to_reset_simple_data(rcdev); |
34 | int reg_width = sizeof(u32); |
35 | int bank = id / (reg_width * BITS_PER_BYTE); |
36 | int offset = id % (reg_width * BITS_PER_BYTE); |
37 | unsigned long flags; |
38 | u32 reg; |
39 | |
40 | spin_lock_irqsave(&data->lock, flags); |
41 | |
42 | reg = readl(addr: data->membase + (bank * reg_width)); |
43 | if (assert ^ data->active_low) |
44 | reg |= BIT(offset); |
45 | else |
46 | reg &= ~BIT(offset); |
47 | writel(val: reg, addr: data->membase + (bank * reg_width)); |
48 | |
49 | spin_unlock_irqrestore(lock: &data->lock, flags); |
50 | |
51 | return 0; |
52 | } |
53 | |
54 | static int reset_simple_assert(struct reset_controller_dev *rcdev, |
55 | unsigned long id) |
56 | { |
57 | return reset_simple_update(rcdev, id, assert: true); |
58 | } |
59 | |
60 | static int reset_simple_deassert(struct reset_controller_dev *rcdev, |
61 | unsigned long id) |
62 | { |
63 | return reset_simple_update(rcdev, id, assert: false); |
64 | } |
65 | |
66 | static int reset_simple_reset(struct reset_controller_dev *rcdev, |
67 | unsigned long id) |
68 | { |
69 | struct reset_simple_data *data = to_reset_simple_data(rcdev); |
70 | int ret; |
71 | |
72 | if (!data->reset_us) |
73 | return -ENOTSUPP; |
74 | |
75 | ret = reset_simple_assert(rcdev, id); |
76 | if (ret) |
77 | return ret; |
78 | |
79 | usleep_range(min: data->reset_us, max: data->reset_us * 2); |
80 | |
81 | return reset_simple_deassert(rcdev, id); |
82 | } |
83 | |
84 | static int reset_simple_status(struct reset_controller_dev *rcdev, |
85 | unsigned long id) |
86 | { |
87 | struct reset_simple_data *data = to_reset_simple_data(rcdev); |
88 | int reg_width = sizeof(u32); |
89 | int bank = id / (reg_width * BITS_PER_BYTE); |
90 | int offset = id % (reg_width * BITS_PER_BYTE); |
91 | u32 reg; |
92 | |
93 | reg = readl(addr: data->membase + (bank * reg_width)); |
94 | |
95 | return !(reg & BIT(offset)) ^ !data->status_active_low; |
96 | } |
97 | |
98 | const struct reset_control_ops reset_simple_ops = { |
99 | .assert = reset_simple_assert, |
100 | .deassert = reset_simple_deassert, |
101 | .reset = reset_simple_reset, |
102 | .status = reset_simple_status, |
103 | }; |
104 | EXPORT_SYMBOL_GPL(reset_simple_ops); |
105 | |
106 | /** |
107 | * struct reset_simple_devdata - simple reset controller properties |
108 | * @reg_offset: offset between base address and first reset register. |
109 | * @nr_resets: number of resets. If not set, default to resource size in bits. |
110 | * @active_low: if true, bits are cleared to assert the reset. Otherwise, bits |
111 | * are set to assert the reset. |
112 | * @status_active_low: if true, bits read back as cleared while the reset is |
113 | * asserted. Otherwise, bits read back as set while the |
114 | * reset is asserted. |
115 | */ |
116 | struct reset_simple_devdata { |
117 | u32 reg_offset; |
118 | u32 nr_resets; |
119 | bool active_low; |
120 | bool status_active_low; |
121 | }; |
122 | |
123 | #define SOCFPGA_NR_BANKS 8 |
124 | |
125 | static const struct reset_simple_devdata reset_simple_socfpga = { |
126 | .reg_offset = 0x20, |
127 | .nr_resets = SOCFPGA_NR_BANKS * 32, |
128 | .status_active_low = true, |
129 | }; |
130 | |
131 | static const struct reset_simple_devdata reset_simple_active_low = { |
132 | .active_low = true, |
133 | .status_active_low = true, |
134 | }; |
135 | |
136 | static const struct of_device_id reset_simple_dt_ids[] = { |
137 | { .compatible = "altr,stratix10-rst-mgr" , |
138 | .data = &reset_simple_socfpga }, |
139 | { .compatible = "st,stm32-rcc" , }, |
140 | { .compatible = "allwinner,sun6i-a31-clock-reset" , |
141 | .data = &reset_simple_active_low }, |
142 | { .compatible = "zte,zx296718-reset" , |
143 | .data = &reset_simple_active_low }, |
144 | { .compatible = "aspeed,ast2400-lpc-reset" }, |
145 | { .compatible = "aspeed,ast2500-lpc-reset" }, |
146 | { .compatible = "aspeed,ast2600-lpc-reset" }, |
147 | { .compatible = "bitmain,bm1880-reset" , |
148 | .data = &reset_simple_active_low }, |
149 | { .compatible = "brcm,bcm4908-misc-pcie-reset" , |
150 | .data = &reset_simple_active_low }, |
151 | { .compatible = "snps,dw-high-reset" }, |
152 | { .compatible = "snps,dw-low-reset" , |
153 | .data = &reset_simple_active_low }, |
154 | { /* sentinel */ }, |
155 | }; |
156 | |
157 | static int reset_simple_probe(struct platform_device *pdev) |
158 | { |
159 | struct device *dev = &pdev->dev; |
160 | const struct reset_simple_devdata *devdata; |
161 | struct reset_simple_data *data; |
162 | void __iomem *membase; |
163 | struct resource *res; |
164 | u32 reg_offset = 0; |
165 | |
166 | devdata = of_device_get_match_data(dev); |
167 | |
168 | data = devm_kzalloc(dev, size: sizeof(*data), GFP_KERNEL); |
169 | if (!data) |
170 | return -ENOMEM; |
171 | |
172 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
173 | membase = devm_ioremap_resource(dev, res); |
174 | if (IS_ERR(ptr: membase)) |
175 | return PTR_ERR(ptr: membase); |
176 | |
177 | spin_lock_init(&data->lock); |
178 | data->membase = membase; |
179 | data->rcdev.owner = THIS_MODULE; |
180 | data->rcdev.nr_resets = resource_size(res) * BITS_PER_BYTE; |
181 | data->rcdev.ops = &reset_simple_ops; |
182 | data->rcdev.of_node = dev->of_node; |
183 | |
184 | if (devdata) { |
185 | reg_offset = devdata->reg_offset; |
186 | if (devdata->nr_resets) |
187 | data->rcdev.nr_resets = devdata->nr_resets; |
188 | data->active_low = devdata->active_low; |
189 | data->status_active_low = devdata->status_active_low; |
190 | } |
191 | |
192 | data->membase += reg_offset; |
193 | |
194 | return devm_reset_controller_register(dev, rcdev: &data->rcdev); |
195 | } |
196 | |
197 | static struct platform_driver reset_simple_driver = { |
198 | .probe = reset_simple_probe, |
199 | .driver = { |
200 | .name = "simple-reset" , |
201 | .of_match_table = reset_simple_dt_ids, |
202 | }, |
203 | }; |
204 | builtin_platform_driver(reset_simple_driver); |
205 | |