1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Copyright (C) STMicroelectronics 2017 |
4 | * Author: Amelie Delaunay <amelie.delaunay@st.com> |
5 | */ |
6 | |
7 | #include <linux/bcd.h> |
8 | #include <linux/clk.h> |
9 | #include <linux/errno.h> |
10 | #include <linux/iopoll.h> |
11 | #include <linux/ioport.h> |
12 | #include <linux/mfd/syscon.h> |
13 | #include <linux/module.h> |
14 | #include <linux/of.h> |
15 | #include <linux/platform_device.h> |
16 | #include <linux/pm_wakeirq.h> |
17 | #include <linux/regmap.h> |
18 | #include <linux/rtc.h> |
19 | |
20 | #define DRIVER_NAME "stm32_rtc" |
21 | |
22 | /* STM32_RTC_TR bit fields */ |
23 | #define STM32_RTC_TR_SEC_SHIFT 0 |
24 | #define STM32_RTC_TR_SEC GENMASK(6, 0) |
25 | #define STM32_RTC_TR_MIN_SHIFT 8 |
26 | #define STM32_RTC_TR_MIN GENMASK(14, 8) |
27 | #define STM32_RTC_TR_HOUR_SHIFT 16 |
28 | #define STM32_RTC_TR_HOUR GENMASK(21, 16) |
29 | |
30 | /* STM32_RTC_DR bit fields */ |
31 | #define STM32_RTC_DR_DATE_SHIFT 0 |
32 | #define STM32_RTC_DR_DATE GENMASK(5, 0) |
33 | #define STM32_RTC_DR_MONTH_SHIFT 8 |
34 | #define STM32_RTC_DR_MONTH GENMASK(12, 8) |
35 | #define STM32_RTC_DR_WDAY_SHIFT 13 |
36 | #define STM32_RTC_DR_WDAY GENMASK(15, 13) |
37 | #define STM32_RTC_DR_YEAR_SHIFT 16 |
38 | #define STM32_RTC_DR_YEAR GENMASK(23, 16) |
39 | |
40 | /* STM32_RTC_CR bit fields */ |
41 | #define STM32_RTC_CR_FMT BIT(6) |
42 | #define STM32_RTC_CR_ALRAE BIT(8) |
43 | #define STM32_RTC_CR_ALRAIE BIT(12) |
44 | |
45 | /* STM32_RTC_ISR/STM32_RTC_ICSR bit fields */ |
46 | #define STM32_RTC_ISR_ALRAWF BIT(0) |
47 | #define STM32_RTC_ISR_INITS BIT(4) |
48 | #define STM32_RTC_ISR_RSF BIT(5) |
49 | #define STM32_RTC_ISR_INITF BIT(6) |
50 | #define STM32_RTC_ISR_INIT BIT(7) |
51 | #define STM32_RTC_ISR_ALRAF BIT(8) |
52 | |
53 | /* STM32_RTC_PRER bit fields */ |
54 | #define STM32_RTC_PRER_PRED_S_SHIFT 0 |
55 | #define STM32_RTC_PRER_PRED_S GENMASK(14, 0) |
56 | #define STM32_RTC_PRER_PRED_A_SHIFT 16 |
57 | #define STM32_RTC_PRER_PRED_A GENMASK(22, 16) |
58 | |
59 | /* STM32_RTC_ALRMAR and STM32_RTC_ALRMBR bit fields */ |
60 | #define STM32_RTC_ALRMXR_SEC_SHIFT 0 |
61 | #define STM32_RTC_ALRMXR_SEC GENMASK(6, 0) |
62 | #define STM32_RTC_ALRMXR_SEC_MASK BIT(7) |
63 | #define STM32_RTC_ALRMXR_MIN_SHIFT 8 |
64 | #define STM32_RTC_ALRMXR_MIN GENMASK(14, 8) |
65 | #define STM32_RTC_ALRMXR_MIN_MASK BIT(15) |
66 | #define STM32_RTC_ALRMXR_HOUR_SHIFT 16 |
67 | #define STM32_RTC_ALRMXR_HOUR GENMASK(21, 16) |
68 | #define STM32_RTC_ALRMXR_PM BIT(22) |
69 | #define STM32_RTC_ALRMXR_HOUR_MASK BIT(23) |
70 | #define STM32_RTC_ALRMXR_DATE_SHIFT 24 |
71 | #define STM32_RTC_ALRMXR_DATE GENMASK(29, 24) |
72 | #define STM32_RTC_ALRMXR_WDSEL BIT(30) |
73 | #define STM32_RTC_ALRMXR_WDAY_SHIFT 24 |
74 | #define STM32_RTC_ALRMXR_WDAY GENMASK(27, 24) |
75 | #define STM32_RTC_ALRMXR_DATE_MASK BIT(31) |
76 | |
77 | /* STM32_RTC_SR/_SCR bit fields */ |
78 | #define STM32_RTC_SR_ALRA BIT(0) |
79 | |
80 | /* STM32_RTC_VERR bit fields */ |
81 | #define STM32_RTC_VERR_MINREV_SHIFT 0 |
82 | #define STM32_RTC_VERR_MINREV GENMASK(3, 0) |
83 | #define STM32_RTC_VERR_MAJREV_SHIFT 4 |
84 | #define STM32_RTC_VERR_MAJREV GENMASK(7, 4) |
85 | |
86 | /* STM32_RTC_WPR key constants */ |
87 | #define RTC_WPR_1ST_KEY 0xCA |
88 | #define RTC_WPR_2ND_KEY 0x53 |
89 | #define RTC_WPR_WRONG_KEY 0xFF |
90 | |
91 | /* Max STM32 RTC register offset is 0x3FC */ |
92 | #define UNDEF_REG 0xFFFF |
93 | |
94 | /* STM32 RTC driver time helpers */ |
95 | #define SEC_PER_DAY (24 * 60 * 60) |
96 | |
97 | struct stm32_rtc; |
98 | |
99 | struct stm32_rtc_registers { |
100 | u16 tr; |
101 | u16 dr; |
102 | u16 cr; |
103 | u16 isr; |
104 | u16 prer; |
105 | u16 alrmar; |
106 | u16 wpr; |
107 | u16 sr; |
108 | u16 scr; |
109 | u16 verr; |
110 | }; |
111 | |
112 | struct stm32_rtc_events { |
113 | u32 alra; |
114 | }; |
115 | |
116 | struct stm32_rtc_data { |
117 | const struct stm32_rtc_registers regs; |
118 | const struct stm32_rtc_events events; |
119 | void (*clear_events)(struct stm32_rtc *rtc, unsigned int flags); |
120 | bool has_pclk; |
121 | bool need_dbp; |
122 | bool need_accuracy; |
123 | }; |
124 | |
125 | struct stm32_rtc { |
126 | struct rtc_device *rtc_dev; |
127 | void __iomem *base; |
128 | struct regmap *dbp; |
129 | unsigned int dbp_reg; |
130 | unsigned int dbp_mask; |
131 | struct clk *pclk; |
132 | struct clk *rtc_ck; |
133 | const struct stm32_rtc_data *data; |
134 | int irq_alarm; |
135 | }; |
136 | |
137 | static void stm32_rtc_wpr_unlock(struct stm32_rtc *rtc) |
138 | { |
139 | const struct stm32_rtc_registers *regs = &rtc->data->regs; |
140 | |
141 | writel_relaxed(RTC_WPR_1ST_KEY, rtc->base + regs->wpr); |
142 | writel_relaxed(RTC_WPR_2ND_KEY, rtc->base + regs->wpr); |
143 | } |
144 | |
145 | static void stm32_rtc_wpr_lock(struct stm32_rtc *rtc) |
146 | { |
147 | const struct stm32_rtc_registers *regs = &rtc->data->regs; |
148 | |
149 | writel_relaxed(RTC_WPR_WRONG_KEY, rtc->base + regs->wpr); |
150 | } |
151 | |
152 | static int stm32_rtc_enter_init_mode(struct stm32_rtc *rtc) |
153 | { |
154 | const struct stm32_rtc_registers *regs = &rtc->data->regs; |
155 | unsigned int isr = readl_relaxed(rtc->base + regs->isr); |
156 | |
157 | if (!(isr & STM32_RTC_ISR_INITF)) { |
158 | isr |= STM32_RTC_ISR_INIT; |
159 | writel_relaxed(isr, rtc->base + regs->isr); |
160 | |
161 | /* |
162 | * It takes around 2 rtc_ck clock cycles to enter in |
163 | * initialization phase mode (and have INITF flag set). As |
164 | * slowest rtc_ck frequency may be 32kHz and highest should be |
165 | * 1MHz, we poll every 10 us with a timeout of 100ms. |
166 | */ |
167 | return readl_relaxed_poll_timeout_atomic(rtc->base + regs->isr, isr, |
168 | (isr & STM32_RTC_ISR_INITF), |
169 | 10, 100000); |
170 | } |
171 | |
172 | return 0; |
173 | } |
174 | |
175 | static void stm32_rtc_exit_init_mode(struct stm32_rtc *rtc) |
176 | { |
177 | const struct stm32_rtc_registers *regs = &rtc->data->regs; |
178 | unsigned int isr = readl_relaxed(rtc->base + regs->isr); |
179 | |
180 | isr &= ~STM32_RTC_ISR_INIT; |
181 | writel_relaxed(isr, rtc->base + regs->isr); |
182 | } |
183 | |
184 | static int stm32_rtc_wait_sync(struct stm32_rtc *rtc) |
185 | { |
186 | const struct stm32_rtc_registers *regs = &rtc->data->regs; |
187 | unsigned int isr = readl_relaxed(rtc->base + regs->isr); |
188 | |
189 | isr &= ~STM32_RTC_ISR_RSF; |
190 | writel_relaxed(isr, rtc->base + regs->isr); |
191 | |
192 | /* |
193 | * Wait for RSF to be set to ensure the calendar registers are |
194 | * synchronised, it takes around 2 rtc_ck clock cycles |
195 | */ |
196 | return readl_relaxed_poll_timeout_atomic(rtc->base + regs->isr, |
197 | isr, |
198 | (isr & STM32_RTC_ISR_RSF), |
199 | 10, 100000); |
200 | } |
201 | |
202 | static void stm32_rtc_clear_event_flags(struct stm32_rtc *rtc, |
203 | unsigned int flags) |
204 | { |
205 | rtc->data->clear_events(rtc, flags); |
206 | } |
207 | |
208 | static irqreturn_t stm32_rtc_alarm_irq(int irq, void *dev_id) |
209 | { |
210 | struct stm32_rtc *rtc = (struct stm32_rtc *)dev_id; |
211 | const struct stm32_rtc_registers *regs = &rtc->data->regs; |
212 | const struct stm32_rtc_events *evts = &rtc->data->events; |
213 | unsigned int status, cr; |
214 | |
215 | rtc_lock(rtc->rtc_dev); |
216 | |
217 | status = readl_relaxed(rtc->base + regs->sr); |
218 | cr = readl_relaxed(rtc->base + regs->cr); |
219 | |
220 | if ((status & evts->alra) && |
221 | (cr & STM32_RTC_CR_ALRAIE)) { |
222 | /* Alarm A flag - Alarm interrupt */ |
223 | dev_dbg(&rtc->rtc_dev->dev, "Alarm occurred\n" ); |
224 | |
225 | /* Pass event to the kernel */ |
226 | rtc_update_irq(rtc: rtc->rtc_dev, num: 1, RTC_IRQF | RTC_AF); |
227 | |
228 | /* Clear event flags, otherwise new events won't be received */ |
229 | stm32_rtc_clear_event_flags(rtc, flags: evts->alra); |
230 | } |
231 | |
232 | rtc_unlock(rtc->rtc_dev); |
233 | |
234 | return IRQ_HANDLED; |
235 | } |
236 | |
237 | /* Convert rtc_time structure from bin to bcd format */ |
238 | static void tm2bcd(struct rtc_time *tm) |
239 | { |
240 | tm->tm_sec = bin2bcd(tm->tm_sec); |
241 | tm->tm_min = bin2bcd(tm->tm_min); |
242 | tm->tm_hour = bin2bcd(tm->tm_hour); |
243 | |
244 | tm->tm_mday = bin2bcd(tm->tm_mday); |
245 | tm->tm_mon = bin2bcd(tm->tm_mon + 1); |
246 | tm->tm_year = bin2bcd(tm->tm_year - 100); |
247 | /* |
248 | * Number of days since Sunday |
249 | * - on kernel side, 0=Sunday...6=Saturday |
250 | * - on rtc side, 0=invalid,1=Monday...7=Sunday |
251 | */ |
252 | tm->tm_wday = (!tm->tm_wday) ? 7 : tm->tm_wday; |
253 | } |
254 | |
255 | /* Convert rtc_time structure from bcd to bin format */ |
256 | static void bcd2tm(struct rtc_time *tm) |
257 | { |
258 | tm->tm_sec = bcd2bin(tm->tm_sec); |
259 | tm->tm_min = bcd2bin(tm->tm_min); |
260 | tm->tm_hour = bcd2bin(tm->tm_hour); |
261 | |
262 | tm->tm_mday = bcd2bin(tm->tm_mday); |
263 | tm->tm_mon = bcd2bin(tm->tm_mon) - 1; |
264 | tm->tm_year = bcd2bin(tm->tm_year) + 100; |
265 | /* |
266 | * Number of days since Sunday |
267 | * - on kernel side, 0=Sunday...6=Saturday |
268 | * - on rtc side, 0=invalid,1=Monday...7=Sunday |
269 | */ |
270 | tm->tm_wday %= 7; |
271 | } |
272 | |
273 | static int stm32_rtc_read_time(struct device *dev, struct rtc_time *tm) |
274 | { |
275 | struct stm32_rtc *rtc = dev_get_drvdata(dev); |
276 | const struct stm32_rtc_registers *regs = &rtc->data->regs; |
277 | unsigned int tr, dr; |
278 | |
279 | /* Time and Date in BCD format */ |
280 | tr = readl_relaxed(rtc->base + regs->tr); |
281 | dr = readl_relaxed(rtc->base + regs->dr); |
282 | |
283 | tm->tm_sec = (tr & STM32_RTC_TR_SEC) >> STM32_RTC_TR_SEC_SHIFT; |
284 | tm->tm_min = (tr & STM32_RTC_TR_MIN) >> STM32_RTC_TR_MIN_SHIFT; |
285 | tm->tm_hour = (tr & STM32_RTC_TR_HOUR) >> STM32_RTC_TR_HOUR_SHIFT; |
286 | |
287 | tm->tm_mday = (dr & STM32_RTC_DR_DATE) >> STM32_RTC_DR_DATE_SHIFT; |
288 | tm->tm_mon = (dr & STM32_RTC_DR_MONTH) >> STM32_RTC_DR_MONTH_SHIFT; |
289 | tm->tm_year = (dr & STM32_RTC_DR_YEAR) >> STM32_RTC_DR_YEAR_SHIFT; |
290 | tm->tm_wday = (dr & STM32_RTC_DR_WDAY) >> STM32_RTC_DR_WDAY_SHIFT; |
291 | |
292 | /* We don't report tm_yday and tm_isdst */ |
293 | |
294 | bcd2tm(tm); |
295 | |
296 | return 0; |
297 | } |
298 | |
299 | static int stm32_rtc_set_time(struct device *dev, struct rtc_time *tm) |
300 | { |
301 | struct stm32_rtc *rtc = dev_get_drvdata(dev); |
302 | const struct stm32_rtc_registers *regs = &rtc->data->regs; |
303 | unsigned int tr, dr; |
304 | int ret = 0; |
305 | |
306 | tm2bcd(tm); |
307 | |
308 | /* Time in BCD format */ |
309 | tr = ((tm->tm_sec << STM32_RTC_TR_SEC_SHIFT) & STM32_RTC_TR_SEC) | |
310 | ((tm->tm_min << STM32_RTC_TR_MIN_SHIFT) & STM32_RTC_TR_MIN) | |
311 | ((tm->tm_hour << STM32_RTC_TR_HOUR_SHIFT) & STM32_RTC_TR_HOUR); |
312 | |
313 | /* Date in BCD format */ |
314 | dr = ((tm->tm_mday << STM32_RTC_DR_DATE_SHIFT) & STM32_RTC_DR_DATE) | |
315 | ((tm->tm_mon << STM32_RTC_DR_MONTH_SHIFT) & STM32_RTC_DR_MONTH) | |
316 | ((tm->tm_year << STM32_RTC_DR_YEAR_SHIFT) & STM32_RTC_DR_YEAR) | |
317 | ((tm->tm_wday << STM32_RTC_DR_WDAY_SHIFT) & STM32_RTC_DR_WDAY); |
318 | |
319 | stm32_rtc_wpr_unlock(rtc); |
320 | |
321 | ret = stm32_rtc_enter_init_mode(rtc); |
322 | if (ret) { |
323 | dev_err(dev, "Can't enter in init mode. Set time aborted.\n" ); |
324 | goto end; |
325 | } |
326 | |
327 | writel_relaxed(tr, rtc->base + regs->tr); |
328 | writel_relaxed(dr, rtc->base + regs->dr); |
329 | |
330 | stm32_rtc_exit_init_mode(rtc); |
331 | |
332 | ret = stm32_rtc_wait_sync(rtc); |
333 | end: |
334 | stm32_rtc_wpr_lock(rtc); |
335 | |
336 | return ret; |
337 | } |
338 | |
339 | static int stm32_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) |
340 | { |
341 | struct stm32_rtc *rtc = dev_get_drvdata(dev); |
342 | const struct stm32_rtc_registers *regs = &rtc->data->regs; |
343 | const struct stm32_rtc_events *evts = &rtc->data->events; |
344 | struct rtc_time *tm = &alrm->time; |
345 | unsigned int alrmar, cr, status; |
346 | |
347 | alrmar = readl_relaxed(rtc->base + regs->alrmar); |
348 | cr = readl_relaxed(rtc->base + regs->cr); |
349 | status = readl_relaxed(rtc->base + regs->sr); |
350 | |
351 | if (alrmar & STM32_RTC_ALRMXR_DATE_MASK) { |
352 | /* |
353 | * Date/day doesn't matter in Alarm comparison so alarm |
354 | * triggers every day |
355 | */ |
356 | tm->tm_mday = -1; |
357 | tm->tm_wday = -1; |
358 | } else { |
359 | if (alrmar & STM32_RTC_ALRMXR_WDSEL) { |
360 | /* Alarm is set to a day of week */ |
361 | tm->tm_mday = -1; |
362 | tm->tm_wday = (alrmar & STM32_RTC_ALRMXR_WDAY) >> |
363 | STM32_RTC_ALRMXR_WDAY_SHIFT; |
364 | tm->tm_wday %= 7; |
365 | } else { |
366 | /* Alarm is set to a day of month */ |
367 | tm->tm_wday = -1; |
368 | tm->tm_mday = (alrmar & STM32_RTC_ALRMXR_DATE) >> |
369 | STM32_RTC_ALRMXR_DATE_SHIFT; |
370 | } |
371 | } |
372 | |
373 | if (alrmar & STM32_RTC_ALRMXR_HOUR_MASK) { |
374 | /* Hours don't matter in Alarm comparison */ |
375 | tm->tm_hour = -1; |
376 | } else { |
377 | tm->tm_hour = (alrmar & STM32_RTC_ALRMXR_HOUR) >> |
378 | STM32_RTC_ALRMXR_HOUR_SHIFT; |
379 | if (alrmar & STM32_RTC_ALRMXR_PM) |
380 | tm->tm_hour += 12; |
381 | } |
382 | |
383 | if (alrmar & STM32_RTC_ALRMXR_MIN_MASK) { |
384 | /* Minutes don't matter in Alarm comparison */ |
385 | tm->tm_min = -1; |
386 | } else { |
387 | tm->tm_min = (alrmar & STM32_RTC_ALRMXR_MIN) >> |
388 | STM32_RTC_ALRMXR_MIN_SHIFT; |
389 | } |
390 | |
391 | if (alrmar & STM32_RTC_ALRMXR_SEC_MASK) { |
392 | /* Seconds don't matter in Alarm comparison */ |
393 | tm->tm_sec = -1; |
394 | } else { |
395 | tm->tm_sec = (alrmar & STM32_RTC_ALRMXR_SEC) >> |
396 | STM32_RTC_ALRMXR_SEC_SHIFT; |
397 | } |
398 | |
399 | bcd2tm(tm); |
400 | |
401 | alrm->enabled = (cr & STM32_RTC_CR_ALRAE) ? 1 : 0; |
402 | alrm->pending = (status & evts->alra) ? 1 : 0; |
403 | |
404 | return 0; |
405 | } |
406 | |
407 | static int stm32_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) |
408 | { |
409 | struct stm32_rtc *rtc = dev_get_drvdata(dev); |
410 | const struct stm32_rtc_registers *regs = &rtc->data->regs; |
411 | const struct stm32_rtc_events *evts = &rtc->data->events; |
412 | unsigned int cr; |
413 | |
414 | cr = readl_relaxed(rtc->base + regs->cr); |
415 | |
416 | stm32_rtc_wpr_unlock(rtc); |
417 | |
418 | /* We expose Alarm A to the kernel */ |
419 | if (enabled) |
420 | cr |= (STM32_RTC_CR_ALRAIE | STM32_RTC_CR_ALRAE); |
421 | else |
422 | cr &= ~(STM32_RTC_CR_ALRAIE | STM32_RTC_CR_ALRAE); |
423 | writel_relaxed(cr, rtc->base + regs->cr); |
424 | |
425 | /* Clear event flags, otherwise new events won't be received */ |
426 | stm32_rtc_clear_event_flags(rtc, flags: evts->alra); |
427 | |
428 | stm32_rtc_wpr_lock(rtc); |
429 | |
430 | return 0; |
431 | } |
432 | |
433 | static int stm32_rtc_valid_alrm(struct device *dev, struct rtc_time *tm) |
434 | { |
435 | static struct rtc_time now; |
436 | time64_t max_alarm_time64; |
437 | int max_day_forward; |
438 | int next_month; |
439 | int next_year; |
440 | |
441 | /* |
442 | * Assuming current date is M-D-Y H:M:S. |
443 | * RTC alarm can't be set on a specific month and year. |
444 | * So the valid alarm range is: |
445 | * M-D-Y H:M:S < alarm <= (M+1)-D-Y H:M:S |
446 | */ |
447 | stm32_rtc_read_time(dev, tm: &now); |
448 | |
449 | /* |
450 | * Find the next month and the year of the next month. |
451 | * Note: tm_mon and next_month are from 0 to 11 |
452 | */ |
453 | next_month = now.tm_mon + 1; |
454 | if (next_month == 12) { |
455 | next_month = 0; |
456 | next_year = now.tm_year + 1; |
457 | } else { |
458 | next_year = now.tm_year; |
459 | } |
460 | |
461 | /* Find the maximum limit of alarm in days. */ |
462 | max_day_forward = rtc_month_days(month: now.tm_mon, year: now.tm_year) |
463 | - now.tm_mday |
464 | + min(rtc_month_days(next_month, next_year), now.tm_mday); |
465 | |
466 | /* Convert to timestamp and compare the alarm time and its upper limit */ |
467 | max_alarm_time64 = rtc_tm_to_time64(tm: &now) + max_day_forward * SEC_PER_DAY; |
468 | return rtc_tm_to_time64(tm) <= max_alarm_time64 ? 0 : -EINVAL; |
469 | } |
470 | |
471 | static int stm32_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) |
472 | { |
473 | struct stm32_rtc *rtc = dev_get_drvdata(dev); |
474 | const struct stm32_rtc_registers *regs = &rtc->data->regs; |
475 | struct rtc_time *tm = &alrm->time; |
476 | unsigned int cr, isr, alrmar; |
477 | int ret = 0; |
478 | |
479 | /* |
480 | * RTC alarm can't be set on a specific date, unless this date is |
481 | * up to the same day of month next month. |
482 | */ |
483 | if (stm32_rtc_valid_alrm(dev, tm) < 0) { |
484 | dev_err(dev, "Alarm can be set only on upcoming month.\n" ); |
485 | return -EINVAL; |
486 | } |
487 | |
488 | tm2bcd(tm); |
489 | |
490 | alrmar = 0; |
491 | /* tm_year and tm_mon are not used because not supported by RTC */ |
492 | alrmar |= (tm->tm_mday << STM32_RTC_ALRMXR_DATE_SHIFT) & |
493 | STM32_RTC_ALRMXR_DATE; |
494 | /* 24-hour format */ |
495 | alrmar &= ~STM32_RTC_ALRMXR_PM; |
496 | alrmar |= (tm->tm_hour << STM32_RTC_ALRMXR_HOUR_SHIFT) & |
497 | STM32_RTC_ALRMXR_HOUR; |
498 | alrmar |= (tm->tm_min << STM32_RTC_ALRMXR_MIN_SHIFT) & |
499 | STM32_RTC_ALRMXR_MIN; |
500 | alrmar |= (tm->tm_sec << STM32_RTC_ALRMXR_SEC_SHIFT) & |
501 | STM32_RTC_ALRMXR_SEC; |
502 | |
503 | stm32_rtc_wpr_unlock(rtc); |
504 | |
505 | /* Disable Alarm */ |
506 | cr = readl_relaxed(rtc->base + regs->cr); |
507 | cr &= ~STM32_RTC_CR_ALRAE; |
508 | writel_relaxed(cr, rtc->base + regs->cr); |
509 | |
510 | /* |
511 | * Poll Alarm write flag to be sure that Alarm update is allowed: it |
512 | * takes around 2 rtc_ck clock cycles |
513 | */ |
514 | ret = readl_relaxed_poll_timeout_atomic(rtc->base + regs->isr, |
515 | isr, |
516 | (isr & STM32_RTC_ISR_ALRAWF), |
517 | 10, 100000); |
518 | |
519 | if (ret) { |
520 | dev_err(dev, "Alarm update not allowed\n" ); |
521 | goto end; |
522 | } |
523 | |
524 | /* Write to Alarm register */ |
525 | writel_relaxed(alrmar, rtc->base + regs->alrmar); |
526 | |
527 | stm32_rtc_alarm_irq_enable(dev, enabled: alrm->enabled); |
528 | end: |
529 | stm32_rtc_wpr_lock(rtc); |
530 | |
531 | return ret; |
532 | } |
533 | |
534 | static const struct rtc_class_ops stm32_rtc_ops = { |
535 | .read_time = stm32_rtc_read_time, |
536 | .set_time = stm32_rtc_set_time, |
537 | .read_alarm = stm32_rtc_read_alarm, |
538 | .set_alarm = stm32_rtc_set_alarm, |
539 | .alarm_irq_enable = stm32_rtc_alarm_irq_enable, |
540 | }; |
541 | |
542 | static void stm32_rtc_clear_events(struct stm32_rtc *rtc, |
543 | unsigned int flags) |
544 | { |
545 | const struct stm32_rtc_registers *regs = &rtc->data->regs; |
546 | |
547 | /* Flags are cleared by writing 0 in RTC_ISR */ |
548 | writel_relaxed(readl_relaxed(rtc->base + regs->isr) & ~flags, |
549 | rtc->base + regs->isr); |
550 | } |
551 | |
552 | static const struct stm32_rtc_data stm32_rtc_data = { |
553 | .has_pclk = false, |
554 | .need_dbp = true, |
555 | .need_accuracy = false, |
556 | .regs = { |
557 | .tr = 0x00, |
558 | .dr = 0x04, |
559 | .cr = 0x08, |
560 | .isr = 0x0C, |
561 | .prer = 0x10, |
562 | .alrmar = 0x1C, |
563 | .wpr = 0x24, |
564 | .sr = 0x0C, /* set to ISR offset to ease alarm management */ |
565 | .scr = UNDEF_REG, |
566 | .verr = UNDEF_REG, |
567 | }, |
568 | .events = { |
569 | .alra = STM32_RTC_ISR_ALRAF, |
570 | }, |
571 | .clear_events = stm32_rtc_clear_events, |
572 | }; |
573 | |
574 | static const struct stm32_rtc_data stm32h7_rtc_data = { |
575 | .has_pclk = true, |
576 | .need_dbp = true, |
577 | .need_accuracy = false, |
578 | .regs = { |
579 | .tr = 0x00, |
580 | .dr = 0x04, |
581 | .cr = 0x08, |
582 | .isr = 0x0C, |
583 | .prer = 0x10, |
584 | .alrmar = 0x1C, |
585 | .wpr = 0x24, |
586 | .sr = 0x0C, /* set to ISR offset to ease alarm management */ |
587 | .scr = UNDEF_REG, |
588 | .verr = UNDEF_REG, |
589 | }, |
590 | .events = { |
591 | .alra = STM32_RTC_ISR_ALRAF, |
592 | }, |
593 | .clear_events = stm32_rtc_clear_events, |
594 | }; |
595 | |
596 | static void stm32mp1_rtc_clear_events(struct stm32_rtc *rtc, |
597 | unsigned int flags) |
598 | { |
599 | struct stm32_rtc_registers regs = rtc->data->regs; |
600 | |
601 | /* Flags are cleared by writing 1 in RTC_SCR */ |
602 | writel_relaxed(flags, rtc->base + regs.scr); |
603 | } |
604 | |
605 | static const struct stm32_rtc_data stm32mp1_data = { |
606 | .has_pclk = true, |
607 | .need_dbp = false, |
608 | .need_accuracy = true, |
609 | .regs = { |
610 | .tr = 0x00, |
611 | .dr = 0x04, |
612 | .cr = 0x18, |
613 | .isr = 0x0C, /* named RTC_ICSR on stm32mp1 */ |
614 | .prer = 0x10, |
615 | .alrmar = 0x40, |
616 | .wpr = 0x24, |
617 | .sr = 0x50, |
618 | .scr = 0x5C, |
619 | .verr = 0x3F4, |
620 | }, |
621 | .events = { |
622 | .alra = STM32_RTC_SR_ALRA, |
623 | }, |
624 | .clear_events = stm32mp1_rtc_clear_events, |
625 | }; |
626 | |
627 | static const struct of_device_id stm32_rtc_of_match[] = { |
628 | { .compatible = "st,stm32-rtc" , .data = &stm32_rtc_data }, |
629 | { .compatible = "st,stm32h7-rtc" , .data = &stm32h7_rtc_data }, |
630 | { .compatible = "st,stm32mp1-rtc" , .data = &stm32mp1_data }, |
631 | {} |
632 | }; |
633 | MODULE_DEVICE_TABLE(of, stm32_rtc_of_match); |
634 | |
635 | static int stm32_rtc_init(struct platform_device *pdev, |
636 | struct stm32_rtc *rtc) |
637 | { |
638 | const struct stm32_rtc_registers *regs = &rtc->data->regs; |
639 | unsigned int prer, pred_a, pred_s, pred_a_max, pred_s_max, cr; |
640 | unsigned int rate; |
641 | int ret; |
642 | |
643 | rate = clk_get_rate(clk: rtc->rtc_ck); |
644 | |
645 | /* Find prediv_a and prediv_s to obtain the 1Hz calendar clock */ |
646 | pred_a_max = STM32_RTC_PRER_PRED_A >> STM32_RTC_PRER_PRED_A_SHIFT; |
647 | pred_s_max = STM32_RTC_PRER_PRED_S >> STM32_RTC_PRER_PRED_S_SHIFT; |
648 | |
649 | if (rate > (pred_a_max + 1) * (pred_s_max + 1)) { |
650 | dev_err(&pdev->dev, "rtc_ck rate is too high: %dHz\n" , rate); |
651 | return -EINVAL; |
652 | } |
653 | |
654 | if (rtc->data->need_accuracy) { |
655 | for (pred_a = 0; pred_a <= pred_a_max; pred_a++) { |
656 | pred_s = (rate / (pred_a + 1)) - 1; |
657 | |
658 | if (pred_s <= pred_s_max && ((pred_s + 1) * (pred_a + 1)) == rate) |
659 | break; |
660 | } |
661 | } else { |
662 | for (pred_a = pred_a_max; pred_a + 1 > 0; pred_a--) { |
663 | pred_s = (rate / (pred_a + 1)) - 1; |
664 | |
665 | if (((pred_s + 1) * (pred_a + 1)) == rate) |
666 | break; |
667 | } |
668 | } |
669 | |
670 | /* |
671 | * Can't find a 1Hz, so give priority to RTC power consumption |
672 | * by choosing the higher possible value for prediv_a |
673 | */ |
674 | if (pred_s > pred_s_max || pred_a > pred_a_max) { |
675 | pred_a = pred_a_max; |
676 | pred_s = (rate / (pred_a + 1)) - 1; |
677 | |
678 | dev_warn(&pdev->dev, "rtc_ck is %s\n" , |
679 | (rate < ((pred_a + 1) * (pred_s + 1))) ? |
680 | "fast" : "slow" ); |
681 | } |
682 | |
683 | cr = readl_relaxed(rtc->base + regs->cr); |
684 | |
685 | prer = readl_relaxed(rtc->base + regs->prer); |
686 | prer &= STM32_RTC_PRER_PRED_S | STM32_RTC_PRER_PRED_A; |
687 | |
688 | pred_s = (pred_s << STM32_RTC_PRER_PRED_S_SHIFT) & |
689 | STM32_RTC_PRER_PRED_S; |
690 | pred_a = (pred_a << STM32_RTC_PRER_PRED_A_SHIFT) & |
691 | STM32_RTC_PRER_PRED_A; |
692 | |
693 | /* quit if there is nothing to initialize */ |
694 | if ((cr & STM32_RTC_CR_FMT) == 0 && prer == (pred_s | pred_a)) |
695 | return 0; |
696 | |
697 | stm32_rtc_wpr_unlock(rtc); |
698 | |
699 | ret = stm32_rtc_enter_init_mode(rtc); |
700 | if (ret) { |
701 | dev_err(&pdev->dev, |
702 | "Can't enter in init mode. Prescaler config failed.\n" ); |
703 | goto end; |
704 | } |
705 | |
706 | writel_relaxed(pred_s, rtc->base + regs->prer); |
707 | writel_relaxed(pred_a | pred_s, rtc->base + regs->prer); |
708 | |
709 | /* Force 24h time format */ |
710 | cr &= ~STM32_RTC_CR_FMT; |
711 | writel_relaxed(cr, rtc->base + regs->cr); |
712 | |
713 | stm32_rtc_exit_init_mode(rtc); |
714 | |
715 | ret = stm32_rtc_wait_sync(rtc); |
716 | end: |
717 | stm32_rtc_wpr_lock(rtc); |
718 | |
719 | return ret; |
720 | } |
721 | |
722 | static int stm32_rtc_probe(struct platform_device *pdev) |
723 | { |
724 | struct stm32_rtc *rtc; |
725 | const struct stm32_rtc_registers *regs; |
726 | int ret; |
727 | |
728 | rtc = devm_kzalloc(dev: &pdev->dev, size: sizeof(*rtc), GFP_KERNEL); |
729 | if (!rtc) |
730 | return -ENOMEM; |
731 | |
732 | rtc->base = devm_platform_ioremap_resource(pdev, index: 0); |
733 | if (IS_ERR(ptr: rtc->base)) |
734 | return PTR_ERR(ptr: rtc->base); |
735 | |
736 | rtc->data = (struct stm32_rtc_data *) |
737 | of_device_get_match_data(dev: &pdev->dev); |
738 | regs = &rtc->data->regs; |
739 | |
740 | if (rtc->data->need_dbp) { |
741 | rtc->dbp = syscon_regmap_lookup_by_phandle(np: pdev->dev.of_node, |
742 | property: "st,syscfg" ); |
743 | if (IS_ERR(ptr: rtc->dbp)) { |
744 | dev_err(&pdev->dev, "no st,syscfg\n" ); |
745 | return PTR_ERR(ptr: rtc->dbp); |
746 | } |
747 | |
748 | ret = of_property_read_u32_index(np: pdev->dev.of_node, propname: "st,syscfg" , |
749 | index: 1, out_value: &rtc->dbp_reg); |
750 | if (ret) { |
751 | dev_err(&pdev->dev, "can't read DBP register offset\n" ); |
752 | return ret; |
753 | } |
754 | |
755 | ret = of_property_read_u32_index(np: pdev->dev.of_node, propname: "st,syscfg" , |
756 | index: 2, out_value: &rtc->dbp_mask); |
757 | if (ret) { |
758 | dev_err(&pdev->dev, "can't read DBP register mask\n" ); |
759 | return ret; |
760 | } |
761 | } |
762 | |
763 | if (!rtc->data->has_pclk) { |
764 | rtc->pclk = NULL; |
765 | rtc->rtc_ck = devm_clk_get(dev: &pdev->dev, NULL); |
766 | } else { |
767 | rtc->pclk = devm_clk_get(dev: &pdev->dev, id: "pclk" ); |
768 | if (IS_ERR(ptr: rtc->pclk)) |
769 | return dev_err_probe(dev: &pdev->dev, err: PTR_ERR(ptr: rtc->pclk), fmt: "no pclk clock" ); |
770 | |
771 | rtc->rtc_ck = devm_clk_get(dev: &pdev->dev, id: "rtc_ck" ); |
772 | } |
773 | if (IS_ERR(ptr: rtc->rtc_ck)) |
774 | return dev_err_probe(dev: &pdev->dev, err: PTR_ERR(ptr: rtc->rtc_ck), fmt: "no rtc_ck clock" ); |
775 | |
776 | if (rtc->data->has_pclk) { |
777 | ret = clk_prepare_enable(clk: rtc->pclk); |
778 | if (ret) |
779 | return ret; |
780 | } |
781 | |
782 | ret = clk_prepare_enable(clk: rtc->rtc_ck); |
783 | if (ret) |
784 | goto err_no_rtc_ck; |
785 | |
786 | if (rtc->data->need_dbp) |
787 | regmap_update_bits(map: rtc->dbp, reg: rtc->dbp_reg, |
788 | mask: rtc->dbp_mask, val: rtc->dbp_mask); |
789 | |
790 | /* |
791 | * After a system reset, RTC_ISR.INITS flag can be read to check if |
792 | * the calendar has been initialized or not. INITS flag is reset by a |
793 | * power-on reset (no vbat, no power-supply). It is not reset if |
794 | * rtc_ck parent clock has changed (so RTC prescalers need to be |
795 | * changed). That's why we cannot rely on this flag to know if RTC |
796 | * init has to be done. |
797 | */ |
798 | ret = stm32_rtc_init(pdev, rtc); |
799 | if (ret) |
800 | goto err; |
801 | |
802 | rtc->irq_alarm = platform_get_irq(pdev, 0); |
803 | if (rtc->irq_alarm <= 0) { |
804 | ret = rtc->irq_alarm; |
805 | goto err; |
806 | } |
807 | |
808 | ret = device_init_wakeup(dev: &pdev->dev, enable: true); |
809 | if (ret) |
810 | goto err; |
811 | |
812 | ret = dev_pm_set_wake_irq(dev: &pdev->dev, irq: rtc->irq_alarm); |
813 | if (ret) |
814 | goto err; |
815 | |
816 | platform_set_drvdata(pdev, data: rtc); |
817 | |
818 | rtc->rtc_dev = devm_rtc_device_register(dev: &pdev->dev, name: pdev->name, |
819 | ops: &stm32_rtc_ops, THIS_MODULE); |
820 | if (IS_ERR(ptr: rtc->rtc_dev)) { |
821 | ret = PTR_ERR(ptr: rtc->rtc_dev); |
822 | dev_err(&pdev->dev, "rtc device registration failed, err=%d\n" , |
823 | ret); |
824 | goto err; |
825 | } |
826 | |
827 | /* Handle RTC alarm interrupts */ |
828 | ret = devm_request_threaded_irq(dev: &pdev->dev, irq: rtc->irq_alarm, NULL, |
829 | thread_fn: stm32_rtc_alarm_irq, IRQF_ONESHOT, |
830 | devname: pdev->name, dev_id: rtc); |
831 | if (ret) { |
832 | dev_err(&pdev->dev, "IRQ%d (alarm interrupt) already claimed\n" , |
833 | rtc->irq_alarm); |
834 | goto err; |
835 | } |
836 | |
837 | /* |
838 | * If INITS flag is reset (calendar year field set to 0x00), calendar |
839 | * must be initialized |
840 | */ |
841 | if (!(readl_relaxed(rtc->base + regs->isr) & STM32_RTC_ISR_INITS)) |
842 | dev_warn(&pdev->dev, "Date/Time must be initialized\n" ); |
843 | |
844 | if (regs->verr != UNDEF_REG) { |
845 | u32 ver = readl_relaxed(rtc->base + regs->verr); |
846 | |
847 | dev_info(&pdev->dev, "registered rev:%d.%d\n" , |
848 | (ver >> STM32_RTC_VERR_MAJREV_SHIFT) & 0xF, |
849 | (ver >> STM32_RTC_VERR_MINREV_SHIFT) & 0xF); |
850 | } |
851 | |
852 | return 0; |
853 | |
854 | err: |
855 | clk_disable_unprepare(clk: rtc->rtc_ck); |
856 | err_no_rtc_ck: |
857 | if (rtc->data->has_pclk) |
858 | clk_disable_unprepare(clk: rtc->pclk); |
859 | |
860 | if (rtc->data->need_dbp) |
861 | regmap_update_bits(map: rtc->dbp, reg: rtc->dbp_reg, mask: rtc->dbp_mask, val: 0); |
862 | |
863 | dev_pm_clear_wake_irq(dev: &pdev->dev); |
864 | device_init_wakeup(dev: &pdev->dev, enable: false); |
865 | |
866 | return ret; |
867 | } |
868 | |
869 | static void stm32_rtc_remove(struct platform_device *pdev) |
870 | { |
871 | struct stm32_rtc *rtc = platform_get_drvdata(pdev); |
872 | const struct stm32_rtc_registers *regs = &rtc->data->regs; |
873 | unsigned int cr; |
874 | |
875 | /* Disable interrupts */ |
876 | stm32_rtc_wpr_unlock(rtc); |
877 | cr = readl_relaxed(rtc->base + regs->cr); |
878 | cr &= ~STM32_RTC_CR_ALRAIE; |
879 | writel_relaxed(cr, rtc->base + regs->cr); |
880 | stm32_rtc_wpr_lock(rtc); |
881 | |
882 | clk_disable_unprepare(clk: rtc->rtc_ck); |
883 | if (rtc->data->has_pclk) |
884 | clk_disable_unprepare(clk: rtc->pclk); |
885 | |
886 | /* Enable backup domain write protection if needed */ |
887 | if (rtc->data->need_dbp) |
888 | regmap_update_bits(map: rtc->dbp, reg: rtc->dbp_reg, mask: rtc->dbp_mask, val: 0); |
889 | |
890 | dev_pm_clear_wake_irq(dev: &pdev->dev); |
891 | device_init_wakeup(dev: &pdev->dev, enable: false); |
892 | } |
893 | |
894 | static int stm32_rtc_suspend(struct device *dev) |
895 | { |
896 | struct stm32_rtc *rtc = dev_get_drvdata(dev); |
897 | |
898 | if (rtc->data->has_pclk) |
899 | clk_disable_unprepare(clk: rtc->pclk); |
900 | |
901 | return 0; |
902 | } |
903 | |
904 | static int stm32_rtc_resume(struct device *dev) |
905 | { |
906 | struct stm32_rtc *rtc = dev_get_drvdata(dev); |
907 | int ret = 0; |
908 | |
909 | if (rtc->data->has_pclk) { |
910 | ret = clk_prepare_enable(clk: rtc->pclk); |
911 | if (ret) |
912 | return ret; |
913 | } |
914 | |
915 | ret = stm32_rtc_wait_sync(rtc); |
916 | if (ret < 0) { |
917 | if (rtc->data->has_pclk) |
918 | clk_disable_unprepare(clk: rtc->pclk); |
919 | return ret; |
920 | } |
921 | |
922 | return ret; |
923 | } |
924 | |
925 | static const struct dev_pm_ops stm32_rtc_pm_ops = { |
926 | NOIRQ_SYSTEM_SLEEP_PM_OPS(stm32_rtc_suspend, stm32_rtc_resume) |
927 | }; |
928 | |
929 | static struct platform_driver stm32_rtc_driver = { |
930 | .probe = stm32_rtc_probe, |
931 | .remove_new = stm32_rtc_remove, |
932 | .driver = { |
933 | .name = DRIVER_NAME, |
934 | .pm = &stm32_rtc_pm_ops, |
935 | .of_match_table = stm32_rtc_of_match, |
936 | }, |
937 | }; |
938 | |
939 | module_platform_driver(stm32_rtc_driver); |
940 | |
941 | MODULE_ALIAS("platform:" DRIVER_NAME); |
942 | MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>" ); |
943 | MODULE_DESCRIPTION("STMicroelectronics STM32 Real Time Clock driver" ); |
944 | MODULE_LICENSE("GPL v2" ); |
945 | |