1/* SPDX-License-Identifier: GPL-2.0 */
2/* -*- mode: c; c-basic-offset: 8 -*- */
3
4/* Driver for 53c700 and 53c700-66 chips from NCR and Symbios
5 *
6 * Copyright (C) 2001 by James.Bottomley@HansenPartnership.com
7 */
8
9#ifndef _53C700_H
10#define _53C700_H
11
12#include <linux/interrupt.h>
13#include <asm/io.h>
14
15#include <scsi/scsi_device.h>
16#include <scsi/scsi_cmnd.h>
17
18/* Turn on for general debugging---too verbose for normal use */
19#undef NCR_700_DEBUG
20/* Debug the tag queues, checking hash queue allocation and deallocation
21 * and search for duplicate tags */
22#undef NCR_700_TAG_DEBUG
23
24#ifdef NCR_700_DEBUG
25#define DEBUG(x) printk x
26#define DDEBUG(prefix, sdev, fmt, a...) \
27 sdev_printk(prefix, sdev, fmt, ##a)
28#define CDEBUG(prefix, scmd, fmt, a...) \
29 scmd_printk(prefix, scmd, fmt, ##a)
30#else
31#define DEBUG(x) do {} while (0)
32#define DDEBUG(prefix, scmd, fmt, a...) do {} while (0)
33#define CDEBUG(prefix, scmd, fmt, a...) do {} while (0)
34#endif
35
36/* The number of available command slots */
37#define NCR_700_COMMAND_SLOTS_PER_HOST 64
38/* The maximum number of Scatter Gathers we allow */
39#define NCR_700_SG_SEGMENTS 32
40/* The maximum number of luns (make this of the form 2^n) */
41#define NCR_700_MAX_LUNS 32
42#define NCR_700_LUN_MASK (NCR_700_MAX_LUNS - 1)
43/* Maximum number of tags the driver ever allows per device */
44#define NCR_700_MAX_TAGS 16
45/* Tag depth the driver starts out with (can be altered in sysfs) */
46#define NCR_700_DEFAULT_TAGS 4
47/* This is the default number of commands per LUN in the untagged case.
48 * two is a good value because it means we can have one command active and
49 * one command fully prepared and waiting
50 */
51#define NCR_700_CMD_PER_LUN 2
52/* magic byte identifying an internally generated REQUEST_SENSE command */
53#define NCR_700_INTERNAL_SENSE_MAGIC 0x42
54
55struct NCR_700_Host_Parameters;
56
57/* These are the externally used routines */
58struct Scsi_Host *NCR_700_detect(struct scsi_host_template *,
59 struct NCR_700_Host_Parameters *, struct device *);
60int NCR_700_release(struct Scsi_Host *host);
61irqreturn_t NCR_700_intr(int, void *);
62
63
64enum NCR_700_Host_State {
65 NCR_700_HOST_BUSY,
66 NCR_700_HOST_FREE,
67};
68
69struct NCR_700_SG_List {
70 /* The following is a script fragment to move the buffer onto the
71 * bus and then link the next fragment or return */
72 #define SCRIPT_MOVE_DATA_IN 0x09000000
73 #define SCRIPT_MOVE_DATA_OUT 0x08000000
74 __u32 ins;
75 __u32 pAddr;
76 #define SCRIPT_NOP 0x80000000
77 #define SCRIPT_RETURN 0x90080000
78};
79
80struct NCR_700_Device_Parameters {
81 /* space for creating a request sense command. Really, except
82 * for the annoying SCSI-2 requirement for LUN information in
83 * cmnd[1], this could be in static storage */
84 unsigned char cmnd[MAX_COMMAND_SIZE];
85 __u8 depth;
86 struct scsi_cmnd *current_cmnd; /* currently active command */
87};
88
89
90/* The SYNC negotiation sequence looks like:
91 *
92 * If DEV_NEGOTIATED_SYNC not set, tack and SDTR message on to the
93 * initial identify for the device and set DEV_BEGIN_SYNC_NEGOTIATION
94 * If we get an SDTR reply, work out the SXFER parameters, squirrel
95 * them away here, clear DEV_BEGIN_SYNC_NEGOTIATION and set
96 * DEV_NEGOTIATED_SYNC. If we get a REJECT msg, squirrel
97 *
98 *
99 * 0:7 SXFER_REG negotiated value for this device
100 * 8:15 Current queue depth
101 * 16 negotiated SYNC flag
102 * 17 begin SYNC negotiation flag
103 * 18 device supports tag queueing */
104#define NCR_700_DEV_NEGOTIATED_SYNC (1<<16)
105#define NCR_700_DEV_BEGIN_SYNC_NEGOTIATION (1<<17)
106#define NCR_700_DEV_PRINT_SYNC_NEGOTIATION (1<<19)
107
108static inline char *NCR_700_get_sense_cmnd(struct scsi_device *SDp)
109{
110 struct NCR_700_Device_Parameters *hostdata = SDp->hostdata;
111
112 return hostdata->cmnd;
113}
114
115static inline void
116NCR_700_set_depth(struct scsi_device *SDp, __u8 depth)
117{
118 struct NCR_700_Device_Parameters *hostdata = SDp->hostdata;
119
120 hostdata->depth = depth;
121}
122static inline __u8
123NCR_700_get_depth(struct scsi_device *SDp)
124{
125 struct NCR_700_Device_Parameters *hostdata = SDp->hostdata;
126
127 return hostdata->depth;
128}
129static inline int
130NCR_700_is_flag_set(struct scsi_device *SDp, __u32 flag)
131{
132 return (spi_flags(SDp->sdev_target) & flag) == flag;
133}
134static inline int
135NCR_700_is_flag_clear(struct scsi_device *SDp, __u32 flag)
136{
137 return (spi_flags(SDp->sdev_target) & flag) == 0;
138}
139static inline void
140NCR_700_set_flag(struct scsi_device *SDp, __u32 flag)
141{
142 spi_flags(SDp->sdev_target) |= flag;
143}
144static inline void
145NCR_700_clear_flag(struct scsi_device *SDp, __u32 flag)
146{
147 spi_flags(SDp->sdev_target) &= ~flag;
148}
149
150enum NCR_700_tag_neg_state {
151 NCR_700_START_TAG_NEGOTIATION = 0,
152 NCR_700_DURING_TAG_NEGOTIATION = 1,
153 NCR_700_FINISHED_TAG_NEGOTIATION = 2,
154};
155
156static inline enum NCR_700_tag_neg_state
157NCR_700_get_tag_neg_state(struct scsi_device *SDp)
158{
159 return (enum NCR_700_tag_neg_state)((spi_flags(SDp->sdev_target)>>20) & 0x3);
160}
161
162static inline void
163NCR_700_set_tag_neg_state(struct scsi_device *SDp,
164 enum NCR_700_tag_neg_state state)
165{
166 /* clear the slot */
167 spi_flags(SDp->sdev_target) &= ~(0x3 << 20);
168 spi_flags(SDp->sdev_target) |= ((__u32)state) << 20;
169}
170
171struct NCR_700_command_slot {
172 struct NCR_700_SG_List SG[NCR_700_SG_SEGMENTS+1];
173 struct NCR_700_SG_List *pSG;
174 #define NCR_700_SLOT_MASK 0xFC
175 #define NCR_700_SLOT_MAGIC 0xb8
176 #define NCR_700_SLOT_FREE (0|NCR_700_SLOT_MAGIC) /* slot may be used */
177 #define NCR_700_SLOT_BUSY (1|NCR_700_SLOT_MAGIC) /* slot has command active on HA */
178 #define NCR_700_SLOT_QUEUED (2|NCR_700_SLOT_MAGIC) /* slot has command to be made active on HA */
179 __u8 state;
180 #define NCR_700_FLAG_AUTOSENSE 0x01
181 __u8 flags;
182 __u8 pad1[2]; /* Needed for m68k where min alignment is 2 bytes */
183 int tag;
184 __u32 resume_offset;
185 struct scsi_cmnd *cmnd;
186 /* The pci_mapped address of the actual command in cmnd */
187 dma_addr_t pCmd;
188 __u32 temp;
189 /* if this command is a pci_single mapping, holds the dma address
190 * for later unmapping in the done routine */
191 dma_addr_t dma_handle;
192 /* historical remnant, now used to link free commands */
193 struct NCR_700_command_slot *ITL_forw;
194};
195
196struct NCR_700_Host_Parameters {
197 /* These must be filled in by the calling driver */
198 int clock; /* board clock speed in MHz */
199 void __iomem *base; /* the base for the port (copied to host) */
200 struct device *dev;
201 __u32 dmode_extra; /* adjustable bus settings */
202 __u32 dcntl_extra; /* adjustable bus settings */
203 __u32 ctest7_extra; /* adjustable bus settings */
204 __u32 differential:1; /* if we are differential */
205#ifdef CONFIG_53C700_LE_ON_BE
206 /* This option is for HP only. Set it if your chip is wired for
207 * little endian on this platform (which is big endian) */
208 __u32 force_le_on_be:1;
209#endif
210 __u32 chip710:1; /* set if really a 710 not 700 */
211 __u32 burst_length:4; /* set to 0 to disable 710 bursting */
212
213 /* NOTHING BELOW HERE NEEDS ALTERING */
214 __u32 fast:1; /* if we can alter the SCSI bus clock
215 speed (so can negiotiate sync) */
216 int sync_clock; /* The speed of the SYNC core */
217
218 __u32 *script; /* pointer to script location */
219 __u32 pScript; /* physical mem addr of script */
220
221 enum NCR_700_Host_State state; /* protected by state lock */
222 struct scsi_cmnd *cmd;
223 /* Note: pScript contains the single consistent block of
224 * memory. All the msgin, msgout and status are allocated in
225 * this memory too (at separate cache lines). TOTAL_MEM_SIZE
226 * represents the total size of this area */
227#define MSG_ARRAY_SIZE 8
228#define MSGOUT_OFFSET (L1_CACHE_ALIGN(sizeof(SCRIPT)))
229 __u8 *msgout;
230#define MSGIN_OFFSET (MSGOUT_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE))
231 __u8 *msgin;
232#define STATUS_OFFSET (MSGIN_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE))
233 __u8 *status;
234#define SLOTS_OFFSET (STATUS_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE))
235 struct NCR_700_command_slot *slots;
236#define TOTAL_MEM_SIZE (SLOTS_OFFSET + L1_CACHE_ALIGN(sizeof(struct NCR_700_command_slot) * NCR_700_COMMAND_SLOTS_PER_HOST))
237 int saved_slot_position;
238 int command_slot_count; /* protected by state lock */
239 __u8 tag_negotiated;
240 __u8 rev;
241 __u8 reselection_id;
242 __u8 min_period;
243
244 /* Free list, singly linked by ITL_forw elements */
245 struct NCR_700_command_slot *free_list;
246 /* Completion for waited for ops, like reset, abort or
247 * device reset.
248 *
249 * NOTE: relies on single threading in the error handler to
250 * have only one outstanding at once */
251 struct completion *eh_complete;
252};
253
254/*
255 * 53C700 Register Interface - the offset from the Selected base
256 * I/O address */
257#ifdef CONFIG_53C700_LE_ON_BE
258#define bE (hostdata->force_le_on_be ? 0 : 3)
259#define bSWAP (hostdata->force_le_on_be)
260#define bEBus (!hostdata->force_le_on_be)
261#elif defined(__BIG_ENDIAN)
262#define bE 3
263#define bSWAP 0
264#elif defined(__LITTLE_ENDIAN)
265#define bE 0
266#define bSWAP 0
267#else
268#error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined, did you include byteorder.h?"
269#endif
270#ifndef bEBus
271#ifdef CONFIG_53C700_BE_BUS
272#define bEBus 1
273#else
274#define bEBus 0
275#endif
276#endif
277#define bS_to_cpu(x) (bSWAP ? le32_to_cpu(x) : (x))
278#define bS_to_host(x) (bSWAP ? cpu_to_le32(x) : (x))
279
280/* NOTE: These registers are in the LE register space only, the required byte
281 * swapping is done by the NCR_700_{read|write}[b] functions */
282#define SCNTL0_REG 0x00
283#define FULL_ARBITRATION 0xc0
284#define PARITY 0x08
285#define ENABLE_PARITY 0x04
286#define AUTO_ATN 0x02
287#define SCNTL1_REG 0x01
288#define SLOW_BUS 0x80
289#define ENABLE_SELECT 0x20
290#define ASSERT_RST 0x08
291#define ASSERT_EVEN_PARITY 0x04
292#define SDID_REG 0x02
293#define SIEN_REG 0x03
294#define PHASE_MM_INT 0x80
295#define FUNC_COMP_INT 0x40
296#define SEL_TIMEOUT_INT 0x20
297#define SELECT_INT 0x10
298#define GROSS_ERR_INT 0x08
299#define UX_DISC_INT 0x04
300#define RST_INT 0x02
301#define PAR_ERR_INT 0x01
302#define SCID_REG 0x04
303#define SXFER_REG 0x05
304#define ASYNC_OPERATION 0x00
305#define SODL_REG 0x06
306#define SOCL_REG 0x07
307#define SFBR_REG 0x08
308#define SIDL_REG 0x09
309#define SBDL_REG 0x0A
310#define SBCL_REG 0x0B
311/* read bits */
312#define SBCL_IO 0x01
313/*write bits */
314#define SYNC_DIV_AS_ASYNC 0x00
315#define SYNC_DIV_1_0 0x01
316#define SYNC_DIV_1_5 0x02
317#define SYNC_DIV_2_0 0x03
318#define DSTAT_REG 0x0C
319#define ILGL_INST_DETECTED 0x01
320#define WATCH_DOG_INTERRUPT 0x02
321#define SCRIPT_INT_RECEIVED 0x04
322#define ABORTED 0x10
323#define SSTAT0_REG 0x0D
324#define PARITY_ERROR 0x01
325#define SCSI_RESET_DETECTED 0x02
326#define UNEXPECTED_DISCONNECT 0x04
327#define SCSI_GROSS_ERROR 0x08
328#define SELECTED 0x10
329#define SELECTION_TIMEOUT 0x20
330#define FUNCTION_COMPLETE 0x40
331#define PHASE_MISMATCH 0x80
332#define SSTAT1_REG 0x0E
333#define SIDL_REG_FULL 0x80
334#define SODR_REG_FULL 0x40
335#define SODL_REG_FULL 0x20
336#define SSTAT2_REG 0x0F
337#define CTEST0_REG 0x14
338#define BTB_TIMER_DISABLE 0x40
339#define CTEST1_REG 0x15
340#define CTEST2_REG 0x16
341#define CTEST3_REG 0x17
342#define CTEST4_REG 0x18
343#define DISABLE_FIFO 0x00
344#define SLBE 0x10
345#define SFWR 0x08
346#define BYTE_LANE0 0x04
347#define BYTE_LANE1 0x05
348#define BYTE_LANE2 0x06
349#define BYTE_LANE3 0x07
350#define SCSI_ZMODE 0x20
351#define ZMODE 0x40
352#define CTEST5_REG 0x19
353#define MASTER_CONTROL 0x10
354#define DMA_DIRECTION 0x08
355#define CTEST7_REG 0x1B
356#define BURST_DISABLE 0x80 /* 710 only */
357#define SEL_TIMEOUT_DISABLE 0x10 /* 710 only */
358#define DFP 0x08
359#define EVP 0x04
360#define CTEST7_TT1 0x02
361#define DIFF 0x01
362#define CTEST6_REG 0x1A
363#define TEMP_REG 0x1C
364#define DFIFO_REG 0x20
365#define FLUSH_DMA_FIFO 0x80
366#define CLR_FIFO 0x40
367#define ISTAT_REG 0x21
368#define ABORT_OPERATION 0x80
369#define SOFTWARE_RESET_710 0x40
370#define DMA_INT_PENDING 0x01
371#define SCSI_INT_PENDING 0x02
372#define CONNECTED 0x08
373#define CTEST8_REG 0x22
374#define LAST_DIS_ENBL 0x01
375#define SHORTEN_FILTERING 0x04
376#define ENABLE_ACTIVE_NEGATION 0x10
377#define GENERATE_RECEIVE_PARITY 0x20
378#define CLR_FIFO_710 0x04
379#define FLUSH_DMA_FIFO_710 0x08
380#define CTEST9_REG 0x23
381#define DBC_REG 0x24
382#define DCMD_REG 0x27
383#define DNAD_REG 0x28
384#define DIEN_REG 0x39
385#define BUS_FAULT 0x20
386#define ABORT_INT 0x10
387#define INT_INST_INT 0x04
388#define WD_INT 0x02
389#define ILGL_INST_INT 0x01
390#define DCNTL_REG 0x3B
391#define SOFTWARE_RESET 0x01
392#define COMPAT_700_MODE 0x01
393#define SCRPTS_16BITS 0x20
394#define EA_710 0x20
395#define ASYNC_DIV_2_0 0x00
396#define ASYNC_DIV_1_5 0x40
397#define ASYNC_DIV_1_0 0x80
398#define ASYNC_DIV_3_0 0xc0
399#define DMODE_710_REG 0x38
400#define DMODE_700_REG 0x34
401#define BURST_LENGTH_1 0x00
402#define BURST_LENGTH_2 0x40
403#define BURST_LENGTH_4 0x80
404#define BURST_LENGTH_8 0xC0
405#define DMODE_FC1 0x10
406#define DMODE_FC2 0x20
407#define BW16 32
408#define MODE_286 16
409#define IO_XFER 8
410#define FIXED_ADDR 4
411
412#define DSP_REG 0x2C
413#define DSPS_REG 0x30
414
415/* Parameters to begin SDTR negotiations. Empirically, I find that
416 * the 53c700-66 cannot handle an offset >8, so don't change this */
417#define NCR_700_MAX_OFFSET 8
418/* Was hoping the max offset would be greater for the 710, but
419 * empirically it seems to be 8 also */
420#define NCR_710_MAX_OFFSET 8
421#define NCR_700_MIN_XFERP 1
422#define NCR_710_MIN_XFERP 0
423#define NCR_700_MIN_PERIOD 25 /* for SDTR message, 100ns */
424
425#define script_patch_32(dev, script, symbol, value) \
426{ \
427 int i; \
428 dma_addr_t da = value; \
429 for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \
430 __u32 val = bS_to_cpu((script)[A_##symbol##_used[i]]) + da; \
431 (script)[A_##symbol##_used[i]] = bS_to_host(val); \
432 dma_cache_sync((dev), &(script)[A_##symbol##_used[i]], 4, DMA_TO_DEVICE); \
433 DEBUG((" script, patching %s at %d to %pad\n", \
434 #symbol, A_##symbol##_used[i], &da)); \
435 } \
436}
437
438#define script_patch_32_abs(dev, script, symbol, value) \
439{ \
440 int i; \
441 dma_addr_t da = value; \
442 for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \
443 (script)[A_##symbol##_used[i]] = bS_to_host(da); \
444 dma_cache_sync((dev), &(script)[A_##symbol##_used[i]], 4, DMA_TO_DEVICE); \
445 DEBUG((" script, patching %s at %d to %pad\n", \
446 #symbol, A_##symbol##_used[i], &da)); \
447 } \
448}
449
450/* Used for patching the SCSI ID in the SELECT instruction */
451#define script_patch_ID(dev, script, symbol, value) \
452{ \
453 int i; \
454 for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \
455 __u32 val = bS_to_cpu((script)[A_##symbol##_used[i]]); \
456 val &= 0xff00ffff; \
457 val |= ((value) & 0xff) << 16; \
458 (script)[A_##symbol##_used[i]] = bS_to_host(val); \
459 dma_cache_sync((dev), &(script)[A_##symbol##_used[i]], 4, DMA_TO_DEVICE); \
460 DEBUG((" script, patching ID field %s at %d to 0x%x\n", \
461 #symbol, A_##symbol##_used[i], val)); \
462 } \
463}
464
465#define script_patch_16(dev, script, symbol, value) \
466{ \
467 int i; \
468 for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \
469 __u32 val = bS_to_cpu((script)[A_##symbol##_used[i]]); \
470 val &= 0xffff0000; \
471 val |= ((value) & 0xffff); \
472 (script)[A_##symbol##_used[i]] = bS_to_host(val); \
473 dma_cache_sync((dev), &(script)[A_##symbol##_used[i]], 4, DMA_TO_DEVICE); \
474 DEBUG((" script, patching short field %s at %d to 0x%x\n", \
475 #symbol, A_##symbol##_used[i], val)); \
476 } \
477}
478
479
480static inline __u8
481NCR_700_readb(struct Scsi_Host *host, __u32 reg)
482{
483 const struct NCR_700_Host_Parameters *hostdata
484 = (struct NCR_700_Host_Parameters *)host->hostdata[0];
485
486 return ioread8(hostdata->base + (reg^bE));
487}
488
489static inline __u32
490NCR_700_readl(struct Scsi_Host *host, __u32 reg)
491{
492 const struct NCR_700_Host_Parameters *hostdata
493 = (struct NCR_700_Host_Parameters *)host->hostdata[0];
494 __u32 value = bEBus ? ioread32be(hostdata->base + reg) :
495 ioread32(hostdata->base + reg);
496#if 1
497 /* sanity check the register */
498 BUG_ON((reg & 0x3) != 0);
499#endif
500
501 return value;
502}
503
504static inline void
505NCR_700_writeb(__u8 value, struct Scsi_Host *host, __u32 reg)
506{
507 const struct NCR_700_Host_Parameters *hostdata
508 = (struct NCR_700_Host_Parameters *)host->hostdata[0];
509
510 iowrite8(value, hostdata->base + (reg^bE));
511}
512
513static inline void
514NCR_700_writel(__u32 value, struct Scsi_Host *host, __u32 reg)
515{
516 const struct NCR_700_Host_Parameters *hostdata
517 = (struct NCR_700_Host_Parameters *)host->hostdata[0];
518
519#if 1
520 /* sanity check the register */
521 BUG_ON((reg & 0x3) != 0);
522#endif
523
524 bEBus ? iowrite32be(value, hostdata->base + reg):
525 iowrite32(value, hostdata->base + reg);
526}
527
528#endif
529