| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | #ifndef _AHA152X_H |
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| 3 | #define _AHA152X_H |
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| 4 | |
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| 5 | /* |
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| 6 | * $Id: aha152x.h,v 2.7 2004/01/24 11:39:03 fischer Exp $ |
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| 7 | */ |
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| 8 | |
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| 9 | /* number of queueable commands |
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| 10 | (unless we support more than 1 cmd_per_lun this should do) */ |
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| 11 | #define AHA152X_MAXQUEUE 7 |
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| 12 | |
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| 13 | #define AHA152X_REVID "Adaptec 152x SCSI driver; $Revision: 2.7 $" |
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| 14 | |
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| 15 | /* port addresses */ |
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| 16 | #define SCSISEQ (HOSTIOPORT0+0x00) /* SCSI sequence control */ |
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| 17 | #define SXFRCTL0 (HOSTIOPORT0+0x01) /* SCSI transfer control 0 */ |
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| 18 | #define SXFRCTL1 (HOSTIOPORT0+0x02) /* SCSI transfer control 1 */ |
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| 19 | #define SCSISIG (HOSTIOPORT0+0x03) /* SCSI signal in/out */ |
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| 20 | #define SCSIRATE (HOSTIOPORT0+0x04) /* SCSI rate control */ |
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| 21 | #define SELID (HOSTIOPORT0+0x05) /* selection/reselection ID */ |
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| 22 | #define SCSIID SELID /* SCSI ID */ |
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| 23 | #define SCSIDAT (HOSTIOPORT0+0x06) /* SCSI latched data */ |
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| 24 | #define SCSIBUS (HOSTIOPORT0+0x07) /* SCSI data bus */ |
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| 25 | #define STCNT0 (HOSTIOPORT0+0x08) /* SCSI transfer count 0 */ |
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| 26 | #define STCNT1 (HOSTIOPORT0+0x09) /* SCSI transfer count 1 */ |
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| 27 | #define STCNT2 (HOSTIOPORT0+0x0a) /* SCSI transfer count 2 */ |
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| 28 | #define SSTAT0 (HOSTIOPORT0+0x0b) /* SCSI interrupt status 0 */ |
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| 29 | #define SSTAT1 (HOSTIOPORT0+0x0c) /* SCSI interrupt status 1 */ |
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| 30 | #define SSTAT2 (HOSTIOPORT0+0x0d) /* SCSI interrupt status 2 */ |
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| 31 | #define SCSITEST (HOSTIOPORT0+0x0e) /* SCSI test control */ |
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| 32 | #define SSTAT3 SCSITEST /* SCSI interrupt status 3 */ |
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| 33 | #define SSTAT4 (HOSTIOPORT0+0x0f) /* SCSI status 4 */ |
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| 34 | #define SIMODE0 (HOSTIOPORT1+0x10) /* SCSI interrupt mode 0 */ |
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| 35 | #define SIMODE1 (HOSTIOPORT1+0x11) /* SCSI interrupt mode 1 */ |
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| 36 | #define DMACNTRL0 (HOSTIOPORT1+0x12) /* DMA control 0 */ |
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| 37 | #define DMACNTRL1 (HOSTIOPORT1+0x13) /* DMA control 1 */ |
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| 38 | #define DMASTAT (HOSTIOPORT1+0x14) /* DMA status */ |
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| 39 | #define FIFOSTAT (HOSTIOPORT1+0x15) /* FIFO status */ |
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| 40 | #define DATAPORT (HOSTIOPORT1+0x16) /* DATA port */ |
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| 41 | #define BRSTCNTRL (HOSTIOPORT1+0x18) /* burst control */ |
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| 42 | #define PORTA (HOSTIOPORT1+0x1a) /* PORT A */ |
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| 43 | #define PORTB (HOSTIOPORT1+0x1b) /* PORT B */ |
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| 44 | #define REV (HOSTIOPORT1+0x1c) /* revision */ |
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| 45 | #define STACK (HOSTIOPORT1+0x1d) /* stack */ |
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| 46 | #define TEST (HOSTIOPORT1+0x1e) /* test register */ |
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| 47 | |
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| 48 | #define IO_RANGE 0x20 |
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| 49 | |
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| 50 | /* used in aha152x_porttest */ |
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| 51 | #define O_PORTA 0x1a /* PORT A */ |
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| 52 | #define O_PORTB 0x1b /* PORT B */ |
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| 53 | #define O_DMACNTRL1 0x13 /* DMA control 1 */ |
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| 54 | #define O_STACK 0x1d /* stack */ |
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| 55 | |
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| 56 | /* used in tc1550_porttest */ |
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| 57 | #define O_TC_PORTA 0x0a /* PORT A */ |
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| 58 | #define O_TC_PORTB 0x0b /* PORT B */ |
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| 59 | #define O_TC_DMACNTRL1 0x03 /* DMA control 1 */ |
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| 60 | #define O_TC_STACK 0x0d /* stack */ |
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| 61 | |
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| 62 | /* bits and bitmasks to ports */ |
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| 63 | |
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| 64 | /* SCSI sequence control */ |
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| 65 | #define TEMODEO 0x80 |
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| 66 | #define ENSELO 0x40 |
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| 67 | #define ENSELI 0x20 |
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| 68 | #define ENRESELI 0x10 |
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| 69 | #define ENAUTOATNO 0x08 |
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| 70 | #define ENAUTOATNI 0x04 |
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| 71 | #define ENAUTOATNP 0x02 |
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| 72 | #define SCSIRSTO 0x01 |
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| 73 | |
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| 74 | /* SCSI transfer control 0 */ |
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| 75 | #define SCSIEN 0x80 |
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| 76 | #define DMAEN 0x40 |
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| 77 | #define CH1 0x20 |
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| 78 | #define CLRSTCNT 0x10 |
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| 79 | #define SPIOEN 0x08 |
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| 80 | #define CLRCH1 0x02 |
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| 81 | |
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| 82 | /* SCSI transfer control 1 */ |
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| 83 | #define BITBUCKET 0x80 |
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| 84 | #define SWRAPEN 0x40 |
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| 85 | #define ENSPCHK 0x20 |
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| 86 | #define STIMESEL 0x18 /* mask */ |
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| 87 | #define STIMESEL_ 3 |
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| 88 | #define ENSTIMER 0x04 |
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| 89 | #define BYTEALIGN 0x02 |
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| 90 | |
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| 91 | /* SCSI signal IN */ |
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| 92 | #define SIG_CDI 0x80 |
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| 93 | #define SIG_IOI 0x40 |
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| 94 | #define SIG_MSGI 0x20 |
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| 95 | #define SIG_ATNI 0x10 |
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| 96 | #define SIG_SELI 0x08 |
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| 97 | #define SIG_BSYI 0x04 |
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| 98 | #define SIG_REQI 0x02 |
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| 99 | #define SIG_ACKI 0x01 |
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| 100 | |
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| 101 | /* SCSI Phases */ |
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| 102 | #define P_MASK (SIG_MSGI|SIG_CDI|SIG_IOI) |
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| 103 | #define P_DATAO (0) |
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| 104 | #define P_DATAI (SIG_IOI) |
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| 105 | #define P_CMD (SIG_CDI) |
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| 106 | #define P_STATUS (SIG_CDI|SIG_IOI) |
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| 107 | #define P_MSGO (SIG_MSGI|SIG_CDI) |
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| 108 | #define P_MSGI (SIG_MSGI|SIG_CDI|SIG_IOI) |
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| 109 | |
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| 110 | /* SCSI signal OUT */ |
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| 111 | #define SIG_CDO 0x80 |
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| 112 | #define SIG_IOO 0x40 |
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| 113 | #define SIG_MSGO 0x20 |
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| 114 | #define SIG_ATNO 0x10 |
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| 115 | #define SIG_SELO 0x08 |
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| 116 | #define SIG_BSYO 0x04 |
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| 117 | #define SIG_REQO 0x02 |
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| 118 | #define SIG_ACKO 0x01 |
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| 119 | |
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| 120 | /* SCSI rate control */ |
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| 121 | #define SXFR 0x70 /* mask */ |
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| 122 | #define SXFR_ 4 |
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| 123 | #define SOFS 0x0f /* mask */ |
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| 124 | |
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| 125 | /* SCSI ID */ |
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| 126 | #define OID 0x70 |
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| 127 | #define OID_ 4 |
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| 128 | #define TID 0x07 |
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| 129 | |
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| 130 | /* SCSI transfer count */ |
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| 131 | #define GETSTCNT() ( (GETPORT(STCNT2)<<16) \ |
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| 132 | + (GETPORT(STCNT1)<< 8) \ |
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| 133 | + GETPORT(STCNT0) ) |
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| 134 | |
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| 135 | #define SETSTCNT(X) { SETPORT(STCNT2, ((X) & 0xFF0000) >> 16); \ |
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| 136 | SETPORT(STCNT1, ((X) & 0x00FF00) >> 8); \ |
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| 137 | SETPORT(STCNT0, ((X) & 0x0000FF) ); } |
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| 138 | |
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| 139 | /* SCSI interrupt status */ |
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| 140 | #define TARGET 0x80 |
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| 141 | #define SELDO 0x40 |
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| 142 | #define SELDI 0x20 |
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| 143 | #define SELINGO 0x10 |
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| 144 | #define SWRAP 0x08 |
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| 145 | #define SDONE 0x04 |
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| 146 | #define SPIORDY 0x02 |
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| 147 | #define DMADONE 0x01 |
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| 148 | |
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| 149 | #define SETSDONE 0x80 |
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| 150 | #define CLRSELDO 0x40 |
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| 151 | #define CLRSELDI 0x20 |
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| 152 | #define CLRSELINGO 0x10 |
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| 153 | #define CLRSWRAP 0x08 |
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| 154 | #define CLRSDONE 0x04 |
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| 155 | #define CLRSPIORDY 0x02 |
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| 156 | #define CLRDMADONE 0x01 |
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| 157 | |
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| 158 | /* SCSI status 1 */ |
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| 159 | #define SELTO 0x80 |
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| 160 | #define ATNTARG 0x40 |
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| 161 | #define SCSIRSTI 0x20 |
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| 162 | #define PHASEMIS 0x10 |
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| 163 | #define BUSFREE 0x08 |
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| 164 | #define SCSIPERR 0x04 |
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| 165 | #define PHASECHG 0x02 |
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| 166 | #define REQINIT 0x01 |
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| 167 | |
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| 168 | #define CLRSELTIMO 0x80 |
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| 169 | #define CLRATNO 0x40 |
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| 170 | #define CLRSCSIRSTI 0x20 |
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| 171 | #define CLRBUSFREE 0x08 |
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| 172 | #define CLRSCSIPERR 0x04 |
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| 173 | #define CLRPHASECHG 0x02 |
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| 174 | #define CLRREQINIT 0x01 |
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| 175 | |
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| 176 | /* SCSI status 2 */ |
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| 177 | #define SOFFSET 0x20 |
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| 178 | #define SEMPTY 0x10 |
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| 179 | #define SFULL 0x08 |
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| 180 | #define SFCNT 0x07 /* mask */ |
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| 181 | |
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| 182 | /* SCSI status 3 */ |
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| 183 | #define SCSICNT 0xf0 /* mask */ |
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| 184 | #define SCSICNT_ 4 |
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| 185 | #define OFFCNT 0x0f /* mask */ |
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| 186 | |
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| 187 | /* SCSI TEST control */ |
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| 188 | #define SCTESTU 0x08 |
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| 189 | #define SCTESTD 0x04 |
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| 190 | #define STCTEST 0x01 |
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| 191 | |
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| 192 | /* SCSI status 4 */ |
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| 193 | #define SYNCERR 0x04 |
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| 194 | #define FWERR 0x02 |
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| 195 | #define FRERR 0x01 |
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| 196 | |
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| 197 | #define CLRSYNCERR 0x04 |
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| 198 | #define CLRFWERR 0x02 |
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| 199 | #define CLRFRERR 0x01 |
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| 200 | |
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| 201 | /* SCSI interrupt mode 0 */ |
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| 202 | #define ENSELDO 0x40 |
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| 203 | #define ENSELDI 0x20 |
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| 204 | #define ENSELINGO 0x10 |
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| 205 | #define ENSWRAP 0x08 |
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| 206 | #define ENSDONE 0x04 |
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| 207 | #define ENSPIORDY 0x02 |
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| 208 | #define ENDMADONE 0x01 |
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| 209 | |
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| 210 | /* SCSI interrupt mode 1 */ |
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| 211 | #define ENSELTIMO 0x80 |
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| 212 | #define ENATNTARG 0x40 |
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| 213 | #define ENSCSIRST 0x20 |
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| 214 | #define ENPHASEMIS 0x10 |
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| 215 | #define ENBUSFREE 0x08 |
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| 216 | #define ENSCSIPERR 0x04 |
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| 217 | #define ENPHASECHG 0x02 |
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| 218 | #define ENREQINIT 0x01 |
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| 219 | |
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| 220 | /* DMA control 0 */ |
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| 221 | #define ENDMA 0x80 |
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| 222 | #define _8BIT 0x40 |
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| 223 | #define DMA 0x20 |
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| 224 | #define WRITE_READ 0x08 |
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| 225 | #define INTEN 0x04 |
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| 226 | #define RSTFIFO 0x02 |
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| 227 | #define SWINT 0x01 |
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| 228 | |
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| 229 | /* DMA control 1 */ |
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| 230 | #define PWRDWN 0x80 |
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| 231 | #define STK 0x07 /* mask */ |
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| 232 | |
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| 233 | /* DMA status */ |
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| 234 | #define ATDONE 0x80 |
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| 235 | #define WORDRDY 0x40 |
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| 236 | #define INTSTAT 0x20 |
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| 237 | #define DFIFOFULL 0x10 |
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| 238 | #define DFIFOEMP 0x08 |
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| 239 | |
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| 240 | /* BURST control */ |
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| 241 | #define BON 0xf0 |
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| 242 | #define BOFF 0x0f |
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| 243 | |
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| 244 | /* TEST REGISTER */ |
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| 245 | #define BOFFTMR 0x40 |
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| 246 | #define BONTMR 0x20 |
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| 247 | #define STCNTH 0x10 |
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| 248 | #define STCNTM 0x08 |
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| 249 | #define STCNTL 0x04 |
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| 250 | #define SCSIBLK 0x02 |
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| 251 | #define DMABLK 0x01 |
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| 252 | |
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| 253 | /* On the AHA-152x board PORTA and PORTB contain |
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| 254 | some information about the board's configuration. */ |
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| 255 | typedef union { |
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| 256 | struct { |
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| 257 | unsigned reserved:2; /* reserved */ |
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| 258 | unsigned tardisc:1; /* Target disconnect: 0=disabled, 1=enabled */ |
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| 259 | unsigned syncneg:1; /* Initial sync neg: 0=disabled, 1=enabled */ |
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| 260 | unsigned msgclasses:2; /* Message classes |
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| 261 | 0=#4 |
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| 262 | 1=#0, #1, #2, #3, #4 |
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| 263 | 2=#0, #3, #4 |
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| 264 | 3=#0, #4 |
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| 265 | */ |
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| 266 | unsigned boot:1; /* boot: 0=disabled, 1=enabled */ |
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| 267 | unsigned dma:1; /* Transfer mode: 0=PIO; 1=DMA */ |
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| 268 | unsigned id:3; /* SCSI-id */ |
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| 269 | unsigned irq:2; /* IRQ-Channel: 0,3=12, 1=10, 2=11 */ |
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| 270 | unsigned dmachan:2; /* DMA-Channel: 0=0, 1=5, 2=6, 3=7 */ |
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| 271 | unsigned parity:1; /* SCSI-parity: 1=enabled 0=disabled */ |
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| 272 | } fields; |
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| 273 | unsigned short port; |
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| 274 | } aha152x_config ; |
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| 275 | |
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| 276 | #define cf_parity fields.parity |
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| 277 | #define cf_dmachan fields.dmachan |
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| 278 | #define cf_irq fields.irq |
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| 279 | #define cf_id fields.id |
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| 280 | #define cf_dma fields.dma |
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| 281 | #define cf_boot fields.boot |
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| 282 | #define cf_msgclasses fields.msgclasses |
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| 283 | #define cf_syncneg fields.syncneg |
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| 284 | #define cf_tardisc fields.tardisc |
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| 285 | #define cf_port port |
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| 286 | |
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| 287 | /* Some macros to manipulate ports and their bits */ |
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| 288 | |
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| 289 | #define SETPORT(PORT, VAL) outb( (VAL), (PORT) ) |
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| 290 | #define GETPORT(PORT) inb( PORT ) |
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| 291 | #define SETBITS(PORT, BITS) outb( (inb(PORT) | (BITS)), (PORT) ) |
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| 292 | #define CLRBITS(PORT, BITS) outb( (inb(PORT) & ~(BITS)), (PORT) ) |
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| 293 | #define TESTHI(PORT, BITS) ((inb(PORT) & (BITS)) == (BITS)) |
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| 294 | #define TESTLO(PORT, BITS) ((inb(PORT) & (BITS)) == 0) |
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| 295 | |
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| 296 | #define SETRATE(RATE) SETPORT(SCSIRATE,(RATE) & 0x7f) |
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| 297 | |
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| 298 | #if defined(AHA152X_DEBUG) |
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| 299 | enum { |
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| 300 | debug_procinfo = 0x0001, |
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| 301 | debug_queue = 0x0002, |
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| 302 | debug_locking = 0x0004, |
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| 303 | debug_intr = 0x0008, |
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| 304 | debug_selection = 0x0010, |
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| 305 | debug_msgo = 0x0020, |
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| 306 | debug_msgi = 0x0040, |
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| 307 | debug_status = 0x0080, |
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| 308 | debug_cmd = 0x0100, |
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| 309 | debug_datai = 0x0200, |
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| 310 | debug_datao = 0x0400, |
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| 311 | debug_eh = 0x0800, |
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| 312 | debug_done = 0x1000, |
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| 313 | debug_phases = 0x2000, |
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| 314 | }; |
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| 315 | #endif |
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| 316 | |
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| 317 | /* for the pcmcia stub */ |
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| 318 | struct aha152x_setup { |
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| 319 | int io_port; |
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| 320 | int irq; |
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| 321 | int scsiid; |
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| 322 | int reconnect; |
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| 323 | int parity; |
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| 324 | int synchronous; |
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| 325 | int delay; |
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| 326 | int ext_trans; |
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| 327 | int tc1550; |
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| 328 | #if defined(AHA152X_DEBUG) |
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| 329 | int debug; |
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| 330 | #endif |
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| 331 | char *conf; |
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| 332 | }; |
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| 333 | |
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| 334 | struct Scsi_Host *aha152x_probe_one(struct aha152x_setup *); |
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| 335 | void aha152x_release(struct Scsi_Host *); |
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| 336 | int aha152x_host_reset_host(struct Scsi_Host *); |
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| 337 | |
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| 338 | #endif /* _AHA152X_H */ |
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| 339 | |
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