1/*
2*******************************************************************************
3** O.S : Linux
4** FILE NAME : arcmsr.h
5** BY : Nick Cheng
6** Description: SCSI RAID Device Driver for
7** ARECA RAID Host adapter
8*******************************************************************************
9** Copyright (C) 2002 - 2005, Areca Technology Corporation All rights reserved.
10**
11** Web site: www.areca.com.tw
12** E-mail: support@areca.com.tw
13**
14** This program is free software; you can redistribute it and/or modify
15** it under the terms of the GNU General Public License version 2 as
16** published by the Free Software Foundation.
17** This program is distributed in the hope that it will be useful,
18** but WITHOUT ANY WARRANTY; without even the implied warranty of
19** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20** GNU General Public License for more details.
21*******************************************************************************
22** Redistribution and use in source and binary forms, with or without
23** modification, are permitted provided that the following conditions
24** are met:
25** 1. Redistributions of source code must retain the above copyright
26** notice, this list of conditions and the following disclaimer.
27** 2. Redistributions in binary form must reproduce the above copyright
28** notice, this list of conditions and the following disclaimer in the
29** documentation and/or other materials provided with the distribution.
30** 3. The name of the author may not be used to endorse or promote products
31** derived from this software without specific prior written permission.
32**
33** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
34** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
35** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
36** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
37** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT
38** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
39** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY
40** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
41**(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF
42** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43*******************************************************************************
44*/
45#include <linux/interrupt.h>
46struct device_attribute;
47/*The limit of outstanding scsi command that firmware can handle*/
48#define ARCMSR_NAME "arcmsr"
49#define ARCMSR_MAX_FREECCB_NUM 1024
50#define ARCMSR_MAX_OUTSTANDING_CMD 1024
51#define ARCMSR_DEFAULT_OUTSTANDING_CMD 128
52#define ARCMSR_MIN_OUTSTANDING_CMD 32
53#define ARCMSR_DRIVER_VERSION "v1.50.00.13-20230206"
54#define ARCMSR_SCSI_INITIATOR_ID 255
55#define ARCMSR_MAX_XFER_SECTORS 512
56#define ARCMSR_MAX_XFER_SECTORS_B 4096
57#define ARCMSR_MAX_XFER_SECTORS_C 304
58#define ARCMSR_MAX_TARGETID 17
59#define ARCMSR_MAX_TARGETLUN 8
60#define ARCMSR_MAX_CMD_PERLUN 128
61#define ARCMSR_DEFAULT_CMD_PERLUN 32
62#define ARCMSR_MIN_CMD_PERLUN 1
63#define ARCMSR_MAX_QBUFFER 4096
64#define ARCMSR_DEFAULT_SG_ENTRIES 38
65#define ARCMSR_MAX_HBB_POSTQUEUE 264
66#define ARCMSR_MAX_ARC1214_POSTQUEUE 256
67#define ARCMSR_MAX_ARC1214_DONEQUEUE 257
68#define ARCMSR_MAX_HBE_DONEQUEUE 512
69#define ARCMSR_MAX_XFER_LEN 0x26000 /* 152K */
70#define ARCMSR_CDB_SG_PAGE_LENGTH 256
71#define ARCMST_NUM_MSIX_VECTORS 4
72#ifndef PCI_DEVICE_ID_ARECA_1880
73#define PCI_DEVICE_ID_ARECA_1880 0x1880
74#endif
75#ifndef PCI_DEVICE_ID_ARECA_1214
76#define PCI_DEVICE_ID_ARECA_1214 0x1214
77#endif
78#ifndef PCI_DEVICE_ID_ARECA_1203
79#define PCI_DEVICE_ID_ARECA_1203 0x1203
80#endif
81#ifndef PCI_DEVICE_ID_ARECA_1884
82#define PCI_DEVICE_ID_ARECA_1884 0x1884
83#endif
84#define PCI_DEVICE_ID_ARECA_1886 0x188A
85#define ARCMSR_HOURS (1000 * 60 * 60 * 4)
86#define ARCMSR_MINUTES (1000 * 60 * 60)
87#define ARCMSR_DEFAULT_TIMEOUT 90
88/*
89**********************************************************************************
90**
91**********************************************************************************
92*/
93#define ARC_SUCCESS 0
94#define ARC_FAILURE 1
95/*
96*******************************************************************************
97** split 64bits dma addressing
98*******************************************************************************
99*/
100#define dma_addr_hi32(addr) (uint32_t) ((addr>>16)>>16)
101#define dma_addr_lo32(addr) (uint32_t) (addr & 0xffffffff)
102/*
103*******************************************************************************
104** MESSAGE CONTROL CODE
105*******************************************************************************
106*/
107struct CMD_MESSAGE
108{
109 uint32_t HeaderLength;
110 uint8_t Signature[8];
111 uint32_t Timeout;
112 uint32_t ControlCode;
113 uint32_t ReturnCode;
114 uint32_t Length;
115};
116/*
117*******************************************************************************
118** IOP Message Transfer Data for user space
119*******************************************************************************
120*/
121#define ARCMSR_API_DATA_BUFLEN 1032
122struct CMD_MESSAGE_FIELD
123{
124 struct CMD_MESSAGE cmdmessage;
125 uint8_t messagedatabuffer[ARCMSR_API_DATA_BUFLEN];
126};
127/* IOP message transfer */
128#define ARCMSR_MESSAGE_FAIL 0x0001
129/* DeviceType */
130#define ARECA_SATA_RAID 0x90000000
131/* FunctionCode */
132#define FUNCTION_READ_RQBUFFER 0x0801
133#define FUNCTION_WRITE_WQBUFFER 0x0802
134#define FUNCTION_CLEAR_RQBUFFER 0x0803
135#define FUNCTION_CLEAR_WQBUFFER 0x0804
136#define FUNCTION_CLEAR_ALLQBUFFER 0x0805
137#define FUNCTION_RETURN_CODE_3F 0x0806
138#define FUNCTION_SAY_HELLO 0x0807
139#define FUNCTION_SAY_GOODBYE 0x0808
140#define FUNCTION_FLUSH_ADAPTER_CACHE 0x0809
141#define FUNCTION_GET_FIRMWARE_STATUS 0x080A
142#define FUNCTION_HARDWARE_RESET 0x080B
143/* ARECA IO CONTROL CODE*/
144#define ARCMSR_MESSAGE_READ_RQBUFFER \
145 ARECA_SATA_RAID | FUNCTION_READ_RQBUFFER
146#define ARCMSR_MESSAGE_WRITE_WQBUFFER \
147 ARECA_SATA_RAID | FUNCTION_WRITE_WQBUFFER
148#define ARCMSR_MESSAGE_CLEAR_RQBUFFER \
149 ARECA_SATA_RAID | FUNCTION_CLEAR_RQBUFFER
150#define ARCMSR_MESSAGE_CLEAR_WQBUFFER \
151 ARECA_SATA_RAID | FUNCTION_CLEAR_WQBUFFER
152#define ARCMSR_MESSAGE_CLEAR_ALLQBUFFER \
153 ARECA_SATA_RAID | FUNCTION_CLEAR_ALLQBUFFER
154#define ARCMSR_MESSAGE_RETURN_CODE_3F \
155 ARECA_SATA_RAID | FUNCTION_RETURN_CODE_3F
156#define ARCMSR_MESSAGE_SAY_HELLO \
157 ARECA_SATA_RAID | FUNCTION_SAY_HELLO
158#define ARCMSR_MESSAGE_SAY_GOODBYE \
159 ARECA_SATA_RAID | FUNCTION_SAY_GOODBYE
160#define ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE \
161 ARECA_SATA_RAID | FUNCTION_FLUSH_ADAPTER_CACHE
162/* ARECA IOCTL ReturnCode */
163#define ARCMSR_MESSAGE_RETURNCODE_OK 0x00000001
164#define ARCMSR_MESSAGE_RETURNCODE_ERROR 0x00000006
165#define ARCMSR_MESSAGE_RETURNCODE_3F 0x0000003F
166#define ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON 0x00000088
167/*
168*************************************************************
169** structure for holding DMA address data
170*************************************************************
171*/
172#define IS_DMA64 (sizeof(dma_addr_t) == 8)
173#define IS_SG64_ADDR 0x01000000 /* bit24 */
174struct SG32ENTRY
175{
176 __le32 length;
177 __le32 address;
178}__attribute__ ((packed));
179struct SG64ENTRY
180{
181 __le32 length;
182 __le32 address;
183 __le32 addresshigh;
184}__attribute__ ((packed));
185/*
186********************************************************************
187** Q Buffer of IOP Message Transfer
188********************************************************************
189*/
190struct QBUFFER
191{
192 uint32_t data_len;
193 uint8_t data[124];
194};
195/*
196*******************************************************************************
197** FIRMWARE INFO for Intel IOP R 80331 processor (Type A)
198*******************************************************************************
199*/
200struct FIRMWARE_INFO
201{
202 uint32_t signature; /*0, 00-03*/
203 uint32_t request_len; /*1, 04-07*/
204 uint32_t numbers_queue; /*2, 08-11*/
205 uint32_t sdram_size; /*3, 12-15*/
206 uint32_t ide_channels; /*4, 16-19*/
207 char vendor[40]; /*5, 20-59*/
208 char model[8]; /*15, 60-67*/
209 char firmware_ver[16]; /*17, 68-83*/
210 char device_map[16]; /*21, 84-99*/
211 uint32_t cfgVersion; /*25,100-103 Added for checking of new firmware capability*/
212 uint8_t cfgSerial[16]; /*26,104-119*/
213 uint32_t cfgPicStatus; /*30,120-123*/
214};
215/* signature of set and get firmware config */
216#define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060
217#define ARCMSR_SIGNATURE_SET_CONFIG 0x87974063
218/* message code of inbound message register */
219#define ARCMSR_INBOUND_MESG0_NOP 0x00000000
220#define ARCMSR_INBOUND_MESG0_GET_CONFIG 0x00000001
221#define ARCMSR_INBOUND_MESG0_SET_CONFIG 0x00000002
222#define ARCMSR_INBOUND_MESG0_ABORT_CMD 0x00000003
223#define ARCMSR_INBOUND_MESG0_STOP_BGRB 0x00000004
224#define ARCMSR_INBOUND_MESG0_FLUSH_CACHE 0x00000005
225#define ARCMSR_INBOUND_MESG0_START_BGRB 0x00000006
226#define ARCMSR_INBOUND_MESG0_CHK331PENDING 0x00000007
227#define ARCMSR_INBOUND_MESG0_SYNC_TIMER 0x00000008
228/* doorbell interrupt generator */
229#define ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK 0x00000001
230#define ARCMSR_INBOUND_DRIVER_DATA_READ_OK 0x00000002
231#define ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK 0x00000001
232#define ARCMSR_OUTBOUND_IOP331_DATA_READ_OK 0x00000002
233/* ccb areca cdb flag */
234#define ARCMSR_CCBPOST_FLAG_SGL_BSIZE 0x80000000
235#define ARCMSR_CCBPOST_FLAG_IAM_BIOS 0x40000000
236#define ARCMSR_CCBREPLY_FLAG_IAM_BIOS 0x40000000
237#define ARCMSR_CCBREPLY_FLAG_ERROR_MODE0 0x10000000
238#define ARCMSR_CCBREPLY_FLAG_ERROR_MODE1 0x00000001
239/* outbound firmware ok */
240#define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000
241/* ARC-1680 Bus Reset*/
242#define ARCMSR_ARC1680_BUS_RESET 0x00000003
243/* ARC-1880 Bus Reset*/
244#define ARCMSR_ARC1880_RESET_ADAPTER 0x00000024
245#define ARCMSR_ARC1880_DiagWrite_ENABLE 0x00000080
246
247/*
248************************************************************************
249** SPEC. for Areca Type B adapter
250************************************************************************
251*/
252/* ARECA HBB COMMAND for its FIRMWARE */
253/* window of "instruction flags" from driver to iop */
254#define ARCMSR_DRV2IOP_DOORBELL 0x00020400
255#define ARCMSR_DRV2IOP_DOORBELL_MASK 0x00020404
256/* window of "instruction flags" from iop to driver */
257#define ARCMSR_IOP2DRV_DOORBELL 0x00020408
258#define ARCMSR_IOP2DRV_DOORBELL_MASK 0x0002040C
259/* window of "instruction flags" from iop to driver */
260#define ARCMSR_IOP2DRV_DOORBELL_1203 0x00021870
261#define ARCMSR_IOP2DRV_DOORBELL_MASK_1203 0x00021874
262/* window of "instruction flags" from driver to iop */
263#define ARCMSR_DRV2IOP_DOORBELL_1203 0x00021878
264#define ARCMSR_DRV2IOP_DOORBELL_MASK_1203 0x0002187C
265/* ARECA FLAG LANGUAGE */
266/* ioctl transfer */
267#define ARCMSR_IOP2DRV_DATA_WRITE_OK 0x00000001
268/* ioctl transfer */
269#define ARCMSR_IOP2DRV_DATA_READ_OK 0x00000002
270#define ARCMSR_IOP2DRV_CDB_DONE 0x00000004
271#define ARCMSR_IOP2DRV_MESSAGE_CMD_DONE 0x00000008
272
273#define ARCMSR_DOORBELL_HANDLE_INT 0x0000000F
274#define ARCMSR_DOORBELL_INT_CLEAR_PATTERN 0xFF00FFF0
275#define ARCMSR_MESSAGE_INT_CLEAR_PATTERN 0xFF00FFF7
276/* (ARCMSR_INBOUND_MESG0_GET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
277#define ARCMSR_MESSAGE_GET_CONFIG 0x00010008
278/* (ARCMSR_INBOUND_MESG0_SET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
279#define ARCMSR_MESSAGE_SET_CONFIG 0x00020008
280/* (ARCMSR_INBOUND_MESG0_ABORT_CMD<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
281#define ARCMSR_MESSAGE_ABORT_CMD 0x00030008
282/* (ARCMSR_INBOUND_MESG0_STOP_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
283#define ARCMSR_MESSAGE_STOP_BGRB 0x00040008
284/* (ARCMSR_INBOUND_MESG0_FLUSH_CACHE<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
285#define ARCMSR_MESSAGE_FLUSH_CACHE 0x00050008
286/* (ARCMSR_INBOUND_MESG0_START_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
287#define ARCMSR_MESSAGE_START_BGRB 0x00060008
288#define ARCMSR_MESSAGE_SYNC_TIMER 0x00080008
289#define ARCMSR_MESSAGE_START_DRIVER_MODE 0x000E0008
290#define ARCMSR_MESSAGE_SET_POST_WINDOW 0x000F0008
291#define ARCMSR_MESSAGE_ACTIVE_EOI_MODE 0x00100008
292/* ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK */
293#define ARCMSR_MESSAGE_FIRMWARE_OK 0x80000000
294/* ioctl transfer */
295#define ARCMSR_DRV2IOP_DATA_WRITE_OK 0x00000001
296/* ioctl transfer */
297#define ARCMSR_DRV2IOP_DATA_READ_OK 0x00000002
298#define ARCMSR_DRV2IOP_CDB_POSTED 0x00000004
299#define ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED 0x00000008
300#define ARCMSR_DRV2IOP_END_OF_INTERRUPT 0x00000010
301
302/* data tunnel buffer between user space program and its firmware */
303/* user space data to iop 128bytes */
304#define ARCMSR_MESSAGE_WBUFFER 0x0000fe00
305/* iop data to user space 128bytes */
306#define ARCMSR_MESSAGE_RBUFFER 0x0000ff00
307/* iop message_rwbuffer for message command */
308#define ARCMSR_MESSAGE_RWBUFFER 0x0000fa00
309
310#define MEM_BASE0(x) (u32 __iomem *)((unsigned long)acb->mem_base0 + x)
311#define MEM_BASE1(x) (u32 __iomem *)((unsigned long)acb->mem_base1 + x)
312/*
313************************************************************************
314** SPEC. for Areca HBC adapter
315************************************************************************
316*/
317#define ARCMSR_HBC_ISR_THROTTLING_LEVEL 12
318#define ARCMSR_HBC_ISR_MAX_DONE_QUEUE 20
319/* Host Interrupt Mask */
320#define ARCMSR_HBCMU_UTILITY_A_ISR_MASK 0x00000001 /* When clear, the Utility_A interrupt routes to the host.*/
321#define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK 0x00000004 /* When clear, the General Outbound Doorbell interrupt routes to the host.*/
322#define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK 0x00000008 /* When clear, the Outbound Post List FIFO Not Empty interrupt routes to the host.*/
323#define ARCMSR_HBCMU_ALL_INTMASKENABLE 0x0000000D /* disable all ISR */
324/* Host Interrupt Status */
325#define ARCMSR_HBCMU_UTILITY_A_ISR 0x00000001
326 /*
327 ** Set when the Utility_A Interrupt bit is set in the Outbound Doorbell Register.
328 ** It clears by writing a 1 to the Utility_A bit in the Outbound Doorbell Clear Register or through automatic clearing (if enabled).
329 */
330#define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR 0x00000004
331 /*
332 ** Set if Outbound Doorbell register bits 30:1 have a non-zero
333 ** value. This bit clears only when Outbound Doorbell bits
334 ** 30:1 are ALL clear. Only a write to the Outbound Doorbell
335 ** Clear register clears bits in the Outbound Doorbell register.
336 */
337#define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR 0x00000008
338 /*
339 ** Set whenever the Outbound Post List Producer/Consumer
340 ** Register (FIFO) is not empty. It clears when the Outbound
341 ** Post List FIFO is empty.
342 */
343#define ARCMSR_HBCMU_SAS_ALL_INT 0x00000010
344 /*
345 ** This bit indicates a SAS interrupt from a source external to
346 ** the PCIe core. This bit is not maskable.
347 */
348 /* DoorBell*/
349#define ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK 0x00000002
350#define ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK 0x00000004
351 /*inbound message 0 ready*/
352#define ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE 0x00000008
353 /*more than 12 request completed in a time*/
354#define ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING 0x00000010
355#define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK 0x00000002
356 /*outbound DATA WRITE isr door bell clear*/
357#define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_DOORBELL_CLEAR 0x00000002
358#define ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK 0x00000004
359 /*outbound DATA READ isr door bell clear*/
360#define ARCMSR_HBCMU_IOP2DRV_DATA_READ_DOORBELL_CLEAR 0x00000004
361 /*outbound message 0 ready*/
362#define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008
363 /*outbound message cmd isr door bell clear*/
364#define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR 0x00000008
365 /*ARCMSR_HBAMU_MESSAGE_FIRMWARE_OK*/
366#define ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK 0x80000000
367/*
368*******************************************************************************
369** SPEC. for Areca Type D adapter
370*******************************************************************************
371*/
372#define ARCMSR_ARC1214_CHIP_ID 0x00004
373#define ARCMSR_ARC1214_CPU_MEMORY_CONFIGURATION 0x00008
374#define ARCMSR_ARC1214_I2_HOST_INTERRUPT_MASK 0x00034
375#define ARCMSR_ARC1214_SAMPLE_RESET 0x00100
376#define ARCMSR_ARC1214_RESET_REQUEST 0x00108
377#define ARCMSR_ARC1214_MAIN_INTERRUPT_STATUS 0x00200
378#define ARCMSR_ARC1214_PCIE_F0_INTERRUPT_ENABLE 0x0020C
379#define ARCMSR_ARC1214_INBOUND_MESSAGE0 0x00400
380#define ARCMSR_ARC1214_INBOUND_MESSAGE1 0x00404
381#define ARCMSR_ARC1214_OUTBOUND_MESSAGE0 0x00420
382#define ARCMSR_ARC1214_OUTBOUND_MESSAGE1 0x00424
383#define ARCMSR_ARC1214_INBOUND_DOORBELL 0x00460
384#define ARCMSR_ARC1214_OUTBOUND_DOORBELL 0x00480
385#define ARCMSR_ARC1214_OUTBOUND_DOORBELL_ENABLE 0x00484
386#define ARCMSR_ARC1214_INBOUND_LIST_BASE_LOW 0x01000
387#define ARCMSR_ARC1214_INBOUND_LIST_BASE_HIGH 0x01004
388#define ARCMSR_ARC1214_INBOUND_LIST_WRITE_POINTER 0x01018
389#define ARCMSR_ARC1214_OUTBOUND_LIST_BASE_LOW 0x01060
390#define ARCMSR_ARC1214_OUTBOUND_LIST_BASE_HIGH 0x01064
391#define ARCMSR_ARC1214_OUTBOUND_LIST_COPY_POINTER 0x0106C
392#define ARCMSR_ARC1214_OUTBOUND_LIST_READ_POINTER 0x01070
393#define ARCMSR_ARC1214_OUTBOUND_INTERRUPT_CAUSE 0x01088
394#define ARCMSR_ARC1214_OUTBOUND_INTERRUPT_ENABLE 0x0108C
395#define ARCMSR_ARC1214_MESSAGE_WBUFFER 0x02000
396#define ARCMSR_ARC1214_MESSAGE_RBUFFER 0x02100
397#define ARCMSR_ARC1214_MESSAGE_RWBUFFER 0x02200
398/* Host Interrupt Mask */
399#define ARCMSR_ARC1214_ALL_INT_ENABLE 0x00001010
400#define ARCMSR_ARC1214_ALL_INT_DISABLE 0x00000000
401/* Host Interrupt Status */
402#define ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR 0x00001000
403#define ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR 0x00000010
404/* DoorBell*/
405#define ARCMSR_ARC1214_DRV2IOP_DATA_IN_READY 0x00000001
406#define ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ 0x00000002
407/*inbound message 0 ready*/
408#define ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK 0x00000001
409/*outbound DATA WRITE isr door bell clear*/
410#define ARCMSR_ARC1214_IOP2DRV_DATA_READ_OK 0x00000002
411/*outbound message 0 ready*/
412#define ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE 0x02000000
413/*outbound message cmd isr door bell clear*/
414/*ARCMSR_HBAMU_MESSAGE_FIRMWARE_OK*/
415#define ARCMSR_ARC1214_MESSAGE_FIRMWARE_OK 0x80000000
416#define ARCMSR_ARC1214_OUTBOUND_LIST_INTERRUPT_CLEAR 0x00000001
417/*
418*******************************************************************************
419** SPEC. for Areca Type E adapter
420*******************************************************************************
421*/
422#define ARCMSR_SIGNATURE_1884 0x188417D3
423
424#define ARCMSR_HBEMU_DRV2IOP_DATA_WRITE_OK 0x00000002
425#define ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK 0x00000004
426#define ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE 0x00000008
427
428#define ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK 0x00000002
429#define ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK 0x00000004
430#define ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008
431
432#define ARCMSR_HBEMU_MESSAGE_FIRMWARE_OK 0x80000000
433
434#define ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR 0x00000001
435#define ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR 0x00000008
436#define ARCMSR_HBEMU_ALL_INTMASKENABLE 0x00000009
437
438/* ARC-1884 doorbell sync */
439#define ARCMSR_HBEMU_DOORBELL_SYNC 0x100
440#define ARCMSR_ARC188X_RESET_ADAPTER 0x00000004
441#define ARCMSR_ARC1884_DiagWrite_ENABLE 0x00000080
442
443/*
444*******************************************************************************
445** SPEC. for Areca Type F adapter
446*******************************************************************************
447*/
448#define ARCMSR_SIGNATURE_1886 0x188617D3
449// Doorbell and interrupt definition are same as Type E adapter
450/* ARC-1886 doorbell sync */
451#define ARCMSR_HBFMU_DOORBELL_SYNC 0x100
452//set host rw buffer physical address at inbound message 0, 1 (low,high)
453#define ARCMSR_HBFMU_DOORBELL_SYNC1 0x300
454#define ARCMSR_HBFMU_MESSAGE_FIRMWARE_OK 0x80000000
455#define ARCMSR_HBFMU_MESSAGE_NO_VOLUME_CHANGE 0x20000000
456
457/*
458*******************************************************************************
459** ARECA SCSI COMMAND DESCRIPTOR BLOCK size 0x1F8 (504)
460*******************************************************************************
461*/
462struct ARCMSR_CDB
463{
464 uint8_t Bus;
465 uint8_t TargetID;
466 uint8_t LUN;
467 uint8_t Function;
468 uint8_t CdbLength;
469 uint8_t sgcount;
470 uint8_t Flags;
471#define ARCMSR_CDB_FLAG_SGL_BSIZE 0x01
472#define ARCMSR_CDB_FLAG_BIOS 0x02
473#define ARCMSR_CDB_FLAG_WRITE 0x04
474#define ARCMSR_CDB_FLAG_SIMPLEQ 0x00
475#define ARCMSR_CDB_FLAG_HEADQ 0x08
476#define ARCMSR_CDB_FLAG_ORDEREDQ 0x10
477
478 uint8_t msgPages;
479 uint32_t msgContext;
480 uint32_t DataLength;
481 uint8_t Cdb[16];
482 uint8_t DeviceStatus;
483#define ARCMSR_DEV_CHECK_CONDITION 0x02
484#define ARCMSR_DEV_SELECT_TIMEOUT 0xF0
485#define ARCMSR_DEV_ABORTED 0xF1
486#define ARCMSR_DEV_INIT_FAIL 0xF2
487
488 uint8_t SenseData[15];
489 union
490 {
491 struct SG32ENTRY sg32entry[1];
492 struct SG64ENTRY sg64entry[1];
493 } u;
494};
495/*
496*******************************************************************************
497** Messaging Unit (MU) of the Intel R 80331 I/O processor(Type A) and Type B processor
498*******************************************************************************
499*/
500struct MessageUnit_A
501{
502 uint32_t resrved0[4]; /*0000 000F*/
503 uint32_t inbound_msgaddr0; /*0010 0013*/
504 uint32_t inbound_msgaddr1; /*0014 0017*/
505 uint32_t outbound_msgaddr0; /*0018 001B*/
506 uint32_t outbound_msgaddr1; /*001C 001F*/
507 uint32_t inbound_doorbell; /*0020 0023*/
508 uint32_t inbound_intstatus; /*0024 0027*/
509 uint32_t inbound_intmask; /*0028 002B*/
510 uint32_t outbound_doorbell; /*002C 002F*/
511 uint32_t outbound_intstatus; /*0030 0033*/
512 uint32_t outbound_intmask; /*0034 0037*/
513 uint32_t reserved1[2]; /*0038 003F*/
514 uint32_t inbound_queueport; /*0040 0043*/
515 uint32_t outbound_queueport; /*0044 0047*/
516 uint32_t reserved2[2]; /*0048 004F*/
517 uint32_t reserved3[492]; /*0050 07FF 492*/
518 uint32_t reserved4[128]; /*0800 09FF 128*/
519 uint32_t message_rwbuffer[256]; /*0a00 0DFF 256*/
520 uint32_t message_wbuffer[32]; /*0E00 0E7F 32*/
521 uint32_t reserved5[32]; /*0E80 0EFF 32*/
522 uint32_t message_rbuffer[32]; /*0F00 0F7F 32*/
523 uint32_t reserved6[32]; /*0F80 0FFF 32*/
524};
525
526struct MessageUnit_B
527{
528 uint32_t post_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE];
529 uint32_t done_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE];
530 uint32_t postq_index;
531 uint32_t doneq_index;
532 uint32_t __iomem *drv2iop_doorbell;
533 uint32_t __iomem *drv2iop_doorbell_mask;
534 uint32_t __iomem *iop2drv_doorbell;
535 uint32_t __iomem *iop2drv_doorbell_mask;
536 uint32_t __iomem *message_rwbuffer;
537 uint32_t __iomem *message_wbuffer;
538 uint32_t __iomem *message_rbuffer;
539};
540/*
541*********************************************************************
542** LSI
543*********************************************************************
544*/
545struct MessageUnit_C{
546 uint32_t message_unit_status; /*0000 0003*/
547 uint32_t slave_error_attribute; /*0004 0007*/
548 uint32_t slave_error_address; /*0008 000B*/
549 uint32_t posted_outbound_doorbell; /*000C 000F*/
550 uint32_t master_error_attribute; /*0010 0013*/
551 uint32_t master_error_address_low; /*0014 0017*/
552 uint32_t master_error_address_high; /*0018 001B*/
553 uint32_t hcb_size; /*001C 001F*/
554 uint32_t inbound_doorbell; /*0020 0023*/
555 uint32_t diagnostic_rw_data; /*0024 0027*/
556 uint32_t diagnostic_rw_address_low; /*0028 002B*/
557 uint32_t diagnostic_rw_address_high; /*002C 002F*/
558 uint32_t host_int_status; /*0030 0033*/
559 uint32_t host_int_mask; /*0034 0037*/
560 uint32_t dcr_data; /*0038 003B*/
561 uint32_t dcr_address; /*003C 003F*/
562 uint32_t inbound_queueport; /*0040 0043*/
563 uint32_t outbound_queueport; /*0044 0047*/
564 uint32_t hcb_pci_address_low; /*0048 004B*/
565 uint32_t hcb_pci_address_high; /*004C 004F*/
566 uint32_t iop_int_status; /*0050 0053*/
567 uint32_t iop_int_mask; /*0054 0057*/
568 uint32_t iop_inbound_queue_port; /*0058 005B*/
569 uint32_t iop_outbound_queue_port; /*005C 005F*/
570 uint32_t inbound_free_list_index; /*0060 0063*/
571 uint32_t inbound_post_list_index; /*0064 0067*/
572 uint32_t outbound_free_list_index; /*0068 006B*/
573 uint32_t outbound_post_list_index; /*006C 006F*/
574 uint32_t inbound_doorbell_clear; /*0070 0073*/
575 uint32_t i2o_message_unit_control; /*0074 0077*/
576 uint32_t last_used_message_source_address_low; /*0078 007B*/
577 uint32_t last_used_message_source_address_high; /*007C 007F*/
578 uint32_t pull_mode_data_byte_count[4]; /*0080 008F*/
579 uint32_t message_dest_address_index; /*0090 0093*/
580 uint32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/
581 uint32_t utility_A_int_counter_timer; /*0098 009B*/
582 uint32_t outbound_doorbell; /*009C 009F*/
583 uint32_t outbound_doorbell_clear; /*00A0 00A3*/
584 uint32_t message_source_address_index; /*00A4 00A7*/
585 uint32_t message_done_queue_index; /*00A8 00AB*/
586 uint32_t reserved0; /*00AC 00AF*/
587 uint32_t inbound_msgaddr0; /*00B0 00B3*/
588 uint32_t inbound_msgaddr1; /*00B4 00B7*/
589 uint32_t outbound_msgaddr0; /*00B8 00BB*/
590 uint32_t outbound_msgaddr1; /*00BC 00BF*/
591 uint32_t inbound_queueport_low; /*00C0 00C3*/
592 uint32_t inbound_queueport_high; /*00C4 00C7*/
593 uint32_t outbound_queueport_low; /*00C8 00CB*/
594 uint32_t outbound_queueport_high; /*00CC 00CF*/
595 uint32_t iop_inbound_queue_port_low; /*00D0 00D3*/
596 uint32_t iop_inbound_queue_port_high; /*00D4 00D7*/
597 uint32_t iop_outbound_queue_port_low; /*00D8 00DB*/
598 uint32_t iop_outbound_queue_port_high; /*00DC 00DF*/
599 uint32_t message_dest_queue_port_low; /*00E0 00E3*/
600 uint32_t message_dest_queue_port_high; /*00E4 00E7*/
601 uint32_t last_used_message_dest_address_low; /*00E8 00EB*/
602 uint32_t last_used_message_dest_address_high; /*00EC 00EF*/
603 uint32_t message_done_queue_base_address_low; /*00F0 00F3*/
604 uint32_t message_done_queue_base_address_high; /*00F4 00F7*/
605 uint32_t host_diagnostic; /*00F8 00FB*/
606 uint32_t write_sequence; /*00FC 00FF*/
607 uint32_t reserved1[34]; /*0100 0187*/
608 uint32_t reserved2[1950]; /*0188 1FFF*/
609 uint32_t message_wbuffer[32]; /*2000 207F*/
610 uint32_t reserved3[32]; /*2080 20FF*/
611 uint32_t message_rbuffer[32]; /*2100 217F*/
612 uint32_t reserved4[32]; /*2180 21FF*/
613 uint32_t msgcode_rwbuffer[256]; /*2200 23FF*/
614};
615/*
616*********************************************************************
617** Messaging Unit (MU) of Type D processor
618*********************************************************************
619*/
620struct InBound_SRB {
621 uint32_t addressLow; /* pointer to SRB block */
622 uint32_t addressHigh;
623 uint32_t length; /* in DWORDs */
624 uint32_t reserved0;
625};
626
627struct OutBound_SRB {
628 uint32_t addressLow; /* pointer to SRB block */
629 uint32_t addressHigh;
630};
631
632struct MessageUnit_D {
633 struct InBound_SRB post_qbuffer[ARCMSR_MAX_ARC1214_POSTQUEUE];
634 volatile struct OutBound_SRB
635 done_qbuffer[ARCMSR_MAX_ARC1214_DONEQUEUE];
636 u16 postq_index;
637 volatile u16 doneq_index;
638 u32 __iomem *chip_id; /* 0x00004 */
639 u32 __iomem *cpu_mem_config; /* 0x00008 */
640 u32 __iomem *i2o_host_interrupt_mask; /* 0x00034 */
641 u32 __iomem *sample_at_reset; /* 0x00100 */
642 u32 __iomem *reset_request; /* 0x00108 */
643 u32 __iomem *host_int_status; /* 0x00200 */
644 u32 __iomem *pcief0_int_enable; /* 0x0020C */
645 u32 __iomem *inbound_msgaddr0; /* 0x00400 */
646 u32 __iomem *inbound_msgaddr1; /* 0x00404 */
647 u32 __iomem *outbound_msgaddr0; /* 0x00420 */
648 u32 __iomem *outbound_msgaddr1; /* 0x00424 */
649 u32 __iomem *inbound_doorbell; /* 0x00460 */
650 u32 __iomem *outbound_doorbell; /* 0x00480 */
651 u32 __iomem *outbound_doorbell_enable; /* 0x00484 */
652 u32 __iomem *inboundlist_base_low; /* 0x01000 */
653 u32 __iomem *inboundlist_base_high; /* 0x01004 */
654 u32 __iomem *inboundlist_write_pointer; /* 0x01018 */
655 u32 __iomem *outboundlist_base_low; /* 0x01060 */
656 u32 __iomem *outboundlist_base_high; /* 0x01064 */
657 u32 __iomem *outboundlist_copy_pointer; /* 0x0106C */
658 u32 __iomem *outboundlist_read_pointer; /* 0x01070 0x01072 */
659 u32 __iomem *outboundlist_interrupt_cause; /* 0x1088 */
660 u32 __iomem *outboundlist_interrupt_enable; /* 0x108C */
661 u32 __iomem *message_wbuffer; /* 0x2000 */
662 u32 __iomem *message_rbuffer; /* 0x2100 */
663 u32 __iomem *msgcode_rwbuffer; /* 0x2200 */
664};
665/*
666*********************************************************************
667** Messaging Unit (MU) of Type E processor(LSI)
668*********************************************************************
669*/
670struct MessageUnit_E{
671 uint32_t iobound_doorbell; /*0000 0003*/
672 uint32_t write_sequence_3xxx; /*0004 0007*/
673 uint32_t host_diagnostic_3xxx; /*0008 000B*/
674 uint32_t posted_outbound_doorbell; /*000C 000F*/
675 uint32_t master_error_attribute; /*0010 0013*/
676 uint32_t master_error_address_low; /*0014 0017*/
677 uint32_t master_error_address_high; /*0018 001B*/
678 uint32_t hcb_size; /*001C 001F*/
679 uint32_t inbound_doorbell; /*0020 0023*/
680 uint32_t diagnostic_rw_data; /*0024 0027*/
681 uint32_t diagnostic_rw_address_low; /*0028 002B*/
682 uint32_t diagnostic_rw_address_high; /*002C 002F*/
683 uint32_t host_int_status; /*0030 0033*/
684 uint32_t host_int_mask; /*0034 0037*/
685 uint32_t dcr_data; /*0038 003B*/
686 uint32_t dcr_address; /*003C 003F*/
687 uint32_t inbound_queueport; /*0040 0043*/
688 uint32_t outbound_queueport; /*0044 0047*/
689 uint32_t hcb_pci_address_low; /*0048 004B*/
690 uint32_t hcb_pci_address_high; /*004C 004F*/
691 uint32_t iop_int_status; /*0050 0053*/
692 uint32_t iop_int_mask; /*0054 0057*/
693 uint32_t iop_inbound_queue_port; /*0058 005B*/
694 uint32_t iop_outbound_queue_port; /*005C 005F*/
695 uint32_t inbound_free_list_index; /*0060 0063*/
696 uint32_t inbound_post_list_index; /*0064 0067*/
697 uint32_t reply_post_producer_index; /*0068 006B*/
698 uint32_t reply_post_consumer_index; /*006C 006F*/
699 uint32_t inbound_doorbell_clear; /*0070 0073*/
700 uint32_t i2o_message_unit_control; /*0074 0077*/
701 uint32_t last_used_message_source_address_low; /*0078 007B*/
702 uint32_t last_used_message_source_address_high; /*007C 007F*/
703 uint32_t pull_mode_data_byte_count[4]; /*0080 008F*/
704 uint32_t message_dest_address_index; /*0090 0093*/
705 uint32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/
706 uint32_t utility_A_int_counter_timer; /*0098 009B*/
707 uint32_t outbound_doorbell; /*009C 009F*/
708 uint32_t outbound_doorbell_clear; /*00A0 00A3*/
709 uint32_t message_source_address_index; /*00A4 00A7*/
710 uint32_t message_done_queue_index; /*00A8 00AB*/
711 uint32_t reserved0; /*00AC 00AF*/
712 uint32_t inbound_msgaddr0; /*00B0 00B3*/
713 uint32_t inbound_msgaddr1; /*00B4 00B7*/
714 uint32_t outbound_msgaddr0; /*00B8 00BB*/
715 uint32_t outbound_msgaddr1; /*00BC 00BF*/
716 uint32_t inbound_queueport_low; /*00C0 00C3*/
717 uint32_t inbound_queueport_high; /*00C4 00C7*/
718 uint32_t outbound_queueport_low; /*00C8 00CB*/
719 uint32_t outbound_queueport_high; /*00CC 00CF*/
720 uint32_t iop_inbound_queue_port_low; /*00D0 00D3*/
721 uint32_t iop_inbound_queue_port_high; /*00D4 00D7*/
722 uint32_t iop_outbound_queue_port_low; /*00D8 00DB*/
723 uint32_t iop_outbound_queue_port_high; /*00DC 00DF*/
724 uint32_t message_dest_queue_port_low; /*00E0 00E3*/
725 uint32_t message_dest_queue_port_high; /*00E4 00E7*/
726 uint32_t last_used_message_dest_address_low; /*00E8 00EB*/
727 uint32_t last_used_message_dest_address_high; /*00EC 00EF*/
728 uint32_t message_done_queue_base_address_low; /*00F0 00F3*/
729 uint32_t message_done_queue_base_address_high; /*00F4 00F7*/
730 uint32_t host_diagnostic; /*00F8 00FB*/
731 uint32_t write_sequence; /*00FC 00FF*/
732 uint32_t reserved1[34]; /*0100 0187*/
733 uint32_t reserved2[1950]; /*0188 1FFF*/
734 uint32_t message_wbuffer[32]; /*2000 207F*/
735 uint32_t reserved3[32]; /*2080 20FF*/
736 uint32_t message_rbuffer[32]; /*2100 217F*/
737 uint32_t reserved4[32]; /*2180 21FF*/
738 uint32_t msgcode_rwbuffer[256]; /*2200 23FF*/
739};
740
741/*
742*********************************************************************
743** Messaging Unit (MU) of Type F processor(LSI)
744*********************************************************************
745*/
746struct MessageUnit_F {
747 uint32_t iobound_doorbell; /*0000 0003*/
748 uint32_t write_sequence_3xxx; /*0004 0007*/
749 uint32_t host_diagnostic_3xxx; /*0008 000B*/
750 uint32_t posted_outbound_doorbell; /*000C 000F*/
751 uint32_t master_error_attribute; /*0010 0013*/
752 uint32_t master_error_address_low; /*0014 0017*/
753 uint32_t master_error_address_high; /*0018 001B*/
754 uint32_t hcb_size; /*001C 001F*/
755 uint32_t inbound_doorbell; /*0020 0023*/
756 uint32_t diagnostic_rw_data; /*0024 0027*/
757 uint32_t diagnostic_rw_address_low; /*0028 002B*/
758 uint32_t diagnostic_rw_address_high; /*002C 002F*/
759 uint32_t host_int_status; /*0030 0033*/
760 uint32_t host_int_mask; /*0034 0037*/
761 uint32_t dcr_data; /*0038 003B*/
762 uint32_t dcr_address; /*003C 003F*/
763 uint32_t inbound_queueport; /*0040 0043*/
764 uint32_t outbound_queueport; /*0044 0047*/
765 uint32_t hcb_pci_address_low; /*0048 004B*/
766 uint32_t hcb_pci_address_high; /*004C 004F*/
767 uint32_t iop_int_status; /*0050 0053*/
768 uint32_t iop_int_mask; /*0054 0057*/
769 uint32_t iop_inbound_queue_port; /*0058 005B*/
770 uint32_t iop_outbound_queue_port; /*005C 005F*/
771 uint32_t inbound_free_list_index; /*0060 0063*/
772 uint32_t inbound_post_list_index; /*0064 0067*/
773 uint32_t reply_post_producer_index; /*0068 006B*/
774 uint32_t reply_post_consumer_index; /*006C 006F*/
775 uint32_t inbound_doorbell_clear; /*0070 0073*/
776 uint32_t i2o_message_unit_control; /*0074 0077*/
777 uint32_t last_used_message_source_address_low; /*0078 007B*/
778 uint32_t last_used_message_source_address_high; /*007C 007F*/
779 uint32_t pull_mode_data_byte_count[4]; /*0080 008F*/
780 uint32_t message_dest_address_index; /*0090 0093*/
781 uint32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/
782 uint32_t utility_A_int_counter_timer; /*0098 009B*/
783 uint32_t outbound_doorbell; /*009C 009F*/
784 uint32_t outbound_doorbell_clear; /*00A0 00A3*/
785 uint32_t message_source_address_index; /*00A4 00A7*/
786 uint32_t message_done_queue_index; /*00A8 00AB*/
787 uint32_t reserved0; /*00AC 00AF*/
788 uint32_t inbound_msgaddr0; /*00B0 00B3*/
789 uint32_t inbound_msgaddr1; /*00B4 00B7*/
790 uint32_t outbound_msgaddr0; /*00B8 00BB*/
791 uint32_t outbound_msgaddr1; /*00BC 00BF*/
792 uint32_t inbound_queueport_low; /*00C0 00C3*/
793 uint32_t inbound_queueport_high; /*00C4 00C7*/
794 uint32_t outbound_queueport_low; /*00C8 00CB*/
795 uint32_t outbound_queueport_high; /*00CC 00CF*/
796 uint32_t iop_inbound_queue_port_low; /*00D0 00D3*/
797 uint32_t iop_inbound_queue_port_high; /*00D4 00D7*/
798 uint32_t iop_outbound_queue_port_low; /*00D8 00DB*/
799 uint32_t iop_outbound_queue_port_high; /*00DC 00DF*/
800 uint32_t message_dest_queue_port_low; /*00E0 00E3*/
801 uint32_t message_dest_queue_port_high; /*00E4 00E7*/
802 uint32_t last_used_message_dest_address_low; /*00E8 00EB*/
803 uint32_t last_used_message_dest_address_high; /*00EC 00EF*/
804 uint32_t message_done_queue_base_address_low; /*00F0 00F3*/
805 uint32_t message_done_queue_base_address_high; /*00F4 00F7*/
806 uint32_t host_diagnostic; /*00F8 00FB*/
807 uint32_t write_sequence; /*00FC 00FF*/
808 uint32_t reserved1[46]; /*0100 01B7*/
809 uint32_t reply_post_producer_index1; /*01B8 01BB*/
810 uint32_t reply_post_consumer_index1; /*01BC 01BF*/
811};
812
813#define MESG_RW_BUFFER_SIZE (256 * 3)
814
815typedef struct deliver_completeQ {
816 uint16_t cmdFlag;
817 uint16_t cmdSMID;
818 uint16_t cmdLMID; // reserved (0)
819 uint16_t cmdFlag2; // reserved (0)
820} DeliverQ, CompletionQ, *pDeliver_Q, *pCompletion_Q;
821/*
822*******************************************************************************
823** Adapter Control Block
824*******************************************************************************
825*/
826struct AdapterControlBlock
827{
828 uint32_t adapter_type; /* adapter A,B..... */
829#define ACB_ADAPTER_TYPE_A 0x00000000 /* hba I IOP */
830#define ACB_ADAPTER_TYPE_B 0x00000001 /* hbb M IOP */
831#define ACB_ADAPTER_TYPE_C 0x00000002 /* hbc L IOP */
832#define ACB_ADAPTER_TYPE_D 0x00000003 /* hbd M IOP */
833#define ACB_ADAPTER_TYPE_E 0x00000004 /* hba L IOP */
834#define ACB_ADAPTER_TYPE_F 0x00000005 /* hba L IOP */
835 u32 ioqueue_size;
836 struct pci_dev * pdev;
837 struct Scsi_Host * host;
838 unsigned long vir2phy_offset;
839 /* Offset is used in making arc cdb physical to virtual calculations */
840 uint32_t outbound_int_enable;
841 uint32_t cdb_phyaddr_hi32;
842 uint32_t reg_mu_acc_handle0;
843 uint64_t cdb_phyadd_hipart;
844 spinlock_t eh_lock;
845 spinlock_t ccblist_lock;
846 spinlock_t postq_lock;
847 spinlock_t doneq_lock;
848 spinlock_t rqbuffer_lock;
849 spinlock_t wqbuffer_lock;
850 union {
851 struct MessageUnit_A __iomem *pmuA;
852 struct MessageUnit_B *pmuB;
853 struct MessageUnit_C __iomem *pmuC;
854 struct MessageUnit_D *pmuD;
855 struct MessageUnit_E __iomem *pmuE;
856 struct MessageUnit_F __iomem *pmuF;
857 };
858 /* message unit ATU inbound base address0 */
859 void __iomem *mem_base0;
860 void __iomem *mem_base1;
861 //0x000 - COMPORT_IN (Host sent to ROC)
862 uint32_t *message_wbuffer;
863 //0x100 - COMPORT_OUT (ROC sent to Host)
864 uint32_t *message_rbuffer;
865 uint32_t *msgcode_rwbuffer; //0x200 - BIOS_AREA
866 uint32_t acb_flags;
867 u16 dev_id;
868 uint8_t adapter_index;
869#define ACB_F_SCSISTOPADAPTER 0x0001
870#define ACB_F_MSG_STOP_BGRB 0x0002
871/* stop RAID background rebuild */
872#define ACB_F_MSG_START_BGRB 0x0004
873/* stop RAID background rebuild */
874#define ACB_F_IOPDATA_OVERFLOW 0x0008
875/* iop message data rqbuffer overflow */
876#define ACB_F_MESSAGE_WQBUFFER_CLEARED 0x0010
877/* message clear wqbuffer */
878#define ACB_F_MESSAGE_RQBUFFER_CLEARED 0x0020
879/* message clear rqbuffer */
880#define ACB_F_MESSAGE_WQBUFFER_READED 0x0040
881#define ACB_F_BUS_RESET 0x0080
882
883#define ACB_F_IOP_INITED 0x0100
884/* iop init */
885#define ACB_F_ABORT 0x0200
886#define ACB_F_FIRMWARE_TRAP 0x0400
887#define ACB_F_ADAPTER_REMOVED 0x0800
888#define ACB_F_MSG_GET_CONFIG 0x1000
889 struct CommandControlBlock * pccb_pool[ARCMSR_MAX_FREECCB_NUM];
890 /* used for memory free */
891 struct list_head ccb_free_list;
892 /* head of free ccb list */
893
894 atomic_t ccboutstandingcount;
895 /*The present outstanding command number that in the IOP that
896 waiting for being handled by FW*/
897
898 void * dma_coherent;
899 /* dma_coherent used for memory free */
900 dma_addr_t dma_coherent_handle;
901 /* dma_coherent_handle used for memory free */
902 dma_addr_t dma_coherent_handle2;
903 void *dma_coherent2;
904 unsigned int uncache_size;
905 uint8_t rqbuffer[ARCMSR_MAX_QBUFFER];
906 /* data collection buffer for read from 80331 */
907 int32_t rqbuf_getIndex;
908 /* first of read buffer */
909 int32_t rqbuf_putIndex;
910 /* last of read buffer */
911 uint8_t wqbuffer[ARCMSR_MAX_QBUFFER];
912 /* data collection buffer for write to 80331 */
913 int32_t wqbuf_getIndex;
914 /* first of write buffer */
915 int32_t wqbuf_putIndex;
916 /* last of write buffer */
917 uint8_t devstate[ARCMSR_MAX_TARGETID][ARCMSR_MAX_TARGETLUN];
918 /* id0 ..... id15, lun0...lun7 */
919#define ARECA_RAID_GONE 0x55
920#define ARECA_RAID_GOOD 0xaa
921 uint32_t num_resets;
922 uint32_t num_aborts;
923 uint32_t signature;
924 uint32_t firm_request_len;
925 uint32_t firm_numbers_queue;
926 uint32_t firm_sdram_size;
927 uint32_t firm_hd_channels;
928 uint32_t firm_cfg_version;
929 char firm_model[12];
930 char firm_version[20];
931 char device_map[20]; /*21,84-99*/
932 struct work_struct arcmsr_do_message_isr_bh;
933 struct timer_list eternal_timer;
934 unsigned short fw_flag;
935#define FW_NORMAL 0x0000
936#define FW_BOG 0x0001
937#define FW_DEADLOCK 0x0010
938 uint32_t maxOutstanding;
939 int vector_count;
940 uint32_t maxFreeCCB;
941 struct timer_list refresh_timer;
942 uint32_t doneq_index;
943 uint32_t ccbsize;
944 uint32_t in_doorbell;
945 uint32_t out_doorbell;
946 uint32_t completionQ_entry;
947 pCompletion_Q pCompletionQ;
948 uint32_t completeQ_size;
949};/* HW_DEVICE_EXTENSION */
950/*
951*******************************************************************************
952** Command Control Block
953** this CCB length must be 32 bytes boundary
954*******************************************************************************
955*/
956struct CommandControlBlock{
957 /*x32:sizeof struct_CCB=(64+60)byte, x64:sizeof struct_CCB=(64+60)byte*/
958 struct list_head list; /*x32: 8byte, x64: 16byte*/
959 struct scsi_cmnd *pcmd; /*8 bytes pointer of linux scsi command */
960 struct AdapterControlBlock *acb; /*x32: 4byte, x64: 8byte*/
961 unsigned long cdb_phyaddr; /*x32: 4byte, x64: 8byte*/
962 uint32_t arc_cdb_size; /*x32:4byte,x64:4byte*/
963 uint16_t ccb_flags; /*x32: 2byte, x64: 2byte*/
964#define CCB_FLAG_READ 0x0000
965#define CCB_FLAG_WRITE 0x0001
966#define CCB_FLAG_ERROR 0x0002
967#define CCB_FLAG_FLUSHCACHE 0x0004
968#define CCB_FLAG_MASTER_ABORTED 0x0008
969 uint16_t startdone; /*x32:2byte,x32:2byte*/
970#define ARCMSR_CCB_DONE 0x0000
971#define ARCMSR_CCB_START 0x55AA
972#define ARCMSR_CCB_ABORTED 0xAA55
973#define ARCMSR_CCB_ILLEGAL 0xFFFF
974 uint32_t smid;
975#if BITS_PER_LONG == 64
976 /* ======================512+64 bytes======================== */
977 uint32_t reserved[3]; /*12 byte*/
978#else
979 /* ======================512+32 bytes======================== */
980 uint32_t reserved[8]; /*32 byte*/
981#endif
982 /* ======================================================= */
983 struct ARCMSR_CDB arcmsr_cdb;
984};
985/*
986*******************************************************************************
987** ARECA SCSI sense data
988*******************************************************************************
989*/
990struct SENSE_DATA
991{
992 uint8_t ErrorCode:7;
993#define SCSI_SENSE_CURRENT_ERRORS 0x70
994#define SCSI_SENSE_DEFERRED_ERRORS 0x71
995 uint8_t Valid:1;
996 uint8_t SegmentNumber;
997 uint8_t SenseKey:4;
998 uint8_t Reserved:1;
999 uint8_t IncorrectLength:1;
1000 uint8_t EndOfMedia:1;
1001 uint8_t FileMark:1;
1002 uint8_t Information[4];
1003 uint8_t AdditionalSenseLength;
1004 uint8_t CommandSpecificInformation[4];
1005 uint8_t AdditionalSenseCode;
1006 uint8_t AdditionalSenseCodeQualifier;
1007 uint8_t FieldReplaceableUnitCode;
1008 uint8_t SenseKeySpecific[3];
1009};
1010/*
1011*******************************************************************************
1012** Outbound Interrupt Status Register - OISR
1013*******************************************************************************
1014*/
1015#define ARCMSR_MU_OUTBOUND_INTERRUPT_STATUS_REG 0x30
1016#define ARCMSR_MU_OUTBOUND_PCI_INT 0x10
1017#define ARCMSR_MU_OUTBOUND_POSTQUEUE_INT 0x08
1018#define ARCMSR_MU_OUTBOUND_DOORBELL_INT 0x04
1019#define ARCMSR_MU_OUTBOUND_MESSAGE1_INT 0x02
1020#define ARCMSR_MU_OUTBOUND_MESSAGE0_INT 0x01
1021#define ARCMSR_MU_OUTBOUND_HANDLE_INT \
1022 (ARCMSR_MU_OUTBOUND_MESSAGE0_INT \
1023 |ARCMSR_MU_OUTBOUND_MESSAGE1_INT \
1024 |ARCMSR_MU_OUTBOUND_DOORBELL_INT \
1025 |ARCMSR_MU_OUTBOUND_POSTQUEUE_INT \
1026 |ARCMSR_MU_OUTBOUND_PCI_INT)
1027/*
1028*******************************************************************************
1029** Outbound Interrupt Mask Register - OIMR
1030*******************************************************************************
1031*/
1032#define ARCMSR_MU_OUTBOUND_INTERRUPT_MASK_REG 0x34
1033#define ARCMSR_MU_OUTBOUND_PCI_INTMASKENABLE 0x10
1034#define ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE 0x08
1035#define ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE 0x04
1036#define ARCMSR_MU_OUTBOUND_MESSAGE1_INTMASKENABLE 0x02
1037#define ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE 0x01
1038#define ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE 0x1F
1039
1040extern void arcmsr_write_ioctldata2iop(struct AdapterControlBlock *);
1041extern uint32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *,
1042 struct QBUFFER __iomem *);
1043extern void arcmsr_clear_iop2drv_rqueue_buffer(struct AdapterControlBlock *);
1044extern struct QBUFFER __iomem *arcmsr_get_iop_rqbuffer(struct AdapterControlBlock *);
1045extern const struct attribute_group *arcmsr_host_groups[];
1046extern int arcmsr_alloc_sysfs_attr(struct AdapterControlBlock *);
1047void arcmsr_free_sysfs_attr(struct AdapterControlBlock *acb);
1048

source code of linux/drivers/scsi/arcmsr/arcmsr.h