| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * Copyright (c) 2005-2014 Brocade Communications Systems, Inc. |
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| 4 | * Copyright (c) 2014- QLogic Corporation. |
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| 5 | * All rights reserved |
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| 6 | * www.qlogic.com |
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| 7 | * |
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| 8 | * Linux driver for QLogic BR-series Fibre Channel Host Bus Adapter. |
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| 9 | */ |
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| 10 | |
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| 11 | /* |
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| 12 | * bfi_reg.h ASIC register defines for all QLogic BR-series adapter ASICs |
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| 13 | */ |
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| 14 | |
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| 15 | #ifndef __BFI_REG_H__ |
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| 16 | #define __BFI_REG_H__ |
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| 17 | |
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| 18 | #define HOSTFN0_INT_STATUS 0x00014000 /* cb/ct */ |
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| 19 | #define HOSTFN1_INT_STATUS 0x00014100 /* cb/ct */ |
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| 20 | #define HOSTFN2_INT_STATUS 0x00014300 /* ct */ |
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| 21 | #define HOSTFN3_INT_STATUS 0x00014400 /* ct */ |
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| 22 | #define HOSTFN0_INT_MSK 0x00014004 /* cb/ct */ |
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| 23 | #define HOSTFN1_INT_MSK 0x00014104 /* cb/ct */ |
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| 24 | #define HOSTFN2_INT_MSK 0x00014304 /* ct */ |
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| 25 | #define HOSTFN3_INT_MSK 0x00014404 /* ct */ |
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| 26 | |
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| 27 | #define HOST_PAGE_NUM_FN0 0x00014008 /* cb/ct */ |
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| 28 | #define HOST_PAGE_NUM_FN1 0x00014108 /* cb/ct */ |
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| 29 | #define HOST_PAGE_NUM_FN2 0x00014308 /* ct */ |
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| 30 | #define HOST_PAGE_NUM_FN3 0x00014408 /* ct */ |
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| 31 | |
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| 32 | #define APP_PLL_LCLK_CTL_REG 0x00014204 /* cb/ct */ |
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| 33 | #define __P_LCLK_PLL_LOCK 0x80000000 |
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| 34 | #define __APP_PLL_LCLK_SRAM_USE_100MHZ 0x00100000 |
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| 35 | #define __APP_PLL_LCLK_RESET_TIMER_MK 0x000e0000 |
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| 36 | #define __APP_PLL_LCLK_RESET_TIMER_SH 17 |
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| 37 | #define __APP_PLL_LCLK_RESET_TIMER(_v) ((_v) << __APP_PLL_LCLK_RESET_TIMER_SH) |
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| 38 | #define __APP_PLL_LCLK_LOGIC_SOFT_RESET 0x00010000 |
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| 39 | #define __APP_PLL_LCLK_CNTLMT0_1_MK 0x0000c000 |
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| 40 | #define __APP_PLL_LCLK_CNTLMT0_1_SH 14 |
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| 41 | #define __APP_PLL_LCLK_CNTLMT0_1(_v) ((_v) << __APP_PLL_LCLK_CNTLMT0_1_SH) |
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| 42 | #define __APP_PLL_LCLK_JITLMT0_1_MK 0x00003000 |
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| 43 | #define __APP_PLL_LCLK_JITLMT0_1_SH 12 |
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| 44 | #define __APP_PLL_LCLK_JITLMT0_1(_v) ((_v) << __APP_PLL_LCLK_JITLMT0_1_SH) |
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| 45 | #define __APP_PLL_LCLK_HREF 0x00000800 |
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| 46 | #define __APP_PLL_LCLK_HDIV 0x00000400 |
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| 47 | #define __APP_PLL_LCLK_P0_1_MK 0x00000300 |
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| 48 | #define __APP_PLL_LCLK_P0_1_SH 8 |
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| 49 | #define __APP_PLL_LCLK_P0_1(_v) ((_v) << __APP_PLL_LCLK_P0_1_SH) |
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| 50 | #define __APP_PLL_LCLK_Z0_2_MK 0x000000e0 |
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| 51 | #define __APP_PLL_LCLK_Z0_2_SH 5 |
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| 52 | #define __APP_PLL_LCLK_Z0_2(_v) ((_v) << __APP_PLL_LCLK_Z0_2_SH) |
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| 53 | #define __APP_PLL_LCLK_RSEL200500 0x00000010 |
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| 54 | #define __APP_PLL_LCLK_ENARST 0x00000008 |
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| 55 | #define __APP_PLL_LCLK_BYPASS 0x00000004 |
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| 56 | #define __APP_PLL_LCLK_LRESETN 0x00000002 |
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| 57 | #define __APP_PLL_LCLK_ENABLE 0x00000001 |
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| 58 | #define APP_PLL_SCLK_CTL_REG 0x00014208 /* cb/ct */ |
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| 59 | #define __P_SCLK_PLL_LOCK 0x80000000 |
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| 60 | #define __APP_PLL_SCLK_RESET_TIMER_MK 0x000e0000 |
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| 61 | #define __APP_PLL_SCLK_RESET_TIMER_SH 17 |
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| 62 | #define __APP_PLL_SCLK_RESET_TIMER(_v) ((_v) << __APP_PLL_SCLK_RESET_TIMER_SH) |
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| 63 | #define __APP_PLL_SCLK_LOGIC_SOFT_RESET 0x00010000 |
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| 64 | #define __APP_PLL_SCLK_CNTLMT0_1_MK 0x0000c000 |
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| 65 | #define __APP_PLL_SCLK_CNTLMT0_1_SH 14 |
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| 66 | #define __APP_PLL_SCLK_CNTLMT0_1(_v) ((_v) << __APP_PLL_SCLK_CNTLMT0_1_SH) |
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| 67 | #define __APP_PLL_SCLK_JITLMT0_1_MK 0x00003000 |
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| 68 | #define __APP_PLL_SCLK_JITLMT0_1_SH 12 |
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| 69 | #define __APP_PLL_SCLK_JITLMT0_1(_v) ((_v) << __APP_PLL_SCLK_JITLMT0_1_SH) |
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| 70 | #define __APP_PLL_SCLK_HREF 0x00000800 |
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| 71 | #define __APP_PLL_SCLK_HDIV 0x00000400 |
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| 72 | #define __APP_PLL_SCLK_P0_1_MK 0x00000300 |
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| 73 | #define __APP_PLL_SCLK_P0_1_SH 8 |
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| 74 | #define __APP_PLL_SCLK_P0_1(_v) ((_v) << __APP_PLL_SCLK_P0_1_SH) |
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| 75 | #define __APP_PLL_SCLK_Z0_2_MK 0x000000e0 |
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| 76 | #define __APP_PLL_SCLK_Z0_2_SH 5 |
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| 77 | #define __APP_PLL_SCLK_Z0_2(_v) ((_v) << __APP_PLL_SCLK_Z0_2_SH) |
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| 78 | #define __APP_PLL_SCLK_RSEL200500 0x00000010 |
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| 79 | #define __APP_PLL_SCLK_ENARST 0x00000008 |
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| 80 | #define __APP_PLL_SCLK_BYPASS 0x00000004 |
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| 81 | #define __APP_PLL_SCLK_LRESETN 0x00000002 |
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| 82 | #define __APP_PLL_SCLK_ENABLE 0x00000001 |
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| 83 | #define __ENABLE_MAC_AHB_1 0x00800000 /* ct */ |
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| 84 | #define __ENABLE_MAC_AHB_0 0x00400000 /* ct */ |
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| 85 | #define __ENABLE_MAC_1 0x00200000 /* ct */ |
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| 86 | #define __ENABLE_MAC_0 0x00100000 /* ct */ |
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| 87 | |
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| 88 | #define HOST_SEM0_REG 0x00014230 /* cb/ct */ |
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| 89 | #define HOST_SEM1_REG 0x00014234 /* cb/ct */ |
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| 90 | #define HOST_SEM2_REG 0x00014238 /* cb/ct */ |
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| 91 | #define HOST_SEM3_REG 0x0001423c /* cb/ct */ |
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| 92 | #define HOST_SEM4_REG 0x00014610 /* cb/ct */ |
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| 93 | #define HOST_SEM5_REG 0x00014614 /* cb/ct */ |
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| 94 | #define HOST_SEM6_REG 0x00014618 /* cb/ct */ |
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| 95 | #define HOST_SEM7_REG 0x0001461c /* cb/ct */ |
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| 96 | #define HOST_SEM0_INFO_REG 0x00014240 /* cb/ct */ |
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| 97 | #define HOST_SEM1_INFO_REG 0x00014244 /* cb/ct */ |
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| 98 | #define HOST_SEM2_INFO_REG 0x00014248 /* cb/ct */ |
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| 99 | #define HOST_SEM3_INFO_REG 0x0001424c /* cb/ct */ |
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| 100 | #define HOST_SEM4_INFO_REG 0x00014620 /* cb/ct */ |
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| 101 | #define HOST_SEM5_INFO_REG 0x00014624 /* cb/ct */ |
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| 102 | #define HOST_SEM6_INFO_REG 0x00014628 /* cb/ct */ |
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| 103 | #define HOST_SEM7_INFO_REG 0x0001462c /* cb/ct */ |
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| 104 | |
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| 105 | #define HOSTFN0_LPU0_CMD_STAT 0x00019000 /* cb/ct */ |
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| 106 | #define HOSTFN0_LPU1_CMD_STAT 0x00019004 /* cb/ct */ |
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| 107 | #define HOSTFN1_LPU0_CMD_STAT 0x00019010 /* cb/ct */ |
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| 108 | #define HOSTFN1_LPU1_CMD_STAT 0x00019014 /* cb/ct */ |
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| 109 | #define HOSTFN2_LPU0_CMD_STAT 0x00019150 /* ct */ |
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| 110 | #define HOSTFN2_LPU1_CMD_STAT 0x00019154 /* ct */ |
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| 111 | #define HOSTFN3_LPU0_CMD_STAT 0x00019160 /* ct */ |
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| 112 | #define HOSTFN3_LPU1_CMD_STAT 0x00019164 /* ct */ |
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| 113 | #define LPU0_HOSTFN0_CMD_STAT 0x00019008 /* cb/ct */ |
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| 114 | #define LPU1_HOSTFN0_CMD_STAT 0x0001900c /* cb/ct */ |
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| 115 | #define LPU0_HOSTFN1_CMD_STAT 0x00019018 /* cb/ct */ |
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| 116 | #define LPU1_HOSTFN1_CMD_STAT 0x0001901c /* cb/ct */ |
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| 117 | #define LPU0_HOSTFN2_CMD_STAT 0x00019158 /* ct */ |
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| 118 | #define LPU1_HOSTFN2_CMD_STAT 0x0001915c /* ct */ |
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| 119 | #define LPU0_HOSTFN3_CMD_STAT 0x00019168 /* ct */ |
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| 120 | #define LPU1_HOSTFN3_CMD_STAT 0x0001916c /* ct */ |
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| 121 | |
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| 122 | #define PSS_CTL_REG 0x00018800 /* cb/ct */ |
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| 123 | #define __PSS_I2C_CLK_DIV_MK 0x007f0000 |
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| 124 | #define __PSS_I2C_CLK_DIV_SH 16 |
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| 125 | #define __PSS_I2C_CLK_DIV(_v) ((_v) << __PSS_I2C_CLK_DIV_SH) |
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| 126 | #define __PSS_LMEM_INIT_DONE 0x00001000 |
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| 127 | #define __PSS_LMEM_RESET 0x00000200 |
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| 128 | #define __PSS_LMEM_INIT_EN 0x00000100 |
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| 129 | #define __PSS_LPU1_RESET 0x00000002 |
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| 130 | #define __PSS_LPU0_RESET 0x00000001 |
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| 131 | #define PSS_ERR_STATUS_REG 0x00018810 /* cb/ct */ |
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| 132 | #define ERR_SET_REG 0x00018818 /* cb/ct */ |
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| 133 | #define PSS_GPIO_OUT_REG 0x000188c0 /* cb/ct */ |
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| 134 | #define __PSS_GPIO_OUT_REG 0x00000fff |
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| 135 | #define PSS_GPIO_OE_REG 0x000188c8 /* cb/ct */ |
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| 136 | #define __PSS_GPIO_OE_REG 0x000000ff |
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| 137 | |
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| 138 | #define HOSTFN0_LPU_MBOX0_0 0x00019200 /* cb/ct */ |
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| 139 | #define HOSTFN1_LPU_MBOX0_8 0x00019260 /* cb/ct */ |
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| 140 | #define LPU_HOSTFN0_MBOX0_0 0x00019280 /* cb/ct */ |
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| 141 | #define LPU_HOSTFN1_MBOX0_8 0x000192e0 /* cb/ct */ |
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| 142 | #define HOSTFN2_LPU_MBOX0_0 0x00019400 /* ct */ |
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| 143 | #define HOSTFN3_LPU_MBOX0_8 0x00019460 /* ct */ |
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| 144 | #define LPU_HOSTFN2_MBOX0_0 0x00019480 /* ct */ |
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| 145 | #define LPU_HOSTFN3_MBOX0_8 0x000194e0 /* ct */ |
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| 146 | |
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| 147 | #define HOST_MSIX_ERR_INDEX_FN0 0x0001400c /* ct */ |
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| 148 | #define HOST_MSIX_ERR_INDEX_FN1 0x0001410c /* ct */ |
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| 149 | #define HOST_MSIX_ERR_INDEX_FN2 0x0001430c /* ct */ |
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| 150 | #define HOST_MSIX_ERR_INDEX_FN3 0x0001440c /* ct */ |
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| 151 | |
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| 152 | #define MBIST_CTL_REG 0x00014220 /* ct */ |
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| 153 | #define __EDRAM_BISTR_START 0x00000004 |
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| 154 | #define MBIST_STAT_REG 0x00014224 /* ct */ |
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| 155 | #define ETH_MAC_SER_REG 0x00014288 /* ct */ |
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| 156 | #define __APP_EMS_CKBUFAMPIN 0x00000020 |
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| 157 | #define __APP_EMS_REFCLKSEL 0x00000010 |
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| 158 | #define __APP_EMS_CMLCKSEL 0x00000008 |
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| 159 | #define __APP_EMS_REFCKBUFEN2 0x00000004 |
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| 160 | #define __APP_EMS_REFCKBUFEN1 0x00000002 |
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| 161 | #define __APP_EMS_CHANNEL_SEL 0x00000001 |
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| 162 | #define FNC_PERS_REG 0x00014604 /* ct */ |
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| 163 | #define __F3_FUNCTION_ACTIVE 0x80000000 |
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| 164 | #define __F3_FUNCTION_MODE 0x40000000 |
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| 165 | #define __F3_PORT_MAP_MK 0x30000000 |
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| 166 | #define __F3_PORT_MAP_SH 28 |
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| 167 | #define __F3_PORT_MAP(_v) ((_v) << __F3_PORT_MAP_SH) |
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| 168 | #define __F3_VM_MODE 0x08000000 |
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| 169 | #define __F3_INTX_STATUS_MK 0x07000000 |
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| 170 | #define __F3_INTX_STATUS_SH 24 |
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| 171 | #define __F3_INTX_STATUS(_v) ((_v) << __F3_INTX_STATUS_SH) |
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| 172 | #define __F2_FUNCTION_ACTIVE 0x00800000 |
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| 173 | #define __F2_FUNCTION_MODE 0x00400000 |
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| 174 | #define __F2_PORT_MAP_MK 0x00300000 |
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| 175 | #define __F2_PORT_MAP_SH 20 |
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| 176 | #define __F2_PORT_MAP(_v) ((_v) << __F2_PORT_MAP_SH) |
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| 177 | #define __F2_VM_MODE 0x00080000 |
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| 178 | #define __F2_INTX_STATUS_MK 0x00070000 |
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| 179 | #define __F2_INTX_STATUS_SH 16 |
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| 180 | #define __F2_INTX_STATUS(_v) ((_v) << __F2_INTX_STATUS_SH) |
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| 181 | #define __F1_FUNCTION_ACTIVE 0x00008000 |
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| 182 | #define __F1_FUNCTION_MODE 0x00004000 |
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| 183 | #define __F1_PORT_MAP_MK 0x00003000 |
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| 184 | #define __F1_PORT_MAP_SH 12 |
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| 185 | #define __F1_PORT_MAP(_v) ((_v) << __F1_PORT_MAP_SH) |
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| 186 | #define __F1_VM_MODE 0x00000800 |
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| 187 | #define __F1_INTX_STATUS_MK 0x00000700 |
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| 188 | #define __F1_INTX_STATUS_SH 8 |
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| 189 | #define __F1_INTX_STATUS(_v) ((_v) << __F1_INTX_STATUS_SH) |
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| 190 | #define __F0_FUNCTION_ACTIVE 0x00000080 |
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| 191 | #define __F0_FUNCTION_MODE 0x00000040 |
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| 192 | #define __F0_PORT_MAP_MK 0x00000030 |
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| 193 | #define __F0_PORT_MAP_SH 4 |
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| 194 | #define __F0_PORT_MAP(_v) ((_v) << __F0_PORT_MAP_SH) |
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| 195 | #define __F0_VM_MODE 0x00000008 |
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| 196 | #define __F0_INTX_STATUS 0x00000007 |
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| 197 | enum { |
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| 198 | __F0_INTX_STATUS_MSIX = 0x0, |
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| 199 | __F0_INTX_STATUS_INTA = 0x1, |
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| 200 | __F0_INTX_STATUS_INTB = 0x2, |
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| 201 | __F0_INTX_STATUS_INTC = 0x3, |
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| 202 | __F0_INTX_STATUS_INTD = 0x4, |
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| 203 | }; |
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| 204 | |
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| 205 | #define OP_MODE 0x0001460c /* ct */ |
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| 206 | #define __APP_ETH_CLK_LOWSPEED 0x00000004 |
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| 207 | #define __GLOBAL_CORECLK_HALFSPEED 0x00000002 |
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| 208 | #define __GLOBAL_FCOE_MODE 0x00000001 |
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| 209 | #define FW_INIT_HALT_P0 0x000191ac /* ct */ |
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| 210 | #define __FW_INIT_HALT_P 0x00000001 |
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| 211 | #define FW_INIT_HALT_P1 0x000191bc /* ct */ |
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| 212 | #define PMM_1T_RESET_REG_P0 0x0002381c /* ct */ |
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| 213 | #define __PMM_1T_RESET_P 0x00000001 |
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| 214 | #define PMM_1T_RESET_REG_P1 0x00023c1c /* ct */ |
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| 215 | |
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| 216 | /** |
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| 217 | * Catapult-2 specific defines |
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| 218 | */ |
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| 219 | #define CT2_PCI_CPQ_BASE 0x00030000 |
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| 220 | #define CT2_PCI_APP_BASE 0x00030100 |
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| 221 | #define CT2_PCI_ETH_BASE 0x00030400 |
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| 222 | |
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| 223 | /* |
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| 224 | * APP block registers |
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| 225 | */ |
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| 226 | #define CT2_HOSTFN_INT_STATUS (CT2_PCI_APP_BASE + 0x00) |
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| 227 | #define CT2_HOSTFN_INTR_MASK (CT2_PCI_APP_BASE + 0x04) |
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| 228 | #define CT2_HOSTFN_PERSONALITY0 (CT2_PCI_APP_BASE + 0x08) |
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| 229 | #define __PME_STATUS_ 0x00200000 |
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| 230 | #define __PF_VF_BAR_SIZE_MODE__MK 0x00180000 |
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| 231 | #define __PF_VF_BAR_SIZE_MODE__SH 19 |
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| 232 | #define __PF_VF_BAR_SIZE_MODE_(_v) ((_v) << __PF_VF_BAR_SIZE_MODE__SH) |
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| 233 | #define __FC_LL_PORT_MAP__MK 0x00060000 |
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| 234 | #define __FC_LL_PORT_MAP__SH 17 |
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| 235 | #define __FC_LL_PORT_MAP_(_v) ((_v) << __FC_LL_PORT_MAP__SH) |
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| 236 | #define __PF_VF_ACTIVE_ 0x00010000 |
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| 237 | #define __PF_VF_CFG_RDY_ 0x00008000 |
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| 238 | #define __PF_VF_ENABLE_ 0x00004000 |
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| 239 | #define __PF_DRIVER_ACTIVE_ 0x00002000 |
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| 240 | #define __PF_PME_SEND_ENABLE_ 0x00001000 |
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| 241 | #define __PF_EXROM_OFFSET__MK 0x00000ff0 |
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| 242 | #define __PF_EXROM_OFFSET__SH 4 |
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| 243 | #define __PF_EXROM_OFFSET_(_v) ((_v) << __PF_EXROM_OFFSET__SH) |
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| 244 | #define __FC_LL_MODE_ 0x00000008 |
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| 245 | #define __PF_INTX_PIN_ 0x00000007 |
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| 246 | #define CT2_HOSTFN_PERSONALITY1 (CT2_PCI_APP_BASE + 0x0C) |
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| 247 | #define __PF_NUM_QUEUES1__MK 0xff000000 |
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| 248 | #define __PF_NUM_QUEUES1__SH 24 |
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| 249 | #define __PF_NUM_QUEUES1_(_v) ((_v) << __PF_NUM_QUEUES1__SH) |
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| 250 | #define __PF_VF_QUE_OFFSET1__MK 0x00ff0000 |
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| 251 | #define __PF_VF_QUE_OFFSET1__SH 16 |
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| 252 | #define __PF_VF_QUE_OFFSET1_(_v) ((_v) << __PF_VF_QUE_OFFSET1__SH) |
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| 253 | #define __PF_VF_NUM_QUEUES__MK 0x0000ff00 |
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| 254 | #define __PF_VF_NUM_QUEUES__SH 8 |
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| 255 | #define __PF_VF_NUM_QUEUES_(_v) ((_v) << __PF_VF_NUM_QUEUES__SH) |
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| 256 | #define __PF_VF_QUE_OFFSET_ 0x000000ff |
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| 257 | #define CT2_HOSTFN_PAGE_NUM (CT2_PCI_APP_BASE + 0x18) |
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| 258 | #define CT2_HOSTFN_MSIX_VT_INDEX_MBOX_ERR (CT2_PCI_APP_BASE + 0x38) |
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| 259 | |
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| 260 | /* |
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| 261 | * Catapult-2 CPQ block registers |
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| 262 | */ |
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| 263 | #define CT2_HOSTFN_LPU0_MBOX0 (CT2_PCI_CPQ_BASE + 0x00) |
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| 264 | #define CT2_HOSTFN_LPU1_MBOX0 (CT2_PCI_CPQ_BASE + 0x20) |
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| 265 | #define CT2_LPU0_HOSTFN_MBOX0 (CT2_PCI_CPQ_BASE + 0x40) |
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| 266 | #define CT2_LPU1_HOSTFN_MBOX0 (CT2_PCI_CPQ_BASE + 0x60) |
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| 267 | #define CT2_HOSTFN_LPU0_CMD_STAT (CT2_PCI_CPQ_BASE + 0x80) |
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| 268 | #define CT2_HOSTFN_LPU1_CMD_STAT (CT2_PCI_CPQ_BASE + 0x84) |
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| 269 | #define CT2_LPU0_HOSTFN_CMD_STAT (CT2_PCI_CPQ_BASE + 0x88) |
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| 270 | #define CT2_LPU1_HOSTFN_CMD_STAT (CT2_PCI_CPQ_BASE + 0x8c) |
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| 271 | #define CT2_HOSTFN_LPU0_READ_STAT (CT2_PCI_CPQ_BASE + 0x90) |
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| 272 | #define CT2_HOSTFN_LPU1_READ_STAT (CT2_PCI_CPQ_BASE + 0x94) |
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| 273 | #define CT2_LPU0_HOSTFN_MBOX0_MSK (CT2_PCI_CPQ_BASE + 0x98) |
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| 274 | #define CT2_LPU1_HOSTFN_MBOX0_MSK (CT2_PCI_CPQ_BASE + 0x9C) |
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| 275 | #define CT2_HOST_SEM0_REG 0x000148f0 |
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| 276 | #define CT2_HOST_SEM1_REG 0x000148f4 |
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| 277 | #define CT2_HOST_SEM2_REG 0x000148f8 |
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| 278 | #define CT2_HOST_SEM3_REG 0x000148fc |
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| 279 | #define CT2_HOST_SEM4_REG 0x00014900 |
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| 280 | #define CT2_HOST_SEM5_REG 0x00014904 |
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| 281 | #define CT2_HOST_SEM6_REG 0x00014908 |
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| 282 | #define CT2_HOST_SEM7_REG 0x0001490c |
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| 283 | #define CT2_HOST_SEM0_INFO_REG 0x000148b0 |
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| 284 | #define CT2_HOST_SEM1_INFO_REG 0x000148b4 |
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| 285 | #define CT2_HOST_SEM2_INFO_REG 0x000148b8 |
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| 286 | #define CT2_HOST_SEM3_INFO_REG 0x000148bc |
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| 287 | #define CT2_HOST_SEM4_INFO_REG 0x000148c0 |
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| 288 | #define CT2_HOST_SEM5_INFO_REG 0x000148c4 |
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| 289 | #define CT2_HOST_SEM6_INFO_REG 0x000148c8 |
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| 290 | #define CT2_HOST_SEM7_INFO_REG 0x000148cc |
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| 291 | |
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| 292 | #define CT2_APP_PLL_LCLK_CTL_REG 0x00014808 |
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| 293 | #define __APP_LPUCLK_HALFSPEED 0x40000000 |
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| 294 | #define __APP_PLL_LCLK_LOAD 0x20000000 |
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| 295 | #define __APP_PLL_LCLK_FBCNT_MK 0x1fe00000 |
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| 296 | #define __APP_PLL_LCLK_FBCNT_SH 21 |
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| 297 | #define __APP_PLL_LCLK_FBCNT(_v) ((_v) << __APP_PLL_SCLK_FBCNT_SH) |
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| 298 | enum { |
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| 299 | __APP_PLL_LCLK_FBCNT_425_MHZ = 6, |
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| 300 | __APP_PLL_LCLK_FBCNT_468_MHZ = 4, |
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| 301 | }; |
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| 302 | #define __APP_PLL_LCLK_EXTFB 0x00000800 |
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| 303 | #define __APP_PLL_LCLK_ENOUTS 0x00000400 |
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| 304 | #define __APP_PLL_LCLK_RATE 0x00000010 |
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| 305 | #define CT2_APP_PLL_SCLK_CTL_REG 0x0001480c |
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| 306 | #define __P_SCLK_PLL_LOCK 0x80000000 |
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| 307 | #define __APP_PLL_SCLK_REFCLK_SEL 0x40000000 |
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| 308 | #define __APP_PLL_SCLK_CLK_DIV2 0x20000000 |
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| 309 | #define __APP_PLL_SCLK_LOAD 0x10000000 |
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| 310 | #define __APP_PLL_SCLK_FBCNT_MK 0x0ff00000 |
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| 311 | #define __APP_PLL_SCLK_FBCNT_SH 20 |
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| 312 | #define __APP_PLL_SCLK_FBCNT(_v) ((_v) << __APP_PLL_SCLK_FBCNT_SH) |
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| 313 | enum { |
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| 314 | __APP_PLL_SCLK_FBCNT_NORM = 6, |
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| 315 | __APP_PLL_SCLK_FBCNT_10G_FC = 10, |
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| 316 | }; |
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| 317 | #define __APP_PLL_SCLK_EXTFB 0x00000800 |
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| 318 | #define __APP_PLL_SCLK_ENOUTS 0x00000400 |
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| 319 | #define __APP_PLL_SCLK_RATE 0x00000010 |
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| 320 | #define CT2_PCIE_MISC_REG 0x00014804 |
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| 321 | #define __ETH_CLK_ENABLE_PORT1 0x00000010 |
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| 322 | #define CT2_CHIP_MISC_PRG 0x000148a4 |
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| 323 | #define __ETH_CLK_ENABLE_PORT0 0x00004000 |
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| 324 | #define __APP_LPU_SPEED 0x00000002 |
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| 325 | #define CT2_MBIST_STAT_REG 0x00014818 |
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| 326 | #define CT2_MBIST_CTL_REG 0x0001481c |
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| 327 | #define CT2_PMM_1T_CONTROL_REG_P0 0x0002381c |
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| 328 | #define __PMM_1T_PNDB_P 0x00000002 |
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| 329 | #define CT2_PMM_1T_CONTROL_REG_P1 0x00023c1c |
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| 330 | #define CT2_WGN_STATUS 0x00014990 |
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| 331 | #define __A2T_AHB_LOAD 0x00000800 |
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| 332 | #define __WGN_READY 0x00000400 |
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| 333 | #define __GLBL_PF_VF_CFG_RDY 0x00000200 |
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| 334 | #define CT2_NFC_STS_REG 0x00027410 |
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| 335 | #define CT2_NFC_CSR_CLR_REG 0x00027420 |
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| 336 | #define CT2_NFC_CSR_SET_REG 0x00027424 |
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| 337 | #define __HALT_NFC_CONTROLLER 0x00000002 |
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| 338 | #define __NFC_CONTROLLER_HALTED 0x00001000 |
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| 339 | #define CT2_RSC_GPR15_REG 0x0002765c |
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| 340 | #define CT2_CSI_FW_CTL_REG 0x00027080 |
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| 341 | #define CT2_CSI_FW_CTL_SET_REG 0x00027088 |
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| 342 | #define __RESET_AND_START_SCLK_LCLK_PLLS 0x00010000 |
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| 343 | |
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| 344 | #define CT2_CSI_MAC0_CONTROL_REG 0x000270d0 |
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| 345 | #define __CSI_MAC_RESET 0x00000010 |
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| 346 | #define __CSI_MAC_AHB_RESET 0x00000008 |
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| 347 | #define CT2_CSI_MAC1_CONTROL_REG 0x000270d4 |
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| 348 | #define CT2_CSI_MAC_CONTROL_REG(__n) \ |
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| 349 | (CT2_CSI_MAC0_CONTROL_REG + \ |
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| 350 | (__n) * (CT2_CSI_MAC1_CONTROL_REG - CT2_CSI_MAC0_CONTROL_REG)) |
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| 351 | |
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| 352 | #define CT2_NFC_FLASH_STS_REG 0x00014834 |
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| 353 | #define __FLASH_PLL_INIT_AND_RESET_IN_PROGRESS 0x00000020 |
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| 354 | /* |
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| 355 | * Name semaphore registers based on usage |
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| 356 | */ |
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| 357 | #define BFA_IOC0_HBEAT_REG HOST_SEM0_INFO_REG |
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| 358 | #define BFA_IOC0_STATE_REG HOST_SEM1_INFO_REG |
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| 359 | #define BFA_IOC1_HBEAT_REG HOST_SEM2_INFO_REG |
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| 360 | #define BFA_IOC1_STATE_REG HOST_SEM3_INFO_REG |
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| 361 | #define BFA_FW_USE_COUNT HOST_SEM4_INFO_REG |
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| 362 | #define BFA_IOC_FAIL_SYNC HOST_SEM5_INFO_REG |
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| 363 | |
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| 364 | /* |
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| 365 | * CT2 semaphore register locations changed |
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| 366 | */ |
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| 367 | #define CT2_BFA_IOC0_HBEAT_REG CT2_HOST_SEM0_INFO_REG |
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| 368 | #define CT2_BFA_IOC0_STATE_REG CT2_HOST_SEM1_INFO_REG |
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| 369 | #define CT2_BFA_IOC1_HBEAT_REG CT2_HOST_SEM2_INFO_REG |
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| 370 | #define CT2_BFA_IOC1_STATE_REG CT2_HOST_SEM3_INFO_REG |
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| 371 | #define CT2_BFA_FW_USE_COUNT CT2_HOST_SEM4_INFO_REG |
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| 372 | #define CT2_BFA_IOC_FAIL_SYNC CT2_HOST_SEM5_INFO_REG |
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| 373 | |
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| 374 | #define CPE_Q_NUM(__fn, __q) (((__fn) << 2) + (__q)) |
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| 375 | #define RME_Q_NUM(__fn, __q) (((__fn) << 2) + (__q)) |
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| 376 | |
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| 377 | /* |
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| 378 | * And corresponding host interrupt status bit field defines |
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| 379 | */ |
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| 380 | #define __HFN_INT_CPE_Q0 0x00000001U |
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| 381 | #define __HFN_INT_CPE_Q1 0x00000002U |
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| 382 | #define __HFN_INT_CPE_Q2 0x00000004U |
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| 383 | #define __HFN_INT_CPE_Q3 0x00000008U |
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| 384 | #define __HFN_INT_CPE_Q4 0x00000010U |
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| 385 | #define __HFN_INT_CPE_Q5 0x00000020U |
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| 386 | #define __HFN_INT_CPE_Q6 0x00000040U |
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| 387 | #define __HFN_INT_CPE_Q7 0x00000080U |
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| 388 | #define __HFN_INT_RME_Q0 0x00000100U |
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| 389 | #define __HFN_INT_RME_Q1 0x00000200U |
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| 390 | #define __HFN_INT_RME_Q2 0x00000400U |
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| 391 | #define __HFN_INT_RME_Q3 0x00000800U |
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| 392 | #define __HFN_INT_RME_Q4 0x00001000U |
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| 393 | #define __HFN_INT_RME_Q5 0x00002000U |
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| 394 | #define __HFN_INT_RME_Q6 0x00004000U |
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| 395 | #define __HFN_INT_RME_Q7 0x00008000U |
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| 396 | #define __HFN_INT_ERR_EMC 0x00010000U |
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| 397 | #define __HFN_INT_ERR_LPU0 0x00020000U |
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| 398 | #define __HFN_INT_ERR_LPU1 0x00040000U |
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| 399 | #define __HFN_INT_ERR_PSS 0x00080000U |
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| 400 | #define __HFN_INT_MBOX_LPU0 0x00100000U |
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| 401 | #define __HFN_INT_MBOX_LPU1 0x00200000U |
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| 402 | #define __HFN_INT_MBOX1_LPU0 0x00400000U |
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| 403 | #define __HFN_INT_MBOX1_LPU1 0x00800000U |
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| 404 | #define __HFN_INT_LL_HALT 0x01000000U |
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| 405 | #define __HFN_INT_CPE_MASK 0x000000ffU |
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| 406 | #define __HFN_INT_RME_MASK 0x0000ff00U |
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| 407 | #define __HFN_INT_ERR_MASK \ |
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| 408 | (__HFN_INT_ERR_EMC | __HFN_INT_ERR_LPU0 | __HFN_INT_ERR_LPU1 | \ |
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| 409 | __HFN_INT_ERR_PSS | __HFN_INT_LL_HALT) |
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| 410 | #define __HFN_INT_FN0_MASK \ |
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| 411 | (__HFN_INT_CPE_Q0 | __HFN_INT_CPE_Q1 | __HFN_INT_CPE_Q2 | \ |
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| 412 | __HFN_INT_CPE_Q3 | __HFN_INT_RME_Q0 | __HFN_INT_RME_Q1 | \ |
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| 413 | __HFN_INT_RME_Q2 | __HFN_INT_RME_Q3 | __HFN_INT_MBOX_LPU0) |
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| 414 | #define __HFN_INT_FN1_MASK \ |
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| 415 | (__HFN_INT_CPE_Q4 | __HFN_INT_CPE_Q5 | __HFN_INT_CPE_Q6 | \ |
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| 416 | __HFN_INT_CPE_Q7 | __HFN_INT_RME_Q4 | __HFN_INT_RME_Q5 | \ |
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| 417 | __HFN_INT_RME_Q6 | __HFN_INT_RME_Q7 | __HFN_INT_MBOX_LPU1) |
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| 418 | |
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| 419 | /* |
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| 420 | * Host interrupt status defines for catapult-2 |
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| 421 | */ |
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| 422 | #define __HFN_INT_MBOX_LPU0_CT2 0x00010000U |
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| 423 | #define __HFN_INT_MBOX_LPU1_CT2 0x00020000U |
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| 424 | #define __HFN_INT_ERR_PSS_CT2 0x00040000U |
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| 425 | #define __HFN_INT_ERR_LPU0_CT2 0x00080000U |
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| 426 | #define __HFN_INT_ERR_LPU1_CT2 0x00100000U |
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| 427 | #define __HFN_INT_CPQ_HALT_CT2 0x00200000U |
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| 428 | #define __HFN_INT_ERR_WGN_CT2 0x00400000U |
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| 429 | #define __HFN_INT_ERR_LEHRX_CT2 0x00800000U |
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| 430 | #define __HFN_INT_ERR_LEHTX_CT2 0x01000000U |
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| 431 | #define __HFN_INT_ERR_MASK_CT2 \ |
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| 432 | (__HFN_INT_ERR_PSS_CT2 | __HFN_INT_ERR_LPU0_CT2 | \ |
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| 433 | __HFN_INT_ERR_LPU1_CT2 | __HFN_INT_CPQ_HALT_CT2 | \ |
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| 434 | __HFN_INT_ERR_WGN_CT2 | __HFN_INT_ERR_LEHRX_CT2 | \ |
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| 435 | __HFN_INT_ERR_LEHTX_CT2) |
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| 436 | #define __HFN_INT_FN0_MASK_CT2 \ |
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| 437 | (__HFN_INT_CPE_Q0 | __HFN_INT_CPE_Q1 | __HFN_INT_CPE_Q2 | \ |
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| 438 | __HFN_INT_CPE_Q3 | __HFN_INT_RME_Q0 | __HFN_INT_RME_Q1 | \ |
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| 439 | __HFN_INT_RME_Q2 | __HFN_INT_RME_Q3 | __HFN_INT_MBOX_LPU0_CT2) |
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| 440 | #define __HFN_INT_FN1_MASK_CT2 \ |
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| 441 | (__HFN_INT_CPE_Q4 | __HFN_INT_CPE_Q5 | __HFN_INT_CPE_Q6 | \ |
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| 442 | __HFN_INT_CPE_Q7 | __HFN_INT_RME_Q4 | __HFN_INT_RME_Q5 | \ |
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| 443 | __HFN_INT_RME_Q6 | __HFN_INT_RME_Q7 | __HFN_INT_MBOX_LPU1_CT2) |
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| 444 | |
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| 445 | /* |
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| 446 | * asic memory map. |
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| 447 | */ |
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| 448 | #define PSS_SMEM_PAGE_START 0x8000 |
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| 449 | #define PSS_SMEM_PGNUM(_pg0, _ma) ((_pg0) + ((_ma) >> 15)) |
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| 450 | #define PSS_SMEM_PGOFF(_ma) ((_ma) & 0x7fff) |
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| 451 | |
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| 452 | #endif /* __BFI_REG_H__ */ |
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| 453 | |
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