1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * Copyright 2008 Cisco Systems, Inc. All rights reserved. |
4 | * Copyright 2007 Nuova Systems, Inc. All rights reserved. |
5 | */ |
6 | #ifndef _VNIC_CQ_H_ |
7 | #define _VNIC_CQ_H_ |
8 | |
9 | #include "cq_desc.h" |
10 | #include "vnic_dev.h" |
11 | |
12 | /* |
13 | * These defines avoid symbol clash between fnic and enic (Cisco 10G Eth |
14 | * Driver) when both are built with CONFIG options =y |
15 | */ |
16 | #define vnic_cq_service fnic_cq_service |
17 | #define vnic_cq_free fnic_cq_free |
18 | #define vnic_cq_alloc fnic_cq_alloc |
19 | #define vnic_cq_init fnic_cq_init |
20 | #define vnic_cq_clean fnic_cq_clean |
21 | |
22 | /* Completion queue control */ |
23 | struct vnic_cq_ctrl { |
24 | u64 ring_base; /* 0x00 */ |
25 | u32 ring_size; /* 0x08 */ |
26 | u32 pad0; |
27 | u32 flow_control_enable; /* 0x10 */ |
28 | u32 pad1; |
29 | u32 color_enable; /* 0x18 */ |
30 | u32 pad2; |
31 | u32 cq_head; /* 0x20 */ |
32 | u32 pad3; |
33 | u32 cq_tail; /* 0x28 */ |
34 | u32 pad4; |
35 | u32 cq_tail_color; /* 0x30 */ |
36 | u32 pad5; |
37 | u32 interrupt_enable; /* 0x38 */ |
38 | u32 pad6; |
39 | u32 cq_entry_enable; /* 0x40 */ |
40 | u32 pad7; |
41 | u32 cq_message_enable; /* 0x48 */ |
42 | u32 pad8; |
43 | u32 interrupt_offset; /* 0x50 */ |
44 | u32 pad9; |
45 | u64 cq_message_addr; /* 0x58 */ |
46 | u32 pad10; |
47 | }; |
48 | |
49 | struct vnic_cq { |
50 | unsigned int index; |
51 | struct vnic_dev *vdev; |
52 | struct vnic_cq_ctrl __iomem *ctrl; /* memory-mapped */ |
53 | struct vnic_dev_ring ring; |
54 | unsigned int to_clean; |
55 | unsigned int last_color; |
56 | }; |
57 | |
58 | static inline unsigned int vnic_cq_service(struct vnic_cq *cq, |
59 | unsigned int work_to_do, |
60 | int (*q_service)(struct vnic_dev *vdev, struct cq_desc *cq_desc, |
61 | u8 type, u16 q_number, u16 completed_index, void *opaque), |
62 | void *opaque) |
63 | { |
64 | struct cq_desc *cq_desc; |
65 | unsigned int work_done = 0; |
66 | u16 q_number, completed_index; |
67 | u8 type, color; |
68 | |
69 | cq_desc = (struct cq_desc *)((u8 *)cq->ring.descs + |
70 | cq->ring.desc_size * cq->to_clean); |
71 | cq_desc_dec(desc_arg: cq_desc, type: &type, color: &color, |
72 | q_number: &q_number, completed_index: &completed_index); |
73 | |
74 | while (color != cq->last_color) { |
75 | |
76 | if ((*q_service)(cq->vdev, cq_desc, type, |
77 | q_number, completed_index, opaque)) |
78 | break; |
79 | |
80 | cq->to_clean++; |
81 | if (cq->to_clean == cq->ring.desc_count) { |
82 | cq->to_clean = 0; |
83 | cq->last_color = cq->last_color ? 0 : 1; |
84 | } |
85 | |
86 | cq_desc = (struct cq_desc *)((u8 *)cq->ring.descs + |
87 | cq->ring.desc_size * cq->to_clean); |
88 | cq_desc_dec(desc_arg: cq_desc, type: &type, color: &color, |
89 | q_number: &q_number, completed_index: &completed_index); |
90 | |
91 | work_done++; |
92 | if (work_done >= work_to_do) |
93 | break; |
94 | } |
95 | |
96 | return work_done; |
97 | } |
98 | |
99 | void vnic_cq_free(struct vnic_cq *cq); |
100 | int vnic_cq_alloc(struct vnic_dev *vdev, struct vnic_cq *cq, unsigned int index, |
101 | unsigned int desc_count, unsigned int desc_size); |
102 | void vnic_cq_init(struct vnic_cq *cq, unsigned int flow_control_enable, |
103 | unsigned int color_enable, unsigned int cq_head, unsigned int cq_tail, |
104 | unsigned int cq_tail_color, unsigned int interrupt_enable, |
105 | unsigned int cq_entry_enable, unsigned int message_enable, |
106 | unsigned int interrupt_offset, u64 message_addr); |
107 | void vnic_cq_clean(struct vnic_cq *cq); |
108 | |
109 | #endif /* _VNIC_CQ_H_ */ |
110 | |