1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef _GDTH_H
3#define _GDTH_H
4
5/*
6 * Header file for the GDT Disk Array/Storage RAID controllers driver for Linux
7 *
8 * gdth.h Copyright (C) 1995-06 ICP vortex, Achim Leubner
9 * See gdth.c for further informations and
10 * below for supported controller types
11 *
12 * <achim_leubner@adaptec.com>
13 *
14 * $Id: gdth.h,v 1.58 2006/01/11 16:14:09 achim Exp $
15 */
16
17#include <linux/types.h>
18
19#ifndef TRUE
20#define TRUE 1
21#endif
22#ifndef FALSE
23#define FALSE 0
24#endif
25
26/* defines, macros */
27
28/* driver version */
29#define GDTH_VERSION_STR "3.05"
30#define GDTH_VERSION 3
31#define GDTH_SUBVERSION 5
32
33/* protocol version */
34#define PROTOCOL_VERSION 1
35
36/* OEM IDs */
37#define OEM_ID_ICP 0x941c
38#define OEM_ID_INTEL 0x8000
39
40/* controller classes */
41#define GDT_PCI 0x03 /* PCI controller */
42#define GDT_PCINEW 0x04 /* new PCI controller */
43#define GDT_PCIMPR 0x05 /* PCI MPR controller */
44
45#ifndef PCI_DEVICE_ID_VORTEX_GDT60x0
46/* GDT_PCI */
47#define PCI_DEVICE_ID_VORTEX_GDT60x0 0 /* GDT6000/6020/6050 */
48#define PCI_DEVICE_ID_VORTEX_GDT6000B 1 /* GDT6000B/6010 */
49/* GDT_PCINEW */
50#define PCI_DEVICE_ID_VORTEX_GDT6x10 2 /* GDT6110/6510 */
51#define PCI_DEVICE_ID_VORTEX_GDT6x20 3 /* GDT6120/6520 */
52#define PCI_DEVICE_ID_VORTEX_GDT6530 4 /* GDT6530 */
53#define PCI_DEVICE_ID_VORTEX_GDT6550 5 /* GDT6550 */
54/* GDT_PCINEW, wide/ultra SCSI controllers */
55#define PCI_DEVICE_ID_VORTEX_GDT6x17 6 /* GDT6117/6517 */
56#define PCI_DEVICE_ID_VORTEX_GDT6x27 7 /* GDT6127/6527 */
57#define PCI_DEVICE_ID_VORTEX_GDT6537 8 /* GDT6537 */
58#define PCI_DEVICE_ID_VORTEX_GDT6557 9 /* GDT6557/6557-ECC */
59/* GDT_PCINEW, wide SCSI controllers */
60#define PCI_DEVICE_ID_VORTEX_GDT6x15 10 /* GDT6115/6515 */
61#define PCI_DEVICE_ID_VORTEX_GDT6x25 11 /* GDT6125/6525 */
62#define PCI_DEVICE_ID_VORTEX_GDT6535 12 /* GDT6535 */
63#define PCI_DEVICE_ID_VORTEX_GDT6555 13 /* GDT6555/6555-ECC */
64#endif
65
66#ifndef PCI_DEVICE_ID_VORTEX_GDT6x17RP
67/* GDT_MPR, RP series, wide/ultra SCSI */
68#define PCI_DEVICE_ID_VORTEX_GDT6x17RP 0x100 /* GDT6117RP/GDT6517RP */
69#define PCI_DEVICE_ID_VORTEX_GDT6x27RP 0x101 /* GDT6127RP/GDT6527RP */
70#define PCI_DEVICE_ID_VORTEX_GDT6537RP 0x102 /* GDT6537RP */
71#define PCI_DEVICE_ID_VORTEX_GDT6557RP 0x103 /* GDT6557RP */
72/* GDT_MPR, RP series, narrow/ultra SCSI */
73#define PCI_DEVICE_ID_VORTEX_GDT6x11RP 0x104 /* GDT6111RP/GDT6511RP */
74#define PCI_DEVICE_ID_VORTEX_GDT6x21RP 0x105 /* GDT6121RP/GDT6521RP */
75#endif
76#ifndef PCI_DEVICE_ID_VORTEX_GDT6x17RD
77/* GDT_MPR, RD series, wide/ultra SCSI */
78#define PCI_DEVICE_ID_VORTEX_GDT6x17RD 0x110 /* GDT6117RD/GDT6517RD */
79#define PCI_DEVICE_ID_VORTEX_GDT6x27RD 0x111 /* GDT6127RD/GDT6527RD */
80#define PCI_DEVICE_ID_VORTEX_GDT6537RD 0x112 /* GDT6537RD */
81#define PCI_DEVICE_ID_VORTEX_GDT6557RD 0x113 /* GDT6557RD */
82/* GDT_MPR, RD series, narrow/ultra SCSI */
83#define PCI_DEVICE_ID_VORTEX_GDT6x11RD 0x114 /* GDT6111RD/GDT6511RD */
84#define PCI_DEVICE_ID_VORTEX_GDT6x21RD 0x115 /* GDT6121RD/GDT6521RD */
85/* GDT_MPR, RD series, wide/ultra2 SCSI */
86#define PCI_DEVICE_ID_VORTEX_GDT6x18RD 0x118 /* GDT6118RD/GDT6518RD/
87 GDT6618RD */
88#define PCI_DEVICE_ID_VORTEX_GDT6x28RD 0x119 /* GDT6128RD/GDT6528RD/
89 GDT6628RD */
90#define PCI_DEVICE_ID_VORTEX_GDT6x38RD 0x11A /* GDT6538RD/GDT6638RD */
91#define PCI_DEVICE_ID_VORTEX_GDT6x58RD 0x11B /* GDT6558RD/GDT6658RD */
92/* GDT_MPR, RN series (64-bit PCI), wide/ultra2 SCSI */
93#define PCI_DEVICE_ID_VORTEX_GDT7x18RN 0x168 /* GDT7118RN/GDT7518RN/
94 GDT7618RN */
95#define PCI_DEVICE_ID_VORTEX_GDT7x28RN 0x169 /* GDT7128RN/GDT7528RN/
96 GDT7628RN */
97#define PCI_DEVICE_ID_VORTEX_GDT7x38RN 0x16A /* GDT7538RN/GDT7638RN */
98#define PCI_DEVICE_ID_VORTEX_GDT7x58RN 0x16B /* GDT7558RN/GDT7658RN */
99#endif
100
101#ifndef PCI_DEVICE_ID_VORTEX_GDT6x19RD
102/* GDT_MPR, RD series, Fibre Channel */
103#define PCI_DEVICE_ID_VORTEX_GDT6x19RD 0x210 /* GDT6519RD/GDT6619RD */
104#define PCI_DEVICE_ID_VORTEX_GDT6x29RD 0x211 /* GDT6529RD/GDT6629RD */
105/* GDT_MPR, RN series (64-bit PCI), Fibre Channel */
106#define PCI_DEVICE_ID_VORTEX_GDT7x19RN 0x260 /* GDT7519RN/GDT7619RN */
107#define PCI_DEVICE_ID_VORTEX_GDT7x29RN 0x261 /* GDT7529RN/GDT7629RN */
108#endif
109
110#ifndef PCI_DEVICE_ID_VORTEX_GDTMAXRP
111/* GDT_MPR, last device ID */
112#define PCI_DEVICE_ID_VORTEX_GDTMAXRP 0x2ff
113#endif
114
115#ifndef PCI_DEVICE_ID_VORTEX_GDTNEWRX
116/* new GDT Rx Controller */
117#define PCI_DEVICE_ID_VORTEX_GDTNEWRX 0x300
118#endif
119
120#ifndef PCI_DEVICE_ID_VORTEX_GDTNEWRX2
121/* new(2) GDT Rx Controller */
122#define PCI_DEVICE_ID_VORTEX_GDTNEWRX2 0x301
123#endif
124
125#ifndef PCI_DEVICE_ID_INTEL_SRC
126/* Intel Storage RAID Controller */
127#define PCI_DEVICE_ID_INTEL_SRC 0x600
128#endif
129
130#ifndef PCI_DEVICE_ID_INTEL_SRC_XSCALE
131/* Intel Storage RAID Controller */
132#define PCI_DEVICE_ID_INTEL_SRC_XSCALE 0x601
133#endif
134
135/* limits */
136#define GDTH_SCRATCH PAGE_SIZE /* 4KB scratch buffer */
137#define GDTH_MAXCMDS 120
138#define GDTH_MAXC_P_L 16 /* max. cmds per lun */
139#define GDTH_MAX_RAW 2 /* max. cmds per raw device */
140#define MAXOFFSETS 128
141#define MAXHA 16
142#define MAXID 127
143#define MAXLUN 8
144#define MAXBUS 6
145#define MAX_EVENTS 100 /* event buffer count */
146#define MAX_RES_ARGS 40 /* device reservation,
147 must be a multiple of 4 */
148#define MAXCYLS 1024
149#define HEADS 64
150#define SECS 32 /* mapping 64*32 */
151#define MEDHEADS 127
152#define MEDSECS 63 /* mapping 127*63 */
153#define BIGHEADS 255
154#define BIGSECS 63 /* mapping 255*63 */
155
156/* special command ptr. */
157#define UNUSED_CMND ((struct scsi_cmnd *)-1)
158#define INTERNAL_CMND ((struct scsi_cmnd *)-2)
159#define SCREEN_CMND ((struct scsi_cmnd *)-3)
160#define SPECIAL_SCP(p) (p==UNUSED_CMND || p==INTERNAL_CMND || p==SCREEN_CMND)
161
162/* controller services */
163#define SCSIRAWSERVICE 3
164#define CACHESERVICE 9
165#define SCREENSERVICE 11
166
167/* screenservice defines */
168#define MSG_INV_HANDLE -1 /* special message handle */
169#define MSGLEN 16 /* size of message text */
170#define MSG_SIZE 34 /* size of message structure */
171#define MSG_REQUEST 0 /* async. event: message */
172
173/* DPMEM constants */
174#define DPMEM_MAGIC 0xC0FFEE11
175#define IC_HEADER_BYTES 48
176#define IC_QUEUE_BYTES 4
177#define DPMEM_COMMAND_OFFSET IC_HEADER_BYTES+IC_QUEUE_BYTES*MAXOFFSETS
178
179/* cluster_type constants */
180#define CLUSTER_DRIVE 1
181#define CLUSTER_MOUNTED 2
182#define CLUSTER_RESERVED 4
183#define CLUSTER_RESERVE_STATE (CLUSTER_DRIVE|CLUSTER_MOUNTED|CLUSTER_RESERVED)
184
185/* commands for all services, cache service */
186#define GDT_INIT 0 /* service initialization */
187#define GDT_READ 1 /* read command */
188#define GDT_WRITE 2 /* write command */
189#define GDT_INFO 3 /* information about devices */
190#define GDT_FLUSH 4 /* flush dirty cache buffers */
191#define GDT_IOCTL 5 /* ioctl command */
192#define GDT_DEVTYPE 9 /* additional information */
193#define GDT_MOUNT 10 /* mount cache device */
194#define GDT_UNMOUNT 11 /* unmount cache device */
195#define GDT_SET_FEAT 12 /* set feat. (scatter/gather) */
196#define GDT_GET_FEAT 13 /* get features */
197#define GDT_WRITE_THR 16 /* write through */
198#define GDT_READ_THR 17 /* read through */
199#define GDT_EXT_INFO 18 /* extended info */
200#define GDT_RESET 19 /* controller reset */
201#define GDT_RESERVE_DRV 20 /* reserve host drive */
202#define GDT_RELEASE_DRV 21 /* release host drive */
203#define GDT_CLUST_INFO 22 /* cluster info */
204#define GDT_RW_ATTRIBS 23 /* R/W attribs (write thru,..)*/
205#define GDT_CLUST_RESET 24 /* releases the cluster drives*/
206#define GDT_FREEZE_IO 25 /* freezes all IOs */
207#define GDT_UNFREEZE_IO 26 /* unfreezes all IOs */
208#define GDT_X_INIT_HOST 29 /* ext. init: 64 bit support */
209#define GDT_X_INFO 30 /* ext. info for drives>2TB */
210
211/* raw service commands */
212#define GDT_RESERVE 14 /* reserve dev. to raw serv. */
213#define GDT_RELEASE 15 /* release device */
214#define GDT_RESERVE_ALL 16 /* reserve all devices */
215#define GDT_RELEASE_ALL 17 /* release all devices */
216#define GDT_RESET_BUS 18 /* reset bus */
217#define GDT_SCAN_START 19 /* start device scan */
218#define GDT_SCAN_END 20 /* stop device scan */
219#define GDT_X_INIT_RAW 21 /* ext. init: 64 bit support */
220
221/* screen service commands */
222#define GDT_REALTIME 3 /* realtime clock to screens. */
223#define GDT_X_INIT_SCR 4 /* ext. init: 64 bit support */
224
225/* IOCTL command defines */
226#define SCSI_DR_INFO 0x00 /* SCSI drive info */
227#define SCSI_CHAN_CNT 0x05 /* SCSI channel count */
228#define SCSI_DR_LIST 0x06 /* SCSI drive list */
229#define SCSI_DEF_CNT 0x15 /* grown/primary defects */
230#define DSK_STATISTICS 0x4b /* SCSI disk statistics */
231#define IOCHAN_DESC 0x5d /* description of IO channel */
232#define IOCHAN_RAW_DESC 0x5e /* description of raw IO chn. */
233#define L_CTRL_PATTERN 0x20000000L /* SCSI IOCTL mask */
234#define ARRAY_INFO 0x12 /* array drive info */
235#define ARRAY_DRV_LIST 0x0f /* array drive list */
236#define ARRAY_DRV_LIST2 0x34 /* array drive list (new) */
237#define LA_CTRL_PATTERN 0x10000000L /* array IOCTL mask */
238#define CACHE_DRV_CNT 0x01 /* cache drive count */
239#define CACHE_DRV_LIST 0x02 /* cache drive list */
240#define CACHE_INFO 0x04 /* cache info */
241#define CACHE_CONFIG 0x05 /* cache configuration */
242#define CACHE_DRV_INFO 0x07 /* cache drive info */
243#define BOARD_FEATURES 0x15 /* controller features */
244#define BOARD_INFO 0x28 /* controller info */
245#define SET_PERF_MODES 0x82 /* set mode (coalescing,..) */
246#define GET_PERF_MODES 0x83 /* get mode */
247#define CACHE_READ_OEM_STRING_RECORD 0x84 /* read OEM string record */
248#define HOST_GET 0x10001L /* get host drive list */
249#define IO_CHANNEL 0x00020000L /* default IO channel */
250#define INVALID_CHANNEL 0x0000ffffL /* invalid channel */
251
252/* service errors */
253#define S_OK 1 /* no error */
254#define S_GENERR 6 /* general error */
255#define S_BSY 7 /* controller busy */
256#define S_CACHE_UNKNOWN 12 /* cache serv.: drive unknown */
257#define S_RAW_SCSI 12 /* raw serv.: target error */
258#define S_RAW_ILL 0xff /* raw serv.: illegal */
259#define S_NOFUNC -2 /* unknown function */
260#define S_CACHE_RESERV -24 /* cache: reserv. conflict */
261
262/* timeout values */
263#define INIT_RETRIES 100000 /* 100000 * 1ms = 100s */
264#define INIT_TIMEOUT 100000 /* 100000 * 1ms = 100s */
265#define POLL_TIMEOUT 10000 /* 10000 * 1ms = 10s */
266
267/* priorities */
268#define DEFAULT_PRI 0x20
269#define IOCTL_PRI 0x10
270#define HIGH_PRI 0x08
271
272/* data directions */
273#define GDTH_DATA_IN 0x01000000L /* data from target */
274#define GDTH_DATA_OUT 0x00000000L /* data to target */
275
276/* other defines */
277#define LINUX_OS 8 /* used for cache optim. */
278#define SECS32 0x1f /* round capacity */
279#define BIOS_ID_OFFS 0x10 /* offset contr-ID in ISABIOS */
280#define LOCALBOARD 0 /* board node always 0 */
281#define ASYNCINDEX 0 /* cmd index async. event */
282#define SPEZINDEX 1 /* cmd index unknown service */
283#define COALINDEX (GDTH_MAXCMDS + 2)
284
285/* features */
286#define SCATTER_GATHER 1 /* s/g feature */
287#define GDT_WR_THROUGH 0x100 /* WRITE_THROUGH supported */
288#define GDT_64BIT 0x200 /* 64bit / drv>2TB support */
289
290#include "gdth_ioctl.h"
291
292/* screenservice message */
293typedef struct {
294 u32 msg_handle; /* message handle */
295 u32 msg_len; /* size of message */
296 u32 msg_alen; /* answer length */
297 u8 msg_answer; /* answer flag */
298 u8 msg_ext; /* more messages */
299 u8 msg_reserved[2];
300 char msg_text[MSGLEN+2]; /* the message text */
301} __attribute__((packed)) gdth_msg_str;
302
303
304/* IOCTL data structures */
305
306/* Status coalescing buffer for returning multiple requests per interrupt */
307typedef struct {
308 u32 status;
309 u32 ext_status;
310 u32 info0;
311 u32 info1;
312} __attribute__((packed)) gdth_coal_status;
313
314/* performance mode data structure */
315typedef struct {
316 u32 version; /* The version of this IOCTL structure. */
317 u32 st_mode; /* 0=dis., 1=st_buf_addr1 valid, 2=both */
318 u32 st_buff_addr1; /* physical address of status buffer 1 */
319 u32 st_buff_u_addr1; /* reserved for 64 bit addressing */
320 u32 st_buff_indx1; /* reserved command idx. for this buffer */
321 u32 st_buff_addr2; /* physical address of status buffer 1 */
322 u32 st_buff_u_addr2; /* reserved for 64 bit addressing */
323 u32 st_buff_indx2; /* reserved command idx. for this buffer */
324 u32 st_buff_size; /* size of each buffer in bytes */
325 u32 cmd_mode; /* 0 = mode disabled, 1 = cmd_buff_addr1 */
326 u32 cmd_buff_addr1; /* physical address of cmd buffer 1 */
327 u32 cmd_buff_u_addr1; /* reserved for 64 bit addressing */
328 u32 cmd_buff_indx1; /* cmd buf addr1 unique identifier */
329 u32 cmd_buff_addr2; /* physical address of cmd buffer 1 */
330 u32 cmd_buff_u_addr2; /* reserved for 64 bit addressing */
331 u32 cmd_buff_indx2; /* cmd buf addr1 unique identifier */
332 u32 cmd_buff_size; /* size of each cmd buffer in bytes */
333 u32 reserved1;
334 u32 reserved2;
335} __attribute__((packed)) gdth_perf_modes;
336
337/* SCSI drive info */
338typedef struct {
339 u8 vendor[8]; /* vendor string */
340 u8 product[16]; /* product string */
341 u8 revision[4]; /* revision */
342 u32 sy_rate; /* current rate for sync. tr. */
343 u32 sy_max_rate; /* max. rate for sync. tr. */
344 u32 no_ldrive; /* belongs to this log. drv.*/
345 u32 blkcnt; /* number of blocks */
346 u16 blksize; /* size of block in bytes */
347 u8 available; /* flag: access is available */
348 u8 init; /* medium is initialized */
349 u8 devtype; /* SCSI devicetype */
350 u8 rm_medium; /* medium is removable */
351 u8 wp_medium; /* medium is write protected */
352 u8 ansi; /* SCSI I/II or III? */
353 u8 protocol; /* same as ansi */
354 u8 sync; /* flag: sync. transfer enab. */
355 u8 disc; /* flag: disconnect enabled */
356 u8 queueing; /* flag: command queing enab. */
357 u8 cached; /* flag: caching enabled */
358 u8 target_id; /* target ID of device */
359 u8 lun; /* LUN id of device */
360 u8 orphan; /* flag: drive fragment */
361 u32 last_error; /* sense key or drive state */
362 u32 last_result; /* result of last command */
363 u32 check_errors; /* err. in last surface check */
364 u8 percent; /* progress for surface check */
365 u8 last_check; /* IOCTRL operation */
366 u8 res[2];
367 u32 flags; /* from 1.19/2.19: raw reserv.*/
368 u8 multi_bus; /* multi bus dev? (fibre ch.) */
369 u8 mb_status; /* status: available? */
370 u8 res2[2];
371 u8 mb_alt_status; /* status on second bus */
372 u8 mb_alt_bid; /* number of second bus */
373 u8 mb_alt_tid; /* target id on second bus */
374 u8 res3;
375 u8 fc_flag; /* from 1.22/2.22: info valid?*/
376 u8 res4;
377 u16 fc_frame_size; /* frame size (bytes) */
378 char wwn[8]; /* world wide name */
379} __attribute__((packed)) gdth_diskinfo_str;
380
381/* get SCSI channel count */
382typedef struct {
383 u32 channel_no; /* number of channel */
384 u32 drive_cnt; /* drive count */
385 u8 siop_id; /* SCSI processor ID */
386 u8 siop_state; /* SCSI processor state */
387} __attribute__((packed)) gdth_getch_str;
388
389/* get SCSI drive numbers */
390typedef struct {
391 u32 sc_no; /* SCSI channel */
392 u32 sc_cnt; /* sc_list[] elements */
393 u32 sc_list[MAXID]; /* minor device numbers */
394} __attribute__((packed)) gdth_drlist_str;
395
396/* get grown/primary defect count */
397typedef struct {
398 u8 sddc_type; /* 0x08: grown, 0x10: prim. */
399 u8 sddc_format; /* list entry format */
400 u8 sddc_len; /* list entry length */
401 u8 sddc_res;
402 u32 sddc_cnt; /* entry count */
403} __attribute__((packed)) gdth_defcnt_str;
404
405/* disk statistics */
406typedef struct {
407 u32 bid; /* SCSI channel */
408 u32 first; /* first SCSI disk */
409 u32 entries; /* number of elements */
410 u32 count; /* (R) number of init. el. */
411 u32 mon_time; /* time stamp */
412 struct {
413 u8 tid; /* target ID */
414 u8 lun; /* LUN */
415 u8 res[2];
416 u32 blk_size; /* block size in bytes */
417 u32 rd_count; /* bytes read */
418 u32 wr_count; /* bytes written */
419 u32 rd_blk_count; /* blocks read */
420 u32 wr_blk_count; /* blocks written */
421 u32 retries; /* retries */
422 u32 reassigns; /* reassigns */
423 } __attribute__((packed)) list[1];
424} __attribute__((packed)) gdth_dskstat_str;
425
426/* IO channel header */
427typedef struct {
428 u32 version; /* version (-1UL: newest) */
429 u8 list_entries; /* list entry count */
430 u8 first_chan; /* first channel number */
431 u8 last_chan; /* last channel number */
432 u8 chan_count; /* (R) channel count */
433 u32 list_offset; /* offset of list[0] */
434} __attribute__((packed)) gdth_iochan_header;
435
436/* get IO channel description */
437typedef struct {
438 gdth_iochan_header hdr;
439 struct {
440 u32 address; /* channel address */
441 u8 type; /* type (SCSI, FCAL) */
442 u8 local_no; /* local number */
443 u16 features; /* channel features */
444 } __attribute__((packed)) list[MAXBUS];
445} __attribute__((packed)) gdth_iochan_str;
446
447/* get raw IO channel description */
448typedef struct {
449 gdth_iochan_header hdr;
450 struct {
451 u8 proc_id; /* processor id */
452 u8 proc_defect; /* defect ? */
453 u8 reserved[2];
454 } __attribute__((packed)) list[MAXBUS];
455} __attribute__((packed)) gdth_raw_iochan_str;
456
457/* array drive component */
458typedef struct {
459 u32 al_controller; /* controller ID */
460 u8 al_cache_drive; /* cache drive number */
461 u8 al_status; /* cache drive state */
462 u8 al_res[2];
463} __attribute__((packed)) gdth_arraycomp_str;
464
465/* array drive information */
466typedef struct {
467 u8 ai_type; /* array type (RAID0,4,5) */
468 u8 ai_cache_drive_cnt; /* active cachedrives */
469 u8 ai_state; /* array drive state */
470 u8 ai_master_cd; /* master cachedrive */
471 u32 ai_master_controller; /* ID of master controller */
472 u32 ai_size; /* user capacity [sectors] */
473 u32 ai_striping_size; /* striping size [sectors] */
474 u32 ai_secsize; /* sector size [bytes] */
475 u32 ai_err_info; /* failed cache drive */
476 u8 ai_name[8]; /* name of the array drive */
477 u8 ai_controller_cnt; /* number of controllers */
478 u8 ai_removable; /* flag: removable */
479 u8 ai_write_protected; /* flag: write protected */
480 u8 ai_devtype; /* type: always direct access */
481 gdth_arraycomp_str ai_drives[35]; /* drive components: */
482 u8 ai_drive_entries; /* number of drive components */
483 u8 ai_protected; /* protection flag */
484 u8 ai_verify_state; /* state of a parity verify */
485 u8 ai_ext_state; /* extended array drive state */
486 u8 ai_expand_state; /* array expand state (>=2.18)*/
487 u8 ai_reserved[3];
488} __attribute__((packed)) gdth_arrayinf_str;
489
490/* get array drive list */
491typedef struct {
492 u32 controller_no; /* controller no. */
493 u8 cd_handle; /* master cachedrive */
494 u8 is_arrayd; /* Flag: is array drive? */
495 u8 is_master; /* Flag: is array master? */
496 u8 is_parity; /* Flag: is parity drive? */
497 u8 is_hotfix; /* Flag: is hotfix drive? */
498 u8 res[3];
499} __attribute__((packed)) gdth_alist_str;
500
501typedef struct {
502 u32 entries_avail; /* allocated entries */
503 u32 entries_init; /* returned entries */
504 u32 first_entry; /* first entry number */
505 u32 list_offset; /* offset of following list */
506 gdth_alist_str list[1]; /* list */
507} __attribute__((packed)) gdth_arcdl_str;
508
509/* cache info/config IOCTL */
510typedef struct {
511 u32 version; /* firmware version */
512 u16 state; /* cache state (on/off) */
513 u16 strategy; /* cache strategy */
514 u16 write_back; /* write back state (on/off) */
515 u16 block_size; /* cache block size */
516} __attribute__((packed)) gdth_cpar_str;
517
518typedef struct {
519 u32 csize; /* cache size */
520 u32 read_cnt; /* read/write counter */
521 u32 write_cnt;
522 u32 tr_hits; /* hits */
523 u32 sec_hits;
524 u32 sec_miss; /* misses */
525} __attribute__((packed)) gdth_cstat_str;
526
527typedef struct {
528 gdth_cpar_str cpar;
529 gdth_cstat_str cstat;
530} __attribute__((packed)) gdth_cinfo_str;
531
532/* cache drive info */
533typedef struct {
534 u8 cd_name[8]; /* cache drive name */
535 u32 cd_devtype; /* SCSI devicetype */
536 u32 cd_ldcnt; /* number of log. drives */
537 u32 cd_last_error; /* last error */
538 u8 cd_initialized; /* drive is initialized */
539 u8 cd_removable; /* media is removable */
540 u8 cd_write_protected; /* write protected */
541 u8 cd_flags; /* Pool Hot Fix? */
542 u32 ld_blkcnt; /* number of blocks */
543 u32 ld_blksize; /* blocksize */
544 u32 ld_dcnt; /* number of disks */
545 u32 ld_slave; /* log. drive index */
546 u32 ld_dtype; /* type of logical drive */
547 u32 ld_last_error; /* last error */
548 u8 ld_name[8]; /* log. drive name */
549 u8 ld_error; /* error */
550} __attribute__((packed)) gdth_cdrinfo_str;
551
552/* OEM string */
553typedef struct {
554 u32 ctl_version;
555 u32 file_major_version;
556 u32 file_minor_version;
557 u32 buffer_size;
558 u32 cpy_count;
559 u32 ext_error;
560 u32 oem_id;
561 u32 board_id;
562} __attribute__((packed)) gdth_oem_str_params;
563
564typedef struct {
565 u8 product_0_1_name[16];
566 u8 product_4_5_name[16];
567 u8 product_cluster_name[16];
568 u8 product_reserved[16];
569 u8 scsi_cluster_target_vendor_id[16];
570 u8 cluster_raid_fw_name[16];
571 u8 oem_brand_name[16];
572 u8 oem_raid_type[16];
573 u8 bios_type[13];
574 u8 bios_title[50];
575 u8 oem_company_name[37];
576 u32 pci_id_1;
577 u32 pci_id_2;
578 u8 validation_status[80];
579 u8 reserved_1[4];
580 u8 scsi_host_drive_inquiry_vendor_id[16];
581 u8 library_file_template[16];
582 u8 reserved_2[16];
583 u8 tool_name_1[32];
584 u8 tool_name_2[32];
585 u8 tool_name_3[32];
586 u8 oem_contact_1[84];
587 u8 oem_contact_2[84];
588 u8 oem_contact_3[84];
589} __attribute__((packed)) gdth_oem_str;
590
591typedef struct {
592 gdth_oem_str_params params;
593 gdth_oem_str text;
594} __attribute__((packed)) gdth_oem_str_ioctl;
595
596/* board features */
597typedef struct {
598 u8 chaining; /* Chaining supported */
599 u8 striping; /* Striping (RAID-0) supp. */
600 u8 mirroring; /* Mirroring (RAID-1) supp. */
601 u8 raid; /* RAID-4/5/10 supported */
602} __attribute__((packed)) gdth_bfeat_str;
603
604/* board info IOCTL */
605typedef struct {
606 u32 ser_no; /* serial no. */
607 u8 oem_id[2]; /* OEM ID */
608 u16 ep_flags; /* eprom flags */
609 u32 proc_id; /* processor ID */
610 u32 memsize; /* memory size (bytes) */
611 u8 mem_banks; /* memory banks */
612 u8 chan_type; /* channel type */
613 u8 chan_count; /* channel count */
614 u8 rdongle_pres; /* dongle present? */
615 u32 epr_fw_ver; /* (eprom) firmware version */
616 u32 upd_fw_ver; /* (update) firmware version */
617 u32 upd_revision; /* update revision */
618 char type_string[16]; /* controller name */
619 char raid_string[16]; /* RAID firmware name */
620 u8 update_pres; /* update present? */
621 u8 xor_pres; /* XOR engine present? */
622 u8 prom_type; /* ROM type (eprom/flash) */
623 u8 prom_count; /* number of ROM devices */
624 u32 dup_pres; /* duplexing module present? */
625 u32 chan_pres; /* number of expansion chn. */
626 u32 mem_pres; /* memory expansion inst. ? */
627 u8 ft_bus_system; /* fault bus supported? */
628 u8 subtype_valid; /* board_subtype valid? */
629 u8 board_subtype; /* subtype/hardware level */
630 u8 ramparity_pres; /* RAM parity check hardware? */
631} __attribute__((packed)) gdth_binfo_str;
632
633/* get host drive info */
634typedef struct {
635 char name[8]; /* host drive name */
636 u32 size; /* size (sectors) */
637 u8 host_drive; /* host drive number */
638 u8 log_drive; /* log. drive (master) */
639 u8 reserved;
640 u8 rw_attribs; /* r/w attribs */
641 u32 start_sec; /* start sector */
642} __attribute__((packed)) gdth_hentry_str;
643
644typedef struct {
645 u32 entries; /* entry count */
646 u32 offset; /* offset of entries */
647 u8 secs_p_head; /* sectors/head */
648 u8 heads_p_cyl; /* heads/cylinder */
649 u8 reserved;
650 u8 clust_drvtype; /* cluster drive type */
651 u32 location; /* controller number */
652 gdth_hentry_str entry[MAX_HDRIVES]; /* entries */
653} __attribute__((packed)) gdth_hget_str;
654
655
656/* DPRAM structures */
657
658/* interface area ISA/PCI */
659typedef struct {
660 u8 S_Cmd_Indx; /* special command */
661 u8 volatile S_Status; /* status special command */
662 u16 reserved1;
663 u32 S_Info[4]; /* add. info special command */
664 u8 volatile Sema0; /* command semaphore */
665 u8 reserved2[3];
666 u8 Cmd_Index; /* command number */
667 u8 reserved3[3];
668 u16 volatile Status; /* command status */
669 u16 Service; /* service(for async.events) */
670 u32 Info[2]; /* additional info */
671 struct {
672 u16 offset; /* command offs. in the DPRAM*/
673 u16 serv_id; /* service */
674 } __attribute__((packed)) comm_queue[MAXOFFSETS]; /* command queue */
675 u32 bios_reserved[2];
676 u8 gdt_dpr_cmd[1]; /* commands */
677} __attribute__((packed)) gdt_dpr_if;
678
679/* SRAM structure PCI controllers */
680typedef struct {
681 u32 magic; /* controller ID from BIOS */
682 u16 need_deinit; /* switch betw. BIOS/driver */
683 u8 switch_support; /* see need_deinit */
684 u8 padding[9];
685 u8 os_used[16]; /* OS code per service */
686 u8 unused[28];
687 u8 fw_magic; /* contr. ID from firmware */
688} __attribute__((packed)) gdt_pci_sram;
689
690/* DPRAM ISA controllers */
691typedef struct {
692 union {
693 struct {
694 u8 bios_used[0x3c00-32]; /* 15KB - 32Bytes BIOS */
695 u16 need_deinit; /* switch betw. BIOS/driver */
696 u8 switch_support; /* see need_deinit */
697 u8 padding[9];
698 u8 os_used[16]; /* OS code per service */
699 } __attribute__((packed)) dp_sram;
700 u8 bios_area[0x4000]; /* 16KB reserved for BIOS */
701 } bu;
702 union {
703 gdt_dpr_if ic; /* interface area */
704 u8 if_area[0x3000]; /* 12KB for interface */
705 } u;
706 struct {
707 u8 memlock; /* write protection DPRAM */
708 u8 event; /* release event */
709 u8 irqen; /* board interrupts enable */
710 u8 irqdel; /* acknowledge board int. */
711 u8 volatile Sema1; /* status semaphore */
712 u8 rq; /* IRQ/DRQ configuration */
713 } __attribute__((packed)) io;
714} __attribute__((packed)) gdt2_dpram_str;
715
716/* DPRAM PCI controllers */
717typedef struct {
718 union {
719 gdt_dpr_if ic; /* interface area */
720 u8 if_area[0xff0-sizeof(gdt_pci_sram)];
721 } u;
722 gdt_pci_sram gdt6sr; /* SRAM structure */
723 struct {
724 u8 unused0[1];
725 u8 volatile Sema1; /* command semaphore */
726 u8 unused1[3];
727 u8 irqen; /* board interrupts enable */
728 u8 unused2[2];
729 u8 event; /* release event */
730 u8 unused3[3];
731 u8 irqdel; /* acknowledge board int. */
732 u8 unused4[3];
733 } __attribute__((packed)) io;
734} __attribute__((packed)) gdt6_dpram_str;
735
736/* PLX register structure (new PCI controllers) */
737typedef struct {
738 u8 cfg_reg; /* DPRAM cfg.(2:below 1MB,0:anywhere)*/
739 u8 unused1[0x3f];
740 u8 volatile sema0_reg; /* command semaphore */
741 u8 volatile sema1_reg; /* status semaphore */
742 u8 unused2[2];
743 u16 volatile status; /* command status */
744 u16 service; /* service */
745 u32 info[2]; /* additional info */
746 u8 unused3[0x10];
747 u8 ldoor_reg; /* PCI to local doorbell */
748 u8 unused4[3];
749 u8 volatile edoor_reg; /* local to PCI doorbell */
750 u8 unused5[3];
751 u8 control0; /* control0 register(unused) */
752 u8 control1; /* board interrupts enable */
753 u8 unused6[0x16];
754} __attribute__((packed)) gdt6c_plx_regs;
755
756/* DPRAM new PCI controllers */
757typedef struct {
758 union {
759 gdt_dpr_if ic; /* interface area */
760 u8 if_area[0x4000-sizeof(gdt_pci_sram)];
761 } u;
762 gdt_pci_sram gdt6sr; /* SRAM structure */
763} __attribute__((packed)) gdt6c_dpram_str;
764
765/* i960 register structure (PCI MPR controllers) */
766typedef struct {
767 u8 unused1[16];
768 u8 volatile sema0_reg; /* command semaphore */
769 u8 unused2;
770 u8 volatile sema1_reg; /* status semaphore */
771 u8 unused3;
772 u16 volatile status; /* command status */
773 u16 service; /* service */
774 u32 info[2]; /* additional info */
775 u8 ldoor_reg; /* PCI to local doorbell */
776 u8 unused4[11];
777 u8 volatile edoor_reg; /* local to PCI doorbell */
778 u8 unused5[7];
779 u8 edoor_en_reg; /* board interrupts enable */
780 u8 unused6[27];
781 u32 unused7[939];
782 u32 severity;
783 char evt_str[256]; /* event string */
784} __attribute__((packed)) gdt6m_i960_regs;
785
786/* DPRAM PCI MPR controllers */
787typedef struct {
788 gdt6m_i960_regs i960r; /* 4KB i960 registers */
789 union {
790 gdt_dpr_if ic; /* interface area */
791 u8 if_area[0x3000-sizeof(gdt_pci_sram)];
792 } u;
793 gdt_pci_sram gdt6sr; /* SRAM structure */
794} __attribute__((packed)) gdt6m_dpram_str;
795
796
797/* PCI resources */
798typedef struct {
799 struct pci_dev *pdev;
800 unsigned long dpmem; /* DPRAM address */
801 unsigned long io; /* IO address */
802} gdth_pci_str;
803
804
805/* controller information structure */
806typedef struct {
807 struct Scsi_Host *shost;
808 struct list_head list;
809 u16 hanum;
810 u16 oem_id; /* OEM */
811 u16 type; /* controller class */
812 u32 stype; /* subtype (PCI: device ID) */
813 u16 fw_vers; /* firmware version */
814 u16 cache_feat; /* feat. cache serv. (s/g,..)*/
815 u16 raw_feat; /* feat. raw service (s/g,..)*/
816 u16 screen_feat; /* feat. raw service (s/g,..)*/
817 void __iomem *brd; /* DPRAM address */
818 u32 brd_phys; /* slot number/BIOS address */
819 gdt6c_plx_regs *plx; /* PLX regs (new PCI contr.) */
820 gdth_cmd_str cmdext;
821 gdth_cmd_str *pccb; /* address command structure */
822 u32 ccb_phys; /* phys. address */
823#ifdef INT_COAL
824 gdth_coal_status *coal_stat; /* buffer for coalescing int.*/
825 u64 coal_stat_phys; /* phys. address */
826#endif
827 char *pscratch; /* scratch (DMA) buffer */
828 u64 scratch_phys; /* phys. address */
829 u8 scratch_busy; /* in use? */
830 u8 dma64_support; /* 64-bit DMA supported? */
831 gdth_msg_str *pmsg; /* message buffer */
832 u64 msg_phys; /* phys. address */
833 u8 scan_mode; /* current scan mode */
834 u8 irq; /* IRQ */
835 u8 drq; /* DRQ (ISA controllers) */
836 u16 status; /* command status */
837 u16 service; /* service/firmware ver./.. */
838 u32 info;
839 u32 info2; /* additional info */
840 struct scsi_cmnd *req_first; /* top of request queue */
841 struct {
842 u8 present; /* Flag: host drive present? */
843 u8 is_logdrv; /* Flag: log. drive (master)? */
844 u8 is_arraydrv; /* Flag: array drive? */
845 u8 is_master; /* Flag: array drive master? */
846 u8 is_parity; /* Flag: parity drive? */
847 u8 is_hotfix; /* Flag: hotfix drive? */
848 u8 master_no; /* number of master drive */
849 u8 lock; /* drive locked? (hot plug) */
850 u8 heads; /* mapping */
851 u8 secs;
852 u16 devtype; /* further information */
853 u64 size; /* capacity */
854 u8 ldr_no; /* log. drive no. */
855 u8 rw_attribs; /* r/w attributes */
856 u8 cluster_type; /* cluster properties */
857 u8 media_changed; /* Flag:MOUNT/UNMOUNT occurred */
858 u32 start_sec; /* start sector */
859 } hdr[MAX_LDRIVES]; /* host drives */
860 struct {
861 u8 lock; /* channel locked? (hot plug) */
862 u8 pdev_cnt; /* physical device count */
863 u8 local_no; /* local channel number */
864 u8 io_cnt[MAXID]; /* current IO count */
865 u32 address; /* channel address */
866 u32 id_list[MAXID]; /* IDs of the phys. devices */
867 } raw[MAXBUS]; /* SCSI channels */
868 struct {
869 struct scsi_cmnd *cmnd; /* pending request */
870 u16 service; /* service */
871 } cmd_tab[GDTH_MAXCMDS]; /* table of pend. requests */
872 struct gdth_cmndinfo { /* per-command private info */
873 int index;
874 int internal_command; /* don't call scsi_done */
875 gdth_cmd_str *internal_cmd_str; /* crier for internal messages*/
876 dma_addr_t sense_paddr; /* sense dma-addr */
877 u8 priority;
878 int timeout_count; /* # of timeout calls */
879 volatile int wait_for_completion;
880 u16 status;
881 u32 info;
882 enum dma_data_direction dma_dir;
883 int phase; /* ???? */
884 int OpCode;
885 } cmndinfo[GDTH_MAXCMDS]; /* index==0 is free */
886 u8 bus_cnt; /* SCSI bus count */
887 u8 tid_cnt; /* Target ID count */
888 u8 bus_id[MAXBUS]; /* IOP IDs */
889 u8 virt_bus; /* number of virtual bus */
890 u8 more_proc; /* more /proc info supported */
891 u16 cmd_cnt; /* command count in DPRAM */
892 u16 cmd_len; /* length of actual command */
893 u16 cmd_offs_dpmem; /* actual offset in DPRAM */
894 u16 ic_all_size; /* sizeof DPRAM interf. area */
895 gdth_cpar_str cpar; /* controller cache par. */
896 gdth_bfeat_str bfeat; /* controller features */
897 gdth_binfo_str binfo; /* controller info */
898 gdth_evt_data dvr; /* event structure */
899 spinlock_t smp_lock;
900 struct pci_dev *pdev;
901 char oem_name[8];
902#ifdef GDTH_DMA_STATISTICS
903 unsigned long dma32_cnt, dma64_cnt; /* statistics: DMA buffer */
904#endif
905 struct scsi_device *sdev;
906} gdth_ha_str;
907
908static inline struct gdth_cmndinfo *gdth_cmnd_priv(struct scsi_cmnd* cmd)
909{
910 return (struct gdth_cmndinfo *)cmd->host_scribble;
911}
912
913/* INQUIRY data format */
914typedef struct {
915 u8 type_qual;
916 u8 modif_rmb;
917 u8 version;
918 u8 resp_aenc;
919 u8 add_length;
920 u8 reserved1;
921 u8 reserved2;
922 u8 misc;
923 u8 vendor[8];
924 u8 product[16];
925 u8 revision[4];
926} __attribute__((packed)) gdth_inq_data;
927
928/* READ_CAPACITY data format */
929typedef struct {
930 u32 last_block_no;
931 u32 block_length;
932} __attribute__((packed)) gdth_rdcap_data;
933
934/* READ_CAPACITY (16) data format */
935typedef struct {
936 u64 last_block_no;
937 u32 block_length;
938} __attribute__((packed)) gdth_rdcap16_data;
939
940/* REQUEST_SENSE data format */
941typedef struct {
942 u8 errorcode;
943 u8 segno;
944 u8 key;
945 u32 info;
946 u8 add_length;
947 u32 cmd_info;
948 u8 adsc;
949 u8 adsq;
950 u8 fruc;
951 u8 key_spec[3];
952} __attribute__((packed)) gdth_sense_data;
953
954/* MODE_SENSE data format */
955typedef struct {
956 struct {
957 u8 data_length;
958 u8 med_type;
959 u8 dev_par;
960 u8 bd_length;
961 } __attribute__((packed)) hd;
962 struct {
963 u8 dens_code;
964 u8 block_count[3];
965 u8 reserved;
966 u8 block_length[3];
967 } __attribute__((packed)) bd;
968} __attribute__((packed)) gdth_modep_data;
969
970/* stack frame */
971typedef struct {
972 unsigned long b[10]; /* 32/64 bit compiler ! */
973} __attribute__((packed)) gdth_stackframe;
974
975
976/* function prototyping */
977
978int gdth_show_info(struct seq_file *, struct Scsi_Host *);
979int gdth_set_info(struct Scsi_Host *, char *, int);
980
981#endif
982