1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2 | /* |
3 | * Copyright (c) 2015 Linaro Ltd. |
4 | * Copyright (c) 2015 Hisilicon Limited. |
5 | */ |
6 | |
7 | #include "hisi_sas.h" |
8 | #define DRV_NAME "hisi_sas_v1_hw" |
9 | |
10 | /* global registers need init*/ |
11 | #define DLVRY_QUEUE_ENABLE 0x0 |
12 | #define IOST_BASE_ADDR_LO 0x8 |
13 | #define IOST_BASE_ADDR_HI 0xc |
14 | #define ITCT_BASE_ADDR_LO 0x10 |
15 | #define ITCT_BASE_ADDR_HI 0x14 |
16 | #define BROKEN_MSG_ADDR_LO 0x18 |
17 | #define BROKEN_MSG_ADDR_HI 0x1c |
18 | #define PHY_CONTEXT 0x20 |
19 | #define PHY_STATE 0x24 |
20 | #define PHY_PORT_NUM_MA 0x28 |
21 | #define PORT_STATE 0x2c |
22 | #define PHY_CONN_RATE 0x30 |
23 | #define HGC_TRANS_TASK_CNT_LIMIT 0x38 |
24 | #define AXI_AHB_CLK_CFG 0x3c |
25 | #define HGC_SAS_TXFAIL_RETRY_CTRL 0x84 |
26 | #define HGC_GET_ITV_TIME 0x90 |
27 | #define DEVICE_MSG_WORK_MODE 0x94 |
28 | #define I_T_NEXUS_LOSS_TIME 0xa0 |
29 | #define BUS_INACTIVE_LIMIT_TIME 0xa8 |
30 | #define REJECT_TO_OPEN_LIMIT_TIME 0xac |
31 | #define CFG_AGING_TIME 0xbc |
32 | #define CFG_AGING_TIME_ITCT_REL_OFF 0 |
33 | #define CFG_AGING_TIME_ITCT_REL_MSK (0x1 << CFG_AGING_TIME_ITCT_REL_OFF) |
34 | #define HGC_DFX_CFG2 0xc0 |
35 | #define FIS_LIST_BADDR_L 0xc4 |
36 | #define CFG_1US_TIMER_TRSH 0xcc |
37 | #define CFG_SAS_CONFIG 0xd4 |
38 | #define HGC_IOST_ECC_ADDR 0x140 |
39 | #define HGC_IOST_ECC_ADDR_BAD_OFF 16 |
40 | #define HGC_IOST_ECC_ADDR_BAD_MSK (0x3ff << HGC_IOST_ECC_ADDR_BAD_OFF) |
41 | #define HGC_DQ_ECC_ADDR 0x144 |
42 | #define HGC_DQ_ECC_ADDR_BAD_OFF 16 |
43 | #define HGC_DQ_ECC_ADDR_BAD_MSK (0xfff << HGC_DQ_ECC_ADDR_BAD_OFF) |
44 | #define HGC_INVLD_DQE_INFO 0x148 |
45 | #define HGC_INVLD_DQE_INFO_DQ_OFF 0 |
46 | #define HGC_INVLD_DQE_INFO_DQ_MSK (0xffff << HGC_INVLD_DQE_INFO_DQ_OFF) |
47 | #define HGC_INVLD_DQE_INFO_TYPE_OFF 16 |
48 | #define HGC_INVLD_DQE_INFO_TYPE_MSK (0x1 << HGC_INVLD_DQE_INFO_TYPE_OFF) |
49 | #define HGC_INVLD_DQE_INFO_FORCE_OFF 17 |
50 | #define HGC_INVLD_DQE_INFO_FORCE_MSK (0x1 << HGC_INVLD_DQE_INFO_FORCE_OFF) |
51 | #define HGC_INVLD_DQE_INFO_PHY_OFF 18 |
52 | #define HGC_INVLD_DQE_INFO_PHY_MSK (0x1 << HGC_INVLD_DQE_INFO_PHY_OFF) |
53 | #define HGC_INVLD_DQE_INFO_ABORT_OFF 19 |
54 | #define HGC_INVLD_DQE_INFO_ABORT_MSK (0x1 << HGC_INVLD_DQE_INFO_ABORT_OFF) |
55 | #define HGC_INVLD_DQE_INFO_IPTT_OF_OFF 20 |
56 | #define HGC_INVLD_DQE_INFO_IPTT_OF_MSK (0x1 << HGC_INVLD_DQE_INFO_IPTT_OF_OFF) |
57 | #define HGC_INVLD_DQE_INFO_SSP_ERR_OFF 21 |
58 | #define HGC_INVLD_DQE_INFO_SSP_ERR_MSK (0x1 << HGC_INVLD_DQE_INFO_SSP_ERR_OFF) |
59 | #define HGC_INVLD_DQE_INFO_OFL_OFF 22 |
60 | #define HGC_INVLD_DQE_INFO_OFL_MSK (0x1 << HGC_INVLD_DQE_INFO_OFL_OFF) |
61 | #define HGC_ITCT_ECC_ADDR 0x150 |
62 | #define HGC_ITCT_ECC_ADDR_BAD_OFF 16 |
63 | #define HGC_ITCT_ECC_ADDR_BAD_MSK (0x3ff << HGC_ITCT_ECC_ADDR_BAD_OFF) |
64 | #define HGC_AXI_FIFO_ERR_INFO 0x154 |
65 | #define INT_COAL_EN 0x1bc |
66 | #define OQ_INT_COAL_TIME 0x1c0 |
67 | #define OQ_INT_COAL_CNT 0x1c4 |
68 | #define ENT_INT_COAL_TIME 0x1c8 |
69 | #define ENT_INT_COAL_CNT 0x1cc |
70 | #define OQ_INT_SRC 0x1d0 |
71 | #define OQ_INT_SRC_MSK 0x1d4 |
72 | #define ENT_INT_SRC1 0x1d8 |
73 | #define ENT_INT_SRC2 0x1dc |
74 | #define ENT_INT_SRC2_DQ_CFG_ERR_OFF 25 |
75 | #define ENT_INT_SRC2_DQ_CFG_ERR_MSK (0x1 << ENT_INT_SRC2_DQ_CFG_ERR_OFF) |
76 | #define ENT_INT_SRC2_CQ_CFG_ERR_OFF 27 |
77 | #define ENT_INT_SRC2_CQ_CFG_ERR_MSK (0x1 << ENT_INT_SRC2_CQ_CFG_ERR_OFF) |
78 | #define ENT_INT_SRC2_AXI_WRONG_INT_OFF 28 |
79 | #define ENT_INT_SRC2_AXI_WRONG_INT_MSK (0x1 << ENT_INT_SRC2_AXI_WRONG_INT_OFF) |
80 | #define ENT_INT_SRC2_AXI_OVERLF_INT_OFF 29 |
81 | #define ENT_INT_SRC2_AXI_OVERLF_INT_MSK (0x1 << ENT_INT_SRC2_AXI_OVERLF_INT_OFF) |
82 | #define ENT_INT_SRC_MSK1 0x1e0 |
83 | #define ENT_INT_SRC_MSK2 0x1e4 |
84 | #define SAS_ECC_INTR 0x1e8 |
85 | #define SAS_ECC_INTR_DQ_ECC1B_OFF 0 |
86 | #define SAS_ECC_INTR_DQ_ECC1B_MSK (0x1 << SAS_ECC_INTR_DQ_ECC1B_OFF) |
87 | #define SAS_ECC_INTR_DQ_ECCBAD_OFF 1 |
88 | #define SAS_ECC_INTR_DQ_ECCBAD_MSK (0x1 << SAS_ECC_INTR_DQ_ECCBAD_OFF) |
89 | #define SAS_ECC_INTR_IOST_ECC1B_OFF 2 |
90 | #define SAS_ECC_INTR_IOST_ECC1B_MSK (0x1 << SAS_ECC_INTR_IOST_ECC1B_OFF) |
91 | #define SAS_ECC_INTR_IOST_ECCBAD_OFF 3 |
92 | #define SAS_ECC_INTR_IOST_ECCBAD_MSK (0x1 << SAS_ECC_INTR_IOST_ECCBAD_OFF) |
93 | #define SAS_ECC_INTR_ITCT_ECC1B_OFF 4 |
94 | #define SAS_ECC_INTR_ITCT_ECC1B_MSK (0x1 << SAS_ECC_INTR_ITCT_ECC1B_OFF) |
95 | #define SAS_ECC_INTR_ITCT_ECCBAD_OFF 5 |
96 | #define SAS_ECC_INTR_ITCT_ECCBAD_MSK (0x1 << SAS_ECC_INTR_ITCT_ECCBAD_OFF) |
97 | #define SAS_ECC_INTR_MSK 0x1ec |
98 | #define HGC_ERR_STAT_EN 0x238 |
99 | #define DLVRY_Q_0_BASE_ADDR_LO 0x260 |
100 | #define DLVRY_Q_0_BASE_ADDR_HI 0x264 |
101 | #define DLVRY_Q_0_DEPTH 0x268 |
102 | #define DLVRY_Q_0_WR_PTR 0x26c |
103 | #define DLVRY_Q_0_RD_PTR 0x270 |
104 | #define COMPL_Q_0_BASE_ADDR_LO 0x4e0 |
105 | #define COMPL_Q_0_BASE_ADDR_HI 0x4e4 |
106 | #define COMPL_Q_0_DEPTH 0x4e8 |
107 | #define COMPL_Q_0_WR_PTR 0x4ec |
108 | #define COMPL_Q_0_RD_PTR 0x4f0 |
109 | #define HGC_ECC_ERR 0x7d0 |
110 | |
111 | /* phy registers need init */ |
112 | #define PORT_BASE (0x800) |
113 | |
114 | #define PHY_CFG (PORT_BASE + 0x0) |
115 | #define PHY_CFG_ENA_OFF 0 |
116 | #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF) |
117 | #define PHY_CFG_DC_OPT_OFF 2 |
118 | #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF) |
119 | #define PROG_PHY_LINK_RATE (PORT_BASE + 0xc) |
120 | #define PROG_PHY_LINK_RATE_MAX_OFF 0 |
121 | #define PROG_PHY_LINK_RATE_MAX_MSK (0xf << PROG_PHY_LINK_RATE_MAX_OFF) |
122 | #define PROG_PHY_LINK_RATE_MIN_OFF 4 |
123 | #define PROG_PHY_LINK_RATE_MIN_MSK (0xf << PROG_PHY_LINK_RATE_MIN_OFF) |
124 | #define PROG_PHY_LINK_RATE_OOB_OFF 8 |
125 | #define PROG_PHY_LINK_RATE_OOB_MSK (0xf << PROG_PHY_LINK_RATE_OOB_OFF) |
126 | #define PHY_CTRL (PORT_BASE + 0x14) |
127 | #define PHY_CTRL_RESET_OFF 0 |
128 | #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF) |
129 | #define PHY_RATE_NEGO (PORT_BASE + 0x30) |
130 | #define PHY_PCN (PORT_BASE + 0x44) |
131 | #define SL_TOUT_CFG (PORT_BASE + 0x8c) |
132 | #define SL_CONTROL (PORT_BASE + 0x94) |
133 | #define SL_CONTROL_NOTIFY_EN_OFF 0 |
134 | #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF) |
135 | #define TX_ID_DWORD0 (PORT_BASE + 0x9c) |
136 | #define TX_ID_DWORD1 (PORT_BASE + 0xa0) |
137 | #define TX_ID_DWORD2 (PORT_BASE + 0xa4) |
138 | #define TX_ID_DWORD3 (PORT_BASE + 0xa8) |
139 | #define TX_ID_DWORD4 (PORT_BASE + 0xaC) |
140 | #define TX_ID_DWORD5 (PORT_BASE + 0xb0) |
141 | #define TX_ID_DWORD6 (PORT_BASE + 0xb4) |
142 | #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4) |
143 | #define RX_IDAF_DWORD1 (PORT_BASE + 0xc8) |
144 | #define RX_IDAF_DWORD2 (PORT_BASE + 0xcc) |
145 | #define RX_IDAF_DWORD3 (PORT_BASE + 0xd0) |
146 | #define RX_IDAF_DWORD4 (PORT_BASE + 0xd4) |
147 | #define RX_IDAF_DWORD5 (PORT_BASE + 0xd8) |
148 | #define RX_IDAF_DWORD6 (PORT_BASE + 0xdc) |
149 | #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc) |
150 | #define DONE_RECEIVED_TIME (PORT_BASE + 0x12c) |
151 | #define CON_CFG_DRIVER (PORT_BASE + 0x130) |
152 | #define PHY_CONFIG2 (PORT_BASE + 0x1a8) |
153 | #define PHY_CONFIG2_FORCE_TXDEEMPH_OFF 3 |
154 | #define PHY_CONFIG2_FORCE_TXDEEMPH_MSK (0x1 << PHY_CONFIG2_FORCE_TXDEEMPH_OFF) |
155 | #define PHY_CONFIG2_TX_TRAIN_COMP_OFF 24 |
156 | #define PHY_CONFIG2_TX_TRAIN_COMP_MSK (0x1 << PHY_CONFIG2_TX_TRAIN_COMP_OFF) |
157 | #define CHL_INT0 (PORT_BASE + 0x1b0) |
158 | #define CHL_INT0_PHYCTRL_NOTRDY_OFF 0 |
159 | #define CHL_INT0_PHYCTRL_NOTRDY_MSK (0x1 << CHL_INT0_PHYCTRL_NOTRDY_OFF) |
160 | #define CHL_INT0_SN_FAIL_NGR_OFF 2 |
161 | #define CHL_INT0_SN_FAIL_NGR_MSK (0x1 << CHL_INT0_SN_FAIL_NGR_OFF) |
162 | #define CHL_INT0_DWS_LOST_OFF 4 |
163 | #define CHL_INT0_DWS_LOST_MSK (0x1 << CHL_INT0_DWS_LOST_OFF) |
164 | #define CHL_INT0_SL_IDAF_FAIL_OFF 10 |
165 | #define CHL_INT0_SL_IDAF_FAIL_MSK (0x1 << CHL_INT0_SL_IDAF_FAIL_OFF) |
166 | #define CHL_INT0_ID_TIMEOUT_OFF 11 |
167 | #define CHL_INT0_ID_TIMEOUT_MSK (0x1 << CHL_INT0_ID_TIMEOUT_OFF) |
168 | #define CHL_INT0_SL_OPAF_FAIL_OFF 12 |
169 | #define CHL_INT0_SL_OPAF_FAIL_MSK (0x1 << CHL_INT0_SL_OPAF_FAIL_OFF) |
170 | #define CHL_INT0_SL_PS_FAIL_OFF 21 |
171 | #define CHL_INT0_SL_PS_FAIL_MSK (0x1 << CHL_INT0_SL_PS_FAIL_OFF) |
172 | #define CHL_INT1 (PORT_BASE + 0x1b4) |
173 | #define CHL_INT2 (PORT_BASE + 0x1b8) |
174 | #define CHL_INT2_SL_RX_BC_ACK_OFF 2 |
175 | #define CHL_INT2_SL_RX_BC_ACK_MSK (0x1 << CHL_INT2_SL_RX_BC_ACK_OFF) |
176 | #define CHL_INT2_SL_PHY_ENA_OFF 6 |
177 | #define CHL_INT2_SL_PHY_ENA_MSK (0x1 << CHL_INT2_SL_PHY_ENA_OFF) |
178 | #define CHL_INT0_MSK (PORT_BASE + 0x1bc) |
179 | #define CHL_INT0_MSK_PHYCTRL_NOTRDY_OFF 0 |
180 | #define CHL_INT0_MSK_PHYCTRL_NOTRDY_MSK (0x1 << CHL_INT0_MSK_PHYCTRL_NOTRDY_OFF) |
181 | #define CHL_INT1_MSK (PORT_BASE + 0x1c0) |
182 | #define CHL_INT2_MSK (PORT_BASE + 0x1c4) |
183 | #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0) |
184 | #define DMA_TX_STATUS (PORT_BASE + 0x2d0) |
185 | #define DMA_TX_STATUS_BUSY_OFF 0 |
186 | #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF) |
187 | #define DMA_RX_STATUS (PORT_BASE + 0x2e8) |
188 | #define DMA_RX_STATUS_BUSY_OFF 0 |
189 | #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF) |
190 | |
191 | #define AXI_CFG 0x5100 |
192 | #define RESET_VALUE 0x7ffff |
193 | |
194 | /* HW dma structures */ |
195 | /* Delivery queue header */ |
196 | /* dw0 */ |
197 | #define CMD_HDR_RESP_REPORT_OFF 5 |
198 | #define CMD_HDR_RESP_REPORT_MSK 0x20 |
199 | #define CMD_HDR_TLR_CTRL_OFF 6 |
200 | #define CMD_HDR_TLR_CTRL_MSK 0xc0 |
201 | #define CMD_HDR_PORT_OFF 17 |
202 | #define CMD_HDR_PORT_MSK 0xe0000 |
203 | #define CMD_HDR_PRIORITY_OFF 27 |
204 | #define CMD_HDR_PRIORITY_MSK 0x8000000 |
205 | #define CMD_HDR_MODE_OFF 28 |
206 | #define CMD_HDR_MODE_MSK 0x10000000 |
207 | #define CMD_HDR_CMD_OFF 29 |
208 | #define CMD_HDR_CMD_MSK 0xe0000000 |
209 | /* dw1 */ |
210 | #define CMD_HDR_VERIFY_DTL_OFF 10 |
211 | #define CMD_HDR_VERIFY_DTL_MSK 0x400 |
212 | #define CMD_HDR_SSP_FRAME_TYPE_OFF 13 |
213 | #define CMD_HDR_SSP_FRAME_TYPE_MSK 0xe000 |
214 | #define CMD_HDR_DEVICE_ID_OFF 16 |
215 | #define CMD_HDR_DEVICE_ID_MSK 0xffff0000 |
216 | /* dw2 */ |
217 | #define CMD_HDR_CFL_OFF 0 |
218 | #define CMD_HDR_CFL_MSK 0x1ff |
219 | #define CMD_HDR_MRFL_OFF 15 |
220 | #define CMD_HDR_MRFL_MSK 0xff8000 |
221 | #define CMD_HDR_FIRST_BURST_OFF 25 |
222 | #define CMD_HDR_FIRST_BURST_MSK 0x2000000 |
223 | /* dw3 */ |
224 | #define CMD_HDR_IPTT_OFF 0 |
225 | #define CMD_HDR_IPTT_MSK 0xffff |
226 | /* dw6 */ |
227 | #define CMD_HDR_DATA_SGL_LEN_OFF 16 |
228 | #define CMD_HDR_DATA_SGL_LEN_MSK 0xffff0000 |
229 | |
230 | /* Completion header */ |
231 | #define CMPLT_HDR_IPTT_OFF 0 |
232 | #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF) |
233 | #define CMPLT_HDR_CMD_CMPLT_OFF 17 |
234 | #define CMPLT_HDR_CMD_CMPLT_MSK (0x1 << CMPLT_HDR_CMD_CMPLT_OFF) |
235 | #define CMPLT_HDR_ERR_RCRD_XFRD_OFF 18 |
236 | #define CMPLT_HDR_ERR_RCRD_XFRD_MSK (0x1 << CMPLT_HDR_ERR_RCRD_XFRD_OFF) |
237 | #define CMPLT_HDR_RSPNS_XFRD_OFF 19 |
238 | #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF) |
239 | #define CMPLT_HDR_IO_CFG_ERR_OFF 27 |
240 | #define CMPLT_HDR_IO_CFG_ERR_MSK (0x1 << CMPLT_HDR_IO_CFG_ERR_OFF) |
241 | |
242 | /* ITCT header */ |
243 | /* qw0 */ |
244 | #define ITCT_HDR_DEV_TYPE_OFF 0 |
245 | #define ITCT_HDR_DEV_TYPE_MSK (0x3ULL << ITCT_HDR_DEV_TYPE_OFF) |
246 | #define ITCT_HDR_VALID_OFF 2 |
247 | #define ITCT_HDR_VALID_MSK (0x1ULL << ITCT_HDR_VALID_OFF) |
248 | #define ITCT_HDR_AWT_CONTROL_OFF 4 |
249 | #define ITCT_HDR_AWT_CONTROL_MSK (0x1ULL << ITCT_HDR_AWT_CONTROL_OFF) |
250 | #define ITCT_HDR_MAX_CONN_RATE_OFF 5 |
251 | #define ITCT_HDR_MAX_CONN_RATE_MSK (0xfULL << ITCT_HDR_MAX_CONN_RATE_OFF) |
252 | #define ITCT_HDR_VALID_LINK_NUM_OFF 9 |
253 | #define ITCT_HDR_VALID_LINK_NUM_MSK (0xfULL << ITCT_HDR_VALID_LINK_NUM_OFF) |
254 | #define ITCT_HDR_PORT_ID_OFF 13 |
255 | #define ITCT_HDR_PORT_ID_MSK (0x7ULL << ITCT_HDR_PORT_ID_OFF) |
256 | #define ITCT_HDR_SMP_TIMEOUT_OFF 16 |
257 | #define ITCT_HDR_SMP_TIMEOUT_MSK (0xffffULL << ITCT_HDR_SMP_TIMEOUT_OFF) |
258 | /* qw1 */ |
259 | #define ITCT_HDR_MAX_SAS_ADDR_OFF 0 |
260 | #define ITCT_HDR_MAX_SAS_ADDR_MSK (0xffffffffffffffff << \ |
261 | ITCT_HDR_MAX_SAS_ADDR_OFF) |
262 | /* qw2 */ |
263 | #define ITCT_HDR_IT_NEXUS_LOSS_TL_OFF 0 |
264 | #define ITCT_HDR_IT_NEXUS_LOSS_TL_MSK (0xffffULL << \ |
265 | ITCT_HDR_IT_NEXUS_LOSS_TL_OFF) |
266 | #define ITCT_HDR_BUS_INACTIVE_TL_OFF 16 |
267 | #define ITCT_HDR_BUS_INACTIVE_TL_MSK (0xffffULL << \ |
268 | ITCT_HDR_BUS_INACTIVE_TL_OFF) |
269 | #define ITCT_HDR_MAX_CONN_TL_OFF 32 |
270 | #define ITCT_HDR_MAX_CONN_TL_MSK (0xffffULL << \ |
271 | ITCT_HDR_MAX_CONN_TL_OFF) |
272 | #define ITCT_HDR_REJ_OPEN_TL_OFF 48 |
273 | #define ITCT_HDR_REJ_OPEN_TL_MSK (0xffffULL << \ |
274 | ITCT_HDR_REJ_OPEN_TL_OFF) |
275 | |
276 | /* Err record header */ |
277 | #define ERR_HDR_DMA_TX_ERR_TYPE_OFF 0 |
278 | #define ERR_HDR_DMA_TX_ERR_TYPE_MSK (0xffff << ERR_HDR_DMA_TX_ERR_TYPE_OFF) |
279 | #define ERR_HDR_DMA_RX_ERR_TYPE_OFF 16 |
280 | #define ERR_HDR_DMA_RX_ERR_TYPE_MSK (0xffff << ERR_HDR_DMA_RX_ERR_TYPE_OFF) |
281 | |
282 | struct hisi_sas_complete_v1_hdr { |
283 | __le32 data; |
284 | }; |
285 | |
286 | struct hisi_sas_err_record_v1 { |
287 | /* dw0 */ |
288 | __le32 dma_err_type; |
289 | |
290 | /* dw1 */ |
291 | __le32 trans_tx_fail_type; |
292 | |
293 | /* dw2 */ |
294 | __le32 trans_rx_fail_type; |
295 | |
296 | /* dw3 */ |
297 | u32 rsvd; |
298 | }; |
299 | |
300 | enum { |
301 | HISI_SAS_PHY_BCAST_ACK = 0, |
302 | HISI_SAS_PHY_SL_PHY_ENABLED, |
303 | HISI_SAS_PHY_INT_ABNORMAL, |
304 | HISI_SAS_PHY_INT_NR |
305 | }; |
306 | |
307 | enum { |
308 | DMA_TX_ERR_BASE = 0x0, |
309 | DMA_RX_ERR_BASE = 0x100, |
310 | TRANS_TX_FAIL_BASE = 0x200, |
311 | TRANS_RX_FAIL_BASE = 0x300, |
312 | |
313 | /* dma tx */ |
314 | DMA_TX_DIF_CRC_ERR = DMA_TX_ERR_BASE, /* 0x0 */ |
315 | DMA_TX_DIF_APP_ERR, /* 0x1 */ |
316 | DMA_TX_DIF_RPP_ERR, /* 0x2 */ |
317 | DMA_TX_AXI_BUS_ERR, /* 0x3 */ |
318 | DMA_TX_DATA_SGL_OVERFLOW_ERR, /* 0x4 */ |
319 | DMA_TX_DIF_SGL_OVERFLOW_ERR, /* 0x5 */ |
320 | DMA_TX_UNEXP_XFER_RDY_ERR, /* 0x6 */ |
321 | DMA_TX_XFER_RDY_OFFSET_ERR, /* 0x7 */ |
322 | DMA_TX_DATA_UNDERFLOW_ERR, /* 0x8 */ |
323 | DMA_TX_XFER_RDY_LENGTH_OVERFLOW_ERR, /* 0x9 */ |
324 | |
325 | /* dma rx */ |
326 | DMA_RX_BUFFER_ECC_ERR = DMA_RX_ERR_BASE, /* 0x100 */ |
327 | DMA_RX_DIF_CRC_ERR, /* 0x101 */ |
328 | DMA_RX_DIF_APP_ERR, /* 0x102 */ |
329 | DMA_RX_DIF_RPP_ERR, /* 0x103 */ |
330 | DMA_RX_RESP_BUFFER_OVERFLOW_ERR, /* 0x104 */ |
331 | DMA_RX_AXI_BUS_ERR, /* 0x105 */ |
332 | DMA_RX_DATA_SGL_OVERFLOW_ERR, /* 0x106 */ |
333 | DMA_RX_DIF_SGL_OVERFLOW_ERR, /* 0x107 */ |
334 | DMA_RX_DATA_OFFSET_ERR, /* 0x108 */ |
335 | DMA_RX_UNEXP_RX_DATA_ERR, /* 0x109 */ |
336 | DMA_RX_DATA_OVERFLOW_ERR, /* 0x10a */ |
337 | DMA_RX_DATA_UNDERFLOW_ERR, /* 0x10b */ |
338 | DMA_RX_UNEXP_RETRANS_RESP_ERR, /* 0x10c */ |
339 | |
340 | /* trans tx */ |
341 | TRANS_TX_RSVD0_ERR = TRANS_TX_FAIL_BASE, /* 0x200 */ |
342 | TRANS_TX_PHY_NOT_ENABLE_ERR, /* 0x201 */ |
343 | TRANS_TX_OPEN_REJCT_WRONG_DEST_ERR, /* 0x202 */ |
344 | TRANS_TX_OPEN_REJCT_ZONE_VIOLATION_ERR, /* 0x203 */ |
345 | TRANS_TX_OPEN_REJCT_BY_OTHER_ERR, /* 0x204 */ |
346 | TRANS_TX_RSVD1_ERR, /* 0x205 */ |
347 | TRANS_TX_OPEN_REJCT_AIP_TIMEOUT_ERR, /* 0x206 */ |
348 | TRANS_TX_OPEN_REJCT_STP_BUSY_ERR, /* 0x207 */ |
349 | TRANS_TX_OPEN_REJCT_PROTOCOL_NOT_SUPPORT_ERR, /* 0x208 */ |
350 | TRANS_TX_OPEN_REJCT_RATE_NOT_SUPPORT_ERR, /* 0x209 */ |
351 | TRANS_TX_OPEN_REJCT_BAD_DEST_ERR, /* 0x20a */ |
352 | TRANS_TX_OPEN_BREAK_RECEIVE_ERR, /* 0x20b */ |
353 | TRANS_TX_LOW_PHY_POWER_ERR, /* 0x20c */ |
354 | TRANS_TX_OPEN_REJCT_PATHWAY_BLOCKED_ERR, /* 0x20d */ |
355 | TRANS_TX_OPEN_TIMEOUT_ERR, /* 0x20e */ |
356 | TRANS_TX_OPEN_REJCT_NO_DEST_ERR, /* 0x20f */ |
357 | TRANS_TX_OPEN_RETRY_ERR, /* 0x210 */ |
358 | TRANS_TX_RSVD2_ERR, /* 0x211 */ |
359 | TRANS_TX_BREAK_TIMEOUT_ERR, /* 0x212 */ |
360 | TRANS_TX_BREAK_REQUEST_ERR, /* 0x213 */ |
361 | TRANS_TX_BREAK_RECEIVE_ERR, /* 0x214 */ |
362 | TRANS_TX_CLOSE_TIMEOUT_ERR, /* 0x215 */ |
363 | TRANS_TX_CLOSE_NORMAL_ERR, /* 0x216 */ |
364 | TRANS_TX_CLOSE_PHYRESET_ERR, /* 0x217 */ |
365 | TRANS_TX_WITH_CLOSE_DWS_TIMEOUT_ERR, /* 0x218 */ |
366 | TRANS_TX_WITH_CLOSE_COMINIT_ERR, /* 0x219 */ |
367 | TRANS_TX_NAK_RECEIVE_ERR, /* 0x21a */ |
368 | TRANS_TX_ACK_NAK_TIMEOUT_ERR, /* 0x21b */ |
369 | TRANS_TX_CREDIT_TIMEOUT_ERR, /* 0x21c */ |
370 | TRANS_TX_IPTT_CONFLICT_ERR, /* 0x21d */ |
371 | TRANS_TX_TXFRM_TYPE_ERR, /* 0x21e */ |
372 | TRANS_TX_TXSMP_LENGTH_ERR, /* 0x21f */ |
373 | |
374 | /* trans rx */ |
375 | TRANS_RX_FRAME_CRC_ERR = TRANS_RX_FAIL_BASE, /* 0x300 */ |
376 | TRANS_RX_FRAME_DONE_ERR, /* 0x301 */ |
377 | TRANS_RX_FRAME_ERRPRM_ERR, /* 0x302 */ |
378 | TRANS_RX_FRAME_NO_CREDIT_ERR, /* 0x303 */ |
379 | TRANS_RX_RSVD0_ERR, /* 0x304 */ |
380 | TRANS_RX_FRAME_OVERRUN_ERR, /* 0x305 */ |
381 | TRANS_RX_FRAME_NO_EOF_ERR, /* 0x306 */ |
382 | TRANS_RX_LINK_BUF_OVERRUN_ERR, /* 0x307 */ |
383 | TRANS_RX_BREAK_TIMEOUT_ERR, /* 0x308 */ |
384 | TRANS_RX_BREAK_REQUEST_ERR, /* 0x309 */ |
385 | TRANS_RX_BREAK_RECEIVE_ERR, /* 0x30a */ |
386 | TRANS_RX_CLOSE_TIMEOUT_ERR, /* 0x30b */ |
387 | TRANS_RX_CLOSE_NORMAL_ERR, /* 0x30c */ |
388 | TRANS_RX_CLOSE_PHYRESET_ERR, /* 0x30d */ |
389 | TRANS_RX_WITH_CLOSE_DWS_TIMEOUT_ERR, /* 0x30e */ |
390 | TRANS_RX_WITH_CLOSE_COMINIT_ERR, /* 0x30f */ |
391 | TRANS_RX_DATA_LENGTH0_ERR, /* 0x310 */ |
392 | TRANS_RX_BAD_HASH_ERR, /* 0x311 */ |
393 | TRANS_RX_XRDY_ZERO_ERR, /* 0x312 */ |
394 | TRANS_RX_SSP_FRAME_LEN_ERR, /* 0x313 */ |
395 | TRANS_RX_TRANS_RX_RSVD1_ERR, /* 0x314 */ |
396 | TRANS_RX_NO_BALANCE_ERR, /* 0x315 */ |
397 | TRANS_RX_TRANS_RX_RSVD2_ERR, /* 0x316 */ |
398 | TRANS_RX_TRANS_RX_RSVD3_ERR, /* 0x317 */ |
399 | TRANS_RX_BAD_FRAME_TYPE_ERR, /* 0x318 */ |
400 | TRANS_RX_SMP_FRAME_LEN_ERR, /* 0x319 */ |
401 | TRANS_RX_SMP_RESP_TIMEOUT_ERR, /* 0x31a */ |
402 | }; |
403 | |
404 | #define HISI_SAS_PHY_MAX_INT_NR (HISI_SAS_PHY_INT_NR * HISI_SAS_MAX_PHYS) |
405 | #define HISI_SAS_CQ_MAX_INT_NR (HISI_SAS_MAX_QUEUES) |
406 | #define HISI_SAS_FATAL_INT_NR (2) |
407 | |
408 | #define HISI_SAS_MAX_INT_NR \ |
409 | (HISI_SAS_PHY_MAX_INT_NR + HISI_SAS_CQ_MAX_INT_NR +\ |
410 | HISI_SAS_FATAL_INT_NR) |
411 | |
412 | static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off) |
413 | { |
414 | void __iomem *regs = hisi_hba->regs + off; |
415 | |
416 | return readl(addr: regs); |
417 | } |
418 | |
419 | static void hisi_sas_write32(struct hisi_hba *hisi_hba, |
420 | u32 off, u32 val) |
421 | { |
422 | void __iomem *regs = hisi_hba->regs + off; |
423 | |
424 | writel(val, addr: regs); |
425 | } |
426 | |
427 | static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, |
428 | int phy_no, u32 off, u32 val) |
429 | { |
430 | void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; |
431 | |
432 | writel(val, addr: regs); |
433 | } |
434 | |
435 | static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba, |
436 | int phy_no, u32 off) |
437 | { |
438 | void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; |
439 | |
440 | return readl(addr: regs); |
441 | } |
442 | |
443 | static void config_phy_opt_mode_v1_hw(struct hisi_hba *hisi_hba, int phy_no) |
444 | { |
445 | u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); |
446 | |
447 | cfg &= ~PHY_CFG_DC_OPT_MSK; |
448 | cfg |= 1 << PHY_CFG_DC_OPT_OFF; |
449 | hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, val: cfg); |
450 | } |
451 | |
452 | static void config_tx_tfe_autoneg_v1_hw(struct hisi_hba *hisi_hba, int phy_no) |
453 | { |
454 | u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CONFIG2); |
455 | |
456 | cfg &= ~PHY_CONFIG2_FORCE_TXDEEMPH_MSK; |
457 | hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CONFIG2, val: cfg); |
458 | } |
459 | |
460 | static void config_id_frame_v1_hw(struct hisi_hba *hisi_hba, int phy_no) |
461 | { |
462 | struct sas_identify_frame identify_frame; |
463 | u32 *identify_buffer; |
464 | |
465 | memset(&identify_frame, 0, sizeof(identify_frame)); |
466 | identify_frame.dev_type = SAS_END_DEVICE; |
467 | identify_frame.frame_type = 0; |
468 | identify_frame._un1 = 1; |
469 | identify_frame.initiator_bits = SAS_PROTOCOL_ALL; |
470 | identify_frame.target_bits = SAS_PROTOCOL_NONE; |
471 | memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); |
472 | memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); |
473 | identify_frame.phy_id = phy_no; |
474 | identify_buffer = (u32 *)(&identify_frame); |
475 | |
476 | hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0, |
477 | __swab32(identify_buffer[0])); |
478 | hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1, |
479 | __swab32(identify_buffer[1])); |
480 | hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2, |
481 | __swab32(identify_buffer[2])); |
482 | hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3, |
483 | __swab32(identify_buffer[3])); |
484 | hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4, |
485 | __swab32(identify_buffer[4])); |
486 | hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5, |
487 | __swab32(identify_buffer[5])); |
488 | } |
489 | |
490 | static void setup_itct_v1_hw(struct hisi_hba *hisi_hba, |
491 | struct hisi_sas_device *sas_dev) |
492 | { |
493 | struct domain_device *device = sas_dev->sas_device; |
494 | struct device *dev = hisi_hba->dev; |
495 | u64 qw0, device_id = sas_dev->device_id; |
496 | struct hisi_sas_itct *itct = &hisi_hba->itct[device_id]; |
497 | struct asd_sas_port *sas_port = device->port; |
498 | struct hisi_sas_port *port = to_hisi_sas_port(sas_port); |
499 | u64 sas_addr; |
500 | |
501 | memset(itct, 0, sizeof(*itct)); |
502 | |
503 | /* qw0 */ |
504 | qw0 = 0; |
505 | switch (sas_dev->dev_type) { |
506 | case SAS_END_DEVICE: |
507 | case SAS_EDGE_EXPANDER_DEVICE: |
508 | case SAS_FANOUT_EXPANDER_DEVICE: |
509 | qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF; |
510 | break; |
511 | default: |
512 | dev_warn(dev, "setup itct: unsupported dev type (%d)\n" , |
513 | sas_dev->dev_type); |
514 | } |
515 | |
516 | qw0 |= ((1 << ITCT_HDR_VALID_OFF) | |
517 | (1 << ITCT_HDR_AWT_CONTROL_OFF) | |
518 | (device->max_linkrate << ITCT_HDR_MAX_CONN_RATE_OFF) | |
519 | (1 << ITCT_HDR_VALID_LINK_NUM_OFF) | |
520 | (port->id << ITCT_HDR_PORT_ID_OFF)); |
521 | itct->qw0 = cpu_to_le64(qw0); |
522 | |
523 | /* qw1 */ |
524 | memcpy(&sas_addr, device->sas_addr, SAS_ADDR_SIZE); |
525 | itct->sas_addr = cpu_to_le64(__swab64(sas_addr)); |
526 | |
527 | /* qw2 */ |
528 | itct->qw2 = cpu_to_le64((500ULL << ITCT_HDR_IT_NEXUS_LOSS_TL_OFF) | |
529 | (0xff00ULL << ITCT_HDR_BUS_INACTIVE_TL_OFF) | |
530 | (0xff00ULL << ITCT_HDR_MAX_CONN_TL_OFF) | |
531 | (0xff00ULL << ITCT_HDR_REJ_OPEN_TL_OFF)); |
532 | } |
533 | |
534 | static int clear_itct_v1_hw(struct hisi_hba *hisi_hba, |
535 | struct hisi_sas_device *sas_dev) |
536 | { |
537 | u64 dev_id = sas_dev->device_id; |
538 | struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id]; |
539 | u64 qw0; |
540 | u32 reg_val = hisi_sas_read32(hisi_hba, CFG_AGING_TIME); |
541 | |
542 | reg_val |= CFG_AGING_TIME_ITCT_REL_MSK; |
543 | hisi_sas_write32(hisi_hba, CFG_AGING_TIME, val: reg_val); |
544 | |
545 | /* free itct */ |
546 | udelay(1); |
547 | reg_val = hisi_sas_read32(hisi_hba, CFG_AGING_TIME); |
548 | reg_val &= ~CFG_AGING_TIME_ITCT_REL_MSK; |
549 | hisi_sas_write32(hisi_hba, CFG_AGING_TIME, val: reg_val); |
550 | |
551 | qw0 = le64_to_cpu(itct->qw0); |
552 | qw0 &= ~ITCT_HDR_VALID_MSK; |
553 | itct->qw0 = cpu_to_le64(qw0); |
554 | |
555 | return 0; |
556 | } |
557 | |
558 | static int reset_hw_v1_hw(struct hisi_hba *hisi_hba) |
559 | { |
560 | int i; |
561 | unsigned long end_time; |
562 | u32 val; |
563 | struct device *dev = hisi_hba->dev; |
564 | |
565 | for (i = 0; i < hisi_hba->n_phy; i++) { |
566 | u32 phy_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no: i, PHY_CTRL); |
567 | |
568 | phy_ctrl |= PHY_CTRL_RESET_MSK; |
569 | hisi_sas_phy_write32(hisi_hba, phy_no: i, PHY_CTRL, val: phy_ctrl); |
570 | } |
571 | msleep(msecs: 1); /* It is safe to wait for 50us */ |
572 | |
573 | /* Ensure DMA tx & rx idle */ |
574 | for (i = 0; i < hisi_hba->n_phy; i++) { |
575 | u32 dma_tx_status, dma_rx_status; |
576 | |
577 | end_time = jiffies + msecs_to_jiffies(m: 1000); |
578 | |
579 | while (1) { |
580 | dma_tx_status = hisi_sas_phy_read32(hisi_hba, phy_no: i, |
581 | DMA_TX_STATUS); |
582 | dma_rx_status = hisi_sas_phy_read32(hisi_hba, phy_no: i, |
583 | DMA_RX_STATUS); |
584 | |
585 | if (!(dma_tx_status & DMA_TX_STATUS_BUSY_MSK) && |
586 | !(dma_rx_status & DMA_RX_STATUS_BUSY_MSK)) |
587 | break; |
588 | |
589 | msleep(msecs: 20); |
590 | if (time_after(jiffies, end_time)) |
591 | return -EIO; |
592 | } |
593 | } |
594 | |
595 | /* Ensure axi bus idle */ |
596 | end_time = jiffies + msecs_to_jiffies(m: 1000); |
597 | while (1) { |
598 | u32 axi_status = |
599 | hisi_sas_read32(hisi_hba, AXI_CFG); |
600 | |
601 | if (axi_status == 0) |
602 | break; |
603 | |
604 | msleep(msecs: 20); |
605 | if (time_after(jiffies, end_time)) |
606 | return -EIO; |
607 | } |
608 | |
609 | if (ACPI_HANDLE(dev)) { |
610 | acpi_status s; |
611 | |
612 | s = acpi_evaluate_object(ACPI_HANDLE(dev), pathname: "_RST" , NULL, NULL); |
613 | if (ACPI_FAILURE(s)) { |
614 | dev_err(dev, "Reset failed\n" ); |
615 | return -EIO; |
616 | } |
617 | } else if (hisi_hba->ctrl) { |
618 | /* Apply reset and disable clock */ |
619 | /* clk disable reg is offset by +4 bytes from clk enable reg */ |
620 | regmap_write(map: hisi_hba->ctrl, reg: hisi_hba->ctrl_reset_reg, |
621 | RESET_VALUE); |
622 | regmap_write(map: hisi_hba->ctrl, reg: hisi_hba->ctrl_clock_ena_reg + 4, |
623 | RESET_VALUE); |
624 | msleep(msecs: 1); |
625 | regmap_read(map: hisi_hba->ctrl, reg: hisi_hba->ctrl_reset_sts_reg, val: &val); |
626 | if (RESET_VALUE != (val & RESET_VALUE)) { |
627 | dev_err(dev, "Reset failed\n" ); |
628 | return -EIO; |
629 | } |
630 | |
631 | /* De-reset and enable clock */ |
632 | /* deassert rst reg is offset by +4 bytes from assert reg */ |
633 | regmap_write(map: hisi_hba->ctrl, reg: hisi_hba->ctrl_reset_reg + 4, |
634 | RESET_VALUE); |
635 | regmap_write(map: hisi_hba->ctrl, reg: hisi_hba->ctrl_clock_ena_reg, |
636 | RESET_VALUE); |
637 | msleep(msecs: 1); |
638 | regmap_read(map: hisi_hba->ctrl, reg: hisi_hba->ctrl_reset_sts_reg, val: &val); |
639 | if (val & RESET_VALUE) { |
640 | dev_err(dev, "De-reset failed\n" ); |
641 | return -EIO; |
642 | } |
643 | } else { |
644 | dev_warn(dev, "no reset method\n" ); |
645 | return -EINVAL; |
646 | } |
647 | |
648 | return 0; |
649 | } |
650 | |
651 | static void init_reg_v1_hw(struct hisi_hba *hisi_hba) |
652 | { |
653 | int i; |
654 | |
655 | /* Global registers init*/ |
656 | hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, |
657 | val: (u32)((1ULL << hisi_hba->queue_count) - 1)); |
658 | hisi_sas_write32(hisi_hba, HGC_TRANS_TASK_CNT_LIMIT, val: 0x11); |
659 | hisi_sas_write32(hisi_hba, DEVICE_MSG_WORK_MODE, val: 0x1); |
660 | hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, val: 0x1ff); |
661 | hisi_sas_write32(hisi_hba, HGC_ERR_STAT_EN, val: 0x401); |
662 | hisi_sas_write32(hisi_hba, CFG_1US_TIMER_TRSH, val: 0x64); |
663 | hisi_sas_write32(hisi_hba, HGC_GET_ITV_TIME, val: 0x1); |
664 | hisi_sas_write32(hisi_hba, I_T_NEXUS_LOSS_TIME, val: 0x64); |
665 | hisi_sas_write32(hisi_hba, BUS_INACTIVE_LIMIT_TIME, val: 0x2710); |
666 | hisi_sas_write32(hisi_hba, REJECT_TO_OPEN_LIMIT_TIME, val: 0x1); |
667 | hisi_sas_write32(hisi_hba, CFG_AGING_TIME, val: 0x7a12); |
668 | hisi_sas_write32(hisi_hba, HGC_DFX_CFG2, val: 0x9c40); |
669 | hisi_sas_write32(hisi_hba, FIS_LIST_BADDR_L, val: 0x2); |
670 | hisi_sas_write32(hisi_hba, INT_COAL_EN, val: 0xc); |
671 | hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, val: 0x186a0); |
672 | hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, val: 1); |
673 | hisi_sas_write32(hisi_hba, ENT_INT_COAL_TIME, val: 0x1); |
674 | hisi_sas_write32(hisi_hba, ENT_INT_COAL_CNT, val: 0x1); |
675 | hisi_sas_write32(hisi_hba, OQ_INT_SRC, val: 0xffffffff); |
676 | hisi_sas_write32(hisi_hba, OQ_INT_SRC_MSK, val: 0); |
677 | hisi_sas_write32(hisi_hba, ENT_INT_SRC1, val: 0xffffffff); |
678 | hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, val: 0); |
679 | hisi_sas_write32(hisi_hba, ENT_INT_SRC2, val: 0xffffffff); |
680 | hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, val: 0); |
681 | hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, val: 0); |
682 | hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, val: 0x2); |
683 | hisi_sas_write32(hisi_hba, CFG_SAS_CONFIG, val: 0x22000000); |
684 | |
685 | for (i = 0; i < hisi_hba->n_phy; i++) { |
686 | hisi_sas_phy_write32(hisi_hba, phy_no: i, PROG_PHY_LINK_RATE, val: 0x88a); |
687 | hisi_sas_phy_write32(hisi_hba, phy_no: i, PHY_CONFIG2, val: 0x7c080); |
688 | hisi_sas_phy_write32(hisi_hba, phy_no: i, PHY_RATE_NEGO, val: 0x415ee00); |
689 | hisi_sas_phy_write32(hisi_hba, phy_no: i, PHY_PCN, val: 0x80a80000); |
690 | hisi_sas_phy_write32(hisi_hba, phy_no: i, SL_TOUT_CFG, val: 0x7d7d7d7d); |
691 | hisi_sas_phy_write32(hisi_hba, phy_no: i, DONE_RECEIVED_TIME, val: 0x0); |
692 | hisi_sas_phy_write32(hisi_hba, phy_no: i, RXOP_CHECK_CFG_H, val: 0x1000); |
693 | hisi_sas_phy_write32(hisi_hba, phy_no: i, DONE_RECEIVED_TIME, val: 0); |
694 | hisi_sas_phy_write32(hisi_hba, phy_no: i, CON_CFG_DRIVER, val: 0x13f0a); |
695 | hisi_sas_phy_write32(hisi_hba, phy_no: i, CHL_INT_COAL_EN, val: 3); |
696 | hisi_sas_phy_write32(hisi_hba, phy_no: i, DONE_RECEIVED_TIME, val: 8); |
697 | } |
698 | |
699 | for (i = 0; i < hisi_hba->queue_count; i++) { |
700 | /* Delivery queue */ |
701 | hisi_sas_write32(hisi_hba, |
702 | DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14), |
703 | upper_32_bits(hisi_hba->cmd_hdr_dma[i])); |
704 | |
705 | hisi_sas_write32(hisi_hba, |
706 | DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14), |
707 | lower_32_bits(hisi_hba->cmd_hdr_dma[i])); |
708 | |
709 | hisi_sas_write32(hisi_hba, |
710 | DLVRY_Q_0_DEPTH + (i * 0x14), |
711 | HISI_SAS_QUEUE_SLOTS); |
712 | |
713 | /* Completion queue */ |
714 | hisi_sas_write32(hisi_hba, |
715 | COMPL_Q_0_BASE_ADDR_HI + (i * 0x14), |
716 | upper_32_bits(hisi_hba->complete_hdr_dma[i])); |
717 | |
718 | hisi_sas_write32(hisi_hba, |
719 | COMPL_Q_0_BASE_ADDR_LO + (i * 0x14), |
720 | lower_32_bits(hisi_hba->complete_hdr_dma[i])); |
721 | |
722 | hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14), |
723 | HISI_SAS_QUEUE_SLOTS); |
724 | } |
725 | |
726 | /* itct */ |
727 | hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO, |
728 | lower_32_bits(hisi_hba->itct_dma)); |
729 | |
730 | hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI, |
731 | upper_32_bits(hisi_hba->itct_dma)); |
732 | |
733 | /* iost */ |
734 | hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO, |
735 | lower_32_bits(hisi_hba->iost_dma)); |
736 | |
737 | hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI, |
738 | upper_32_bits(hisi_hba->iost_dma)); |
739 | |
740 | /* breakpoint */ |
741 | hisi_sas_write32(hisi_hba, BROKEN_MSG_ADDR_LO, |
742 | lower_32_bits(hisi_hba->breakpoint_dma)); |
743 | |
744 | hisi_sas_write32(hisi_hba, BROKEN_MSG_ADDR_HI, |
745 | upper_32_bits(hisi_hba->breakpoint_dma)); |
746 | } |
747 | |
748 | static int hw_init_v1_hw(struct hisi_hba *hisi_hba) |
749 | { |
750 | struct device *dev = hisi_hba->dev; |
751 | int rc; |
752 | |
753 | rc = reset_hw_v1_hw(hisi_hba); |
754 | if (rc) { |
755 | dev_err(dev, "hisi_sas_reset_hw failed, rc=%d\n" , rc); |
756 | return rc; |
757 | } |
758 | |
759 | msleep(msecs: 100); |
760 | init_reg_v1_hw(hisi_hba); |
761 | |
762 | return 0; |
763 | } |
764 | |
765 | static void enable_phy_v1_hw(struct hisi_hba *hisi_hba, int phy_no) |
766 | { |
767 | u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); |
768 | |
769 | cfg |= PHY_CFG_ENA_MSK; |
770 | hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, val: cfg); |
771 | } |
772 | |
773 | static void disable_phy_v1_hw(struct hisi_hba *hisi_hba, int phy_no) |
774 | { |
775 | u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); |
776 | |
777 | cfg &= ~PHY_CFG_ENA_MSK; |
778 | hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, val: cfg); |
779 | } |
780 | |
781 | static void start_phy_v1_hw(struct hisi_hba *hisi_hba, int phy_no) |
782 | { |
783 | config_id_frame_v1_hw(hisi_hba, phy_no); |
784 | config_phy_opt_mode_v1_hw(hisi_hba, phy_no); |
785 | config_tx_tfe_autoneg_v1_hw(hisi_hba, phy_no); |
786 | enable_phy_v1_hw(hisi_hba, phy_no); |
787 | } |
788 | |
789 | static void phy_hard_reset_v1_hw(struct hisi_hba *hisi_hba, int phy_no) |
790 | { |
791 | hisi_sas_phy_enable(hisi_hba, phy_no, enable: 0); |
792 | msleep(msecs: 100); |
793 | hisi_sas_phy_enable(hisi_hba, phy_no, enable: 1); |
794 | } |
795 | |
796 | static void start_phys_v1_hw(struct timer_list *t) |
797 | { |
798 | struct hisi_hba *hisi_hba = from_timer(hisi_hba, t, timer); |
799 | int i; |
800 | |
801 | for (i = 0; i < hisi_hba->n_phy; i++) { |
802 | hisi_sas_phy_write32(hisi_hba, phy_no: i, CHL_INT2_MSK, val: 0x12a); |
803 | hisi_sas_phy_enable(hisi_hba, phy_no: i, enable: 1); |
804 | } |
805 | } |
806 | |
807 | static void phys_init_v1_hw(struct hisi_hba *hisi_hba) |
808 | { |
809 | int i; |
810 | struct timer_list *timer = &hisi_hba->timer; |
811 | |
812 | for (i = 0; i < hisi_hba->n_phy; i++) { |
813 | hisi_sas_phy_write32(hisi_hba, phy_no: i, CHL_INT2_MSK, val: 0x6a); |
814 | hisi_sas_phy_read32(hisi_hba, phy_no: i, CHL_INT2_MSK); |
815 | } |
816 | |
817 | timer_setup(timer, start_phys_v1_hw, 0); |
818 | mod_timer(timer, expires: jiffies + HZ); |
819 | } |
820 | |
821 | static void sl_notify_ssp_v1_hw(struct hisi_hba *hisi_hba, int phy_no) |
822 | { |
823 | u32 sl_control; |
824 | |
825 | sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); |
826 | sl_control |= SL_CONTROL_NOTIFY_EN_MSK; |
827 | hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, val: sl_control); |
828 | msleep(msecs: 1); |
829 | sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); |
830 | sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK; |
831 | hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, val: sl_control); |
832 | } |
833 | |
834 | static enum sas_linkrate phy_get_max_linkrate_v1_hw(void) |
835 | { |
836 | return SAS_LINK_RATE_6_0_GBPS; |
837 | } |
838 | |
839 | static void phy_set_linkrate_v1_hw(struct hisi_hba *hisi_hba, int phy_no, |
840 | struct sas_phy_linkrates *r) |
841 | { |
842 | enum sas_linkrate max = r->maximum_linkrate; |
843 | u32 prog_phy_link_rate = 0x800; |
844 | |
845 | prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max); |
846 | hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE, |
847 | val: prog_phy_link_rate); |
848 | } |
849 | |
850 | static int get_wideport_bitmap_v1_hw(struct hisi_hba *hisi_hba, int port_id) |
851 | { |
852 | int i, bitmap = 0; |
853 | u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); |
854 | |
855 | for (i = 0; i < hisi_hba->n_phy; i++) |
856 | if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id) |
857 | bitmap |= 1 << i; |
858 | |
859 | return bitmap; |
860 | } |
861 | |
862 | /* DQ lock must be taken here */ |
863 | static void start_delivery_v1_hw(struct hisi_sas_dq *dq) |
864 | { |
865 | struct hisi_hba *hisi_hba = dq->hisi_hba; |
866 | struct hisi_sas_slot *s, *s1, *s2 = NULL; |
867 | int dlvry_queue = dq->id; |
868 | int wp; |
869 | |
870 | list_for_each_entry_safe(s, s1, &dq->list, delivery) { |
871 | if (!s->ready) |
872 | break; |
873 | s2 = s; |
874 | list_del(entry: &s->delivery); |
875 | } |
876 | |
877 | if (!s2) |
878 | return; |
879 | |
880 | /* |
881 | * Ensure that memories for slots built on other CPUs is observed. |
882 | */ |
883 | smp_rmb(); |
884 | wp = (s2->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS; |
885 | |
886 | hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), val: wp); |
887 | } |
888 | |
889 | static void prep_prd_sge_v1_hw(struct hisi_hba *hisi_hba, |
890 | struct hisi_sas_slot *slot, |
891 | struct hisi_sas_cmd_hdr *hdr, |
892 | struct scatterlist *scatter, |
893 | int n_elem) |
894 | { |
895 | struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot); |
896 | struct scatterlist *sg; |
897 | int i; |
898 | |
899 | for_each_sg(scatter, sg, n_elem, i) { |
900 | struct hisi_sas_sge *entry = &sge_page->sge[i]; |
901 | |
902 | entry->addr = cpu_to_le64(sg_dma_address(sg)); |
903 | entry->page_ctrl_0 = entry->page_ctrl_1 = 0; |
904 | entry->data_len = cpu_to_le32(sg_dma_len(sg)); |
905 | entry->data_off = 0; |
906 | } |
907 | |
908 | hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot)); |
909 | |
910 | hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF); |
911 | } |
912 | |
913 | static void prep_smp_v1_hw(struct hisi_hba *hisi_hba, |
914 | struct hisi_sas_slot *slot) |
915 | { |
916 | struct sas_task *task = slot->task; |
917 | struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; |
918 | struct domain_device *device = task->dev; |
919 | struct hisi_sas_port *port = slot->port; |
920 | struct scatterlist *sg_req; |
921 | struct hisi_sas_device *sas_dev = device->lldd_dev; |
922 | dma_addr_t req_dma_addr; |
923 | unsigned int req_len; |
924 | |
925 | /* req */ |
926 | sg_req = &task->smp_task.smp_req; |
927 | req_len = sg_dma_len(sg_req); |
928 | req_dma_addr = sg_dma_address(sg_req); |
929 | |
930 | /* create header */ |
931 | /* dw0 */ |
932 | hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) | |
933 | (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */ |
934 | (1 << CMD_HDR_MODE_OFF) | /* ini mode */ |
935 | (2 << CMD_HDR_CMD_OFF)); /* smp */ |
936 | |
937 | /* map itct entry */ |
938 | hdr->dw1 = cpu_to_le32(sas_dev->device_id << CMD_HDR_DEVICE_ID_OFF); |
939 | |
940 | /* dw2 */ |
941 | hdr->dw2 = cpu_to_le32((((req_len-4)/4) << CMD_HDR_CFL_OFF) | |
942 | (HISI_SAS_MAX_SMP_RESP_SZ/4 << |
943 | CMD_HDR_MRFL_OFF)); |
944 | |
945 | hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF); |
946 | |
947 | hdr->cmd_table_addr = cpu_to_le64(req_dma_addr); |
948 | hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); |
949 | } |
950 | |
951 | static void prep_ssp_v1_hw(struct hisi_hba *hisi_hba, |
952 | struct hisi_sas_slot *slot) |
953 | { |
954 | struct sas_task *task = slot->task; |
955 | struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; |
956 | struct domain_device *device = task->dev; |
957 | struct hisi_sas_device *sas_dev = device->lldd_dev; |
958 | struct hisi_sas_port *port = slot->port; |
959 | struct sas_ssp_task *ssp_task = &task->ssp_task; |
960 | struct scsi_cmnd *scsi_cmnd = ssp_task->cmd; |
961 | struct sas_tmf_task *tmf = slot->tmf; |
962 | int has_data = 0, priority = !!tmf; |
963 | u8 *buf_cmd; |
964 | u32 dw1, dw2; |
965 | |
966 | /* create header */ |
967 | hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) | |
968 | (0x2 << CMD_HDR_TLR_CTRL_OFF) | |
969 | (port->id << CMD_HDR_PORT_OFF) | |
970 | (priority << CMD_HDR_PRIORITY_OFF) | |
971 | (1 << CMD_HDR_MODE_OFF) | /* ini mode */ |
972 | (1 << CMD_HDR_CMD_OFF)); /* ssp */ |
973 | |
974 | dw1 = 1 << CMD_HDR_VERIFY_DTL_OFF; |
975 | |
976 | if (tmf) { |
977 | dw1 |= 3 << CMD_HDR_SSP_FRAME_TYPE_OFF; |
978 | } else { |
979 | switch (scsi_cmnd->sc_data_direction) { |
980 | case DMA_TO_DEVICE: |
981 | dw1 |= 2 << CMD_HDR_SSP_FRAME_TYPE_OFF; |
982 | has_data = 1; |
983 | break; |
984 | case DMA_FROM_DEVICE: |
985 | dw1 |= 1 << CMD_HDR_SSP_FRAME_TYPE_OFF; |
986 | has_data = 1; |
987 | break; |
988 | default: |
989 | dw1 |= 0 << CMD_HDR_SSP_FRAME_TYPE_OFF; |
990 | } |
991 | } |
992 | |
993 | /* map itct entry */ |
994 | dw1 |= sas_dev->device_id << CMD_HDR_DEVICE_ID_OFF; |
995 | hdr->dw1 = cpu_to_le32(dw1); |
996 | |
997 | if (tmf) { |
998 | dw2 = ((sizeof(struct ssp_tmf_iu) + |
999 | sizeof(struct ssp_frame_hdr)+3)/4) << |
1000 | CMD_HDR_CFL_OFF; |
1001 | } else { |
1002 | dw2 = ((sizeof(struct ssp_command_iu) + |
1003 | sizeof(struct ssp_frame_hdr)+3)/4) << |
1004 | CMD_HDR_CFL_OFF; |
1005 | } |
1006 | |
1007 | dw2 |= (HISI_SAS_MAX_SSP_RESP_SZ/4) << CMD_HDR_MRFL_OFF; |
1008 | |
1009 | hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF); |
1010 | |
1011 | if (has_data) |
1012 | prep_prd_sge_v1_hw(hisi_hba, slot, hdr, scatter: task->scatter, |
1013 | n_elem: slot->n_elem); |
1014 | |
1015 | hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len); |
1016 | hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot)); |
1017 | hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); |
1018 | |
1019 | buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) + |
1020 | sizeof(struct ssp_frame_hdr); |
1021 | hdr->dw2 = cpu_to_le32(dw2); |
1022 | |
1023 | memcpy(buf_cmd, &task->ssp_task.LUN, 8); |
1024 | if (!tmf) { |
1025 | buf_cmd[9] = task->ssp_task.task_attr; |
1026 | memcpy(buf_cmd + 12, task->ssp_task.cmd->cmnd, |
1027 | task->ssp_task.cmd->cmd_len); |
1028 | } else { |
1029 | buf_cmd[10] = tmf->tmf; |
1030 | switch (tmf->tmf) { |
1031 | case TMF_ABORT_TASK: |
1032 | case TMF_QUERY_TASK: |
1033 | buf_cmd[12] = |
1034 | (tmf->tag_of_task_to_be_managed >> 8) & 0xff; |
1035 | buf_cmd[13] = |
1036 | tmf->tag_of_task_to_be_managed & 0xff; |
1037 | break; |
1038 | default: |
1039 | break; |
1040 | } |
1041 | } |
1042 | } |
1043 | |
1044 | /* by default, task resp is complete */ |
1045 | static void slot_err_v1_hw(struct hisi_hba *hisi_hba, |
1046 | struct sas_task *task, |
1047 | struct hisi_sas_slot *slot) |
1048 | { |
1049 | struct task_status_struct *ts = &task->task_status; |
1050 | struct hisi_sas_err_record_v1 *err_record = |
1051 | hisi_sas_status_buf_addr_mem(slot); |
1052 | struct device *dev = hisi_hba->dev; |
1053 | |
1054 | switch (task->task_proto) { |
1055 | case SAS_PROTOCOL_SSP: |
1056 | { |
1057 | int error = -1; |
1058 | u32 dma_err_type = le32_to_cpu(err_record->dma_err_type); |
1059 | u32 dma_tx_err_type = ((dma_err_type & |
1060 | ERR_HDR_DMA_TX_ERR_TYPE_MSK)) >> |
1061 | ERR_HDR_DMA_TX_ERR_TYPE_OFF; |
1062 | u32 dma_rx_err_type = ((dma_err_type & |
1063 | ERR_HDR_DMA_RX_ERR_TYPE_MSK)) >> |
1064 | ERR_HDR_DMA_RX_ERR_TYPE_OFF; |
1065 | u32 trans_tx_fail_type = |
1066 | le32_to_cpu(err_record->trans_tx_fail_type); |
1067 | u32 trans_rx_fail_type = |
1068 | le32_to_cpu(err_record->trans_rx_fail_type); |
1069 | |
1070 | if (dma_tx_err_type) { |
1071 | /* dma tx err */ |
1072 | error = ffs(dma_tx_err_type) |
1073 | - 1 + DMA_TX_ERR_BASE; |
1074 | } else if (dma_rx_err_type) { |
1075 | /* dma rx err */ |
1076 | error = ffs(dma_rx_err_type) |
1077 | - 1 + DMA_RX_ERR_BASE; |
1078 | } else if (trans_tx_fail_type) { |
1079 | /* trans tx err */ |
1080 | error = ffs(trans_tx_fail_type) |
1081 | - 1 + TRANS_TX_FAIL_BASE; |
1082 | } else if (trans_rx_fail_type) { |
1083 | /* trans rx err */ |
1084 | error = ffs(trans_rx_fail_type) |
1085 | - 1 + TRANS_RX_FAIL_BASE; |
1086 | } |
1087 | |
1088 | switch (error) { |
1089 | case DMA_TX_DATA_UNDERFLOW_ERR: |
1090 | case DMA_RX_DATA_UNDERFLOW_ERR: |
1091 | { |
1092 | ts->residual = 0; |
1093 | ts->stat = SAS_DATA_UNDERRUN; |
1094 | break; |
1095 | } |
1096 | case DMA_TX_DATA_SGL_OVERFLOW_ERR: |
1097 | case DMA_TX_DIF_SGL_OVERFLOW_ERR: |
1098 | case DMA_TX_XFER_RDY_LENGTH_OVERFLOW_ERR: |
1099 | case DMA_RX_DATA_OVERFLOW_ERR: |
1100 | case TRANS_RX_FRAME_OVERRUN_ERR: |
1101 | case TRANS_RX_LINK_BUF_OVERRUN_ERR: |
1102 | { |
1103 | ts->stat = SAS_DATA_OVERRUN; |
1104 | ts->residual = 0; |
1105 | break; |
1106 | } |
1107 | case TRANS_TX_PHY_NOT_ENABLE_ERR: |
1108 | { |
1109 | ts->stat = SAS_PHY_DOWN; |
1110 | break; |
1111 | } |
1112 | case TRANS_TX_OPEN_REJCT_WRONG_DEST_ERR: |
1113 | case TRANS_TX_OPEN_REJCT_ZONE_VIOLATION_ERR: |
1114 | case TRANS_TX_OPEN_REJCT_BY_OTHER_ERR: |
1115 | case TRANS_TX_OPEN_REJCT_AIP_TIMEOUT_ERR: |
1116 | case TRANS_TX_OPEN_REJCT_STP_BUSY_ERR: |
1117 | case TRANS_TX_OPEN_REJCT_PROTOCOL_NOT_SUPPORT_ERR: |
1118 | case TRANS_TX_OPEN_REJCT_RATE_NOT_SUPPORT_ERR: |
1119 | case TRANS_TX_OPEN_REJCT_BAD_DEST_ERR: |
1120 | case TRANS_TX_OPEN_BREAK_RECEIVE_ERR: |
1121 | case TRANS_TX_OPEN_REJCT_PATHWAY_BLOCKED_ERR: |
1122 | case TRANS_TX_OPEN_REJCT_NO_DEST_ERR: |
1123 | case TRANS_TX_OPEN_RETRY_ERR: |
1124 | { |
1125 | ts->stat = SAS_OPEN_REJECT; |
1126 | ts->open_rej_reason = SAS_OREJ_UNKNOWN; |
1127 | break; |
1128 | } |
1129 | case TRANS_TX_OPEN_TIMEOUT_ERR: |
1130 | { |
1131 | ts->stat = SAS_OPEN_TO; |
1132 | break; |
1133 | } |
1134 | case TRANS_TX_NAK_RECEIVE_ERR: |
1135 | case TRANS_TX_ACK_NAK_TIMEOUT_ERR: |
1136 | { |
1137 | ts->stat = SAS_NAK_R_ERR; |
1138 | break; |
1139 | } |
1140 | case TRANS_TX_CREDIT_TIMEOUT_ERR: |
1141 | case TRANS_TX_CLOSE_NORMAL_ERR: |
1142 | { |
1143 | /* This will request a retry */ |
1144 | ts->stat = SAS_QUEUE_FULL; |
1145 | slot->abort = 1; |
1146 | break; |
1147 | } |
1148 | default: |
1149 | { |
1150 | ts->stat = SAS_SAM_STAT_CHECK_CONDITION; |
1151 | break; |
1152 | } |
1153 | } |
1154 | } |
1155 | break; |
1156 | case SAS_PROTOCOL_SMP: |
1157 | ts->stat = SAS_SAM_STAT_CHECK_CONDITION; |
1158 | break; |
1159 | |
1160 | case SAS_PROTOCOL_SATA: |
1161 | case SAS_PROTOCOL_STP: |
1162 | case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: |
1163 | { |
1164 | dev_err(dev, "slot err: SATA/STP not supported\n" ); |
1165 | } |
1166 | break; |
1167 | default: |
1168 | break; |
1169 | } |
1170 | |
1171 | } |
1172 | |
1173 | static void slot_complete_v1_hw(struct hisi_hba *hisi_hba, |
1174 | struct hisi_sas_slot *slot) |
1175 | { |
1176 | struct sas_task *task = slot->task; |
1177 | struct hisi_sas_device *sas_dev; |
1178 | struct device *dev = hisi_hba->dev; |
1179 | struct task_status_struct *ts; |
1180 | struct domain_device *device; |
1181 | struct hisi_sas_complete_v1_hdr *complete_queue = |
1182 | hisi_hba->complete_hdr[slot->cmplt_queue]; |
1183 | struct hisi_sas_complete_v1_hdr *complete_hdr; |
1184 | unsigned long flags; |
1185 | u32 cmplt_hdr_data; |
1186 | |
1187 | complete_hdr = &complete_queue[slot->cmplt_queue_slot]; |
1188 | cmplt_hdr_data = le32_to_cpu(complete_hdr->data); |
1189 | |
1190 | if (unlikely(!task || !task->lldd_task || !task->dev)) |
1191 | return; |
1192 | |
1193 | ts = &task->task_status; |
1194 | device = task->dev; |
1195 | sas_dev = device->lldd_dev; |
1196 | |
1197 | spin_lock_irqsave(&task->task_state_lock, flags); |
1198 | task->task_state_flags &= ~SAS_TASK_STATE_PENDING; |
1199 | task->task_state_flags |= SAS_TASK_STATE_DONE; |
1200 | spin_unlock_irqrestore(lock: &task->task_state_lock, flags); |
1201 | |
1202 | memset(ts, 0, sizeof(*ts)); |
1203 | ts->resp = SAS_TASK_COMPLETE; |
1204 | |
1205 | if (unlikely(!sas_dev)) { |
1206 | dev_dbg(dev, "slot complete: port has no device\n" ); |
1207 | ts->stat = SAS_PHY_DOWN; |
1208 | goto out; |
1209 | } |
1210 | |
1211 | if (cmplt_hdr_data & CMPLT_HDR_IO_CFG_ERR_MSK) { |
1212 | u32 info_reg = hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO); |
1213 | |
1214 | if (info_reg & HGC_INVLD_DQE_INFO_DQ_MSK) |
1215 | dev_err(dev, "slot complete: [%d:%d] has dq IPTT err\n" , |
1216 | slot->cmplt_queue, slot->cmplt_queue_slot); |
1217 | |
1218 | if (info_reg & HGC_INVLD_DQE_INFO_TYPE_MSK) |
1219 | dev_err(dev, "slot complete: [%d:%d] has dq type err\n" , |
1220 | slot->cmplt_queue, slot->cmplt_queue_slot); |
1221 | |
1222 | if (info_reg & HGC_INVLD_DQE_INFO_FORCE_MSK) |
1223 | dev_err(dev, "slot complete: [%d:%d] has dq force phy err\n" , |
1224 | slot->cmplt_queue, slot->cmplt_queue_slot); |
1225 | |
1226 | if (info_reg & HGC_INVLD_DQE_INFO_PHY_MSK) |
1227 | dev_err(dev, "slot complete: [%d:%d] has dq phy id err\n" , |
1228 | slot->cmplt_queue, slot->cmplt_queue_slot); |
1229 | |
1230 | if (info_reg & HGC_INVLD_DQE_INFO_ABORT_MSK) |
1231 | dev_err(dev, "slot complete: [%d:%d] has dq abort flag err\n" , |
1232 | slot->cmplt_queue, slot->cmplt_queue_slot); |
1233 | |
1234 | if (info_reg & HGC_INVLD_DQE_INFO_IPTT_OF_MSK) |
1235 | dev_err(dev, "slot complete: [%d:%d] has dq IPTT or ICT err\n" , |
1236 | slot->cmplt_queue, slot->cmplt_queue_slot); |
1237 | |
1238 | if (info_reg & HGC_INVLD_DQE_INFO_SSP_ERR_MSK) |
1239 | dev_err(dev, "slot complete: [%d:%d] has dq SSP frame type err\n" , |
1240 | slot->cmplt_queue, slot->cmplt_queue_slot); |
1241 | |
1242 | if (info_reg & HGC_INVLD_DQE_INFO_OFL_MSK) |
1243 | dev_err(dev, "slot complete: [%d:%d] has dq order frame len err\n" , |
1244 | slot->cmplt_queue, slot->cmplt_queue_slot); |
1245 | |
1246 | ts->stat = SAS_OPEN_REJECT; |
1247 | ts->open_rej_reason = SAS_OREJ_UNKNOWN; |
1248 | goto out; |
1249 | } |
1250 | |
1251 | if (cmplt_hdr_data & CMPLT_HDR_ERR_RCRD_XFRD_MSK && |
1252 | !(cmplt_hdr_data & CMPLT_HDR_RSPNS_XFRD_MSK)) { |
1253 | |
1254 | slot_err_v1_hw(hisi_hba, task, slot); |
1255 | if (unlikely(slot->abort)) { |
1256 | if (dev_is_sata(dev: device) && task->ata_task.use_ncq) |
1257 | sas_ata_device_link_abort(dev: device, force_reset: true); |
1258 | else |
1259 | sas_task_abort(task); |
1260 | |
1261 | return; |
1262 | } |
1263 | goto out; |
1264 | } |
1265 | |
1266 | switch (task->task_proto) { |
1267 | case SAS_PROTOCOL_SSP: |
1268 | { |
1269 | struct hisi_sas_status_buffer *status_buffer = |
1270 | hisi_sas_status_buf_addr_mem(slot); |
1271 | struct ssp_response_iu *iu = (struct ssp_response_iu *) |
1272 | &status_buffer->iu[0]; |
1273 | |
1274 | sas_ssp_task_response(dev, task, iu); |
1275 | break; |
1276 | } |
1277 | case SAS_PROTOCOL_SMP: |
1278 | { |
1279 | struct scatterlist *sg_resp = &task->smp_task.smp_resp; |
1280 | void *to = page_address(sg_page(sg_resp)); |
1281 | |
1282 | ts->stat = SAS_SAM_STAT_GOOD; |
1283 | |
1284 | memcpy(to + sg_resp->offset, |
1285 | hisi_sas_status_buf_addr_mem(slot) + |
1286 | sizeof(struct hisi_sas_err_record), |
1287 | sg_resp->length); |
1288 | break; |
1289 | } |
1290 | case SAS_PROTOCOL_SATA: |
1291 | case SAS_PROTOCOL_STP: |
1292 | case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: |
1293 | dev_err(dev, "slot complete: SATA/STP not supported\n" ); |
1294 | break; |
1295 | |
1296 | default: |
1297 | ts->stat = SAS_SAM_STAT_CHECK_CONDITION; |
1298 | break; |
1299 | } |
1300 | |
1301 | if (!slot->port->port_attached) { |
1302 | dev_err(dev, "slot complete: port %d has removed\n" , |
1303 | slot->port->sas_port.id); |
1304 | ts->stat = SAS_PHY_DOWN; |
1305 | } |
1306 | |
1307 | out: |
1308 | hisi_sas_slot_task_free(hisi_hba, task, slot, need_lock: true); |
1309 | |
1310 | if (task->task_done) |
1311 | task->task_done(task); |
1312 | } |
1313 | |
1314 | /* Interrupts */ |
1315 | static irqreturn_t int_phyup_v1_hw(int irq_no, void *p) |
1316 | { |
1317 | struct hisi_sas_phy *phy = p; |
1318 | struct hisi_hba *hisi_hba = phy->hisi_hba; |
1319 | struct device *dev = hisi_hba->dev; |
1320 | struct asd_sas_phy *sas_phy = &phy->sas_phy; |
1321 | int i, phy_no = sas_phy->id; |
1322 | u32 irq_value, context, port_id, link_rate; |
1323 | u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd; |
1324 | struct sas_identify_frame *id = (struct sas_identify_frame *)frame_rcvd; |
1325 | irqreturn_t res = IRQ_HANDLED; |
1326 | |
1327 | irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2); |
1328 | if (!(irq_value & CHL_INT2_SL_PHY_ENA_MSK)) { |
1329 | dev_dbg(dev, "phyup: irq_value = %x not set enable bit\n" , |
1330 | irq_value); |
1331 | res = IRQ_NONE; |
1332 | goto end; |
1333 | } |
1334 | |
1335 | context = hisi_sas_read32(hisi_hba, PHY_CONTEXT); |
1336 | if (context & 1 << phy_no) { |
1337 | dev_err(dev, "phyup: phy%d SATA attached equipment\n" , |
1338 | phy_no); |
1339 | goto end; |
1340 | } |
1341 | |
1342 | port_id = (hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA) >> (4 * phy_no)) |
1343 | & 0xf; |
1344 | if (port_id == 0xf) { |
1345 | dev_err(dev, "phyup: phy%d invalid portid\n" , phy_no); |
1346 | res = IRQ_NONE; |
1347 | goto end; |
1348 | } |
1349 | |
1350 | for (i = 0; i < 6; i++) { |
1351 | u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no, |
1352 | RX_IDAF_DWORD0 + (i * 4)); |
1353 | frame_rcvd[i] = __swab32(idaf); |
1354 | } |
1355 | |
1356 | /* Get the linkrate */ |
1357 | link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE); |
1358 | link_rate = (link_rate >> (phy_no * 4)) & 0xf; |
1359 | sas_phy->linkrate = link_rate; |
1360 | sas_phy->oob_mode = SAS_OOB_MODE; |
1361 | memcpy(sas_phy->attached_sas_addr, |
1362 | &id->sas_addr, SAS_ADDR_SIZE); |
1363 | dev_info(dev, "phyup: phy%d link_rate=%d\n" , |
1364 | phy_no, link_rate); |
1365 | phy->port_id = port_id; |
1366 | phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA); |
1367 | phy->phy_type |= PORT_TYPE_SAS; |
1368 | phy->phy_attached = 1; |
1369 | phy->identify.device_type = id->dev_type; |
1370 | phy->frame_rcvd_size = sizeof(struct sas_identify_frame); |
1371 | if (phy->identify.device_type == SAS_END_DEVICE) |
1372 | phy->identify.target_port_protocols = |
1373 | SAS_PROTOCOL_SSP; |
1374 | else if (phy->identify.device_type != SAS_PHY_UNUSED) |
1375 | phy->identify.target_port_protocols = |
1376 | SAS_PROTOCOL_SMP; |
1377 | hisi_sas_notify_phy_event(phy, event: HISI_PHYE_PHY_UP); |
1378 | end: |
1379 | if (phy->reset_completion) |
1380 | complete(phy->reset_completion); |
1381 | hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, |
1382 | CHL_INT2_SL_PHY_ENA_MSK); |
1383 | |
1384 | if (irq_value & CHL_INT2_SL_PHY_ENA_MSK) { |
1385 | u32 chl_int0 = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0); |
1386 | |
1387 | chl_int0 &= ~CHL_INT0_PHYCTRL_NOTRDY_MSK; |
1388 | hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, val: chl_int0); |
1389 | hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK, val: 0x3ce3ee); |
1390 | } |
1391 | |
1392 | return res; |
1393 | } |
1394 | |
1395 | static irqreturn_t int_bcast_v1_hw(int irq, void *p) |
1396 | { |
1397 | struct hisi_sas_phy *phy = p; |
1398 | struct hisi_hba *hisi_hba = phy->hisi_hba; |
1399 | struct asd_sas_phy *sas_phy = &phy->sas_phy; |
1400 | struct device *dev = hisi_hba->dev; |
1401 | int phy_no = sas_phy->id; |
1402 | u32 irq_value; |
1403 | irqreturn_t res = IRQ_HANDLED; |
1404 | |
1405 | irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2); |
1406 | |
1407 | if (!(irq_value & CHL_INT2_SL_RX_BC_ACK_MSK)) { |
1408 | dev_err(dev, "bcast: irq_value = %x not set enable bit\n" , |
1409 | irq_value); |
1410 | res = IRQ_NONE; |
1411 | goto end; |
1412 | } |
1413 | |
1414 | hisi_sas_phy_bcast(phy); |
1415 | |
1416 | end: |
1417 | hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, |
1418 | CHL_INT2_SL_RX_BC_ACK_MSK); |
1419 | |
1420 | return res; |
1421 | } |
1422 | |
1423 | static irqreturn_t int_abnormal_v1_hw(int irq, void *p) |
1424 | { |
1425 | struct hisi_sas_phy *phy = p; |
1426 | struct hisi_hba *hisi_hba = phy->hisi_hba; |
1427 | struct device *dev = hisi_hba->dev; |
1428 | struct asd_sas_phy *sas_phy = &phy->sas_phy; |
1429 | u32 irq_value, irq_mask_old; |
1430 | int phy_no = sas_phy->id; |
1431 | |
1432 | /* mask_int0 */ |
1433 | irq_mask_old = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0_MSK); |
1434 | hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK, val: 0x3fffff); |
1435 | |
1436 | /* read int0 */ |
1437 | irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0); |
1438 | |
1439 | if (irq_value & CHL_INT0_PHYCTRL_NOTRDY_MSK) { |
1440 | u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); |
1441 | |
1442 | hisi_sas_phy_down(hisi_hba, phy_no, |
1443 | rdy: (phy_state & 1 << phy_no) ? 1 : 0, |
1444 | GFP_ATOMIC); |
1445 | } |
1446 | |
1447 | if (irq_value & CHL_INT0_ID_TIMEOUT_MSK) |
1448 | dev_dbg(dev, "abnormal: ID_TIMEOUT phy%d identify timeout\n" , |
1449 | phy_no); |
1450 | |
1451 | if (irq_value & CHL_INT0_DWS_LOST_MSK) |
1452 | dev_dbg(dev, "abnormal: DWS_LOST phy%d dws lost\n" , phy_no); |
1453 | |
1454 | if (irq_value & CHL_INT0_SN_FAIL_NGR_MSK) |
1455 | dev_dbg(dev, "abnormal: SN_FAIL_NGR phy%d sn fail ngr\n" , |
1456 | phy_no); |
1457 | |
1458 | if (irq_value & CHL_INT0_SL_IDAF_FAIL_MSK || |
1459 | irq_value & CHL_INT0_SL_OPAF_FAIL_MSK) |
1460 | dev_dbg(dev, "abnormal: SL_ID/OPAF_FAIL phy%d check adr frm err\n" , |
1461 | phy_no); |
1462 | |
1463 | if (irq_value & CHL_INT0_SL_PS_FAIL_OFF) |
1464 | dev_dbg(dev, "abnormal: SL_PS_FAIL phy%d fail\n" , phy_no); |
1465 | |
1466 | /* write to zero */ |
1467 | hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, val: irq_value); |
1468 | |
1469 | if (irq_value & CHL_INT0_PHYCTRL_NOTRDY_MSK) |
1470 | hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK, |
1471 | val: 0x3fffff & ~CHL_INT0_MSK_PHYCTRL_NOTRDY_MSK); |
1472 | else |
1473 | hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK, |
1474 | val: irq_mask_old); |
1475 | |
1476 | return IRQ_HANDLED; |
1477 | } |
1478 | |
1479 | static irqreturn_t cq_interrupt_v1_hw(int irq, void *p) |
1480 | { |
1481 | struct hisi_sas_cq *cq = p; |
1482 | struct hisi_hba *hisi_hba = cq->hisi_hba; |
1483 | struct hisi_sas_slot *slot; |
1484 | int queue = cq->id; |
1485 | struct hisi_sas_complete_v1_hdr *complete_queue = |
1486 | (struct hisi_sas_complete_v1_hdr *) |
1487 | hisi_hba->complete_hdr[queue]; |
1488 | u32 rd_point = cq->rd_point, wr_point; |
1489 | |
1490 | spin_lock(lock: &hisi_hba->lock); |
1491 | hisi_sas_write32(hisi_hba, OQ_INT_SRC, val: 1 << queue); |
1492 | wr_point = hisi_sas_read32(hisi_hba, |
1493 | COMPL_Q_0_WR_PTR + (0x14 * queue)); |
1494 | |
1495 | while (rd_point != wr_point) { |
1496 | struct hisi_sas_complete_v1_hdr *complete_hdr; |
1497 | int idx; |
1498 | u32 cmplt_hdr_data; |
1499 | |
1500 | complete_hdr = &complete_queue[rd_point]; |
1501 | cmplt_hdr_data = le32_to_cpu(complete_hdr->data); |
1502 | idx = (cmplt_hdr_data & CMPLT_HDR_IPTT_MSK) >> |
1503 | CMPLT_HDR_IPTT_OFF; |
1504 | slot = &hisi_hba->slot_info[idx]; |
1505 | |
1506 | /* The completion queue and queue slot index are not |
1507 | * necessarily the same as the delivery queue and |
1508 | * queue slot index. |
1509 | */ |
1510 | slot->cmplt_queue_slot = rd_point; |
1511 | slot->cmplt_queue = queue; |
1512 | slot_complete_v1_hw(hisi_hba, slot); |
1513 | |
1514 | if (++rd_point >= HISI_SAS_QUEUE_SLOTS) |
1515 | rd_point = 0; |
1516 | } |
1517 | |
1518 | /* update rd_point */ |
1519 | cq->rd_point = rd_point; |
1520 | hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), val: rd_point); |
1521 | spin_unlock(lock: &hisi_hba->lock); |
1522 | |
1523 | return IRQ_HANDLED; |
1524 | } |
1525 | |
1526 | static irqreturn_t fatal_ecc_int_v1_hw(int irq, void *p) |
1527 | { |
1528 | struct hisi_hba *hisi_hba = p; |
1529 | struct device *dev = hisi_hba->dev; |
1530 | u32 ecc_int = hisi_sas_read32(hisi_hba, SAS_ECC_INTR); |
1531 | |
1532 | if (ecc_int & SAS_ECC_INTR_DQ_ECC1B_MSK) { |
1533 | u32 ecc_err = hisi_sas_read32(hisi_hba, HGC_ECC_ERR); |
1534 | |
1535 | panic(fmt: "%s: Fatal DQ 1b ECC interrupt (0x%x)\n" , |
1536 | dev_name(dev), ecc_err); |
1537 | } |
1538 | |
1539 | if (ecc_int & SAS_ECC_INTR_DQ_ECCBAD_MSK) { |
1540 | u32 addr = (hisi_sas_read32(hisi_hba, HGC_DQ_ECC_ADDR) & |
1541 | HGC_DQ_ECC_ADDR_BAD_MSK) >> |
1542 | HGC_DQ_ECC_ADDR_BAD_OFF; |
1543 | |
1544 | panic(fmt: "%s: Fatal DQ RAM ECC interrupt @ 0x%08x\n" , |
1545 | dev_name(dev), addr); |
1546 | } |
1547 | |
1548 | if (ecc_int & SAS_ECC_INTR_IOST_ECC1B_MSK) { |
1549 | u32 ecc_err = hisi_sas_read32(hisi_hba, HGC_ECC_ERR); |
1550 | |
1551 | panic(fmt: "%s: Fatal IOST 1b ECC interrupt (0x%x)\n" , |
1552 | dev_name(dev), ecc_err); |
1553 | } |
1554 | |
1555 | if (ecc_int & SAS_ECC_INTR_IOST_ECCBAD_MSK) { |
1556 | u32 addr = (hisi_sas_read32(hisi_hba, HGC_IOST_ECC_ADDR) & |
1557 | HGC_IOST_ECC_ADDR_BAD_MSK) >> |
1558 | HGC_IOST_ECC_ADDR_BAD_OFF; |
1559 | |
1560 | panic(fmt: "%s: Fatal IOST RAM ECC interrupt @ 0x%08x\n" , |
1561 | dev_name(dev), addr); |
1562 | } |
1563 | |
1564 | if (ecc_int & SAS_ECC_INTR_ITCT_ECCBAD_MSK) { |
1565 | u32 addr = (hisi_sas_read32(hisi_hba, HGC_ITCT_ECC_ADDR) & |
1566 | HGC_ITCT_ECC_ADDR_BAD_MSK) >> |
1567 | HGC_ITCT_ECC_ADDR_BAD_OFF; |
1568 | |
1569 | panic(fmt: "%s: Fatal TCT RAM ECC interrupt @ 0x%08x\n" , |
1570 | dev_name(dev), addr); |
1571 | } |
1572 | |
1573 | if (ecc_int & SAS_ECC_INTR_ITCT_ECC1B_MSK) { |
1574 | u32 ecc_err = hisi_sas_read32(hisi_hba, HGC_ECC_ERR); |
1575 | |
1576 | panic(fmt: "%s: Fatal ITCT 1b ECC interrupt (0x%x)\n" , |
1577 | dev_name(dev), ecc_err); |
1578 | } |
1579 | |
1580 | hisi_sas_write32(hisi_hba, SAS_ECC_INTR, val: ecc_int | 0x3f); |
1581 | |
1582 | return IRQ_HANDLED; |
1583 | } |
1584 | |
1585 | static irqreturn_t fatal_axi_int_v1_hw(int irq, void *p) |
1586 | { |
1587 | struct hisi_hba *hisi_hba = p; |
1588 | struct device *dev = hisi_hba->dev; |
1589 | u32 axi_int = hisi_sas_read32(hisi_hba, ENT_INT_SRC2); |
1590 | u32 axi_info = hisi_sas_read32(hisi_hba, HGC_AXI_FIFO_ERR_INFO); |
1591 | |
1592 | if (axi_int & ENT_INT_SRC2_DQ_CFG_ERR_MSK) |
1593 | panic(fmt: "%s: Fatal DQ_CFG_ERR interrupt (0x%x)\n" , |
1594 | dev_name(dev), axi_info); |
1595 | |
1596 | if (axi_int & ENT_INT_SRC2_CQ_CFG_ERR_MSK) |
1597 | panic(fmt: "%s: Fatal CQ_CFG_ERR interrupt (0x%x)\n" , |
1598 | dev_name(dev), axi_info); |
1599 | |
1600 | if (axi_int & ENT_INT_SRC2_AXI_WRONG_INT_MSK) |
1601 | panic(fmt: "%s: Fatal AXI_WRONG_INT interrupt (0x%x)\n" , |
1602 | dev_name(dev), axi_info); |
1603 | |
1604 | if (axi_int & ENT_INT_SRC2_AXI_OVERLF_INT_MSK) |
1605 | panic(fmt: "%s: Fatal AXI_OVERLF_INT incorrect interrupt (0x%x)\n" , |
1606 | dev_name(dev), axi_info); |
1607 | |
1608 | hisi_sas_write32(hisi_hba, ENT_INT_SRC2, val: axi_int | 0x30000000); |
1609 | |
1610 | return IRQ_HANDLED; |
1611 | } |
1612 | |
1613 | static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = { |
1614 | int_bcast_v1_hw, |
1615 | int_phyup_v1_hw, |
1616 | int_abnormal_v1_hw |
1617 | }; |
1618 | |
1619 | static irq_handler_t fatal_interrupts[HISI_SAS_MAX_QUEUES] = { |
1620 | fatal_ecc_int_v1_hw, |
1621 | fatal_axi_int_v1_hw |
1622 | }; |
1623 | |
1624 | static int interrupt_init_v1_hw(struct hisi_hba *hisi_hba) |
1625 | { |
1626 | struct platform_device *pdev = hisi_hba->platform_dev; |
1627 | struct device *dev = &pdev->dev; |
1628 | int i, j, irq, rc, idx; |
1629 | |
1630 | for (i = 0; i < hisi_hba->n_phy; i++) { |
1631 | struct hisi_sas_phy *phy = &hisi_hba->phy[i]; |
1632 | |
1633 | idx = i * HISI_SAS_PHY_INT_NR; |
1634 | for (j = 0; j < HISI_SAS_PHY_INT_NR; j++, idx++) { |
1635 | irq = platform_get_irq(pdev, idx); |
1636 | if (irq < 0) |
1637 | return irq; |
1638 | |
1639 | rc = devm_request_irq(dev, irq, handler: phy_interrupts[j], irqflags: 0, |
1640 | DRV_NAME " phy" , dev_id: phy); |
1641 | if (rc) { |
1642 | dev_err(dev, "irq init: could not request phy interrupt %d, rc=%d\n" , |
1643 | irq, rc); |
1644 | return rc; |
1645 | } |
1646 | } |
1647 | } |
1648 | |
1649 | idx = hisi_hba->n_phy * HISI_SAS_PHY_INT_NR; |
1650 | for (i = 0; i < hisi_hba->queue_count; i++, idx++) { |
1651 | irq = platform_get_irq(pdev, idx); |
1652 | if (irq < 0) |
1653 | return irq; |
1654 | |
1655 | rc = devm_request_irq(dev, irq, handler: cq_interrupt_v1_hw, irqflags: 0, |
1656 | DRV_NAME " cq" , dev_id: &hisi_hba->cq[i]); |
1657 | if (rc) { |
1658 | dev_err(dev, "irq init: could not request cq interrupt %d, rc=%d\n" , |
1659 | irq, rc); |
1660 | return rc; |
1661 | } |
1662 | } |
1663 | |
1664 | idx = (hisi_hba->n_phy * HISI_SAS_PHY_INT_NR) + hisi_hba->queue_count; |
1665 | for (i = 0; i < HISI_SAS_FATAL_INT_NR; i++, idx++) { |
1666 | irq = platform_get_irq(pdev, idx); |
1667 | if (irq < 0) |
1668 | return irq; |
1669 | |
1670 | rc = devm_request_irq(dev, irq, handler: fatal_interrupts[i], irqflags: 0, |
1671 | DRV_NAME " fatal" , dev_id: hisi_hba); |
1672 | if (rc) { |
1673 | dev_err(dev, "irq init: could not request fatal interrupt %d, rc=%d\n" , |
1674 | irq, rc); |
1675 | return rc; |
1676 | } |
1677 | } |
1678 | |
1679 | hisi_hba->cq_nvecs = hisi_hba->queue_count; |
1680 | |
1681 | return 0; |
1682 | } |
1683 | |
1684 | static int interrupt_openall_v1_hw(struct hisi_hba *hisi_hba) |
1685 | { |
1686 | int i; |
1687 | u32 val; |
1688 | |
1689 | for (i = 0; i < hisi_hba->n_phy; i++) { |
1690 | /* Clear interrupt status */ |
1691 | val = hisi_sas_phy_read32(hisi_hba, phy_no: i, CHL_INT0); |
1692 | hisi_sas_phy_write32(hisi_hba, phy_no: i, CHL_INT0, val); |
1693 | val = hisi_sas_phy_read32(hisi_hba, phy_no: i, CHL_INT1); |
1694 | hisi_sas_phy_write32(hisi_hba, phy_no: i, CHL_INT1, val); |
1695 | val = hisi_sas_phy_read32(hisi_hba, phy_no: i, CHL_INT2); |
1696 | hisi_sas_phy_write32(hisi_hba, phy_no: i, CHL_INT2, val); |
1697 | |
1698 | /* Unmask interrupt */ |
1699 | hisi_sas_phy_write32(hisi_hba, phy_no: i, CHL_INT0_MSK, val: 0x3ce3ee); |
1700 | hisi_sas_phy_write32(hisi_hba, phy_no: i, CHL_INT1_MSK, val: 0x17fff); |
1701 | hisi_sas_phy_write32(hisi_hba, phy_no: i, CHL_INT2_MSK, val: 0x8000012a); |
1702 | |
1703 | /* bypass chip bug mask abnormal intr */ |
1704 | hisi_sas_phy_write32(hisi_hba, phy_no: i, CHL_INT0_MSK, |
1705 | val: 0x3fffff & ~CHL_INT0_MSK_PHYCTRL_NOTRDY_MSK); |
1706 | } |
1707 | |
1708 | return 0; |
1709 | } |
1710 | |
1711 | static int hisi_sas_v1_init(struct hisi_hba *hisi_hba) |
1712 | { |
1713 | int rc; |
1714 | |
1715 | rc = hw_init_v1_hw(hisi_hba); |
1716 | if (rc) |
1717 | return rc; |
1718 | |
1719 | rc = interrupt_init_v1_hw(hisi_hba); |
1720 | if (rc) |
1721 | return rc; |
1722 | |
1723 | rc = interrupt_openall_v1_hw(hisi_hba); |
1724 | if (rc) |
1725 | return rc; |
1726 | |
1727 | return 0; |
1728 | } |
1729 | |
1730 | static struct attribute *host_v1_hw_attrs[] = { |
1731 | &dev_attr_phy_event_threshold.attr, |
1732 | NULL |
1733 | }; |
1734 | |
1735 | ATTRIBUTE_GROUPS(host_v1_hw); |
1736 | |
1737 | static const struct scsi_host_template sht_v1_hw = { |
1738 | .name = DRV_NAME, |
1739 | .proc_name = DRV_NAME, |
1740 | .module = THIS_MODULE, |
1741 | .queuecommand = sas_queuecommand, |
1742 | .dma_need_drain = ata_scsi_dma_need_drain, |
1743 | .target_alloc = sas_target_alloc, |
1744 | .slave_configure = hisi_sas_slave_configure, |
1745 | .scan_finished = hisi_sas_scan_finished, |
1746 | .scan_start = hisi_sas_scan_start, |
1747 | .change_queue_depth = sas_change_queue_depth, |
1748 | .bios_param = sas_bios_param, |
1749 | .this_id = -1, |
1750 | .sg_tablesize = HISI_SAS_SGE_PAGE_CNT, |
1751 | .max_sectors = SCSI_DEFAULT_MAX_SECTORS, |
1752 | .eh_device_reset_handler = sas_eh_device_reset_handler, |
1753 | .eh_target_reset_handler = sas_eh_target_reset_handler, |
1754 | .slave_alloc = hisi_sas_slave_alloc, |
1755 | .target_destroy = sas_target_destroy, |
1756 | .ioctl = sas_ioctl, |
1757 | #ifdef CONFIG_COMPAT |
1758 | .compat_ioctl = sas_ioctl, |
1759 | #endif |
1760 | .shost_groups = host_v1_hw_groups, |
1761 | .host_reset = hisi_sas_host_reset, |
1762 | }; |
1763 | |
1764 | static const struct hisi_sas_hw hisi_sas_v1_hw = { |
1765 | .hw_init = hisi_sas_v1_init, |
1766 | .setup_itct = setup_itct_v1_hw, |
1767 | .sl_notify_ssp = sl_notify_ssp_v1_hw, |
1768 | .clear_itct = clear_itct_v1_hw, |
1769 | .prep_smp = prep_smp_v1_hw, |
1770 | .prep_ssp = prep_ssp_v1_hw, |
1771 | .start_delivery = start_delivery_v1_hw, |
1772 | .phys_init = phys_init_v1_hw, |
1773 | .phy_start = start_phy_v1_hw, |
1774 | .phy_disable = disable_phy_v1_hw, |
1775 | .phy_hard_reset = phy_hard_reset_v1_hw, |
1776 | .phy_set_linkrate = phy_set_linkrate_v1_hw, |
1777 | .phy_get_max_linkrate = phy_get_max_linkrate_v1_hw, |
1778 | .get_wideport_bitmap = get_wideport_bitmap_v1_hw, |
1779 | .complete_hdr_size = sizeof(struct hisi_sas_complete_v1_hdr), |
1780 | .sht = &sht_v1_hw, |
1781 | }; |
1782 | |
1783 | static int hisi_sas_v1_probe(struct platform_device *pdev) |
1784 | { |
1785 | return hisi_sas_probe(pdev, ops: &hisi_sas_v1_hw); |
1786 | } |
1787 | |
1788 | static const struct of_device_id sas_v1_of_match[] = { |
1789 | { .compatible = "hisilicon,hip05-sas-v1" ,}, |
1790 | {}, |
1791 | }; |
1792 | MODULE_DEVICE_TABLE(of, sas_v1_of_match); |
1793 | |
1794 | static const struct acpi_device_id sas_v1_acpi_match[] = { |
1795 | { "HISI0161" , 0 }, |
1796 | { } |
1797 | }; |
1798 | |
1799 | MODULE_DEVICE_TABLE(acpi, sas_v1_acpi_match); |
1800 | |
1801 | static struct platform_driver hisi_sas_v1_driver = { |
1802 | .probe = hisi_sas_v1_probe, |
1803 | .remove_new = hisi_sas_remove, |
1804 | .driver = { |
1805 | .name = DRV_NAME, |
1806 | .of_match_table = sas_v1_of_match, |
1807 | .acpi_match_table = ACPI_PTR(sas_v1_acpi_match), |
1808 | }, |
1809 | }; |
1810 | |
1811 | module_platform_driver(hisi_sas_v1_driver); |
1812 | |
1813 | MODULE_LICENSE("GPL" ); |
1814 | MODULE_AUTHOR("John Garry <john.garry@huawei.com>" ); |
1815 | MODULE_DESCRIPTION("HISILICON SAS controller v1 hw driver" ); |
1816 | MODULE_ALIAS("platform:" DRV_NAME); |
1817 | |