1/*
2 * Disk Array driver for HP Smart Array SAS controllers
3 * Copyright 2016 Microsemi Corporation
4 * Copyright 2014-2015 PMC-Sierra, Inc.
5 * Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
14 * NON INFRINGEMENT. See the GNU General Public License for more details.
15 *
16 * Questions/Comments/Bugfixes to esc.storagedev@microsemi.com
17 *
18 */
19#ifndef HPSA_CMD_H
20#define HPSA_CMD_H
21
22/* general boundary defintions */
23#define SENSEINFOBYTES 32 /* may vary between hbas */
24#define SG_ENTRIES_IN_CMD 32 /* Max SG entries excluding chain blocks */
25#define HPSA_SG_CHAIN 0x80000000
26#define HPSA_SG_LAST 0x40000000
27#define MAXREPLYQS 256
28
29/* Command Status value */
30#define CMD_SUCCESS 0x0000
31#define CMD_TARGET_STATUS 0x0001
32#define CMD_DATA_UNDERRUN 0x0002
33#define CMD_DATA_OVERRUN 0x0003
34#define CMD_INVALID 0x0004
35#define CMD_PROTOCOL_ERR 0x0005
36#define CMD_HARDWARE_ERR 0x0006
37#define CMD_CONNECTION_LOST 0x0007
38#define CMD_ABORTED 0x0008
39#define CMD_ABORT_FAILED 0x0009
40#define CMD_UNSOLICITED_ABORT 0x000A
41#define CMD_TIMEOUT 0x000B
42#define CMD_UNABORTABLE 0x000C
43#define CMD_TMF_STATUS 0x000D
44#define CMD_IOACCEL_DISABLED 0x000E
45#define CMD_CTLR_LOCKUP 0xffff
46/* Note: CMD_CTLR_LOCKUP is not a value defined by the CISS spec
47 * it is a value defined by the driver that commands can be marked
48 * with when a controller lockup has been detected by the driver
49 */
50
51/* TMF function status values */
52#define CISS_TMF_COMPLETE 0x00
53#define CISS_TMF_INVALID_FRAME 0x02
54#define CISS_TMF_NOT_SUPPORTED 0x04
55#define CISS_TMF_FAILED 0x05
56#define CISS_TMF_SUCCESS 0x08
57#define CISS_TMF_WRONG_LUN 0x09
58#define CISS_TMF_OVERLAPPED_TAG 0x0a
59
60/* Unit Attentions ASC's as defined for the MSA2012sa */
61#define POWER_OR_RESET 0x29
62#define STATE_CHANGED 0x2a
63#define UNIT_ATTENTION_CLEARED 0x2f
64#define LUN_FAILED 0x3e
65#define REPORT_LUNS_CHANGED 0x3f
66
67/* Unit Attentions ASCQ's as defined for the MSA2012sa */
68
69 /* These ASCQ's defined for ASC = POWER_OR_RESET */
70#define POWER_ON_RESET 0x00
71#define POWER_ON_REBOOT 0x01
72#define SCSI_BUS_RESET 0x02
73#define MSA_TARGET_RESET 0x03
74#define CONTROLLER_FAILOVER 0x04
75#define TRANSCEIVER_SE 0x05
76#define TRANSCEIVER_LVD 0x06
77
78 /* These ASCQ's defined for ASC = STATE_CHANGED */
79#define RESERVATION_PREEMPTED 0x03
80#define ASYM_ACCESS_CHANGED 0x06
81#define LUN_CAPACITY_CHANGED 0x09
82
83/* transfer direction */
84#define XFER_NONE 0x00
85#define XFER_WRITE 0x01
86#define XFER_READ 0x02
87#define XFER_RSVD 0x03
88
89/* task attribute */
90#define ATTR_UNTAGGED 0x00
91#define ATTR_SIMPLE 0x04
92#define ATTR_HEADOFQUEUE 0x05
93#define ATTR_ORDERED 0x06
94#define ATTR_ACA 0x07
95
96/* cdb type */
97#define TYPE_CMD 0x00
98#define TYPE_MSG 0x01
99#define TYPE_IOACCEL2_CMD 0x81 /* 0x81 is not used by hardware */
100
101/* Message Types */
102#define HPSA_TASK_MANAGEMENT 0x00
103#define HPSA_RESET 0x01
104#define HPSA_SCAN 0x02
105#define HPSA_NOOP 0x03
106
107#define HPSA_CTLR_RESET_TYPE 0x00
108#define HPSA_BUS_RESET_TYPE 0x01
109#define HPSA_TARGET_RESET_TYPE 0x03
110#define HPSA_LUN_RESET_TYPE 0x04
111#define HPSA_NEXUS_RESET_TYPE 0x05
112
113/* Task Management Functions */
114#define HPSA_TMF_ABORT_TASK 0x00
115#define HPSA_TMF_ABORT_TASK_SET 0x01
116#define HPSA_TMF_CLEAR_ACA 0x02
117#define HPSA_TMF_CLEAR_TASK_SET 0x03
118#define HPSA_TMF_QUERY_TASK 0x04
119#define HPSA_TMF_QUERY_TASK_SET 0x05
120#define HPSA_TMF_QUERY_ASYNCEVENT 0x06
121
122
123
124/* config space register offsets */
125#define CFG_VENDORID 0x00
126#define CFG_DEVICEID 0x02
127#define CFG_I2OBAR 0x10
128#define CFG_MEM1BAR 0x14
129
130/* i2o space register offsets */
131#define I2O_IBDB_SET 0x20
132#define I2O_IBDB_CLEAR 0x70
133#define I2O_INT_STATUS 0x30
134#define I2O_INT_MASK 0x34
135#define I2O_IBPOST_Q 0x40
136#define I2O_OBPOST_Q 0x44
137#define I2O_DMA1_CFG 0x214
138
139/* Configuration Table */
140#define CFGTBL_ChangeReq 0x00000001l
141#define CFGTBL_AccCmds 0x00000001l
142#define DOORBELL_CTLR_RESET 0x00000004l
143#define DOORBELL_CTLR_RESET2 0x00000020l
144#define DOORBELL_CLEAR_EVENTS 0x00000040l
145#define DOORBELL_GENERATE_CHKPT 0x00000080l
146
147#define CFGTBL_Trans_Simple 0x00000002l
148#define CFGTBL_Trans_Performant 0x00000004l
149#define CFGTBL_Trans_io_accel1 0x00000080l
150#define CFGTBL_Trans_io_accel2 0x00000100l
151#define CFGTBL_Trans_use_short_tags 0x20000000l
152#define CFGTBL_Trans_enable_directed_msix (1 << 30)
153
154#define CFGTBL_BusType_Ultra2 0x00000001l
155#define CFGTBL_BusType_Ultra3 0x00000002l
156#define CFGTBL_BusType_Fibre1G 0x00000100l
157#define CFGTBL_BusType_Fibre2G 0x00000200l
158
159/* VPD Inquiry types */
160#define HPSA_INQUIRY_FAILED 0x02
161#define HPSA_VPD_SUPPORTED_PAGES 0x00
162#define HPSA_VPD_LV_DEVICE_ID 0x83
163#define HPSA_VPD_LV_DEVICE_GEOMETRY 0xC1
164#define HPSA_VPD_LV_IOACCEL_STATUS 0xC2
165#define HPSA_VPD_LV_STATUS 0xC3
166#define HPSA_VPD_HEADER_SZ 4
167
168/* Logical volume states */
169#define HPSA_VPD_LV_STATUS_UNSUPPORTED 0xff
170#define HPSA_LV_OK 0x0
171#define HPSA_LV_FAILED 0x01
172#define HPSA_LV_NOT_AVAILABLE 0x0b
173#define HPSA_LV_UNDERGOING_ERASE 0x0F
174#define HPSA_LV_UNDERGOING_RPI 0x12
175#define HPSA_LV_PENDING_RPI 0x13
176#define HPSA_LV_ENCRYPTED_NO_KEY 0x14
177#define HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER 0x15
178#define HPSA_LV_UNDERGOING_ENCRYPTION 0x16
179#define HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING 0x17
180#define HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER 0x18
181#define HPSA_LV_PENDING_ENCRYPTION 0x19
182#define HPSA_LV_PENDING_ENCRYPTION_REKEYING 0x1A
183
184struct vals32 {
185 u32 lower;
186 u32 upper;
187};
188
189union u64bit {
190 struct vals32 val32;
191 u64 val;
192};
193
194/* FIXME this is a per controller value (barf!) */
195#define HPSA_MAX_LUN 1024
196#define HPSA_MAX_PHYS_LUN 1024
197#define MAX_EXT_TARGETS 32
198#define HPSA_MAX_DEVICES (HPSA_MAX_PHYS_LUN + HPSA_MAX_LUN + \
199 MAX_EXT_TARGETS + 1) /* + 1 is for the controller itself */
200
201/* SCSI-3 Commands */
202#pragma pack(1)
203
204#define HPSA_INQUIRY 0x12
205struct InquiryData {
206 u8 data_byte[36];
207};
208
209#define HPSA_REPORT_LOG 0xc2 /* Report Logical LUNs */
210#define HPSA_REPORT_PHYS 0xc3 /* Report Physical LUNs */
211#define HPSA_REPORT_PHYS_EXTENDED 0x02
212#define HPSA_CISS_READ 0xc0 /* CISS Read */
213#define HPSA_GET_RAID_MAP 0xc8 /* CISS Get RAID Layout Map */
214
215#define RAID_MAP_MAX_ENTRIES 256
216
217struct raid_map_disk_data {
218 u32 ioaccel_handle; /**< Handle to access this disk via the
219 * I/O accelerator */
220 u8 xor_mult[2]; /**< XOR multipliers for this position,
221 * valid for data disks only */
222 u8 reserved[2];
223};
224
225struct raid_map_data {
226 __le32 structure_size; /* Size of entire structure in bytes */
227 __le32 volume_blk_size; /* bytes / block in the volume */
228 __le64 volume_blk_cnt; /* logical blocks on the volume */
229 u8 phys_blk_shift; /* Shift factor to convert between
230 * units of logical blocks and physical
231 * disk blocks */
232 u8 parity_rotation_shift; /* Shift factor to convert between units
233 * of logical stripes and physical
234 * stripes */
235 __le16 strip_size; /* blocks used on each disk / stripe */
236 __le64 disk_starting_blk; /* First disk block used in volume */
237 __le64 disk_blk_cnt; /* disk blocks used by volume / disk */
238 __le16 data_disks_per_row; /* data disk entries / row in the map */
239 __le16 metadata_disks_per_row;/* mirror/parity disk entries / row
240 * in the map */
241 __le16 row_cnt; /* rows in each layout map */
242 __le16 layout_map_count; /* layout maps (1 map per mirror/parity
243 * group) */
244 __le16 flags; /* Bit 0 set if encryption enabled */
245#define RAID_MAP_FLAG_ENCRYPT_ON 0x01
246 __le16 dekindex; /* Data encryption key index. */
247 u8 reserved[16];
248 struct raid_map_disk_data data[RAID_MAP_MAX_ENTRIES];
249};
250
251struct ReportLUNdata {
252 u8 LUNListLength[4];
253 u8 extended_response_flag;
254 u8 reserved[3];
255 u8 LUN[HPSA_MAX_LUN][8];
256};
257
258struct ext_report_lun_entry {
259 u8 lunid[8];
260#define MASKED_DEVICE(x) ((x)[3] & 0xC0)
261#define GET_BMIC_BUS(lunid) ((lunid)[7] & 0x3F)
262#define GET_BMIC_LEVEL_TWO_TARGET(lunid) ((lunid)[6])
263#define GET_BMIC_DRIVE_NUMBER(lunid) (((GET_BMIC_BUS((lunid)) - 1) << 8) + \
264 GET_BMIC_LEVEL_TWO_TARGET((lunid)))
265 u8 wwid[8];
266 u8 device_type;
267 u8 device_flags;
268 u8 lun_count; /* multi-lun device, how many luns */
269 u8 redundant_paths;
270 u32 ioaccel_handle; /* ioaccel1 only uses lower 16 bits */
271};
272
273struct ReportExtendedLUNdata {
274 u8 LUNListLength[4];
275 u8 extended_response_flag;
276 u8 reserved[3];
277 struct ext_report_lun_entry LUN[HPSA_MAX_PHYS_LUN];
278};
279
280struct SenseSubsystem_info {
281 u8 reserved[36];
282 u8 portname[8];
283 u8 reserved1[1108];
284};
285
286/* BMIC commands */
287#define BMIC_READ 0x26
288#define BMIC_WRITE 0x27
289#define BMIC_CACHE_FLUSH 0xc2
290#define HPSA_CACHE_FLUSH 0x01 /* C2 was already being used by HPSA */
291#define BMIC_FLASH_FIRMWARE 0xF7
292#define BMIC_SENSE_CONTROLLER_PARAMETERS 0x64
293#define BMIC_IDENTIFY_PHYSICAL_DEVICE 0x15
294#define BMIC_IDENTIFY_CONTROLLER 0x11
295#define BMIC_SET_DIAG_OPTIONS 0xF4
296#define BMIC_SENSE_DIAG_OPTIONS 0xF5
297#define HPSA_DIAG_OPTS_DISABLE_RLD_CACHING 0x80000000
298#define BMIC_SENSE_SUBSYSTEM_INFORMATION 0x66
299#define BMIC_SENSE_STORAGE_BOX_PARAMS 0x65
300
301/* Command List Structure */
302union SCSI3Addr {
303 struct {
304 u8 Dev;
305 u8 Bus:6;
306 u8 Mode:2; /* b00 */
307 } PeripDev;
308 struct {
309 u8 DevLSB;
310 u8 DevMSB:6;
311 u8 Mode:2; /* b01 */
312 } LogDev;
313 struct {
314 u8 Dev:5;
315 u8 Bus:3;
316 u8 Targ:6;
317 u8 Mode:2; /* b10 */
318 } LogUnit;
319};
320
321struct PhysDevAddr {
322 u32 TargetId:24;
323 u32 Bus:6;
324 u32 Mode:2;
325 /* 2 level target device addr */
326 union SCSI3Addr Target[2];
327};
328
329struct LogDevAddr {
330 u32 VolId:30;
331 u32 Mode:2;
332 u8 reserved[4];
333};
334
335union LUNAddr {
336 u8 LunAddrBytes[8];
337 union SCSI3Addr SCSI3Lun[4];
338 struct PhysDevAddr PhysDev;
339 struct LogDevAddr LogDev;
340};
341
342struct CommandListHeader {
343 u8 ReplyQueue;
344 u8 SGList;
345 __le16 SGTotal;
346 __le64 tag;
347 union LUNAddr LUN;
348};
349
350struct RequestBlock {
351 u8 CDBLen;
352 /*
353 * type_attr_dir:
354 * type: low 3 bits
355 * attr: middle 3 bits
356 * dir: high 2 bits
357 */
358 u8 type_attr_dir;
359#define TYPE_ATTR_DIR(t, a, d) ((((d) & 0x03) << 6) |\
360 (((a) & 0x07) << 3) |\
361 ((t) & 0x07))
362#define GET_TYPE(tad) ((tad) & 0x07)
363#define GET_ATTR(tad) (((tad) >> 3) & 0x07)
364#define GET_DIR(tad) (((tad) >> 6) & 0x03)
365 u16 Timeout;
366 u8 CDB[16];
367};
368
369struct ErrDescriptor {
370 __le64 Addr;
371 __le32 Len;
372};
373
374struct SGDescriptor {
375 __le64 Addr;
376 __le32 Len;
377 __le32 Ext;
378};
379
380union MoreErrInfo {
381 struct {
382 u8 Reserved[3];
383 u8 Type;
384 u32 ErrorInfo;
385 } Common_Info;
386 struct {
387 u8 Reserved[2];
388 u8 offense_size; /* size of offending entry */
389 u8 offense_num; /* byte # of offense 0-base */
390 u32 offense_value;
391 } Invalid_Cmd;
392};
393struct ErrorInfo {
394 u8 ScsiStatus;
395 u8 SenseLen;
396 u16 CommandStatus;
397 u32 ResidualCnt;
398 union MoreErrInfo MoreErrInfo;
399 u8 SenseInfo[SENSEINFOBYTES];
400};
401/* Command types */
402#define CMD_IOCTL_PEND 0x01
403#define CMD_SCSI 0x03
404#define CMD_IOACCEL1 0x04
405#define CMD_IOACCEL2 0x05
406#define IOACCEL2_TMF 0x06
407
408#define DIRECT_LOOKUP_SHIFT 4
409#define DIRECT_LOOKUP_MASK (~((1 << DIRECT_LOOKUP_SHIFT) - 1))
410
411#define HPSA_ERROR_BIT 0x02
412struct ctlr_info; /* defined in hpsa.h */
413/* The size of this structure needs to be divisible by 128
414 * on all architectures. The low 4 bits of the addresses
415 * are used as follows:
416 *
417 * bit 0: to device, used to indicate "performant mode" command
418 * from device, indidcates error status.
419 * bit 1-3: to device, indicates block fetch table entry for
420 * reducing DMA in fetching commands from host memory.
421 */
422
423#define COMMANDLIST_ALIGNMENT 128
424struct CommandList {
425 struct CommandListHeader Header;
426 struct RequestBlock Request;
427 struct ErrDescriptor ErrDesc;
428 struct SGDescriptor SG[SG_ENTRIES_IN_CMD];
429 /* information associated with the command */
430 u32 busaddr; /* physical addr of this record */
431 struct ErrorInfo *err_info; /* pointer to the allocated mem */
432 struct ctlr_info *h;
433 int cmd_type;
434 long cmdindex;
435 struct completion *waiting;
436 struct scsi_cmnd *scsi_cmd;
437 struct work_struct work;
438
439 /*
440 * For commands using either of the two "ioaccel" paths to
441 * bypass the RAID stack and go directly to the physical disk
442 * phys_disk is a pointer to the hpsa_scsi_dev_t to which the
443 * i/o is destined. We need to store that here because the command
444 * may potentially encounter TASK SET FULL and need to be resubmitted
445 * For "normal" i/o's not using the "ioaccel" paths, phys_disk is
446 * not used.
447 */
448 struct hpsa_scsi_dev_t *phys_disk;
449
450 int abort_pending;
451 struct hpsa_scsi_dev_t *reset_pending;
452 atomic_t refcount; /* Must be last to avoid memset in hpsa_cmd_init() */
453} __aligned(COMMANDLIST_ALIGNMENT);
454
455/* Max S/G elements in I/O accelerator command */
456#define IOACCEL1_MAXSGENTRIES 24
457#define IOACCEL2_MAXSGENTRIES 28
458
459/*
460 * Structure for I/O accelerator (mode 1) commands.
461 * Note that this structure must be 128-byte aligned in size.
462 */
463#define IOACCEL1_COMMANDLIST_ALIGNMENT 128
464struct io_accel1_cmd {
465 __le16 dev_handle; /* 0x00 - 0x01 */
466 u8 reserved1; /* 0x02 */
467 u8 function; /* 0x03 */
468 u8 reserved2[8]; /* 0x04 - 0x0B */
469 u32 err_info; /* 0x0C - 0x0F */
470 u8 reserved3[2]; /* 0x10 - 0x11 */
471 u8 err_info_len; /* 0x12 */
472 u8 reserved4; /* 0x13 */
473 u8 sgl_offset; /* 0x14 */
474 u8 reserved5[7]; /* 0x15 - 0x1B */
475 __le32 transfer_len; /* 0x1C - 0x1F */
476 u8 reserved6[4]; /* 0x20 - 0x23 */
477 __le16 io_flags; /* 0x24 - 0x25 */
478 u8 reserved7[14]; /* 0x26 - 0x33 */
479 u8 LUN[8]; /* 0x34 - 0x3B */
480 __le32 control; /* 0x3C - 0x3F */
481 u8 CDB[16]; /* 0x40 - 0x4F */
482 u8 reserved8[16]; /* 0x50 - 0x5F */
483 __le16 host_context_flags; /* 0x60 - 0x61 */
484 __le16 timeout_sec; /* 0x62 - 0x63 */
485 u8 ReplyQueue; /* 0x64 */
486 u8 reserved9[3]; /* 0x65 - 0x67 */
487 __le64 tag; /* 0x68 - 0x6F */
488 __le64 host_addr; /* 0x70 - 0x77 */
489 u8 CISS_LUN[8]; /* 0x78 - 0x7F */
490 struct SGDescriptor SG[IOACCEL1_MAXSGENTRIES];
491} __aligned(IOACCEL1_COMMANDLIST_ALIGNMENT);
492
493#define IOACCEL1_FUNCTION_SCSIIO 0x00
494#define IOACCEL1_SGLOFFSET 32
495
496#define IOACCEL1_IOFLAGS_IO_REQ 0x4000
497#define IOACCEL1_IOFLAGS_CDBLEN_MASK 0x001F
498#define IOACCEL1_IOFLAGS_CDBLEN_MAX 16
499
500#define IOACCEL1_CONTROL_NODATAXFER 0x00000000
501#define IOACCEL1_CONTROL_DATA_OUT 0x01000000
502#define IOACCEL1_CONTROL_DATA_IN 0x02000000
503#define IOACCEL1_CONTROL_TASKPRIO_MASK 0x00007800
504#define IOACCEL1_CONTROL_TASKPRIO_SHIFT 11
505#define IOACCEL1_CONTROL_SIMPLEQUEUE 0x00000000
506#define IOACCEL1_CONTROL_HEADOFQUEUE 0x00000100
507#define IOACCEL1_CONTROL_ORDEREDQUEUE 0x00000200
508#define IOACCEL1_CONTROL_ACA 0x00000400
509
510#define IOACCEL1_HCFLAGS_CISS_FORMAT 0x0013
511
512#define IOACCEL1_BUSADDR_CMDTYPE 0x00000060
513
514struct ioaccel2_sg_element {
515 __le64 address;
516 __le32 length;
517 u8 reserved[3];
518 u8 chain_indicator;
519#define IOACCEL2_CHAIN 0x80
520};
521
522/*
523 * SCSI Response Format structure for IO Accelerator Mode 2
524 */
525struct io_accel2_scsi_response {
526 u8 IU_type;
527#define IOACCEL2_IU_TYPE_SRF 0x60
528 u8 reserved1[3];
529 u8 req_id[4]; /* request identifier */
530 u8 reserved2[4];
531 u8 serv_response; /* service response */
532#define IOACCEL2_SERV_RESPONSE_COMPLETE 0x000
533#define IOACCEL2_SERV_RESPONSE_FAILURE 0x001
534#define IOACCEL2_SERV_RESPONSE_TMF_COMPLETE 0x002
535#define IOACCEL2_SERV_RESPONSE_TMF_SUCCESS 0x003
536#define IOACCEL2_SERV_RESPONSE_TMF_REJECTED 0x004
537#define IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN 0x005
538 u8 status; /* status */
539#define IOACCEL2_STATUS_SR_TASK_COMP_GOOD 0x00
540#define IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND 0x02
541#define IOACCEL2_STATUS_SR_TASK_COMP_BUSY 0x08
542#define IOACCEL2_STATUS_SR_TASK_COMP_RES_CON 0x18
543#define IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL 0x28
544#define IOACCEL2_STATUS_SR_TASK_COMP_ABORTED 0x40
545#define IOACCEL2_STATUS_SR_IOACCEL_DISABLED 0x0E
546#define IOACCEL2_STATUS_SR_IO_ERROR 0x01
547#define IOACCEL2_STATUS_SR_IO_ABORTED 0x02
548#define IOACCEL2_STATUS_SR_NO_PATH_TO_DEVICE 0x03
549#define IOACCEL2_STATUS_SR_INVALID_DEVICE 0x04
550#define IOACCEL2_STATUS_SR_UNDERRUN 0x51
551#define IOACCEL2_STATUS_SR_OVERRUN 0x75
552 u8 data_present; /* low 2 bits */
553#define IOACCEL2_NO_DATAPRESENT 0x000
554#define IOACCEL2_RESPONSE_DATAPRESENT 0x001
555#define IOACCEL2_SENSE_DATA_PRESENT 0x002
556#define IOACCEL2_RESERVED 0x003
557 u8 sense_data_len; /* sense/response data length */
558 u8 resid_cnt[4]; /* residual count */
559 u8 sense_data_buff[32]; /* sense/response data buffer */
560};
561
562/*
563 * Structure for I/O accelerator (mode 2 or m2) commands.
564 * Note that this structure must be 128-byte aligned in size.
565 */
566#define IOACCEL2_COMMANDLIST_ALIGNMENT 128
567struct io_accel2_cmd {
568 u8 IU_type; /* IU Type */
569 u8 direction; /* direction, memtype, and encryption */
570#define IOACCEL2_DIRECTION_MASK 0x03 /* bits 0,1: direction */
571#define IOACCEL2_DIRECTION_MEMTYPE_MASK 0x04 /* bit 2: memtype source/dest */
572 /* 0b=PCIe, 1b=DDR */
573#define IOACCEL2_DIRECTION_ENCRYPT_MASK 0x08 /* bit 3: encryption flag */
574 /* 0=off, 1=on */
575 u8 reply_queue; /* Reply Queue ID */
576 u8 reserved1; /* Reserved */
577 __le32 scsi_nexus; /* Device Handle */
578 __le32 Tag; /* cciss tag, lower 4 bytes only */
579 __le32 tweak_lower; /* Encryption tweak, lower 4 bytes */
580 u8 cdb[16]; /* SCSI Command Descriptor Block */
581 u8 cciss_lun[8]; /* 8 byte SCSI address */
582 __le32 data_len; /* Total bytes to transfer */
583 u8 cmd_priority_task_attr; /* priority and task attrs */
584#define IOACCEL2_PRIORITY_MASK 0x78
585#define IOACCEL2_ATTR_MASK 0x07
586 u8 sg_count; /* Number of sg elements */
587 __le16 dekindex; /* Data encryption key index */
588 __le64 err_ptr; /* Error Pointer */
589 __le32 err_len; /* Error Length*/
590 __le32 tweak_upper; /* Encryption tweak, upper 4 bytes */
591 struct ioaccel2_sg_element sg[IOACCEL2_MAXSGENTRIES];
592 struct io_accel2_scsi_response error_data;
593} __aligned(IOACCEL2_COMMANDLIST_ALIGNMENT);
594
595/*
596 * defines for Mode 2 command struct
597 * FIXME: this can't be all I need mfm
598 */
599#define IOACCEL2_IU_TYPE 0x40
600#define IOACCEL2_IU_TMF_TYPE 0x41
601#define IOACCEL2_DIR_NO_DATA 0x00
602#define IOACCEL2_DIR_DATA_IN 0x01
603#define IOACCEL2_DIR_DATA_OUT 0x02
604#define IOACCEL2_TMF_ABORT 0x01
605/*
606 * SCSI Task Management Request format for Accelerator Mode 2
607 */
608struct hpsa_tmf_struct {
609 u8 iu_type; /* Information Unit Type */
610 u8 reply_queue; /* Reply Queue ID */
611 u8 tmf; /* Task Management Function */
612 u8 reserved1; /* byte 3 Reserved */
613 __le32 it_nexus; /* SCSI I-T Nexus */
614 u8 lun_id[8]; /* LUN ID for TMF request */
615 __le64 tag; /* cciss tag associated w/ request */
616 __le64 abort_tag; /* cciss tag of SCSI cmd or TMF to abort */
617 __le64 error_ptr; /* Error Pointer */
618 __le32 error_len; /* Error Length */
619} __aligned(IOACCEL2_COMMANDLIST_ALIGNMENT);
620
621/* Configuration Table Structure */
622struct HostWrite {
623 __le32 TransportRequest;
624 __le32 command_pool_addr_hi;
625 __le32 CoalIntDelay;
626 __le32 CoalIntCount;
627};
628
629#define SIMPLE_MODE 0x02
630#define PERFORMANT_MODE 0x04
631#define MEMQ_MODE 0x08
632#define IOACCEL_MODE_1 0x80
633
634#define DRIVER_SUPPORT_UA_ENABLE 0x00000001
635
636struct CfgTable {
637 u8 Signature[4];
638 __le32 SpecValence;
639 __le32 TransportSupport;
640 __le32 TransportActive;
641 struct HostWrite HostWrite;
642 __le32 CmdsOutMax;
643 __le32 BusTypes;
644 __le32 TransMethodOffset;
645 u8 ServerName[16];
646 __le32 HeartBeat;
647 __le32 driver_support;
648#define ENABLE_SCSI_PREFETCH 0x100
649#define ENABLE_UNIT_ATTN 0x01
650 __le32 MaxScatterGatherElements;
651 __le32 MaxLogicalUnits;
652 __le32 MaxPhysicalDevices;
653 __le32 MaxPhysicalDrivesPerLogicalUnit;
654 __le32 MaxPerformantModeCommands;
655 __le32 MaxBlockFetch;
656 __le32 PowerConservationSupport;
657 __le32 PowerConservationEnable;
658 __le32 TMFSupportFlags;
659 u8 TMFTagMask[8];
660 u8 reserved[0x78 - 0x70];
661 __le32 misc_fw_support; /* offset 0x78 */
662#define MISC_FW_DOORBELL_RESET 0x02
663#define MISC_FW_DOORBELL_RESET2 0x010
664#define MISC_FW_RAID_OFFLOAD_BASIC 0x020
665#define MISC_FW_EVENT_NOTIFY 0x080
666 u8 driver_version[32];
667 __le32 max_cached_write_size;
668 u8 driver_scratchpad[16];
669 __le32 max_error_info_length;
670 __le32 io_accel_max_embedded_sg_count;
671 __le32 io_accel_request_size_offset;
672 __le32 event_notify;
673#define HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE (1 << 30)
674#define HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE (1 << 31)
675 __le32 clear_event_notify;
676};
677
678#define NUM_BLOCKFETCH_ENTRIES 8
679struct TransTable_struct {
680 __le32 BlockFetch[NUM_BLOCKFETCH_ENTRIES];
681 __le32 RepQSize;
682 __le32 RepQCount;
683 __le32 RepQCtrAddrLow32;
684 __le32 RepQCtrAddrHigh32;
685#define MAX_REPLY_QUEUES 64
686 struct vals32 RepQAddr[MAX_REPLY_QUEUES];
687};
688
689struct hpsa_pci_info {
690 unsigned char bus;
691 unsigned char dev_fn;
692 unsigned short domain;
693 u32 board_id;
694};
695
696struct bmic_identify_controller {
697 u8 configured_logical_drive_count; /* offset 0 */
698 u8 pad1[153];
699 __le16 extended_logical_unit_count; /* offset 154 */
700 u8 pad2[136];
701 u8 controller_mode; /* offset 292 */
702 u8 pad3[32];
703};
704
705
706struct bmic_identify_physical_device {
707 u8 scsi_bus; /* SCSI Bus number on controller */
708 u8 scsi_id; /* SCSI ID on this bus */
709 __le16 block_size; /* sector size in bytes */
710 __le32 total_blocks; /* number for sectors on drive */
711 __le32 reserved_blocks; /* controller reserved (RIS) */
712 u8 model[40]; /* Physical Drive Model */
713 u8 serial_number[40]; /* Drive Serial Number */
714 u8 firmware_revision[8]; /* drive firmware revision */
715 u8 scsi_inquiry_bits; /* inquiry byte 7 bits */
716 u8 compaq_drive_stamp; /* 0 means drive not stamped */
717 u8 last_failure_reason;
718#define BMIC_LAST_FAILURE_TOO_SMALL_IN_LOAD_CONFIG 0x01
719#define BMIC_LAST_FAILURE_ERROR_ERASING_RIS 0x02
720#define BMIC_LAST_FAILURE_ERROR_SAVING_RIS 0x03
721#define BMIC_LAST_FAILURE_FAIL_DRIVE_COMMAND 0x04
722#define BMIC_LAST_FAILURE_MARK_BAD_FAILED 0x05
723#define BMIC_LAST_FAILURE_MARK_BAD_FAILED_IN_FINISH_REMAP 0x06
724#define BMIC_LAST_FAILURE_TIMEOUT 0x07
725#define BMIC_LAST_FAILURE_AUTOSENSE_FAILED 0x08
726#define BMIC_LAST_FAILURE_MEDIUM_ERROR_1 0x09
727#define BMIC_LAST_FAILURE_MEDIUM_ERROR_2 0x0a
728#define BMIC_LAST_FAILURE_NOT_READY_BAD_SENSE 0x0b
729#define BMIC_LAST_FAILURE_NOT_READY 0x0c
730#define BMIC_LAST_FAILURE_HARDWARE_ERROR 0x0d
731#define BMIC_LAST_FAILURE_ABORTED_COMMAND 0x0e
732#define BMIC_LAST_FAILURE_WRITE_PROTECTED 0x0f
733#define BMIC_LAST_FAILURE_SPIN_UP_FAILURE_IN_RECOVER 0x10
734#define BMIC_LAST_FAILURE_REBUILD_WRITE_ERROR 0x11
735#define BMIC_LAST_FAILURE_TOO_SMALL_IN_HOT_PLUG 0x12
736#define BMIC_LAST_FAILURE_BUS_RESET_RECOVERY_ABORTED 0x13
737#define BMIC_LAST_FAILURE_REMOVED_IN_HOT_PLUG 0x14
738#define BMIC_LAST_FAILURE_INIT_REQUEST_SENSE_FAILED 0x15
739#define BMIC_LAST_FAILURE_INIT_START_UNIT_FAILED 0x16
740#define BMIC_LAST_FAILURE_INQUIRY_FAILED 0x17
741#define BMIC_LAST_FAILURE_NON_DISK_DEVICE 0x18
742#define BMIC_LAST_FAILURE_READ_CAPACITY_FAILED 0x19
743#define BMIC_LAST_FAILURE_INVALID_BLOCK_SIZE 0x1a
744#define BMIC_LAST_FAILURE_HOT_PLUG_REQUEST_SENSE_FAILED 0x1b
745#define BMIC_LAST_FAILURE_HOT_PLUG_START_UNIT_FAILED 0x1c
746#define BMIC_LAST_FAILURE_WRITE_ERROR_AFTER_REMAP 0x1d
747#define BMIC_LAST_FAILURE_INIT_RESET_RECOVERY_ABORTED 0x1e
748#define BMIC_LAST_FAILURE_DEFERRED_WRITE_ERROR 0x1f
749#define BMIC_LAST_FAILURE_MISSING_IN_SAVE_RIS 0x20
750#define BMIC_LAST_FAILURE_WRONG_REPLACE 0x21
751#define BMIC_LAST_FAILURE_GDP_VPD_INQUIRY_FAILED 0x22
752#define BMIC_LAST_FAILURE_GDP_MODE_SENSE_FAILED 0x23
753#define BMIC_LAST_FAILURE_DRIVE_NOT_IN_48BIT_MODE 0x24
754#define BMIC_LAST_FAILURE_DRIVE_TYPE_MIX_IN_HOT_PLUG 0x25
755#define BMIC_LAST_FAILURE_DRIVE_TYPE_MIX_IN_LOAD_CFG 0x26
756#define BMIC_LAST_FAILURE_PROTOCOL_ADAPTER_FAILED 0x27
757#define BMIC_LAST_FAILURE_FAULTY_ID_BAY_EMPTY 0x28
758#define BMIC_LAST_FAILURE_FAULTY_ID_BAY_OCCUPIED 0x29
759#define BMIC_LAST_FAILURE_FAULTY_ID_INVALID_BAY 0x2a
760#define BMIC_LAST_FAILURE_WRITE_RETRIES_FAILED 0x2b
761
762#define BMIC_LAST_FAILURE_SMART_ERROR_REPORTED 0x37
763#define BMIC_LAST_FAILURE_PHY_RESET_FAILED 0x38
764#define BMIC_LAST_FAILURE_ONLY_ONE_CTLR_CAN_SEE_DRIVE 0x40
765#define BMIC_LAST_FAILURE_KC_VOLUME_FAILED 0x41
766#define BMIC_LAST_FAILURE_UNEXPECTED_REPLACEMENT 0x42
767#define BMIC_LAST_FAILURE_OFFLINE_ERASE 0x80
768#define BMIC_LAST_FAILURE_OFFLINE_TOO_SMALL 0x81
769#define BMIC_LAST_FAILURE_OFFLINE_DRIVE_TYPE_MIX 0x82
770#define BMIC_LAST_FAILURE_OFFLINE_ERASE_COMPLETE 0x83
771
772 u8 flags;
773 u8 more_flags;
774 u8 scsi_lun; /* SCSI LUN for phys drive */
775 u8 yet_more_flags;
776 u8 even_more_flags;
777 __le32 spi_speed_rules;/* SPI Speed data:Ultra disable diagnose */
778 u8 phys_connector[2]; /* connector number on controller */
779 u8 phys_box_on_bus; /* phys enclosure this drive resides */
780 u8 phys_bay_in_box; /* phys drv bay this drive resides */
781 __le32 rpm; /* Drive rotational speed in rpm */
782 u8 device_type; /* type of drive */
783#define BMIC_DEVICE_TYPE_CONTROLLER 0x07
784
785 u8 sata_version; /* only valid when drive_type is SATA */
786 __le64 big_total_block_count;
787 __le64 ris_starting_lba;
788 __le32 ris_size;
789 u8 wwid[20];
790 u8 controller_phy_map[32];
791 __le16 phy_count;
792 u8 phy_connected_dev_type[256];
793 u8 phy_to_drive_bay_num[256];
794 __le16 phy_to_attached_dev_index[256];
795 u8 box_index;
796 u8 reserved;
797 __le16 extra_physical_drive_flags;
798#define BMIC_PHYS_DRIVE_SUPPORTS_GAS_GAUGE(idphydrv) \
799 (idphydrv->extra_physical_drive_flags & (1 << 10))
800 u8 negotiated_link_rate[256];
801 u8 phy_to_phy_map[256];
802 u8 redundant_path_present_map;
803 u8 redundant_path_failure_map;
804 u8 active_path_number;
805 __le16 alternate_paths_phys_connector[8];
806 u8 alternate_paths_phys_box_on_port[8];
807 u8 multi_lun_device_lun_count;
808 u8 minimum_good_fw_revision[8];
809 u8 unique_inquiry_bytes[20];
810 u8 current_temperature_degreesC;
811 u8 temperature_threshold_degreesC;
812 u8 max_temperature_degreesC;
813 u8 logical_blocks_per_phys_block_exp; /* phyblocksize = 512*2^exp */
814 __le16 current_queue_depth_limit;
815 u8 reserved_switch_stuff[60];
816 __le16 power_on_hours; /* valid only if gas gauge supported */
817 __le16 percent_endurance_used; /* valid only if gas gauge supported. */
818#define BMIC_PHYS_DRIVE_SSD_WEAROUT(idphydrv) \
819 ((idphydrv->percent_endurance_used & 0x80) || \
820 (idphydrv->percent_endurance_used > 10000))
821 u8 drive_authentication;
822#define BMIC_PHYS_DRIVE_AUTHENTICATED(idphydrv) \
823 (idphydrv->drive_authentication == 0x80)
824 u8 smart_carrier_authentication;
825#define BMIC_SMART_CARRIER_AUTHENTICATION_SUPPORTED(idphydrv) \
826 (idphydrv->smart_carrier_authentication != 0x0)
827#define BMIC_SMART_CARRIER_AUTHENTICATED(idphydrv) \
828 (idphydrv->smart_carrier_authentication == 0x01)
829 u8 smart_carrier_app_fw_version;
830 u8 smart_carrier_bootloader_fw_version;
831 u8 sanitize_support_flags;
832 u8 drive_key_flags;
833 u8 encryption_key_name[64];
834 __le32 misc_drive_flags;
835 __le16 dek_index;
836 __le16 hba_drive_encryption_flags;
837 __le16 max_overwrite_time;
838 __le16 max_block_erase_time;
839 __le16 max_crypto_erase_time;
840 u8 device_connector_info[5];
841 u8 connector_name[8][8];
842 u8 page_83_id[16];
843 u8 max_link_rate[256];
844 u8 neg_phys_link_rate[256];
845 u8 box_conn_name[8];
846} __attribute((aligned(512)));
847
848struct bmic_sense_subsystem_info {
849 u8 primary_slot_number;
850 u8 reserved[3];
851 u8 chasis_serial_number[32];
852 u8 primary_world_wide_id[8];
853 u8 primary_array_serial_number[32]; /* NULL terminated */
854 u8 primary_cache_serial_number[32]; /* NULL terminated */
855 u8 reserved_2[8];
856 u8 secondary_array_serial_number[32];
857 u8 secondary_cache_serial_number[32];
858 u8 pad[332];
859};
860
861struct bmic_sense_storage_box_params {
862 u8 reserved[36];
863 u8 inquiry_valid;
864 u8 reserved_1[68];
865 u8 phys_box_on_port;
866 u8 reserved_2[22];
867 u16 connection_info;
868 u8 reserver_3[84];
869 u8 phys_connector[2];
870 u8 reserved_4[296];
871};
872
873#pragma pack()
874#endif /* HPSA_CMD_H */
875