1/*
2 * ipr.h -- driver for IBM Power Linux RAID adapters
3 *
4 * Written By: Brian King <brking@us.ibm.com>, IBM Corporation
5 *
6 * Copyright (C) 2003, 2004 IBM Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 * Alan Cox <alan@lxorguk.ukuu.org.uk> - Removed several careless u32/dma_addr_t errors
23 * that broke 64bit platforms.
24 */
25
26#ifndef _IPR_H
27#define _IPR_H
28
29#include <asm/unaligned.h>
30#include <linux/types.h>
31#include <linux/completion.h>
32#include <linux/libata.h>
33#include <linux/list.h>
34#include <linux/kref.h>
35#include <linux/irq_poll.h>
36#include <scsi/scsi.h>
37#include <scsi/scsi_cmnd.h>
38
39/*
40 * Literals
41 */
42#define IPR_DRIVER_VERSION "2.6.4"
43#define IPR_DRIVER_DATE "(March 14, 2017)"
44
45/*
46 * IPR_MAX_CMD_PER_LUN: This defines the maximum number of outstanding
47 * ops per device for devices not running tagged command queuing.
48 * This can be adjusted at runtime through sysfs device attributes.
49 */
50#define IPR_MAX_CMD_PER_LUN 6
51#define IPR_MAX_CMD_PER_ATA_LUN 1
52
53/*
54 * IPR_NUM_BASE_CMD_BLKS: This defines the maximum number of
55 * ops the mid-layer can send to the adapter.
56 */
57#define IPR_NUM_BASE_CMD_BLKS (ioa_cfg->max_cmds)
58
59#define PCI_DEVICE_ID_IBM_OBSIDIAN_E 0x0339
60
61#define PCI_DEVICE_ID_IBM_CROC_FPGA_E2 0x033D
62#define PCI_DEVICE_ID_IBM_CROCODILE 0x034A
63#define PCI_DEVICE_ID_IBM_RATTLESNAKE 0x04DA
64
65#define IPR_SUBS_DEV_ID_2780 0x0264
66#define IPR_SUBS_DEV_ID_5702 0x0266
67#define IPR_SUBS_DEV_ID_5703 0x0278
68#define IPR_SUBS_DEV_ID_572E 0x028D
69#define IPR_SUBS_DEV_ID_573E 0x02D3
70#define IPR_SUBS_DEV_ID_573D 0x02D4
71#define IPR_SUBS_DEV_ID_571A 0x02C0
72#define IPR_SUBS_DEV_ID_571B 0x02BE
73#define IPR_SUBS_DEV_ID_571E 0x02BF
74#define IPR_SUBS_DEV_ID_571F 0x02D5
75#define IPR_SUBS_DEV_ID_572A 0x02C1
76#define IPR_SUBS_DEV_ID_572B 0x02C2
77#define IPR_SUBS_DEV_ID_572F 0x02C3
78#define IPR_SUBS_DEV_ID_574E 0x030A
79#define IPR_SUBS_DEV_ID_575B 0x030D
80#define IPR_SUBS_DEV_ID_575C 0x0338
81#define IPR_SUBS_DEV_ID_57B3 0x033A
82#define IPR_SUBS_DEV_ID_57B7 0x0360
83#define IPR_SUBS_DEV_ID_57B8 0x02C2
84
85#define IPR_SUBS_DEV_ID_57B4 0x033B
86#define IPR_SUBS_DEV_ID_57B2 0x035F
87#define IPR_SUBS_DEV_ID_57C0 0x0352
88#define IPR_SUBS_DEV_ID_57C3 0x0353
89#define IPR_SUBS_DEV_ID_57C4 0x0354
90#define IPR_SUBS_DEV_ID_57C6 0x0357
91#define IPR_SUBS_DEV_ID_57CC 0x035C
92
93#define IPR_SUBS_DEV_ID_57B5 0x033C
94#define IPR_SUBS_DEV_ID_57CE 0x035E
95#define IPR_SUBS_DEV_ID_57B1 0x0355
96
97#define IPR_SUBS_DEV_ID_574D 0x0356
98#define IPR_SUBS_DEV_ID_57C8 0x035D
99
100#define IPR_SUBS_DEV_ID_57D5 0x03FB
101#define IPR_SUBS_DEV_ID_57D6 0x03FC
102#define IPR_SUBS_DEV_ID_57D7 0x03FF
103#define IPR_SUBS_DEV_ID_57D8 0x03FE
104#define IPR_SUBS_DEV_ID_57D9 0x046D
105#define IPR_SUBS_DEV_ID_57DA 0x04CA
106#define IPR_SUBS_DEV_ID_57EB 0x0474
107#define IPR_SUBS_DEV_ID_57EC 0x0475
108#define IPR_SUBS_DEV_ID_57ED 0x0499
109#define IPR_SUBS_DEV_ID_57EE 0x049A
110#define IPR_SUBS_DEV_ID_57EF 0x049B
111#define IPR_SUBS_DEV_ID_57F0 0x049C
112#define IPR_SUBS_DEV_ID_2CCA 0x04C7
113#define IPR_SUBS_DEV_ID_2CD2 0x04C8
114#define IPR_SUBS_DEV_ID_2CCD 0x04C9
115#define IPR_SUBS_DEV_ID_580A 0x04FC
116#define IPR_SUBS_DEV_ID_580B 0x04FB
117#define IPR_NAME "ipr"
118
119/*
120 * Return codes
121 */
122#define IPR_RC_JOB_CONTINUE 1
123#define IPR_RC_JOB_RETURN 2
124
125/*
126 * IOASCs
127 */
128#define IPR_IOASC_NR_INIT_CMD_REQUIRED 0x02040200
129#define IPR_IOASC_NR_IOA_RESET_REQUIRED 0x02048000
130#define IPR_IOASC_SYNC_REQUIRED 0x023f0000
131#define IPR_IOASC_MED_DO_NOT_REALLOC 0x03110C00
132#define IPR_IOASC_HW_SEL_TIMEOUT 0x04050000
133#define IPR_IOASC_HW_DEV_BUS_STATUS 0x04448500
134#define IPR_IOASC_IOASC_MASK 0xFFFFFF00
135#define IPR_IOASC_SCSI_STATUS_MASK 0x000000FF
136#define IPR_IOASC_HW_CMD_FAILED 0x046E0000
137#define IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT 0x05240000
138#define IPR_IOASC_IR_RESOURCE_HANDLE 0x05250000
139#define IPR_IOASC_IR_NO_CMDS_TO_2ND_IOA 0x05258100
140#define IPR_IOASA_IR_DUAL_IOA_DISABLED 0x052C8000
141#define IPR_IOASC_BUS_WAS_RESET 0x06290000
142#define IPR_IOASC_BUS_WAS_RESET_BY_OTHER 0x06298000
143#define IPR_IOASC_ABORTED_CMD_TERM_BY_HOST 0x0B5A0000
144#define IPR_IOASC_IR_NON_OPTIMIZED 0x05258200
145
146#define IPR_FIRST_DRIVER_IOASC 0x10000000
147#define IPR_IOASC_IOA_WAS_RESET 0x10000001
148#define IPR_IOASC_PCI_ACCESS_ERROR 0x10000002
149
150/* Driver data flags */
151#define IPR_USE_LONG_TRANSOP_TIMEOUT 0x00000001
152#define IPR_USE_PCI_WARM_RESET 0x00000002
153
154#define IPR_DEFAULT_MAX_ERROR_DUMP 984
155#define IPR_NUM_LOG_HCAMS 2
156#define IPR_NUM_CFG_CHG_HCAMS 2
157#define IPR_NUM_HCAM_QUEUE 12
158#define IPR_NUM_HCAMS (IPR_NUM_LOG_HCAMS + IPR_NUM_CFG_CHG_HCAMS)
159#define IPR_MAX_HCAMS (IPR_NUM_HCAMS + IPR_NUM_HCAM_QUEUE)
160
161#define IPR_MAX_SIS64_TARGETS_PER_BUS 1024
162#define IPR_MAX_SIS64_LUNS_PER_TARGET 0xffffffff
163
164#define IPR_MAX_NUM_TARGETS_PER_BUS 256
165#define IPR_MAX_NUM_LUNS_PER_TARGET 256
166#define IPR_VSET_BUS 0xff
167#define IPR_IOA_BUS 0xff
168#define IPR_IOA_TARGET 0xff
169#define IPR_IOA_LUN 0xff
170#define IPR_MAX_NUM_BUSES 16
171
172#define IPR_NUM_RESET_RELOAD_RETRIES 3
173
174/* We need resources for HCAMS, IOA reset, IOA bringdown, and ERP */
175#define IPR_NUM_INTERNAL_CMD_BLKS (IPR_NUM_HCAMS + \
176 ((IPR_NUM_RESET_RELOAD_RETRIES + 1) * 2) + 4)
177
178#define IPR_MAX_COMMANDS 100
179#define IPR_NUM_CMD_BLKS (IPR_NUM_BASE_CMD_BLKS + \
180 IPR_NUM_INTERNAL_CMD_BLKS)
181
182#define IPR_MAX_PHYSICAL_DEVS 192
183#define IPR_DEFAULT_SIS64_DEVS 1024
184#define IPR_MAX_SIS64_DEVS 4096
185
186#define IPR_MAX_SGLIST 64
187#define IPR_IOA_MAX_SECTORS 32767
188#define IPR_VSET_MAX_SECTORS 512
189#define IPR_MAX_CDB_LEN 16
190#define IPR_MAX_HRRQ_RETRIES 3
191
192#define IPR_DEFAULT_BUS_WIDTH 16
193#define IPR_80MBs_SCSI_RATE ((80 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
194#define IPR_U160_SCSI_RATE ((160 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
195#define IPR_U320_SCSI_RATE ((320 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
196#define IPR_MAX_SCSI_RATE(width) ((320 * 10) / ((width) / 8))
197
198#define IPR_IOA_RES_HANDLE 0xffffffff
199#define IPR_INVALID_RES_HANDLE 0
200#define IPR_IOA_RES_ADDR 0x00ffffff
201
202/*
203 * Adapter Commands
204 */
205#define IPR_CANCEL_REQUEST 0xC0
206#define IPR_CANCEL_64BIT_IOARCB 0x01
207#define IPR_QUERY_RSRC_STATE 0xC2
208#define IPR_RESET_DEVICE 0xC3
209#define IPR_RESET_TYPE_SELECT 0x80
210#define IPR_LUN_RESET 0x40
211#define IPR_TARGET_RESET 0x20
212#define IPR_BUS_RESET 0x10
213#define IPR_ATA_PHY_RESET 0x80
214#define IPR_ID_HOST_RR_Q 0xC4
215#define IPR_QUERY_IOA_CONFIG 0xC5
216#define IPR_CANCEL_ALL_REQUESTS 0xCE
217#define IPR_HOST_CONTROLLED_ASYNC 0xCF
218#define IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE 0x01
219#define IPR_HCAM_CDB_OP_CODE_LOG_DATA 0x02
220#define IPR_SET_SUPPORTED_DEVICES 0xFB
221#define IPR_SET_ALL_SUPPORTED_DEVICES 0x80
222#define IPR_IOA_SHUTDOWN 0xF7
223#define IPR_WR_BUF_DOWNLOAD_AND_SAVE 0x05
224#define IPR_IOA_SERVICE_ACTION 0xD2
225
226/* IOA Service Actions */
227#define IPR_IOA_SA_CHANGE_CACHE_PARAMS 0x14
228
229/*
230 * Timeouts
231 */
232#define IPR_SHUTDOWN_TIMEOUT (ipr_fastfail ? 60 * HZ : 10 * 60 * HZ)
233#define IPR_VSET_RW_TIMEOUT (ipr_fastfail ? 30 * HZ : 2 * 60 * HZ)
234#define IPR_ABBREV_SHUTDOWN_TIMEOUT (10 * HZ)
235#define IPR_DUAL_IOA_ABBR_SHUTDOWN_TO (2 * 60 * HZ)
236#define IPR_DEVICE_RESET_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
237#define IPR_CANCEL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
238#define IPR_CANCEL_ALL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
239#define IPR_ABORT_TASK_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
240#define IPR_INTERNAL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
241#define IPR_WRITE_BUFFER_TIMEOUT (30 * 60 * HZ)
242#define IPR_SET_SUP_DEVICE_TIMEOUT (2 * 60 * HZ)
243#define IPR_REQUEST_SENSE_TIMEOUT (10 * HZ)
244#define IPR_OPERATIONAL_TIMEOUT (5 * 60)
245#define IPR_LONG_OPERATIONAL_TIMEOUT (12 * 60)
246#define IPR_WAIT_FOR_RESET_TIMEOUT (2 * HZ)
247#define IPR_CHECK_FOR_RESET_TIMEOUT (HZ / 10)
248#define IPR_WAIT_FOR_BIST_TIMEOUT (2 * HZ)
249#define IPR_PCI_ERROR_RECOVERY_TIMEOUT (120 * HZ)
250#define IPR_PCI_RESET_TIMEOUT (HZ / 2)
251#define IPR_SIS32_DUMP_TIMEOUT (15 * HZ)
252#define IPR_SIS64_DUMP_TIMEOUT (40 * HZ)
253#define IPR_DUMP_DELAY_SECONDS 4
254#define IPR_DUMP_DELAY_TIMEOUT (IPR_DUMP_DELAY_SECONDS * HZ)
255
256/*
257 * SCSI Literals
258 */
259#define IPR_VENDOR_ID_LEN 8
260#define IPR_PROD_ID_LEN 16
261#define IPR_SERIAL_NUM_LEN 8
262
263/*
264 * Hardware literals
265 */
266#define IPR_FMT2_MBX_ADDR_MASK 0x0fffffff
267#define IPR_FMT2_MBX_BAR_SEL_MASK 0xf0000000
268#define IPR_FMT2_MKR_BAR_SEL_SHIFT 28
269#define IPR_GET_FMT2_BAR_SEL(mbx) \
270(((mbx) & IPR_FMT2_MBX_BAR_SEL_MASK) >> IPR_FMT2_MKR_BAR_SEL_SHIFT)
271#define IPR_SDT_FMT2_BAR0_SEL 0x0
272#define IPR_SDT_FMT2_BAR1_SEL 0x1
273#define IPR_SDT_FMT2_BAR2_SEL 0x2
274#define IPR_SDT_FMT2_BAR3_SEL 0x3
275#define IPR_SDT_FMT2_BAR4_SEL 0x4
276#define IPR_SDT_FMT2_BAR5_SEL 0x5
277#define IPR_SDT_FMT2_EXP_ROM_SEL 0x8
278#define IPR_FMT2_SDT_READY_TO_USE 0xC4D4E3F2
279#define IPR_FMT3_SDT_READY_TO_USE 0xC4D4E3F3
280#define IPR_DOORBELL 0x82800000
281#define IPR_RUNTIME_RESET 0x40000000
282
283#define IPR_IPL_INIT_MIN_STAGE_TIME 5
284#define IPR_IPL_INIT_DEFAULT_STAGE_TIME 30
285#define IPR_IPL_INIT_STAGE_UNKNOWN 0x0
286#define IPR_IPL_INIT_STAGE_TRANSOP 0xB0000000
287#define IPR_IPL_INIT_STAGE_MASK 0xff000000
288#define IPR_IPL_INIT_STAGE_TIME_MASK 0x0000ffff
289#define IPR_PCII_IPL_STAGE_CHANGE (0x80000000 >> 0)
290
291#define IPR_PCII_MAILBOX_STABLE (0x80000000 >> 4)
292#define IPR_WAIT_FOR_MAILBOX (2 * HZ)
293
294#define IPR_PCII_IOA_TRANS_TO_OPER (0x80000000 >> 0)
295#define IPR_PCII_IOARCB_XFER_FAILED (0x80000000 >> 3)
296#define IPR_PCII_IOA_UNIT_CHECKED (0x80000000 >> 4)
297#define IPR_PCII_NO_HOST_RRQ (0x80000000 >> 5)
298#define IPR_PCII_CRITICAL_OPERATION (0x80000000 >> 6)
299#define IPR_PCII_IO_DEBUG_ACKNOWLEDGE (0x80000000 >> 7)
300#define IPR_PCII_IOARRIN_LOST (0x80000000 >> 27)
301#define IPR_PCII_MMIO_ERROR (0x80000000 >> 28)
302#define IPR_PCII_PROC_ERR_STATE (0x80000000 >> 29)
303#define IPR_PCII_HRRQ_UPDATED (0x80000000 >> 30)
304#define IPR_PCII_CORE_ISSUED_RST_REQ (0x80000000 >> 31)
305
306#define IPR_PCII_ERROR_INTERRUPTS \
307(IPR_PCII_IOARCB_XFER_FAILED | IPR_PCII_IOA_UNIT_CHECKED | \
308IPR_PCII_NO_HOST_RRQ | IPR_PCII_IOARRIN_LOST | IPR_PCII_MMIO_ERROR)
309
310#define IPR_PCII_OPER_INTERRUPTS \
311(IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED | IPR_PCII_IOA_TRANS_TO_OPER)
312
313#define IPR_UPROCI_RESET_ALERT (0x80000000 >> 7)
314#define IPR_UPROCI_IO_DEBUG_ALERT (0x80000000 >> 9)
315#define IPR_UPROCI_SIS64_START_BIST (0x80000000 >> 23)
316
317#define IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC 200000 /* 200 ms */
318#define IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC 200000 /* 200 ms */
319
320/*
321 * Dump literals
322 */
323#define IPR_FMT2_MAX_IOA_DUMP_SIZE (4 * 1024 * 1024)
324#define IPR_FMT3_MAX_IOA_DUMP_SIZE (80 * 1024 * 1024)
325#define IPR_FMT2_NUM_SDT_ENTRIES 511
326#define IPR_FMT3_NUM_SDT_ENTRIES 0xFFF
327#define IPR_FMT2_MAX_NUM_DUMP_PAGES ((IPR_FMT2_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
328#define IPR_FMT3_MAX_NUM_DUMP_PAGES ((IPR_FMT3_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
329
330/*
331 * Misc literals
332 */
333#define IPR_NUM_IOADL_ENTRIES IPR_MAX_SGLIST
334#define IPR_MAX_MSIX_VECTORS 0x10
335#define IPR_MAX_HRRQ_NUM 0x10
336#define IPR_INIT_HRRQ 0x0
337
338/*
339 * Adapter interface types
340 */
341
342struct ipr_res_addr {
343 u8 reserved;
344 u8 bus;
345 u8 target;
346 u8 lun;
347#define IPR_GET_PHYS_LOC(res_addr) \
348 (((res_addr).bus << 16) | ((res_addr).target << 8) | (res_addr).lun)
349}__attribute__((packed, aligned (4)));
350
351struct ipr_std_inq_vpids {
352 u8 vendor_id[IPR_VENDOR_ID_LEN];
353 u8 product_id[IPR_PROD_ID_LEN];
354}__attribute__((packed));
355
356struct ipr_vpd {
357 struct ipr_std_inq_vpids vpids;
358 u8 sn[IPR_SERIAL_NUM_LEN];
359}__attribute__((packed));
360
361struct ipr_ext_vpd {
362 struct ipr_vpd vpd;
363 __be32 wwid[2];
364}__attribute__((packed));
365
366struct ipr_ext_vpd64 {
367 struct ipr_vpd vpd;
368 __be32 wwid[4];
369}__attribute__((packed));
370
371struct ipr_std_inq_data {
372 u8 peri_qual_dev_type;
373#define IPR_STD_INQ_PERI_QUAL(peri) ((peri) >> 5)
374#define IPR_STD_INQ_PERI_DEV_TYPE(peri) ((peri) & 0x1F)
375
376 u8 removeable_medium_rsvd;
377#define IPR_STD_INQ_REMOVEABLE_MEDIUM 0x80
378
379#define IPR_IS_DASD_DEVICE(std_inq) \
380((IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_DISK) && \
381!(((std_inq).removeable_medium_rsvd) & IPR_STD_INQ_REMOVEABLE_MEDIUM))
382
383#define IPR_IS_SES_DEVICE(std_inq) \
384(IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_ENCLOSURE)
385
386 u8 version;
387 u8 aen_naca_fmt;
388 u8 additional_len;
389 u8 sccs_rsvd;
390 u8 bq_enc_multi;
391 u8 sync_cmdq_flags;
392
393 struct ipr_std_inq_vpids vpids;
394
395 u8 ros_rsvd_ram_rsvd[4];
396
397 u8 serial_num[IPR_SERIAL_NUM_LEN];
398}__attribute__ ((packed));
399
400#define IPR_RES_TYPE_AF_DASD 0x00
401#define IPR_RES_TYPE_GENERIC_SCSI 0x01
402#define IPR_RES_TYPE_VOLUME_SET 0x02
403#define IPR_RES_TYPE_REMOTE_AF_DASD 0x03
404#define IPR_RES_TYPE_GENERIC_ATA 0x04
405#define IPR_RES_TYPE_ARRAY 0x05
406#define IPR_RES_TYPE_IOAFP 0xff
407
408struct ipr_config_table_entry {
409 u8 proto;
410#define IPR_PROTO_SATA 0x02
411#define IPR_PROTO_SATA_ATAPI 0x03
412#define IPR_PROTO_SAS_STP 0x06
413#define IPR_PROTO_SAS_STP_ATAPI 0x07
414 u8 array_id;
415 u8 flags;
416#define IPR_IS_IOA_RESOURCE 0x80
417 u8 rsvd_subtype;
418
419#define IPR_QUEUEING_MODEL(res) ((((res)->flags) & 0x70) >> 4)
420#define IPR_QUEUE_FROZEN_MODEL 0
421#define IPR_QUEUE_NACA_MODEL 1
422
423 struct ipr_res_addr res_addr;
424 __be32 res_handle;
425 __be32 lun_wwn[2];
426 struct ipr_std_inq_data std_inq_data;
427}__attribute__ ((packed, aligned (4)));
428
429struct ipr_config_table_entry64 {
430 u8 res_type;
431 u8 proto;
432 u8 vset_num;
433 u8 array_id;
434 __be16 flags;
435 __be16 res_flags;
436#define IPR_QUEUEING_MODEL64(res) ((((res)->res_flags) & 0x7000) >> 12)
437 __be32 res_handle;
438 u8 dev_id_type;
439 u8 reserved[3];
440 __be64 dev_id;
441 __be64 lun;
442 __be64 lun_wwn[2];
443#define IPR_MAX_RES_PATH_LENGTH 48
444 __be64 res_path;
445 struct ipr_std_inq_data std_inq_data;
446 u8 reserved2[4];
447 __be64 reserved3[2];
448 u8 reserved4[8];
449}__attribute__ ((packed, aligned (8)));
450
451struct ipr_config_table_hdr {
452 u8 num_entries;
453 u8 flags;
454#define IPR_UCODE_DOWNLOAD_REQ 0x10
455 __be16 reserved;
456}__attribute__((packed, aligned (4)));
457
458struct ipr_config_table_hdr64 {
459 __be16 num_entries;
460 __be16 reserved;
461 u8 flags;
462 u8 reserved2[11];
463}__attribute__((packed, aligned (4)));
464
465struct ipr_config_table {
466 struct ipr_config_table_hdr hdr;
467 struct ipr_config_table_entry dev[0];
468}__attribute__((packed, aligned (4)));
469
470struct ipr_config_table64 {
471 struct ipr_config_table_hdr64 hdr64;
472 struct ipr_config_table_entry64 dev[0];
473}__attribute__((packed, aligned (8)));
474
475struct ipr_config_table_entry_wrapper {
476 union {
477 struct ipr_config_table_entry *cfgte;
478 struct ipr_config_table_entry64 *cfgte64;
479 } u;
480};
481
482struct ipr_hostrcb_cfg_ch_not {
483 union {
484 struct ipr_config_table_entry cfgte;
485 struct ipr_config_table_entry64 cfgte64;
486 } u;
487 u8 reserved[936];
488}__attribute__((packed, aligned (4)));
489
490struct ipr_supported_device {
491 __be16 data_length;
492 u8 reserved;
493 u8 num_records;
494 struct ipr_std_inq_vpids vpids;
495 u8 reserved2[16];
496}__attribute__((packed, aligned (4)));
497
498struct ipr_hrr_queue {
499 struct ipr_ioa_cfg *ioa_cfg;
500 __be32 *host_rrq;
501 dma_addr_t host_rrq_dma;
502#define IPR_HRRQ_REQ_RESP_HANDLE_MASK 0xfffffffc
503#define IPR_HRRQ_RESP_BIT_SET 0x00000002
504#define IPR_HRRQ_TOGGLE_BIT 0x00000001
505#define IPR_HRRQ_REQ_RESP_HANDLE_SHIFT 2
506#define IPR_ID_HRRQ_SELE_ENABLE 0x02
507 volatile __be32 *hrrq_start;
508 volatile __be32 *hrrq_end;
509 volatile __be32 *hrrq_curr;
510
511 struct list_head hrrq_free_q;
512 struct list_head hrrq_pending_q;
513 spinlock_t _lock;
514 spinlock_t *lock;
515
516 volatile u32 toggle_bit;
517 u32 size;
518 u32 min_cmd_id;
519 u32 max_cmd_id;
520 u8 allow_interrupts:1;
521 u8 ioa_is_dead:1;
522 u8 allow_cmds:1;
523 u8 removing_ioa:1;
524
525 struct irq_poll iopoll;
526};
527
528/* Command packet structure */
529struct ipr_cmd_pkt {
530 u8 reserved; /* Reserved by IOA */
531 u8 hrrq_id;
532 u8 request_type;
533#define IPR_RQTYPE_SCSICDB 0x00
534#define IPR_RQTYPE_IOACMD 0x01
535#define IPR_RQTYPE_HCAM 0x02
536#define IPR_RQTYPE_ATA_PASSTHRU 0x04
537#define IPR_RQTYPE_PIPE 0x05
538
539 u8 reserved2;
540
541 u8 flags_hi;
542#define IPR_FLAGS_HI_WRITE_NOT_READ 0x80
543#define IPR_FLAGS_HI_NO_ULEN_CHK 0x20
544#define IPR_FLAGS_HI_SYNC_OVERRIDE 0x10
545#define IPR_FLAGS_HI_SYNC_COMPLETE 0x08
546#define IPR_FLAGS_HI_NO_LINK_DESC 0x04
547
548 u8 flags_lo;
549#define IPR_FLAGS_LO_ALIGNED_BFR 0x20
550#define IPR_FLAGS_LO_DELAY_AFTER_RST 0x10
551#define IPR_FLAGS_LO_UNTAGGED_TASK 0x00
552#define IPR_FLAGS_LO_SIMPLE_TASK 0x02
553#define IPR_FLAGS_LO_ORDERED_TASK 0x04
554#define IPR_FLAGS_LO_HEAD_OF_Q_TASK 0x06
555#define IPR_FLAGS_LO_ACA_TASK 0x08
556
557 u8 cdb[16];
558 __be16 timeout;
559}__attribute__ ((packed, aligned(4)));
560
561struct ipr_ioarcb_ata_regs { /* 22 bytes */
562 u8 flags;
563#define IPR_ATA_FLAG_PACKET_CMD 0x80
564#define IPR_ATA_FLAG_XFER_TYPE_DMA 0x40
565#define IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION 0x20
566 u8 reserved[3];
567
568 __be16 data;
569 u8 feature;
570 u8 nsect;
571 u8 lbal;
572 u8 lbam;
573 u8 lbah;
574 u8 device;
575 u8 command;
576 u8 reserved2[3];
577 u8 hob_feature;
578 u8 hob_nsect;
579 u8 hob_lbal;
580 u8 hob_lbam;
581 u8 hob_lbah;
582 u8 ctl;
583}__attribute__ ((packed, aligned(2)));
584
585struct ipr_ioadl_desc {
586 __be32 flags_and_data_len;
587#define IPR_IOADL_FLAGS_MASK 0xff000000
588#define IPR_IOADL_GET_FLAGS(x) (be32_to_cpu(x) & IPR_IOADL_FLAGS_MASK)
589#define IPR_IOADL_DATA_LEN_MASK 0x00ffffff
590#define IPR_IOADL_GET_DATA_LEN(x) (be32_to_cpu(x) & IPR_IOADL_DATA_LEN_MASK)
591#define IPR_IOADL_FLAGS_READ 0x48000000
592#define IPR_IOADL_FLAGS_READ_LAST 0x49000000
593#define IPR_IOADL_FLAGS_WRITE 0x68000000
594#define IPR_IOADL_FLAGS_WRITE_LAST 0x69000000
595#define IPR_IOADL_FLAGS_LAST 0x01000000
596
597 __be32 address;
598}__attribute__((packed, aligned (8)));
599
600struct ipr_ioadl64_desc {
601 __be32 flags;
602 __be32 data_len;
603 __be64 address;
604}__attribute__((packed, aligned (16)));
605
606struct ipr_ata64_ioadl {
607 struct ipr_ioarcb_ata_regs regs;
608 u16 reserved[5];
609 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
610}__attribute__((packed, aligned (16)));
611
612struct ipr_ioarcb_add_data {
613 union {
614 struct ipr_ioarcb_ata_regs regs;
615 struct ipr_ioadl_desc ioadl[5];
616 __be32 add_cmd_parms[10];
617 } u;
618}__attribute__ ((packed, aligned (4)));
619
620struct ipr_ioarcb_sis64_add_addr_ecb {
621 __be64 ioasa_host_pci_addr;
622 __be64 data_ioadl_addr;
623 __be64 reserved;
624 __be32 ext_control_buf[4];
625}__attribute__((packed, aligned (8)));
626
627/* IOA Request Control Block 128 bytes */
628struct ipr_ioarcb {
629 union {
630 __be32 ioarcb_host_pci_addr;
631 __be64 ioarcb_host_pci_addr64;
632 } a;
633 __be32 res_handle;
634 __be32 host_response_handle;
635 __be32 reserved1;
636 __be32 reserved2;
637 __be32 reserved3;
638
639 __be32 data_transfer_length;
640 __be32 read_data_transfer_length;
641 __be32 write_ioadl_addr;
642 __be32 ioadl_len;
643 __be32 read_ioadl_addr;
644 __be32 read_ioadl_len;
645
646 __be32 ioasa_host_pci_addr;
647 __be16 ioasa_len;
648 __be16 reserved4;
649
650 struct ipr_cmd_pkt cmd_pkt;
651
652 __be16 add_cmd_parms_offset;
653 __be16 add_cmd_parms_len;
654
655 union {
656 struct ipr_ioarcb_add_data add_data;
657 struct ipr_ioarcb_sis64_add_addr_ecb sis64_addr_data;
658 } u;
659
660}__attribute__((packed, aligned (4)));
661
662struct ipr_ioasa_vset {
663 __be32 failing_lba_hi;
664 __be32 failing_lba_lo;
665 __be32 reserved;
666}__attribute__((packed, aligned (4)));
667
668struct ipr_ioasa_af_dasd {
669 __be32 failing_lba;
670 __be32 reserved[2];
671}__attribute__((packed, aligned (4)));
672
673struct ipr_ioasa_gpdd {
674 u8 end_state;
675 u8 bus_phase;
676 __be16 reserved;
677 __be32 ioa_data[2];
678}__attribute__((packed, aligned (4)));
679
680struct ipr_ioasa_gata {
681 u8 error;
682 u8 nsect; /* Interrupt reason */
683 u8 lbal;
684 u8 lbam;
685 u8 lbah;
686 u8 device;
687 u8 status;
688 u8 alt_status; /* ATA CTL */
689 u8 hob_nsect;
690 u8 hob_lbal;
691 u8 hob_lbam;
692 u8 hob_lbah;
693}__attribute__((packed, aligned (4)));
694
695struct ipr_auto_sense {
696 __be16 auto_sense_len;
697 __be16 ioa_data_len;
698 __be32 data[SCSI_SENSE_BUFFERSIZE/sizeof(__be32)];
699};
700
701struct ipr_ioasa_hdr {
702 __be32 ioasc;
703#define IPR_IOASC_SENSE_KEY(ioasc) ((ioasc) >> 24)
704#define IPR_IOASC_SENSE_CODE(ioasc) (((ioasc) & 0x00ff0000) >> 16)
705#define IPR_IOASC_SENSE_QUAL(ioasc) (((ioasc) & 0x0000ff00) >> 8)
706#define IPR_IOASC_SENSE_STATUS(ioasc) ((ioasc) & 0x000000ff)
707
708 __be16 ret_stat_len; /* Length of the returned IOASA */
709
710 __be16 avail_stat_len; /* Total Length of status available. */
711
712 __be32 residual_data_len; /* number of bytes in the host data */
713 /* buffers that were not used by the IOARCB command. */
714
715 __be32 ilid;
716#define IPR_NO_ILID 0
717#define IPR_DRIVER_ILID 0xffffffff
718
719 __be32 fd_ioasc;
720
721 __be32 fd_phys_locator;
722
723 __be32 fd_res_handle;
724
725 __be32 ioasc_specific; /* status code specific field */
726#define IPR_ADDITIONAL_STATUS_FMT 0x80000000
727#define IPR_AUTOSENSE_VALID 0x40000000
728#define IPR_ATA_DEVICE_WAS_RESET 0x20000000
729#define IPR_IOASC_SPECIFIC_MASK 0x00ffffff
730#define IPR_FIELD_POINTER_VALID (0x80000000 >> 8)
731#define IPR_FIELD_POINTER_MASK 0x0000ffff
732
733}__attribute__((packed, aligned (4)));
734
735struct ipr_ioasa {
736 struct ipr_ioasa_hdr hdr;
737
738 union {
739 struct ipr_ioasa_vset vset;
740 struct ipr_ioasa_af_dasd dasd;
741 struct ipr_ioasa_gpdd gpdd;
742 struct ipr_ioasa_gata gata;
743 } u;
744
745 struct ipr_auto_sense auto_sense;
746}__attribute__((packed, aligned (4)));
747
748struct ipr_ioasa64 {
749 struct ipr_ioasa_hdr hdr;
750 u8 fd_res_path[8];
751
752 union {
753 struct ipr_ioasa_vset vset;
754 struct ipr_ioasa_af_dasd dasd;
755 struct ipr_ioasa_gpdd gpdd;
756 struct ipr_ioasa_gata gata;
757 } u;
758
759 struct ipr_auto_sense auto_sense;
760}__attribute__((packed, aligned (4)));
761
762struct ipr_mode_parm_hdr {
763 u8 length;
764 u8 medium_type;
765 u8 device_spec_parms;
766 u8 block_desc_len;
767}__attribute__((packed));
768
769struct ipr_mode_pages {
770 struct ipr_mode_parm_hdr hdr;
771 u8 data[255 - sizeof(struct ipr_mode_parm_hdr)];
772}__attribute__((packed));
773
774struct ipr_mode_page_hdr {
775 u8 ps_page_code;
776#define IPR_MODE_PAGE_PS 0x80
777#define IPR_GET_MODE_PAGE_CODE(hdr) ((hdr)->ps_page_code & 0x3F)
778 u8 page_length;
779}__attribute__ ((packed));
780
781struct ipr_dev_bus_entry {
782 struct ipr_res_addr res_addr;
783 u8 flags;
784#define IPR_SCSI_ATTR_ENABLE_QAS 0x80
785#define IPR_SCSI_ATTR_DISABLE_QAS 0x40
786#define IPR_SCSI_ATTR_QAS_MASK 0xC0
787#define IPR_SCSI_ATTR_ENABLE_TM 0x20
788#define IPR_SCSI_ATTR_NO_TERM_PWR 0x10
789#define IPR_SCSI_ATTR_TM_SUPPORTED 0x08
790#define IPR_SCSI_ATTR_LVD_TO_SE_NOT_ALLOWED 0x04
791
792 u8 scsi_id;
793 u8 bus_width;
794 u8 extended_reset_delay;
795#define IPR_EXTENDED_RESET_DELAY 7
796
797 __be32 max_xfer_rate;
798
799 u8 spinup_delay;
800 u8 reserved3;
801 __be16 reserved4;
802}__attribute__((packed, aligned (4)));
803
804struct ipr_mode_page28 {
805 struct ipr_mode_page_hdr hdr;
806 u8 num_entries;
807 u8 entry_length;
808 struct ipr_dev_bus_entry bus[0];
809}__attribute__((packed));
810
811struct ipr_mode_page24 {
812 struct ipr_mode_page_hdr hdr;
813 u8 flags;
814#define IPR_ENABLE_DUAL_IOA_AF 0x80
815}__attribute__((packed));
816
817struct ipr_ioa_vpd {
818 struct ipr_std_inq_data std_inq_data;
819 u8 ascii_part_num[12];
820 u8 reserved[40];
821 u8 ascii_plant_code[4];
822}__attribute__((packed));
823
824struct ipr_inquiry_page3 {
825 u8 peri_qual_dev_type;
826 u8 page_code;
827 u8 reserved1;
828 u8 page_length;
829 u8 ascii_len;
830 u8 reserved2[3];
831 u8 load_id[4];
832 u8 major_release;
833 u8 card_type;
834 u8 minor_release[2];
835 u8 ptf_number[4];
836 u8 patch_number[4];
837}__attribute__((packed));
838
839struct ipr_inquiry_cap {
840 u8 peri_qual_dev_type;
841 u8 page_code;
842 u8 reserved1;
843 u8 page_length;
844 u8 ascii_len;
845 u8 reserved2;
846 u8 sis_version[2];
847 u8 cap;
848#define IPR_CAP_DUAL_IOA_RAID 0x80
849 u8 reserved3[15];
850}__attribute__((packed));
851
852#define IPR_INQUIRY_PAGE0_ENTRIES 20
853struct ipr_inquiry_page0 {
854 u8 peri_qual_dev_type;
855 u8 page_code;
856 u8 reserved1;
857 u8 len;
858 u8 page[IPR_INQUIRY_PAGE0_ENTRIES];
859}__attribute__((packed));
860
861struct ipr_inquiry_pageC4 {
862 u8 peri_qual_dev_type;
863 u8 page_code;
864 u8 reserved1;
865 u8 len;
866 u8 cache_cap[4];
867#define IPR_CAP_SYNC_CACHE 0x08
868 u8 reserved2[20];
869} __packed;
870
871struct ipr_hostrcb_device_data_entry {
872 struct ipr_vpd vpd;
873 struct ipr_res_addr dev_res_addr;
874 struct ipr_vpd new_vpd;
875 struct ipr_vpd ioa_last_with_dev_vpd;
876 struct ipr_vpd cfc_last_with_dev_vpd;
877 __be32 ioa_data[5];
878}__attribute__((packed, aligned (4)));
879
880struct ipr_hostrcb_device_data_entry_enhanced {
881 struct ipr_ext_vpd vpd;
882 u8 ccin[4];
883 struct ipr_res_addr dev_res_addr;
884 struct ipr_ext_vpd new_vpd;
885 u8 new_ccin[4];
886 struct ipr_ext_vpd ioa_last_with_dev_vpd;
887 struct ipr_ext_vpd cfc_last_with_dev_vpd;
888}__attribute__((packed, aligned (4)));
889
890struct ipr_hostrcb64_device_data_entry_enhanced {
891 struct ipr_ext_vpd vpd;
892 u8 ccin[4];
893 u8 res_path[8];
894 struct ipr_ext_vpd new_vpd;
895 u8 new_ccin[4];
896 struct ipr_ext_vpd ioa_last_with_dev_vpd;
897 struct ipr_ext_vpd cfc_last_with_dev_vpd;
898}__attribute__((packed, aligned (4)));
899
900struct ipr_hostrcb_array_data_entry {
901 struct ipr_vpd vpd;
902 struct ipr_res_addr expected_dev_res_addr;
903 struct ipr_res_addr dev_res_addr;
904}__attribute__((packed, aligned (4)));
905
906struct ipr_hostrcb64_array_data_entry {
907 struct ipr_ext_vpd vpd;
908 u8 ccin[4];
909 u8 expected_res_path[8];
910 u8 res_path[8];
911}__attribute__((packed, aligned (4)));
912
913struct ipr_hostrcb_array_data_entry_enhanced {
914 struct ipr_ext_vpd vpd;
915 u8 ccin[4];
916 struct ipr_res_addr expected_dev_res_addr;
917 struct ipr_res_addr dev_res_addr;
918}__attribute__((packed, aligned (4)));
919
920struct ipr_hostrcb_type_ff_error {
921 __be32 ioa_data[758];
922}__attribute__((packed, aligned (4)));
923
924struct ipr_hostrcb_type_01_error {
925 __be32 seek_counter;
926 __be32 read_counter;
927 u8 sense_data[32];
928 __be32 ioa_data[236];
929}__attribute__((packed, aligned (4)));
930
931struct ipr_hostrcb_type_21_error {
932 __be32 wwn[4];
933 u8 res_path[8];
934 u8 primary_problem_desc[32];
935 u8 second_problem_desc[32];
936 __be32 sense_data[8];
937 __be32 cdb[4];
938 __be32 residual_trans_length;
939 __be32 length_of_error;
940 __be32 ioa_data[236];
941}__attribute__((packed, aligned (4)));
942
943struct ipr_hostrcb_type_02_error {
944 struct ipr_vpd ioa_vpd;
945 struct ipr_vpd cfc_vpd;
946 struct ipr_vpd ioa_last_attached_to_cfc_vpd;
947 struct ipr_vpd cfc_last_attached_to_ioa_vpd;
948 __be32 ioa_data[3];
949}__attribute__((packed, aligned (4)));
950
951struct ipr_hostrcb_type_12_error {
952 struct ipr_ext_vpd ioa_vpd;
953 struct ipr_ext_vpd cfc_vpd;
954 struct ipr_ext_vpd ioa_last_attached_to_cfc_vpd;
955 struct ipr_ext_vpd cfc_last_attached_to_ioa_vpd;
956 __be32 ioa_data[3];
957}__attribute__((packed, aligned (4)));
958
959struct ipr_hostrcb_type_03_error {
960 struct ipr_vpd ioa_vpd;
961 struct ipr_vpd cfc_vpd;
962 __be32 errors_detected;
963 __be32 errors_logged;
964 u8 ioa_data[12];
965 struct ipr_hostrcb_device_data_entry dev[3];
966}__attribute__((packed, aligned (4)));
967
968struct ipr_hostrcb_type_13_error {
969 struct ipr_ext_vpd ioa_vpd;
970 struct ipr_ext_vpd cfc_vpd;
971 __be32 errors_detected;
972 __be32 errors_logged;
973 struct ipr_hostrcb_device_data_entry_enhanced dev[3];
974}__attribute__((packed, aligned (4)));
975
976struct ipr_hostrcb_type_23_error {
977 struct ipr_ext_vpd ioa_vpd;
978 struct ipr_ext_vpd cfc_vpd;
979 __be32 errors_detected;
980 __be32 errors_logged;
981 struct ipr_hostrcb64_device_data_entry_enhanced dev[3];
982}__attribute__((packed, aligned (4)));
983
984struct ipr_hostrcb_type_04_error {
985 struct ipr_vpd ioa_vpd;
986 struct ipr_vpd cfc_vpd;
987 u8 ioa_data[12];
988 struct ipr_hostrcb_array_data_entry array_member[10];
989 __be32 exposed_mode_adn;
990 __be32 array_id;
991 struct ipr_vpd incomp_dev_vpd;
992 __be32 ioa_data2;
993 struct ipr_hostrcb_array_data_entry array_member2[8];
994 struct ipr_res_addr last_func_vset_res_addr;
995 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
996 u8 protection_level[8];
997}__attribute__((packed, aligned (4)));
998
999struct ipr_hostrcb_type_14_error {
1000 struct ipr_ext_vpd ioa_vpd;
1001 struct ipr_ext_vpd cfc_vpd;
1002 __be32 exposed_mode_adn;
1003 __be32 array_id;
1004 struct ipr_res_addr last_func_vset_res_addr;
1005 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
1006 u8 protection_level[8];
1007 __be32 num_entries;
1008 struct ipr_hostrcb_array_data_entry_enhanced array_member[18];
1009}__attribute__((packed, aligned (4)));
1010
1011struct ipr_hostrcb_type_24_error {
1012 struct ipr_ext_vpd ioa_vpd;
1013 struct ipr_ext_vpd cfc_vpd;
1014 u8 reserved[2];
1015 u8 exposed_mode_adn;
1016#define IPR_INVALID_ARRAY_DEV_NUM 0xff
1017 u8 array_id;
1018 u8 last_res_path[8];
1019 u8 protection_level[8];
1020 struct ipr_ext_vpd64 array_vpd;
1021 u8 description[16];
1022 u8 reserved2[3];
1023 u8 num_entries;
1024 struct ipr_hostrcb64_array_data_entry array_member[32];
1025}__attribute__((packed, aligned (4)));
1026
1027struct ipr_hostrcb_type_07_error {
1028 u8 failure_reason[64];
1029 struct ipr_vpd vpd;
1030 __be32 data[222];
1031}__attribute__((packed, aligned (4)));
1032
1033struct ipr_hostrcb_type_17_error {
1034 u8 failure_reason[64];
1035 struct ipr_ext_vpd vpd;
1036 __be32 data[476];
1037}__attribute__((packed, aligned (4)));
1038
1039struct ipr_hostrcb_config_element {
1040 u8 type_status;
1041#define IPR_PATH_CFG_TYPE_MASK 0xF0
1042#define IPR_PATH_CFG_NOT_EXIST 0x00
1043#define IPR_PATH_CFG_IOA_PORT 0x10
1044#define IPR_PATH_CFG_EXP_PORT 0x20
1045#define IPR_PATH_CFG_DEVICE_PORT 0x30
1046#define IPR_PATH_CFG_DEVICE_LUN 0x40
1047
1048#define IPR_PATH_CFG_STATUS_MASK 0x0F
1049#define IPR_PATH_CFG_NO_PROB 0x00
1050#define IPR_PATH_CFG_DEGRADED 0x01
1051#define IPR_PATH_CFG_FAILED 0x02
1052#define IPR_PATH_CFG_SUSPECT 0x03
1053#define IPR_PATH_NOT_DETECTED 0x04
1054#define IPR_PATH_INCORRECT_CONN 0x05
1055
1056 u8 cascaded_expander;
1057 u8 phy;
1058 u8 link_rate;
1059#define IPR_PHY_LINK_RATE_MASK 0x0F
1060
1061 __be32 wwid[2];
1062}__attribute__((packed, aligned (4)));
1063
1064struct ipr_hostrcb64_config_element {
1065 __be16 length;
1066 u8 descriptor_id;
1067#define IPR_DESCRIPTOR_MASK 0xC0
1068#define IPR_DESCRIPTOR_SIS64 0x00
1069
1070 u8 reserved;
1071 u8 type_status;
1072
1073 u8 reserved2[2];
1074 u8 link_rate;
1075
1076 u8 res_path[8];
1077 __be32 wwid[2];
1078}__attribute__((packed, aligned (8)));
1079
1080struct ipr_hostrcb_fabric_desc {
1081 __be16 length;
1082 u8 ioa_port;
1083 u8 cascaded_expander;
1084 u8 phy;
1085 u8 path_state;
1086#define IPR_PATH_ACTIVE_MASK 0xC0
1087#define IPR_PATH_NO_INFO 0x00
1088#define IPR_PATH_ACTIVE 0x40
1089#define IPR_PATH_NOT_ACTIVE 0x80
1090
1091#define IPR_PATH_STATE_MASK 0x0F
1092#define IPR_PATH_STATE_NO_INFO 0x00
1093#define IPR_PATH_HEALTHY 0x01
1094#define IPR_PATH_DEGRADED 0x02
1095#define IPR_PATH_FAILED 0x03
1096
1097 __be16 num_entries;
1098 struct ipr_hostrcb_config_element elem[1];
1099}__attribute__((packed, aligned (4)));
1100
1101struct ipr_hostrcb64_fabric_desc {
1102 __be16 length;
1103 u8 descriptor_id;
1104
1105 u8 reserved[2];
1106 u8 path_state;
1107
1108 u8 reserved2[2];
1109 u8 res_path[8];
1110 u8 reserved3[6];
1111 __be16 num_entries;
1112 struct ipr_hostrcb64_config_element elem[1];
1113}__attribute__((packed, aligned (8)));
1114
1115#define for_each_hrrq(hrrq, ioa_cfg) \
1116 for (hrrq = (ioa_cfg)->hrrq; \
1117 hrrq < ((ioa_cfg)->hrrq + (ioa_cfg)->hrrq_num); hrrq++)
1118
1119#define for_each_fabric_cfg(fabric, cfg) \
1120 for (cfg = (fabric)->elem; \
1121 cfg < ((fabric)->elem + be16_to_cpu((fabric)->num_entries)); \
1122 cfg++)
1123
1124struct ipr_hostrcb_type_20_error {
1125 u8 failure_reason[64];
1126 u8 reserved[3];
1127 u8 num_entries;
1128 struct ipr_hostrcb_fabric_desc desc[1];
1129}__attribute__((packed, aligned (4)));
1130
1131struct ipr_hostrcb_type_30_error {
1132 u8 failure_reason[64];
1133 u8 reserved[3];
1134 u8 num_entries;
1135 struct ipr_hostrcb64_fabric_desc desc[1];
1136}__attribute__((packed, aligned (4)));
1137
1138struct ipr_hostrcb_type_41_error {
1139 u8 failure_reason[64];
1140 __be32 data[200];
1141}__attribute__((packed, aligned (4)));
1142
1143struct ipr_hostrcb_error {
1144 __be32 fd_ioasc;
1145 struct ipr_res_addr fd_res_addr;
1146 __be32 fd_res_handle;
1147 __be32 prc;
1148 union {
1149 struct ipr_hostrcb_type_ff_error type_ff_error;
1150 struct ipr_hostrcb_type_01_error type_01_error;
1151 struct ipr_hostrcb_type_02_error type_02_error;
1152 struct ipr_hostrcb_type_03_error type_03_error;
1153 struct ipr_hostrcb_type_04_error type_04_error;
1154 struct ipr_hostrcb_type_07_error type_07_error;
1155 struct ipr_hostrcb_type_12_error type_12_error;
1156 struct ipr_hostrcb_type_13_error type_13_error;
1157 struct ipr_hostrcb_type_14_error type_14_error;
1158 struct ipr_hostrcb_type_17_error type_17_error;
1159 struct ipr_hostrcb_type_20_error type_20_error;
1160 } u;
1161}__attribute__((packed, aligned (4)));
1162
1163struct ipr_hostrcb64_error {
1164 __be32 fd_ioasc;
1165 __be32 ioa_fw_level;
1166 __be32 fd_res_handle;
1167 __be32 prc;
1168 __be64 fd_dev_id;
1169 __be64 fd_lun;
1170 u8 fd_res_path[8];
1171 __be64 time_stamp;
1172 u8 reserved[16];
1173 union {
1174 struct ipr_hostrcb_type_ff_error type_ff_error;
1175 struct ipr_hostrcb_type_12_error type_12_error;
1176 struct ipr_hostrcb_type_17_error type_17_error;
1177 struct ipr_hostrcb_type_21_error type_21_error;
1178 struct ipr_hostrcb_type_23_error type_23_error;
1179 struct ipr_hostrcb_type_24_error type_24_error;
1180 struct ipr_hostrcb_type_30_error type_30_error;
1181 struct ipr_hostrcb_type_41_error type_41_error;
1182 } u;
1183}__attribute__((packed, aligned (8)));
1184
1185struct ipr_hostrcb_raw {
1186 __be32 data[sizeof(struct ipr_hostrcb_error)/sizeof(__be32)];
1187}__attribute__((packed, aligned (4)));
1188
1189struct ipr_hcam {
1190 u8 op_code;
1191#define IPR_HOST_RCB_OP_CODE_CONFIG_CHANGE 0xE1
1192#define IPR_HOST_RCB_OP_CODE_LOG_DATA 0xE2
1193
1194 u8 notify_type;
1195#define IPR_HOST_RCB_NOTIF_TYPE_EXISTING_CHANGED 0x00
1196#define IPR_HOST_RCB_NOTIF_TYPE_NEW_ENTRY 0x01
1197#define IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY 0x02
1198#define IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY 0x10
1199#define IPR_HOST_RCB_NOTIF_TYPE_INFORMATION_ENTRY 0x11
1200
1201 u8 notifications_lost;
1202#define IPR_HOST_RCB_NO_NOTIFICATIONS_LOST 0
1203#define IPR_HOST_RCB_NOTIFICATIONS_LOST 0x80
1204
1205 u8 flags;
1206#define IPR_HOSTRCB_INTERNAL_OPER 0x80
1207#define IPR_HOSTRCB_ERR_RESP_SENT 0x40
1208
1209 u8 overlay_id;
1210#define IPR_HOST_RCB_OVERLAY_ID_1 0x01
1211#define IPR_HOST_RCB_OVERLAY_ID_2 0x02
1212#define IPR_HOST_RCB_OVERLAY_ID_3 0x03
1213#define IPR_HOST_RCB_OVERLAY_ID_4 0x04
1214#define IPR_HOST_RCB_OVERLAY_ID_6 0x06
1215#define IPR_HOST_RCB_OVERLAY_ID_7 0x07
1216#define IPR_HOST_RCB_OVERLAY_ID_12 0x12
1217#define IPR_HOST_RCB_OVERLAY_ID_13 0x13
1218#define IPR_HOST_RCB_OVERLAY_ID_14 0x14
1219#define IPR_HOST_RCB_OVERLAY_ID_16 0x16
1220#define IPR_HOST_RCB_OVERLAY_ID_17 0x17
1221#define IPR_HOST_RCB_OVERLAY_ID_20 0x20
1222#define IPR_HOST_RCB_OVERLAY_ID_21 0x21
1223#define IPR_HOST_RCB_OVERLAY_ID_23 0x23
1224#define IPR_HOST_RCB_OVERLAY_ID_24 0x24
1225#define IPR_HOST_RCB_OVERLAY_ID_26 0x26
1226#define IPR_HOST_RCB_OVERLAY_ID_30 0x30
1227#define IPR_HOST_RCB_OVERLAY_ID_41 0x41
1228#define IPR_HOST_RCB_OVERLAY_ID_DEFAULT 0xFF
1229
1230 u8 reserved1[3];
1231 __be32 ilid;
1232 __be32 time_since_last_ioa_reset;
1233 __be32 reserved2;
1234 __be32 length;
1235
1236 union {
1237 struct ipr_hostrcb_error error;
1238 struct ipr_hostrcb64_error error64;
1239 struct ipr_hostrcb_cfg_ch_not ccn;
1240 struct ipr_hostrcb_raw raw;
1241 } u;
1242}__attribute__((packed, aligned (4)));
1243
1244struct ipr_hostrcb {
1245 struct ipr_hcam hcam;
1246 dma_addr_t hostrcb_dma;
1247 struct list_head queue;
1248 struct ipr_ioa_cfg *ioa_cfg;
1249 char rp_buffer[IPR_MAX_RES_PATH_LENGTH];
1250};
1251
1252/* IPR smart dump table structures */
1253struct ipr_sdt_entry {
1254 __be32 start_token;
1255 __be32 end_token;
1256 u8 reserved[4];
1257
1258 u8 flags;
1259#define IPR_SDT_ENDIAN 0x80
1260#define IPR_SDT_VALID_ENTRY 0x20
1261
1262 u8 resv;
1263 __be16 priority;
1264}__attribute__((packed, aligned (4)));
1265
1266struct ipr_sdt_header {
1267 __be32 state;
1268 __be32 num_entries;
1269 __be32 num_entries_used;
1270 __be32 dump_size;
1271}__attribute__((packed, aligned (4)));
1272
1273struct ipr_sdt {
1274 struct ipr_sdt_header hdr;
1275 struct ipr_sdt_entry entry[IPR_FMT3_NUM_SDT_ENTRIES];
1276}__attribute__((packed, aligned (4)));
1277
1278struct ipr_uc_sdt {
1279 struct ipr_sdt_header hdr;
1280 struct ipr_sdt_entry entry[1];
1281}__attribute__((packed, aligned (4)));
1282
1283/*
1284 * Driver types
1285 */
1286struct ipr_bus_attributes {
1287 u8 bus;
1288 u8 qas_enabled;
1289 u8 bus_width;
1290 u8 reserved;
1291 u32 max_xfer_rate;
1292};
1293
1294struct ipr_sata_port {
1295 struct ipr_ioa_cfg *ioa_cfg;
1296 struct ata_port *ap;
1297 struct ipr_resource_entry *res;
1298 struct ipr_ioasa_gata ioasa;
1299};
1300
1301struct ipr_resource_entry {
1302 u8 needs_sync_complete:1;
1303 u8 in_erp:1;
1304 u8 add_to_ml:1;
1305 u8 del_from_ml:1;
1306 u8 resetting_device:1;
1307 u8 reset_occurred:1;
1308 u8 raw_mode:1;
1309
1310 u32 bus; /* AKA channel */
1311 u32 target; /* AKA id */
1312 u32 lun;
1313#define IPR_ARRAY_VIRTUAL_BUS 0x1
1314#define IPR_VSET_VIRTUAL_BUS 0x2
1315#define IPR_IOAFP_VIRTUAL_BUS 0x3
1316
1317#define IPR_GET_RES_PHYS_LOC(res) \
1318 (((res)->bus << 24) | ((res)->target << 8) | (res)->lun)
1319
1320 u8 ata_class;
1321 u8 type;
1322
1323 u16 flags;
1324 u16 res_flags;
1325
1326 u8 qmodel;
1327 struct ipr_std_inq_data std_inq_data;
1328
1329 __be32 res_handle;
1330 __be64 dev_id;
1331 u64 lun_wwn;
1332 struct scsi_lun dev_lun;
1333 u8 res_path[8];
1334
1335 struct ipr_ioa_cfg *ioa_cfg;
1336 struct scsi_device *sdev;
1337 struct ipr_sata_port *sata_port;
1338 struct list_head queue;
1339}; /* struct ipr_resource_entry */
1340
1341struct ipr_resource_hdr {
1342 u16 num_entries;
1343 u16 reserved;
1344};
1345
1346struct ipr_misc_cbs {
1347 struct ipr_ioa_vpd ioa_vpd;
1348 struct ipr_inquiry_page0 page0_data;
1349 struct ipr_inquiry_page3 page3_data;
1350 struct ipr_inquiry_cap cap;
1351 struct ipr_inquiry_pageC4 pageC4_data;
1352 struct ipr_mode_pages mode_pages;
1353 struct ipr_supported_device supp_dev;
1354};
1355
1356struct ipr_interrupt_offsets {
1357 unsigned long set_interrupt_mask_reg;
1358 unsigned long clr_interrupt_mask_reg;
1359 unsigned long clr_interrupt_mask_reg32;
1360 unsigned long sense_interrupt_mask_reg;
1361 unsigned long sense_interrupt_mask_reg32;
1362 unsigned long clr_interrupt_reg;
1363 unsigned long clr_interrupt_reg32;
1364
1365 unsigned long sense_interrupt_reg;
1366 unsigned long sense_interrupt_reg32;
1367 unsigned long ioarrin_reg;
1368 unsigned long sense_uproc_interrupt_reg;
1369 unsigned long sense_uproc_interrupt_reg32;
1370 unsigned long set_uproc_interrupt_reg;
1371 unsigned long set_uproc_interrupt_reg32;
1372 unsigned long clr_uproc_interrupt_reg;
1373 unsigned long clr_uproc_interrupt_reg32;
1374
1375 unsigned long init_feedback_reg;
1376
1377 unsigned long dump_addr_reg;
1378 unsigned long dump_data_reg;
1379
1380#define IPR_ENDIAN_SWAP_KEY 0x00080800
1381 unsigned long endian_swap_reg;
1382};
1383
1384struct ipr_interrupts {
1385 void __iomem *set_interrupt_mask_reg;
1386 void __iomem *clr_interrupt_mask_reg;
1387 void __iomem *clr_interrupt_mask_reg32;
1388 void __iomem *sense_interrupt_mask_reg;
1389 void __iomem *sense_interrupt_mask_reg32;
1390 void __iomem *clr_interrupt_reg;
1391 void __iomem *clr_interrupt_reg32;
1392
1393 void __iomem *sense_interrupt_reg;
1394 void __iomem *sense_interrupt_reg32;
1395 void __iomem *ioarrin_reg;
1396 void __iomem *sense_uproc_interrupt_reg;
1397 void __iomem *sense_uproc_interrupt_reg32;
1398 void __iomem *set_uproc_interrupt_reg;
1399 void __iomem *set_uproc_interrupt_reg32;
1400 void __iomem *clr_uproc_interrupt_reg;
1401 void __iomem *clr_uproc_interrupt_reg32;
1402
1403 void __iomem *init_feedback_reg;
1404
1405 void __iomem *dump_addr_reg;
1406 void __iomem *dump_data_reg;
1407
1408 void __iomem *endian_swap_reg;
1409};
1410
1411struct ipr_chip_cfg_t {
1412 u32 mailbox;
1413 u16 max_cmds;
1414 u8 cache_line_size;
1415 u8 clear_isr;
1416 u32 iopoll_weight;
1417 struct ipr_interrupt_offsets regs;
1418};
1419
1420struct ipr_chip_t {
1421 u16 vendor;
1422 u16 device;
1423 bool has_msi;
1424 u16 sis_type;
1425#define IPR_SIS32 0x00
1426#define IPR_SIS64 0x01
1427 u16 bist_method;
1428#define IPR_PCI_CFG 0x00
1429#define IPR_MMIO 0x01
1430 const struct ipr_chip_cfg_t *cfg;
1431};
1432
1433enum ipr_shutdown_type {
1434 IPR_SHUTDOWN_NORMAL = 0x00,
1435 IPR_SHUTDOWN_PREPARE_FOR_NORMAL = 0x40,
1436 IPR_SHUTDOWN_ABBREV = 0x80,
1437 IPR_SHUTDOWN_NONE = 0x100,
1438 IPR_SHUTDOWN_QUIESCE = 0x101,
1439};
1440
1441struct ipr_trace_entry {
1442 u32 time;
1443
1444 u8 op_code;
1445 u8 ata_op_code;
1446 u8 type;
1447#define IPR_TRACE_START 0x00
1448#define IPR_TRACE_FINISH 0xff
1449 u8 cmd_index;
1450
1451 __be32 res_handle;
1452 union {
1453 u32 ioasc;
1454 u32 add_data;
1455 u32 res_addr;
1456 } u;
1457};
1458
1459struct ipr_sglist {
1460 u32 order;
1461 u32 num_sg;
1462 u32 num_dma_sg;
1463 u32 buffer_len;
1464 struct scatterlist *scatterlist;
1465};
1466
1467enum ipr_sdt_state {
1468 INACTIVE,
1469 WAIT_FOR_DUMP,
1470 GET_DUMP,
1471 READ_DUMP,
1472 ABORT_DUMP,
1473 DUMP_OBTAINED
1474};
1475
1476/* Per-controller data */
1477struct ipr_ioa_cfg {
1478 char eye_catcher[8];
1479#define IPR_EYECATCHER "iprcfg"
1480
1481 struct list_head queue;
1482
1483 u8 in_reset_reload:1;
1484 u8 in_ioa_bringdown:1;
1485 u8 ioa_unit_checked:1;
1486 u8 dump_taken:1;
1487 u8 scan_enabled:1;
1488 u8 scan_done:1;
1489 u8 needs_hard_reset:1;
1490 u8 dual_raid:1;
1491 u8 needs_warm_reset:1;
1492 u8 msi_received:1;
1493 u8 sis64:1;
1494 u8 dump_timeout:1;
1495 u8 cfg_locked:1;
1496 u8 clear_isr:1;
1497 u8 probe_done:1;
1498 u8 scsi_unblock:1;
1499 u8 scsi_blocked:1;
1500
1501 u8 revid;
1502
1503 /*
1504 * Bitmaps for SIS64 generated target values
1505 */
1506 unsigned long target_ids[BITS_TO_LONGS(IPR_MAX_SIS64_DEVS)];
1507 unsigned long array_ids[BITS_TO_LONGS(IPR_MAX_SIS64_DEVS)];
1508 unsigned long vset_ids[BITS_TO_LONGS(IPR_MAX_SIS64_DEVS)];
1509
1510 u16 type; /* CCIN of the card */
1511
1512 u8 log_level;
1513#define IPR_MAX_LOG_LEVEL 4
1514#define IPR_DEFAULT_LOG_LEVEL 2
1515#define IPR_DEBUG_LOG_LEVEL 3
1516
1517#define IPR_NUM_TRACE_INDEX_BITS 8
1518#define IPR_NUM_TRACE_ENTRIES (1 << IPR_NUM_TRACE_INDEX_BITS)
1519#define IPR_TRACE_INDEX_MASK (IPR_NUM_TRACE_ENTRIES - 1)
1520#define IPR_TRACE_SIZE (sizeof(struct ipr_trace_entry) * IPR_NUM_TRACE_ENTRIES)
1521 char trace_start[8];
1522#define IPR_TRACE_START_LABEL "trace"
1523 struct ipr_trace_entry *trace;
1524 atomic_t trace_index;
1525
1526 char cfg_table_start[8];
1527#define IPR_CFG_TBL_START "cfg"
1528 union {
1529 struct ipr_config_table *cfg_table;
1530 struct ipr_config_table64 *cfg_table64;
1531 } u;
1532 dma_addr_t cfg_table_dma;
1533 u32 cfg_table_size;
1534 u32 max_devs_supported;
1535
1536 char resource_table_label[8];
1537#define IPR_RES_TABLE_LABEL "res_tbl"
1538 struct ipr_resource_entry *res_entries;
1539 struct list_head free_res_q;
1540 struct list_head used_res_q;
1541
1542 char ipr_hcam_label[8];
1543#define IPR_HCAM_LABEL "hcams"
1544 struct ipr_hostrcb *hostrcb[IPR_MAX_HCAMS];
1545 dma_addr_t hostrcb_dma[IPR_MAX_HCAMS];
1546 struct list_head hostrcb_free_q;
1547 struct list_head hostrcb_pending_q;
1548 struct list_head hostrcb_report_q;
1549
1550 struct ipr_hrr_queue hrrq[IPR_MAX_HRRQ_NUM];
1551 u32 hrrq_num;
1552 atomic_t hrrq_index;
1553 u16 identify_hrrq_index;
1554
1555 struct ipr_bus_attributes bus_attr[IPR_MAX_NUM_BUSES];
1556
1557 unsigned int transop_timeout;
1558 const struct ipr_chip_cfg_t *chip_cfg;
1559 const struct ipr_chip_t *ipr_chip;
1560
1561 void __iomem *hdw_dma_regs; /* iomapped PCI memory space */
1562 unsigned long hdw_dma_regs_pci; /* raw PCI memory space */
1563 void __iomem *ioa_mailbox;
1564 struct ipr_interrupts regs;
1565
1566 u16 saved_pcix_cmd_reg;
1567 u16 reset_retries;
1568
1569 u32 errors_logged;
1570 u32 doorbell;
1571
1572 struct Scsi_Host *host;
1573 struct pci_dev *pdev;
1574 struct ipr_sglist *ucode_sglist;
1575 u8 saved_mode_page_len;
1576
1577 struct work_struct work_q;
1578 struct work_struct scsi_add_work_q;
1579 struct workqueue_struct *reset_work_q;
1580
1581 wait_queue_head_t reset_wait_q;
1582 wait_queue_head_t msi_wait_q;
1583 wait_queue_head_t eeh_wait_q;
1584
1585 struct ipr_dump *dump;
1586 enum ipr_sdt_state sdt_state;
1587
1588 struct ipr_misc_cbs *vpd_cbs;
1589 dma_addr_t vpd_cbs_dma;
1590
1591 struct dma_pool *ipr_cmd_pool;
1592
1593 struct ipr_cmnd *reset_cmd;
1594 int (*reset) (struct ipr_cmnd *);
1595
1596 struct ata_host ata_host;
1597 char ipr_cmd_label[8];
1598#define IPR_CMD_LABEL "ipr_cmd"
1599 u32 max_cmds;
1600 struct ipr_cmnd **ipr_cmnd_list;
1601 dma_addr_t *ipr_cmnd_list_dma;
1602
1603 unsigned int nvectors;
1604
1605 struct {
1606 char desc[22];
1607 } vectors_info[IPR_MAX_MSIX_VECTORS];
1608
1609 u32 iopoll_weight;
1610
1611}; /* struct ipr_ioa_cfg */
1612
1613struct ipr_cmnd {
1614 struct ipr_ioarcb ioarcb;
1615 union {
1616 struct ipr_ioadl_desc ioadl[IPR_NUM_IOADL_ENTRIES];
1617 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
1618 struct ipr_ata64_ioadl ata_ioadl;
1619 } i;
1620 union {
1621 struct ipr_ioasa ioasa;
1622 struct ipr_ioasa64 ioasa64;
1623 } s;
1624 struct list_head queue;
1625 struct scsi_cmnd *scsi_cmd;
1626 struct ata_queued_cmd *qc;
1627 struct completion completion;
1628 struct timer_list timer;
1629 struct work_struct work;
1630 void (*fast_done) (struct ipr_cmnd *);
1631 void (*done) (struct ipr_cmnd *);
1632 int (*job_step) (struct ipr_cmnd *);
1633 int (*job_step_failed) (struct ipr_cmnd *);
1634 u16 cmd_index;
1635 u8 sense_buffer[SCSI_SENSE_BUFFERSIZE];
1636 dma_addr_t sense_buffer_dma;
1637 unsigned short dma_use_sg;
1638 dma_addr_t dma_addr;
1639 struct ipr_cmnd *sibling;
1640 union {
1641 enum ipr_shutdown_type shutdown_type;
1642 struct ipr_hostrcb *hostrcb;
1643 unsigned long time_left;
1644 unsigned long scratch;
1645 struct ipr_resource_entry *res;
1646 struct scsi_device *sdev;
1647 } u;
1648
1649 struct completion *eh_comp;
1650 struct ipr_hrr_queue *hrrq;
1651 struct ipr_ioa_cfg *ioa_cfg;
1652};
1653
1654struct ipr_ses_table_entry {
1655 char product_id[17];
1656 char compare_product_id_byte[17];
1657 u32 max_bus_speed_limit; /* MB/sec limit for this backplane */
1658};
1659
1660struct ipr_dump_header {
1661 u32 eye_catcher;
1662#define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1663 u32 len;
1664 u32 num_entries;
1665 u32 first_entry_offset;
1666 u32 status;
1667#define IPR_DUMP_STATUS_SUCCESS 0
1668#define IPR_DUMP_STATUS_QUAL_SUCCESS 2
1669#define IPR_DUMP_STATUS_FAILED 0xffffffff
1670 u32 os;
1671#define IPR_DUMP_OS_LINUX 0x4C4E5558
1672 u32 driver_name;
1673#define IPR_DUMP_DRIVER_NAME 0x49505232
1674}__attribute__((packed, aligned (4)));
1675
1676struct ipr_dump_entry_header {
1677 u32 eye_catcher;
1678#define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1679 u32 len;
1680 u32 num_elems;
1681 u32 offset;
1682 u32 data_type;
1683#define IPR_DUMP_DATA_TYPE_ASCII 0x41534349
1684#define IPR_DUMP_DATA_TYPE_BINARY 0x42494E41
1685 u32 id;
1686#define IPR_DUMP_IOA_DUMP_ID 0x494F4131
1687#define IPR_DUMP_LOCATION_ID 0x4C4F4341
1688#define IPR_DUMP_TRACE_ID 0x54524143
1689#define IPR_DUMP_DRIVER_VERSION_ID 0x44525652
1690#define IPR_DUMP_DRIVER_TYPE_ID 0x54595045
1691#define IPR_DUMP_IOA_CTRL_BLK 0x494F4342
1692#define IPR_DUMP_PEND_OPS 0x414F5053
1693 u32 status;
1694}__attribute__((packed, aligned (4)));
1695
1696struct ipr_dump_location_entry {
1697 struct ipr_dump_entry_header hdr;
1698 u8 location[20];
1699}__attribute__((packed));
1700
1701struct ipr_dump_trace_entry {
1702 struct ipr_dump_entry_header hdr;
1703 u32 trace[IPR_TRACE_SIZE / sizeof(u32)];
1704}__attribute__((packed, aligned (4)));
1705
1706struct ipr_dump_version_entry {
1707 struct ipr_dump_entry_header hdr;
1708 u8 version[sizeof(IPR_DRIVER_VERSION)];
1709};
1710
1711struct ipr_dump_ioa_type_entry {
1712 struct ipr_dump_entry_header hdr;
1713 u32 type;
1714 u32 fw_version;
1715};
1716
1717struct ipr_driver_dump {
1718 struct ipr_dump_header hdr;
1719 struct ipr_dump_version_entry version_entry;
1720 struct ipr_dump_location_entry location_entry;
1721 struct ipr_dump_ioa_type_entry ioa_type_entry;
1722 struct ipr_dump_trace_entry trace_entry;
1723}__attribute__((packed));
1724
1725struct ipr_ioa_dump {
1726 struct ipr_dump_entry_header hdr;
1727 struct ipr_sdt sdt;
1728 __be32 **ioa_data;
1729 u32 reserved;
1730 u32 next_page_index;
1731 u32 page_offset;
1732 u32 format;
1733}__attribute__((packed, aligned (4)));
1734
1735struct ipr_dump {
1736 struct kref kref;
1737 struct ipr_ioa_cfg *ioa_cfg;
1738 struct ipr_driver_dump driver_dump;
1739 struct ipr_ioa_dump ioa_dump;
1740};
1741
1742struct ipr_error_table_t {
1743 u32 ioasc;
1744 int log_ioasa;
1745 int log_hcam;
1746 char *error;
1747};
1748
1749struct ipr_software_inq_lid_info {
1750 __be32 load_id;
1751 __be32 timestamp[3];
1752}__attribute__((packed, aligned (4)));
1753
1754struct ipr_ucode_image_header {
1755 __be32 header_length;
1756 __be32 lid_table_offset;
1757 u8 major_release;
1758 u8 card_type;
1759 u8 minor_release[2];
1760 u8 reserved[20];
1761 char eyecatcher[16];
1762 __be32 num_lids;
1763 struct ipr_software_inq_lid_info lid[1];
1764}__attribute__((packed, aligned (4)));
1765
1766/*
1767 * Macros
1768 */
1769#define IPR_DBG_CMD(CMD) if (ipr_debug) { CMD; }
1770
1771#ifdef CONFIG_SCSI_IPR_TRACE
1772#define ipr_create_trace_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1773#define ipr_remove_trace_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1774#else
1775#define ipr_create_trace_file(kobj, attr) 0
1776#define ipr_remove_trace_file(kobj, attr) do { } while(0)
1777#endif
1778
1779#ifdef CONFIG_SCSI_IPR_DUMP
1780#define ipr_create_dump_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1781#define ipr_remove_dump_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1782#else
1783#define ipr_create_dump_file(kobj, attr) 0
1784#define ipr_remove_dump_file(kobj, attr) do { } while(0)
1785#endif
1786
1787/*
1788 * Error logging macros
1789 */
1790#define ipr_err(...) printk(KERN_ERR IPR_NAME ": "__VA_ARGS__)
1791#define ipr_info(...) printk(KERN_INFO IPR_NAME ": "__VA_ARGS__)
1792#define ipr_dbg(...) IPR_DBG_CMD(printk(KERN_INFO IPR_NAME ": "__VA_ARGS__))
1793
1794#define ipr_res_printk(level, ioa_cfg, bus, target, lun, fmt, ...) \
1795 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1796 bus, target, lun, ##__VA_ARGS__)
1797
1798#define ipr_res_err(ioa_cfg, res, fmt, ...) \
1799 ipr_res_printk(KERN_ERR, ioa_cfg, (res)->bus, (res)->target, (res)->lun, fmt, ##__VA_ARGS__)
1800
1801#define ipr_ra_printk(level, ioa_cfg, ra, fmt, ...) \
1802 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1803 (ra).bus, (ra).target, (ra).lun, ##__VA_ARGS__)
1804
1805#define ipr_ra_err(ioa_cfg, ra, fmt, ...) \
1806 ipr_ra_printk(KERN_ERR, ioa_cfg, ra, fmt, ##__VA_ARGS__)
1807
1808#define ipr_phys_res_err(ioa_cfg, res, fmt, ...) \
1809{ \
1810 if ((res).bus >= IPR_MAX_NUM_BUSES) { \
1811 ipr_err(fmt": unknown\n", ##__VA_ARGS__); \
1812 } else { \
1813 ipr_err(fmt": %d:%d:%d:%d\n", \
1814 ##__VA_ARGS__, (ioa_cfg)->host->host_no, \
1815 (res).bus, (res).target, (res).lun); \
1816 } \
1817}
1818
1819#define ipr_hcam_err(hostrcb, fmt, ...) \
1820{ \
1821 if (ipr_is_device(hostrcb)) { \
1822 if ((hostrcb)->ioa_cfg->sis64) { \
1823 printk(KERN_ERR IPR_NAME ": %s: " fmt, \
1824 ipr_format_res_path(hostrcb->ioa_cfg, \
1825 hostrcb->hcam.u.error64.fd_res_path, \
1826 hostrcb->rp_buffer, \
1827 sizeof(hostrcb->rp_buffer)), \
1828 __VA_ARGS__); \
1829 } else { \
1830 ipr_ra_err((hostrcb)->ioa_cfg, \
1831 (hostrcb)->hcam.u.error.fd_res_addr, \
1832 fmt, __VA_ARGS__); \
1833 } \
1834 } else { \
1835 dev_err(&(hostrcb)->ioa_cfg->pdev->dev, fmt, __VA_ARGS__); \
1836 } \
1837}
1838
1839#define ipr_trace ipr_dbg("%s: %s: Line: %d\n",\
1840 __FILE__, __func__, __LINE__)
1841
1842#define ENTER IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Entering %s\n", __func__))
1843#define LEAVE IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Leaving %s\n", __func__))
1844
1845#define ipr_err_separator \
1846ipr_err("----------------------------------------------------------\n")
1847
1848
1849/*
1850 * Inlines
1851 */
1852
1853/**
1854 * ipr_is_ioa_resource - Determine if a resource is the IOA
1855 * @res: resource entry struct
1856 *
1857 * Return value:
1858 * 1 if IOA / 0 if not IOA
1859 **/
1860static inline int ipr_is_ioa_resource(struct ipr_resource_entry *res)
1861{
1862 return res->type == IPR_RES_TYPE_IOAFP;
1863}
1864
1865/**
1866 * ipr_is_af_dasd_device - Determine if a resource is an AF DASD
1867 * @res: resource entry struct
1868 *
1869 * Return value:
1870 * 1 if AF DASD / 0 if not AF DASD
1871 **/
1872static inline int ipr_is_af_dasd_device(struct ipr_resource_entry *res)
1873{
1874 return res->type == IPR_RES_TYPE_AF_DASD ||
1875 res->type == IPR_RES_TYPE_REMOTE_AF_DASD;
1876}
1877
1878/**
1879 * ipr_is_vset_device - Determine if a resource is a VSET
1880 * @res: resource entry struct
1881 *
1882 * Return value:
1883 * 1 if VSET / 0 if not VSET
1884 **/
1885static inline int ipr_is_vset_device(struct ipr_resource_entry *res)
1886{
1887 return res->type == IPR_RES_TYPE_VOLUME_SET;
1888}
1889
1890/**
1891 * ipr_is_gscsi - Determine if a resource is a generic scsi resource
1892 * @res: resource entry struct
1893 *
1894 * Return value:
1895 * 1 if GSCSI / 0 if not GSCSI
1896 **/
1897static inline int ipr_is_gscsi(struct ipr_resource_entry *res)
1898{
1899 return res->type == IPR_RES_TYPE_GENERIC_SCSI;
1900}
1901
1902/**
1903 * ipr_is_scsi_disk - Determine if a resource is a SCSI disk
1904 * @res: resource entry struct
1905 *
1906 * Return value:
1907 * 1 if SCSI disk / 0 if not SCSI disk
1908 **/
1909static inline int ipr_is_scsi_disk(struct ipr_resource_entry *res)
1910{
1911 if (ipr_is_af_dasd_device(res) ||
1912 (ipr_is_gscsi(res) && IPR_IS_DASD_DEVICE(res->std_inq_data)))
1913 return 1;
1914 else
1915 return 0;
1916}
1917
1918/**
1919 * ipr_is_gata - Determine if a resource is a generic ATA resource
1920 * @res: resource entry struct
1921 *
1922 * Return value:
1923 * 1 if GATA / 0 if not GATA
1924 **/
1925static inline int ipr_is_gata(struct ipr_resource_entry *res)
1926{
1927 return res->type == IPR_RES_TYPE_GENERIC_ATA;
1928}
1929
1930/**
1931 * ipr_is_naca_model - Determine if a resource is using NACA queueing model
1932 * @res: resource entry struct
1933 *
1934 * Return value:
1935 * 1 if NACA queueing model / 0 if not NACA queueing model
1936 **/
1937static inline int ipr_is_naca_model(struct ipr_resource_entry *res)
1938{
1939 if (ipr_is_gscsi(res) && res->qmodel == IPR_QUEUE_NACA_MODEL)
1940 return 1;
1941 return 0;
1942}
1943
1944/**
1945 * ipr_is_device - Determine if the hostrcb structure is related to a device
1946 * @hostrcb: host resource control blocks struct
1947 *
1948 * Return value:
1949 * 1 if AF / 0 if not AF
1950 **/
1951static inline int ipr_is_device(struct ipr_hostrcb *hostrcb)
1952{
1953 struct ipr_res_addr *res_addr;
1954 u8 *res_path;
1955
1956 if (hostrcb->ioa_cfg->sis64) {
1957 res_path = &hostrcb->hcam.u.error64.fd_res_path[0];
1958 if ((res_path[0] == 0x00 || res_path[0] == 0x80 ||
1959 res_path[0] == 0x81) && res_path[2] != 0xFF)
1960 return 1;
1961 } else {
1962 res_addr = &hostrcb->hcam.u.error.fd_res_addr;
1963
1964 if ((res_addr->bus < IPR_MAX_NUM_BUSES) &&
1965 (res_addr->target < (IPR_MAX_NUM_TARGETS_PER_BUS - 1)))
1966 return 1;
1967 }
1968 return 0;
1969}
1970
1971/**
1972 * ipr_sdt_is_fmt2 - Determine if a SDT address is in format 2
1973 * @sdt_word: SDT address
1974 *
1975 * Return value:
1976 * 1 if format 2 / 0 if not
1977 **/
1978static inline int ipr_sdt_is_fmt2(u32 sdt_word)
1979{
1980 u32 bar_sel = IPR_GET_FMT2_BAR_SEL(sdt_word);
1981
1982 switch (bar_sel) {
1983 case IPR_SDT_FMT2_BAR0_SEL:
1984 case IPR_SDT_FMT2_BAR1_SEL:
1985 case IPR_SDT_FMT2_BAR2_SEL:
1986 case IPR_SDT_FMT2_BAR3_SEL:
1987 case IPR_SDT_FMT2_BAR4_SEL:
1988 case IPR_SDT_FMT2_BAR5_SEL:
1989 case IPR_SDT_FMT2_EXP_ROM_SEL:
1990 return 1;
1991 };
1992
1993 return 0;
1994}
1995
1996#ifndef writeq
1997static inline void writeq(u64 val, void __iomem *addr)
1998{
1999 writel(((u32) (val >> 32)), addr);
2000 writel(((u32) (val)), (addr + 4));
2001}
2002#endif
2003
2004#endif /* _IPR_H */
2005