1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
2 | /* |
3 | * Workbit NinjaSCSI-32Bi/UDE PCI/CardBus SCSI Host Bus Adapter driver |
4 | * Basic data header |
5 | */ |
6 | |
7 | #ifndef _NSP32_H |
8 | #define _NSP32_H |
9 | |
10 | //#define NSP32_DEBUG 9 |
11 | |
12 | /* |
13 | * VENDOR/DEVICE ID |
14 | */ |
15 | #define PCI_VENDOR_ID_IODATA 0x10fc |
16 | #define PCI_VENDOR_ID_WORKBIT 0x1145 |
17 | |
18 | #define PCI_DEVICE_ID_NINJASCSI_32BI_CBSC_II 0x0005 |
19 | #define PCI_DEVICE_ID_NINJASCSI_32BI_KME 0xf007 |
20 | #define PCI_DEVICE_ID_NINJASCSI_32BI_WBT 0x8007 |
21 | #define PCI_DEVICE_ID_WORKBIT_STANDARD 0xf010 |
22 | #define PCI_DEVICE_ID_WORKBIT_DUALEDGE 0xf011 |
23 | #define PCI_DEVICE_ID_NINJASCSI_32BI_LOGITEC 0xf012 |
24 | #define PCI_DEVICE_ID_NINJASCSI_32BIB_LOGITEC 0xf013 |
25 | #define PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO 0xf015 |
26 | #define PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO_II 0x8009 |
27 | |
28 | /* |
29 | * MODEL |
30 | */ |
31 | enum { |
32 | MODEL_IODATA = 0, |
33 | MODEL_KME = 1, |
34 | MODEL_WORKBIT = 2, |
35 | MODEL_LOGITEC = 3, |
36 | MODEL_PCI_WORKBIT = 4, |
37 | MODEL_PCI_LOGITEC = 5, |
38 | MODEL_PCI_MELCO = 6, |
39 | }; |
40 | |
41 | static char * nsp32_model[] = { |
42 | "I-O DATA CBSC-II CardBus card" , |
43 | "KME SCSI CardBus card" , |
44 | "Workbit duo SCSI CardBus card" , |
45 | "Logitec CardBus card with external ROM" , |
46 | "Workbit / I-O DATA PCI card" , |
47 | "Logitec PCI card with external ROM" , |
48 | "Melco CardBus/PCI card with external ROM" , |
49 | }; |
50 | |
51 | |
52 | /* |
53 | * SCSI Generic Definitions |
54 | */ |
55 | #define EXTENDED_SDTR_LEN 0x03 |
56 | |
57 | /* Little Endian */ |
58 | typedef u32 u32_le; |
59 | typedef u16 u16_le; |
60 | |
61 | /* |
62 | * BASIC Definitions |
63 | */ |
64 | #ifndef TRUE |
65 | # define TRUE 1 |
66 | #endif |
67 | #ifndef FALSE |
68 | # define FALSE 0 |
69 | #endif |
70 | #define ASSERT 1 |
71 | #define NEGATE 0 |
72 | |
73 | |
74 | /*******************/ |
75 | /* normal register */ |
76 | /*******************/ |
77 | /* |
78 | * Don't access below register with Double Word: |
79 | * +00, +04, +08, +0c, +64, +80, +84, +88, +90, +c4, +c8, +cc, +d0. |
80 | */ |
81 | #define IRQ_CONTROL 0x00 /* BASE+00, W, W */ |
82 | #define IRQ_STATUS 0x00 /* BASE+00, W, R */ |
83 | # define IRQSTATUS_LATCHED_MSG BIT(0) |
84 | # define IRQSTATUS_LATCHED_IO BIT(1) |
85 | # define IRQSTATUS_LATCHED_CD BIT(2) |
86 | # define IRQSTATUS_LATCHED_BUS_FREE BIT(3) |
87 | # define IRQSTATUS_RESELECT_OCCUER BIT(4) |
88 | # define IRQSTATUS_PHASE_CHANGE_IRQ BIT(5) |
89 | # define IRQSTATUS_SCSIRESET_IRQ BIT(6) |
90 | # define IRQSTATUS_TIMER_IRQ BIT(7) |
91 | # define IRQSTATUS_FIFO_SHLD_IRQ BIT(8) |
92 | # define IRQSTATUS_PCI_IRQ BIT(9) |
93 | # define IRQSTATUS_BMCNTERR_IRQ BIT(10) |
94 | # define IRQSTATUS_AUTOSCSI_IRQ BIT(11) |
95 | # define PCI_IRQ_MASK BIT(12) |
96 | # define TIMER_IRQ_MASK BIT(13) |
97 | # define FIFO_IRQ_MASK BIT(14) |
98 | # define SCSI_IRQ_MASK BIT(15) |
99 | # define IRQ_CONTROL_ALL_IRQ_MASK (PCI_IRQ_MASK | \ |
100 | TIMER_IRQ_MASK | \ |
101 | FIFO_IRQ_MASK | \ |
102 | SCSI_IRQ_MASK ) |
103 | # define IRQSTATUS_ANY_IRQ (IRQSTATUS_RESELECT_OCCUER | \ |
104 | IRQSTATUS_PHASE_CHANGE_IRQ | \ |
105 | IRQSTATUS_SCSIRESET_IRQ | \ |
106 | IRQSTATUS_TIMER_IRQ | \ |
107 | IRQSTATUS_FIFO_SHLD_IRQ | \ |
108 | IRQSTATUS_PCI_IRQ | \ |
109 | IRQSTATUS_BMCNTERR_IRQ | \ |
110 | IRQSTATUS_AUTOSCSI_IRQ ) |
111 | |
112 | #define TRANSFER_CONTROL 0x02 /* BASE+02, W, W */ |
113 | #define TRANSFER_STATUS 0x02 /* BASE+02, W, R */ |
114 | # define CB_MMIO_MODE BIT(0) |
115 | # define CB_IO_MODE BIT(1) |
116 | # define BM_TEST BIT(2) |
117 | # define BM_TEST_DIR BIT(3) |
118 | # define DUAL_EDGE_ENABLE BIT(4) |
119 | # define NO_TRANSFER_TO_HOST BIT(5) |
120 | # define TRANSFER_GO BIT(7) |
121 | # define BLIEND_MODE BIT(8) |
122 | # define BM_START BIT(9) |
123 | # define ADVANCED_BM_WRITE BIT(10) |
124 | # define BM_SINGLE_MODE BIT(11) |
125 | # define FIFO_TRUE_FULL BIT(12) |
126 | # define FIFO_TRUE_EMPTY BIT(13) |
127 | # define ALL_COUNTER_CLR BIT(14) |
128 | # define FIFOTEST BIT(15) |
129 | |
130 | #define INDEX_REG 0x04 /* BASE+04, Byte(R/W), Word(R) */ |
131 | |
132 | #define TIMER_SET 0x06 /* BASE+06, W, R/W */ |
133 | # define TIMER_CNT_MASK (0xff) |
134 | # define TIMER_STOP BIT(8) |
135 | |
136 | #define DATA_REG_LOW 0x08 /* BASE+08, LowW, R/W */ |
137 | #define DATA_REG_HI 0x0a /* BASE+0a, Hi-W, R/W */ |
138 | |
139 | #define FIFO_REST_CNT 0x0c /* BASE+0c, W, R/W */ |
140 | # define FIFO_REST_MASK 0x1ff |
141 | # define FIFO_EMPTY_SHLD_FLAG BIT(14) |
142 | # define FIFO_FULL_SHLD_FLAG BIT(15) |
143 | |
144 | #define SREQ_SMPL_RATE 0x0f /* BASE+0f, B, R/W */ |
145 | # define SREQSMPLRATE_RATE0 BIT(0) |
146 | # define SREQSMPLRATE_RATE1 BIT(1) |
147 | # define SAMPLING_ENABLE BIT(2) |
148 | # define SMPL_40M (0) /* 40MHz: 0-100ns/period */ |
149 | # define SMPL_20M (SREQSMPLRATE_RATE0) /* 20MHz: 100-200ns/period */ |
150 | # define SMPL_10M (SREQSMPLRATE_RATE1) /* 10Mhz: 200- ns/period */ |
151 | |
152 | #define SCSI_BUS_CONTROL 0x10 /* BASE+10, B, R/W */ |
153 | # define BUSCTL_SEL BIT(0) |
154 | # define BUSCTL_RST BIT(1) |
155 | # define BUSCTL_DATAOUT_ENB BIT(2) |
156 | # define BUSCTL_ATN BIT(3) |
157 | # define BUSCTL_ACK BIT(4) |
158 | # define BUSCTL_BSY BIT(5) |
159 | # define AUTODIRECTION BIT(6) |
160 | # define ACKENB BIT(7) |
161 | |
162 | #define CLR_COUNTER 0x12 /* BASE+12, B, W */ |
163 | # define ACK_COUNTER_CLR BIT(0) |
164 | # define SREQ_COUNTER_CLR BIT(1) |
165 | # define FIFO_HOST_POINTER_CLR BIT(2) |
166 | # define FIFO_REST_COUNT_CLR BIT(3) |
167 | # define BM_COUNTER_CLR BIT(4) |
168 | # define SAVED_ACK_CLR BIT(5) |
169 | # define CLRCOUNTER_ALLMASK (ACK_COUNTER_CLR | \ |
170 | SREQ_COUNTER_CLR | \ |
171 | FIFO_HOST_POINTER_CLR | \ |
172 | FIFO_REST_COUNT_CLR | \ |
173 | BM_COUNTER_CLR | \ |
174 | SAVED_ACK_CLR ) |
175 | |
176 | #define SCSI_BUS_MONITOR 0x12 /* BASE+12, B, R */ |
177 | # define BUSMON_MSG BIT(0) |
178 | # define BUSMON_IO BIT(1) |
179 | # define BUSMON_CD BIT(2) |
180 | # define BUSMON_BSY BIT(3) |
181 | # define BUSMON_ACK BIT(4) |
182 | # define BUSMON_REQ BIT(5) |
183 | # define BUSMON_SEL BIT(6) |
184 | # define BUSMON_ATN BIT(7) |
185 | |
186 | #define COMMAND_DATA 0x14 /* BASE+14, B, R/W */ |
187 | |
188 | #define PARITY_CONTROL 0x16 /* BASE+16, B, W */ |
189 | # define PARITY_CHECK_ENABLE BIT(0) |
190 | # define PARITY_ERROR_CLEAR BIT(1) |
191 | #define PARITY_STATUS 0x16 /* BASE+16, B, R */ |
192 | //# define PARITY_CHECK_ENABLE BIT(0) |
193 | # define PARITY_ERROR_NORMAL BIT(1) |
194 | # define PARITY_ERROR_LSB BIT(1) |
195 | # define PARITY_ERROR_MSB BIT(2) |
196 | |
197 | #define RESELECT_ID 0x18 /* BASE+18, B, R */ |
198 | |
199 | #define COMMAND_CONTROL 0x18 /* BASE+18, W, W */ |
200 | # define CLEAR_CDB_FIFO_POINTER BIT(0) |
201 | # define AUTO_COMMAND_PHASE BIT(1) |
202 | # define AUTOSCSI_START BIT(2) |
203 | # define AUTOSCSI_RESTART BIT(3) |
204 | # define AUTO_PARAMETER BIT(4) |
205 | # define AUTO_ATN BIT(5) |
206 | # define AUTO_MSGIN_00_OR_04 BIT(6) |
207 | # define AUTO_MSGIN_02 BIT(7) |
208 | # define AUTO_MSGIN_03 BIT(8) |
209 | |
210 | #define SET_ARBIT 0x1a /* BASE+1a, B, W */ |
211 | # define ARBIT_GO BIT(0) |
212 | # define ARBIT_CLEAR BIT(1) |
213 | |
214 | #define ARBIT_STATUS 0x1a /* BASE+1a, B, R */ |
215 | //# define ARBIT_GO BIT(0) |
216 | # define ARBIT_WIN BIT(1) |
217 | # define ARBIT_FAIL BIT(2) |
218 | # define AUTO_PARAMETER_VALID BIT(3) |
219 | # define SGT_VALID BIT(4) |
220 | |
221 | #define SYNC_REG 0x1c /* BASE+1c, B, R/W */ |
222 | |
223 | #define ACK_WIDTH 0x1d /* BASE+1d, B, R/W */ |
224 | |
225 | #define SCSI_DATA_WITH_ACK 0x20 /* BASE+20, B, R/W */ |
226 | #define SCSI_OUT_LATCH_TARGET_ID 0x22 /* BASE+22, B, W */ |
227 | #define SCSI_DATA_IN 0x22 /* BASE+22, B, R */ |
228 | |
229 | #define SCAM_CONTROL 0x24 /* BASE+24, B, W */ |
230 | #define SCAM_STATUS 0x24 /* BASE+24, B, R */ |
231 | # define SCAM_MSG BIT(0) |
232 | # define SCAM_IO BIT(1) |
233 | # define SCAM_CD BIT(2) |
234 | # define SCAM_BSY BIT(3) |
235 | # define SCAM_SEL BIT(4) |
236 | # define SCAM_XFEROK BIT(5) |
237 | |
238 | #define SCAM_DATA 0x26 /* BASE+26, B, R/W */ |
239 | # define SD0 BIT(0) |
240 | # define SD1 BIT(1) |
241 | # define SD2 BIT(2) |
242 | # define SD3 BIT(3) |
243 | # define SD4 BIT(4) |
244 | # define SD5 BIT(5) |
245 | # define SD6 BIT(6) |
246 | # define SD7 BIT(7) |
247 | |
248 | #define SACK_CNT 0x28 /* BASE+28, DW, R/W */ |
249 | #define SREQ_CNT 0x2c /* BASE+2c, DW, R/W */ |
250 | |
251 | #define FIFO_DATA_LOW 0x30 /* BASE+30, B/W/DW, R/W */ |
252 | #define FIFO_DATA_HIGH 0x32 /* BASE+32, B/W, R/W */ |
253 | #define BM_START_ADR 0x34 /* BASE+34, DW, R/W */ |
254 | |
255 | #define BM_CNT 0x38 /* BASE+38, DW, R/W */ |
256 | # define BM_COUNT_MASK 0x0001ffffUL |
257 | # define SGTEND BIT(31) /* Last SGT marker */ |
258 | |
259 | #define SGT_ADR 0x3c /* BASE+3c, DW, R/W */ |
260 | #define WAIT_REG 0x40 /* Bi only */ |
261 | |
262 | #define SCSI_EXECUTE_PHASE 0x40 /* BASE+40, W, R */ |
263 | # define COMMAND_PHASE BIT(0) |
264 | # define DATA_IN_PHASE BIT(1) |
265 | # define DATA_OUT_PHASE BIT(2) |
266 | # define MSGOUT_PHASE BIT(3) |
267 | # define STATUS_PHASE BIT(4) |
268 | # define ILLEGAL_PHASE BIT(5) |
269 | # define BUS_FREE_OCCUER BIT(6) |
270 | # define MSG_IN_OCCUER BIT(7) |
271 | # define MSG_OUT_OCCUER BIT(8) |
272 | # define SELECTION_TIMEOUT BIT(9) |
273 | # define MSGIN_00_VALID BIT(10) |
274 | # define MSGIN_02_VALID BIT(11) |
275 | # define MSGIN_03_VALID BIT(12) |
276 | # define MSGIN_04_VALID BIT(13) |
277 | # define AUTOSCSI_BUSY BIT(15) |
278 | |
279 | #define SCSI_CSB_IN 0x42 /* BASE+42, B, R */ |
280 | |
281 | #define SCSI_MSG_OUT 0x44 /* BASE+44, DW, R/W */ |
282 | # define MSGOUT_COUNT_MASK (BIT(0)|BIT(1)) |
283 | # define MV_VALID BIT(7) |
284 | |
285 | #define SEL_TIME_OUT 0x48 /* BASE+48, W, R/W */ |
286 | #define SAVED_SACK_CNT 0x4c /* BASE+4c, DW, R */ |
287 | |
288 | #define HTOSDATADELAY 0x50 /* BASE+50, B, R/W */ |
289 | #define STOHDATADELAY 0x54 /* BASE+54, B, R/W */ |
290 | #define ACKSUMCHECKRD 0x58 /* BASE+58, W, R */ |
291 | #define REQSUMCHECKRD 0x5c /* BASE+5c, W, R */ |
292 | |
293 | |
294 | /********************/ |
295 | /* indexed register */ |
296 | /********************/ |
297 | |
298 | #define CLOCK_DIV 0x00 /* BASE+08, IDX+00, B, R/W */ |
299 | # define CLOCK_2 BIT(0) /* MCLK/2 */ |
300 | # define CLOCK_4 BIT(1) /* MCLK/4 */ |
301 | # define PCICLK BIT(7) /* PCICLK (33MHz) */ |
302 | |
303 | #define TERM_PWR_CONTROL 0x01 /* BASE+08, IDX+01, B, R/W */ |
304 | # define BPWR BIT(0) |
305 | # define SENSE BIT(1) /* Read Only */ |
306 | |
307 | #define EXT_PORT_DDR 0x02 /* BASE+08, IDX+02, B, R/W */ |
308 | #define EXT_PORT 0x03 /* BASE+08, IDX+03, B, R/W */ |
309 | # define LED_ON (0) |
310 | # define LED_OFF BIT(0) |
311 | |
312 | #define IRQ_SELECT 0x04 /* BASE+08, IDX+04, W, R/W */ |
313 | # define IRQSELECT_RESELECT_IRQ BIT(0) |
314 | # define IRQSELECT_PHASE_CHANGE_IRQ BIT(1) |
315 | # define IRQSELECT_SCSIRESET_IRQ BIT(2) |
316 | # define IRQSELECT_TIMER_IRQ BIT(3) |
317 | # define IRQSELECT_FIFO_SHLD_IRQ BIT(4) |
318 | # define IRQSELECT_TARGET_ABORT_IRQ BIT(5) |
319 | # define IRQSELECT_MASTER_ABORT_IRQ BIT(6) |
320 | # define IRQSELECT_SERR_IRQ BIT(7) |
321 | # define IRQSELECT_PERR_IRQ BIT(8) |
322 | # define IRQSELECT_BMCNTERR_IRQ BIT(9) |
323 | # define IRQSELECT_AUTO_SCSI_SEQ_IRQ BIT(10) |
324 | |
325 | #define OLD_SCSI_PHASE 0x05 /* BASE+08, IDX+05, B, R */ |
326 | # define OLD_MSG BIT(0) |
327 | # define OLD_IO BIT(1) |
328 | # define OLD_CD BIT(2) |
329 | # define OLD_BUSY BIT(3) |
330 | |
331 | #define FIFO_FULL_SHLD_COUNT 0x06 /* BASE+08, IDX+06, B, R/W */ |
332 | #define FIFO_EMPTY_SHLD_COUNT 0x07 /* BASE+08, IDX+07, B, R/W */ |
333 | |
334 | #define EXP_ROM_CONTROL 0x08 /* BASE+08, IDX+08, B, R/W */ /* external ROM control */ |
335 | # define ROM_WRITE_ENB BIT(0) |
336 | # define IO_ACCESS_ENB BIT(1) |
337 | # define ROM_ADR_CLEAR BIT(2) |
338 | |
339 | #define EXP_ROM_ADR 0x09 /* BASE+08, IDX+09, W, R/W */ |
340 | |
341 | #define EXP_ROM_DATA 0x0a /* BASE+08, IDX+0a, B, R/W */ |
342 | |
343 | #define CHIP_MODE 0x0b /* BASE+08, IDX+0b, B, R */ /* NinjaSCSI-32Bi only */ |
344 | # define OEM0 BIT(1) /* OEM select */ /* 00=I-O DATA, 01=KME, 10=Workbit, 11=Ext ROM */ |
345 | # define OEM1 BIT(2) /* OEM select */ |
346 | # define OPTB BIT(3) /* KME mode select */ |
347 | # define OPTC BIT(4) /* KME mode select */ |
348 | # define OPTD BIT(5) /* KME mode select */ |
349 | # define OPTE BIT(6) /* KME mode select */ |
350 | # define OPTF BIT(7) /* Power management */ |
351 | |
352 | #define MISC_WR 0x0c /* BASE+08, IDX+0c, W, R/W */ |
353 | #define MISC_RD 0x0c |
354 | # define SCSI_DIRECTION_DETECTOR_SELECT BIT(0) |
355 | # define SCSI2_HOST_DIRECTION_VALID BIT(1) /* Read only */ |
356 | # define HOST2_SCSI_DIRECTION_VALID BIT(2) /* Read only */ |
357 | # define DELAYED_BMSTART BIT(3) |
358 | # define MASTER_TERMINATION_SELECT BIT(4) |
359 | # define BMREQ_NEGATE_TIMING_SEL BIT(5) |
360 | # define AUTOSEL_TIMING_SEL BIT(6) |
361 | # define MISC_MABORT_MASK BIT(7) |
362 | # define BMSTOP_CHANGE2_NONDATA_PHASE BIT(8) |
363 | |
364 | #define BM_CYCLE 0x0d /* BASE+08, IDX+0d, B, R/W */ |
365 | # define BM_CYCLE0 BIT(0) |
366 | # define BM_CYCLE1 BIT(1) |
367 | # define BM_FRAME_ASSERT_TIMING BIT(2) |
368 | # define BM_IRDY_ASSERT_TIMING BIT(3) |
369 | # define BM_SINGLE_BUS_MASTER BIT(4) |
370 | # define MEMRD_CMD0 BIT(5) |
371 | # define SGT_AUTO_PARA_MEMED_CMD BIT(6) |
372 | # define MEMRD_CMD1 BIT(7) |
373 | |
374 | |
375 | #define SREQ_EDGH 0x0e /* BASE+08, IDX+0e, B, W */ |
376 | # define SREQ_EDGH_SELECT BIT(0) |
377 | |
378 | #define UP_CNT 0x0f /* BASE+08, IDX+0f, B, W */ |
379 | # define REQCNT_UP BIT(0) |
380 | # define ACKCNT_UP BIT(1) |
381 | # define BMADR_UP BIT(4) |
382 | # define BMCNT_UP BIT(5) |
383 | # define SGT_CNT_UP BIT(7) |
384 | |
385 | #define CFG_CMD_STR 0x10 /* BASE+08, IDX+10, W, R */ |
386 | #define CFG_LATE_CACHE 0x11 /* BASE+08, IDX+11, W, R/W */ |
387 | #define CFG_BASE_ADR_1 0x12 /* BASE+08, IDX+12, W, R */ |
388 | #define CFG_BASE_ADR_2 0x13 /* BASE+08, IDX+13, W, R */ |
389 | #define CFG_INLINE 0x14 /* BASE+08, IDX+14, W, R */ |
390 | |
391 | #define SERIAL_ROM_CTL 0x15 /* BASE+08, IDX+15, B, R */ |
392 | # define SCL BIT(0) |
393 | # define ENA BIT(1) |
394 | # define SDA BIT(2) |
395 | |
396 | #define FIFO_HST_POINTER 0x16 /* BASE+08, IDX+16, B, R/W */ |
397 | #define SREQ_DELAY 0x17 /* BASE+08, IDX+17, B, R/W */ |
398 | #define SACK_DELAY 0x18 /* BASE+08, IDX+18, B, R/W */ |
399 | #define SREQ_NOISE_CANCEL 0x19 /* BASE+08, IDX+19, B, R/W */ |
400 | #define SDP_NOISE_CANCEL 0x1a /* BASE+08, IDX+1a, B, R/W */ |
401 | #define DELAY_TEST 0x1b /* BASE+08, IDX+1b, B, R/W */ |
402 | #define SD0_NOISE_CANCEL 0x20 /* BASE+08, IDX+20, B, R/W */ |
403 | #define SD1_NOISE_CANCEL 0x21 /* BASE+08, IDX+21, B, R/W */ |
404 | #define SD2_NOISE_CANCEL 0x22 /* BASE+08, IDX+22, B, R/W */ |
405 | #define SD3_NOISE_CANCEL 0x23 /* BASE+08, IDX+23, B, R/W */ |
406 | #define SD4_NOISE_CANCEL 0x24 /* BASE+08, IDX+24, B, R/W */ |
407 | #define SD5_NOISE_CANCEL 0x25 /* BASE+08, IDX+25, B, R/W */ |
408 | #define SD6_NOISE_CANCEL 0x26 /* BASE+08, IDX+26, B, R/W */ |
409 | #define SD7_NOISE_CANCEL 0x27 /* BASE+08, IDX+27, B, R/W */ |
410 | |
411 | |
412 | /* |
413 | * Useful Bus Monitor status combinations. |
414 | */ |
415 | #define BUSMON_BUS_FREE 0 |
416 | #define BUSMON_COMMAND ( BUSMON_BSY | BUSMON_CD | BUSMON_REQ ) |
417 | #define BUSMON_MESSAGE_IN ( BUSMON_BSY | BUSMON_MSG | BUSMON_IO | BUSMON_CD | BUSMON_REQ ) |
418 | #define BUSMON_MESSAGE_OUT ( BUSMON_BSY | BUSMON_MSG | BUSMON_CD | BUSMON_REQ ) |
419 | #define BUSMON_DATA_IN ( BUSMON_BSY | BUSMON_IO | BUSMON_REQ ) |
420 | #define BUSMON_DATA_OUT ( BUSMON_BSY | BUSMON_REQ ) |
421 | #define BUSMON_STATUS ( BUSMON_BSY | BUSMON_IO | BUSMON_CD | BUSMON_REQ ) |
422 | #define BUSMON_RESELECT ( BUSMON_IO | BUSMON_SEL) |
423 | #define BUSMON_PHASE_MASK ( BUSMON_MSG | BUSMON_IO | BUSMON_CD | BUSMON_SEL) |
424 | |
425 | #define BUSPHASE_COMMAND ( BUSMON_COMMAND & BUSMON_PHASE_MASK ) |
426 | #define BUSPHASE_MESSAGE_IN ( BUSMON_MESSAGE_IN & BUSMON_PHASE_MASK ) |
427 | #define BUSPHASE_MESSAGE_OUT ( BUSMON_MESSAGE_OUT & BUSMON_PHASE_MASK ) |
428 | #define BUSPHASE_DATA_IN ( BUSMON_DATA_IN & BUSMON_PHASE_MASK ) |
429 | #define BUSPHASE_DATA_OUT ( BUSMON_DATA_OUT & BUSMON_PHASE_MASK ) |
430 | #define BUSPHASE_STATUS ( BUSMON_STATUS & BUSMON_PHASE_MASK ) |
431 | #define BUSPHASE_SELECT ( BUSMON_SEL | BUSMON_IO ) |
432 | |
433 | |
434 | /************************************************************************ |
435 | * structure for DMA/Scatter Gather list |
436 | */ |
437 | #define NSP32_SG_SIZE SG_ALL |
438 | |
439 | typedef struct _nsp32_sgtable { |
440 | /* values must be little endian */ |
441 | u32_le addr; /* transfer address */ |
442 | u32_le len; /* transfer length. BIT(31) is for SGT_END mark */ |
443 | } __attribute__ ((packed)) nsp32_sgtable; |
444 | |
445 | typedef struct _nsp32_sglun { |
446 | nsp32_sgtable sgt[NSP32_SG_SIZE+1]; /* SG table */ |
447 | } __attribute__ ((packed)) nsp32_sglun; |
448 | #define NSP32_SG_TABLE_SIZE (sizeof(nsp32_sgtable) * NSP32_SG_SIZE * MAX_TARGET * MAX_LUN) |
449 | |
450 | /* Auto parameter mode memory map. */ |
451 | /* All values must be little endian. */ |
452 | typedef struct _nsp32_autoparam { |
453 | u8 cdb[4 * 0x10]; /* SCSI Command */ |
454 | u32_le msgout; /* outgoing messages */ |
455 | u8 syncreg; /* sync register value */ |
456 | u8 ackwidth; /* ack width register value */ |
457 | u8 target_id; /* target/host device id */ |
458 | u8 sample_reg; /* hazard killer sampling rate */ |
459 | u16_le command_control; /* command control register */ |
460 | u16_le transfer_control; /* transfer control register */ |
461 | u32_le sgt_pointer; /* SG table physical address for DMA */ |
462 | u32_le dummy[2]; |
463 | } __attribute__ ((packed)) nsp32_autoparam; /* must be packed struct */ |
464 | |
465 | /* |
466 | * host data structure |
467 | */ |
468 | /* message in/out buffer */ |
469 | #define MSGOUTBUF_MAX 20 |
470 | #define MSGINBUF_MAX 20 |
471 | |
472 | /* flag for trans_method */ |
473 | #define NSP32_TRANSFER_BUSMASTER BIT(0) |
474 | #define NSP32_TRANSFER_MMIO BIT(1) /* Not supported yet */ |
475 | #define NSP32_TRANSFER_PIO BIT(2) /* Not supported yet */ |
476 | |
477 | |
478 | /* |
479 | * structure for connected LUN dynamic data |
480 | * |
481 | * Note: Currently tagged queuing is disabled, each nsp32_lunt holds |
482 | * one SCSI command and one state. |
483 | */ |
484 | #define DISCPRIV_OK BIT(0) /* DISCPRIV Enable mode */ |
485 | #define MSGIN03 BIT(1) /* Auto Msg In 03 Flag */ |
486 | |
487 | typedef struct _nsp32_lunt { |
488 | struct scsi_cmnd *SCpnt; /* Current Handling struct scsi_cmnd */ |
489 | unsigned long save_datp; /* Save Data Pointer - saved position from initial address */ |
490 | int msgin03; /* auto msg in 03 flag */ |
491 | unsigned int sg_num; /* Total number of SG entries */ |
492 | int cur_entry; /* Current SG entry number */ |
493 | nsp32_sglun *sglun; /* sg table per lun */ |
494 | dma_addr_t sglun_paddr; /* sglun physical address */ |
495 | } nsp32_lunt; |
496 | |
497 | |
498 | /* |
499 | * SCSI TARGET/LUN definition |
500 | */ |
501 | #define NSP32_HOST_SCSIID 7 /* SCSI initiator is every time defined as 7 */ |
502 | #define MAX_TARGET 8 |
503 | #define MAX_LUN 8 /* XXX: In SPI3, max number of LUN is 64. */ |
504 | |
505 | |
506 | typedef struct _nsp32_sync_table { |
507 | unsigned char period_num; /* period number */ |
508 | unsigned char ackwidth; /* ack width designated by period */ |
509 | unsigned char start_period; /* search range - start period */ |
510 | unsigned char end_period; /* search range - end period */ |
511 | unsigned char sample_rate; /* hazard killer parameter */ |
512 | } nsp32_sync_table; |
513 | |
514 | |
515 | /* |
516 | * structure for target device static data |
517 | */ |
518 | /* flag for nsp32_target.sync_flag */ |
519 | #define SDTR_INITIATOR BIT(0) /* sending SDTR from initiator */ |
520 | #define SDTR_TARGET BIT(1) /* sending SDTR from target */ |
521 | #define SDTR_DONE BIT(2) /* exchanging SDTR has been processed */ |
522 | |
523 | /* syncronous period value for nsp32_target.config_max */ |
524 | #define FAST5M 0x32 |
525 | #define FAST10M 0x19 |
526 | #define ULTRA20M 0x0c |
527 | |
528 | /* flag for nsp32_target.{sync_offset}, period */ |
529 | #define ASYNC_OFFSET 0 /* asynchronous transfer */ |
530 | #define SYNC_OFFSET 0xf /* synchronous transfer max offset */ |
531 | |
532 | /* syncreg: |
533 | bit:07 06 05 04 03 02 01 00 |
534 | ---PERIOD-- ---OFFSET-- */ |
535 | #define TO_SYNCREG(period, offset) (((period) & 0x0f) << 4 | ((offset) & 0x0f)) |
536 | |
537 | struct nsp32_cmd_priv { |
538 | enum sam_status status; |
539 | }; |
540 | |
541 | static inline struct nsp32_cmd_priv *nsp32_priv(struct scsi_cmnd *cmd) |
542 | { |
543 | return scsi_cmd_priv(cmd); |
544 | } |
545 | |
546 | typedef struct _nsp32_target { |
547 | unsigned char syncreg; /* value for SYNCREG */ |
548 | unsigned char ackwidth; /* value for ACKWIDTH */ |
549 | unsigned char period; /* sync period (0-255) */ |
550 | unsigned char offset; /* sync offset (0-15) */ |
551 | int sync_flag; /* SDTR_*, 0 */ |
552 | int limit_entry; /* max speed limit entry designated |
553 | by EEPROM configuration */ |
554 | unsigned char sample_reg; /* SREQ hazard killer register */ |
555 | } nsp32_target; |
556 | |
557 | typedef struct _nsp32_hw_data { |
558 | int IrqNumber; |
559 | int BaseAddress; |
560 | int NumAddress; |
561 | void __iomem *MmioAddress; |
562 | #define NSP32_MMIO_OFFSET 0x0800 |
563 | unsigned long MmioLength; |
564 | |
565 | struct scsi_cmnd *CurrentSC; |
566 | |
567 | struct pci_dev *Pci; |
568 | const struct pci_device_id *pci_devid; |
569 | struct Scsi_Host *Host; |
570 | spinlock_t Lock; |
571 | |
572 | char info_str[100]; |
573 | |
574 | /* allocated memory region */ |
575 | nsp32_sglun *sg_list; /* sglist virtuxal address */ |
576 | dma_addr_t sg_paddr; /* physical address of hw_sg_table */ |
577 | nsp32_autoparam *autoparam; /* auto parameter transfer region */ |
578 | dma_addr_t auto_paddr; /* physical address of autoparam */ |
579 | int cur_entry; /* current sgt entry */ |
580 | |
581 | /* target/LUN */ |
582 | nsp32_lunt *cur_lunt; /* Current connected LUN table */ |
583 | nsp32_lunt lunt[MAX_TARGET][MAX_LUN]; /* All LUN table */ |
584 | |
585 | nsp32_target *cur_target; /* Current connected SCSI ID */ |
586 | nsp32_target target[MAX_TARGET]; /* SCSI ID */ |
587 | int cur_id; /* Current connected target ID */ |
588 | int cur_lun; /* Current connected target LUN */ |
589 | |
590 | /* behavior setting parameters */ |
591 | int trans_method; /* transfer method flag */ |
592 | int resettime; /* Reset time */ |
593 | int clock; /* clock dividing flag */ |
594 | nsp32_sync_table *synct; /* sync_table determined by clock */ |
595 | int syncnum; /* the max number of synct element */ |
596 | |
597 | /* message buffer */ |
598 | unsigned char msgoutbuf[MSGOUTBUF_MAX]; /* msgout buffer */ |
599 | char msgout_len; /* msgoutbuf length */ |
600 | unsigned char msginbuf [MSGINBUF_MAX]; /* megin buffer */ |
601 | char msgin_len; /* msginbuf length */ |
602 | |
603 | } nsp32_hw_data; |
604 | |
605 | /* |
606 | * TIME definition |
607 | */ |
608 | #define RESET_HOLD_TIME 10000 /* reset time in us (SCSI-2 says the |
609 | minimum is 25us) */ |
610 | #define SEL_TIMEOUT_TIME 10000 /* 250ms defined in SCSI specification |
611 | (25.6us/1unit) */ |
612 | #define ARBIT_TIMEOUT_TIME 100 /* 100us */ |
613 | #define REQSACK_TIMEOUT_TIME 10000 /* max wait time for REQ/SACK assertion |
614 | or negation, 10000us == 10ms */ |
615 | |
616 | #endif /* _NSP32_H */ |
617 | /* end */ |
618 | |