1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * QLogic Fibre Channel HBA Driver |
4 | * Copyright (c) 2003-2014 QLogic Corporation |
5 | */ |
6 | #ifndef __QLA_MR_H |
7 | #define __QLA_MR_H |
8 | |
9 | #include "qla_dsd.h" |
10 | |
11 | /* |
12 | * The PCI VendorID and DeviceID for our board. |
13 | */ |
14 | #define PCI_DEVICE_ID_QLOGIC_ISPF001 0xF001 |
15 | |
16 | /* FX00 specific definitions */ |
17 | |
18 | #define FX00_COMMAND_TYPE_7 0x07 /* Command Type 7 entry for 7XXX */ |
19 | struct cmd_type_7_fx00 { |
20 | uint8_t entry_type; /* Entry type. */ |
21 | uint8_t entry_count; /* Entry count. */ |
22 | uint8_t sys_define; /* System defined. */ |
23 | uint8_t entry_status; /* Entry Status. */ |
24 | |
25 | uint32_t handle; /* System handle. */ |
26 | uint8_t reserved_0; |
27 | uint8_t port_path_ctrl; |
28 | uint16_t reserved_1; |
29 | |
30 | __le16 tgt_idx; /* Target Idx. */ |
31 | uint16_t timeout; /* Command timeout. */ |
32 | |
33 | __le16 dseg_count; /* Data segment count. */ |
34 | uint8_t scsi_rsp_dsd_len; |
35 | uint8_t reserved_2; |
36 | |
37 | struct scsi_lun lun; /* LUN (LE). */ |
38 | |
39 | uint8_t cntrl_flags; |
40 | |
41 | uint8_t task_mgmt_flags; /* Task management flags. */ |
42 | |
43 | uint8_t task; |
44 | |
45 | uint8_t crn; |
46 | |
47 | uint8_t fcp_cdb[MAX_CMDSZ]; /* SCSI command words. */ |
48 | __le32 byte_count; /* Total byte count. */ |
49 | |
50 | struct dsd64 dsd; |
51 | }; |
52 | |
53 | #define STATUS_TYPE_FX00 0x01 /* Status entry. */ |
54 | struct sts_entry_fx00 { |
55 | uint8_t entry_type; /* Entry type. */ |
56 | uint8_t entry_count; /* Entry count. */ |
57 | uint8_t sys_define; /* System defined. */ |
58 | uint8_t entry_status; /* Entry Status. */ |
59 | |
60 | uint32_t handle; /* System handle. */ |
61 | uint32_t reserved_3; /* System handle. */ |
62 | |
63 | __le16 comp_status; /* Completion status. */ |
64 | uint16_t reserved_0; /* OX_ID used by the firmware. */ |
65 | |
66 | __le32 residual_len; /* FW calc residual transfer length. */ |
67 | |
68 | uint16_t reserved_1; |
69 | uint16_t state_flags; /* State flags. */ |
70 | |
71 | uint16_t reserved_2; |
72 | __le16 scsi_status; /* SCSI status. */ |
73 | |
74 | uint32_t sense_len; /* FCP SENSE length. */ |
75 | uint8_t data[32]; /* FCP response/sense information. */ |
76 | }; |
77 | |
78 | |
79 | #define MAX_HANDLE_COUNT 15 |
80 | #define MULTI_STATUS_TYPE_FX00 0x0D |
81 | |
82 | struct multi_sts_entry_fx00 { |
83 | uint8_t entry_type; /* Entry type. */ |
84 | uint8_t entry_count; /* Entry count. */ |
85 | uint8_t handle_count; |
86 | uint8_t entry_status; |
87 | |
88 | __le32 handles[MAX_HANDLE_COUNT]; |
89 | }; |
90 | |
91 | #define TSK_MGMT_IOCB_TYPE_FX00 0x05 |
92 | struct tsk_mgmt_entry_fx00 { |
93 | uint8_t entry_type; /* Entry type. */ |
94 | uint8_t entry_count; /* Entry count. */ |
95 | uint8_t sys_define; |
96 | uint8_t entry_status; /* Entry Status. */ |
97 | |
98 | uint32_t handle; /* System handle. */ |
99 | |
100 | uint32_t reserved_0; |
101 | |
102 | __le16 tgt_id; /* Target Idx. */ |
103 | |
104 | uint16_t reserved_1; |
105 | uint16_t reserved_3; |
106 | uint16_t reserved_4; |
107 | |
108 | struct scsi_lun lun; /* LUN (LE). */ |
109 | |
110 | __le32 control_flags; /* Control Flags. */ |
111 | |
112 | uint8_t reserved_2[32]; |
113 | }; |
114 | |
115 | |
116 | #define ABORT_IOCB_TYPE_FX00 0x08 /* Abort IOCB status. */ |
117 | struct abort_iocb_entry_fx00 { |
118 | uint8_t entry_type; /* Entry type. */ |
119 | uint8_t entry_count; /* Entry count. */ |
120 | uint8_t sys_define; /* System defined. */ |
121 | uint8_t entry_status; /* Entry Status. */ |
122 | |
123 | uint32_t handle; /* System handle. */ |
124 | __le32 reserved_0; |
125 | |
126 | __le16 tgt_id_sts; /* Completion status. */ |
127 | __le16 options; |
128 | |
129 | uint32_t abort_handle; /* System handle. */ |
130 | __le32 reserved_2; |
131 | |
132 | __le16 req_que_no; |
133 | uint8_t reserved_1[38]; |
134 | }; |
135 | |
136 | #define IOCTL_IOSB_TYPE_FX00 0x0C |
137 | struct ioctl_iocb_entry_fx00 { |
138 | uint8_t entry_type; /* Entry type. */ |
139 | uint8_t entry_count; /* Entry count. */ |
140 | uint8_t sys_define; /* System defined. */ |
141 | uint8_t entry_status; /* Entry Status. */ |
142 | |
143 | uint32_t handle; /* System handle. */ |
144 | uint32_t reserved_0; /* System handle. */ |
145 | |
146 | uint16_t comp_func_num; |
147 | __le16 fw_iotcl_flags; |
148 | |
149 | __le32 dataword_r; /* Data word returned */ |
150 | uint32_t adapid; /* Adapter ID */ |
151 | uint32_t ; |
152 | |
153 | __le32 seq_no; |
154 | uint8_t reserved_2[20]; |
155 | uint32_t residuallen; |
156 | __le32 status; |
157 | }; |
158 | |
159 | #define STATUS_CONT_TYPE_FX00 0x04 |
160 | |
161 | #define FX00_IOCB_TYPE 0x0B |
162 | struct fxdisc_entry_fx00 { |
163 | uint8_t entry_type; /* Entry type. */ |
164 | uint8_t entry_count; /* Entry count. */ |
165 | uint8_t sys_define; /* System Defined. */ |
166 | uint8_t entry_status; /* Entry Status. */ |
167 | |
168 | uint32_t handle; /* System handle. */ |
169 | __le32 reserved_0; /* System handle. */ |
170 | |
171 | __le16 func_num; |
172 | __le16 req_xfrcnt; |
173 | __le16 req_dsdcnt; |
174 | __le16 rsp_xfrcnt; |
175 | __le16 rsp_dsdcnt; |
176 | uint8_t flags; |
177 | uint8_t reserved_1; |
178 | |
179 | /* |
180 | * Use array size 1 below to prevent that Coverity complains about |
181 | * the append_dsd64() calls for the two arrays below. |
182 | */ |
183 | struct dsd64 dseg_rq[1]; |
184 | struct dsd64 dseg_rsp[1]; |
185 | |
186 | __le32 dataword; |
187 | __le32 adapid; |
188 | __le32 adapid_hi; |
189 | __le32 ; |
190 | }; |
191 | |
192 | struct qlafx00_tgt_node_info { |
193 | uint8_t tgt_node_wwpn[WWN_SIZE]; |
194 | uint8_t tgt_node_wwnn[WWN_SIZE]; |
195 | uint32_t tgt_node_state; |
196 | uint8_t reserved[128]; |
197 | uint32_t reserved_1[8]; |
198 | uint64_t reserved_2[4]; |
199 | } __packed; |
200 | |
201 | #define QLAFX00_TGT_NODE_INFO sizeof(struct qlafx00_tgt_node_info) |
202 | |
203 | #define QLAFX00_LINK_STATUS_DOWN 0x10 |
204 | #define QLAFX00_LINK_STATUS_UP 0x11 |
205 | |
206 | #define QLAFX00_PORT_SPEED_2G 0x2 |
207 | #define QLAFX00_PORT_SPEED_4G 0x4 |
208 | #define QLAFX00_PORT_SPEED_8G 0x8 |
209 | #define QLAFX00_PORT_SPEED_10G 0xa |
210 | struct port_info_data { |
211 | uint8_t port_state; |
212 | uint8_t port_type; |
213 | uint16_t port_identifier; |
214 | uint32_t up_port_state; |
215 | uint8_t fw_ver_num[32]; |
216 | uint8_t portal_attrib; |
217 | uint16_t host_option; |
218 | uint8_t reset_delay; |
219 | uint8_t pdwn_retry_cnt; |
220 | uint16_t max_luns2tgt; |
221 | uint8_t risc_ver; |
222 | uint8_t pconn_option; |
223 | uint16_t risc_option; |
224 | uint16_t max_frame_len; |
225 | uint16_t max_iocb_alloc; |
226 | uint16_t exec_throttle; |
227 | uint8_t retry_cnt; |
228 | uint8_t retry_delay; |
229 | uint8_t port_name[8]; |
230 | uint8_t port_id[3]; |
231 | uint8_t link_status; |
232 | uint8_t plink_rate; |
233 | uint32_t link_config; |
234 | uint16_t adap_haddr; |
235 | uint8_t tgt_disc; |
236 | uint8_t log_tout; |
237 | uint8_t node_name[8]; |
238 | uint16_t erisc_opt1; |
239 | uint8_t resp_acc_tmr; |
240 | uint8_t intr_del_tmr; |
241 | uint8_t erisc_opt2; |
242 | uint8_t alt_port_name[8]; |
243 | uint8_t alt_node_name[8]; |
244 | uint8_t link_down_tout; |
245 | uint8_t conn_type; |
246 | uint8_t fc_fw_mode; |
247 | uint32_t uiReserved[48]; |
248 | } __packed; |
249 | |
250 | /* OS Type Designations */ |
251 | #define OS_TYPE_UNKNOWN 0 |
252 | #define OS_TYPE_LINUX 2 |
253 | |
254 | /* Linux Info */ |
255 | #define SYSNAME_LENGTH 128 |
256 | #define NODENAME_LENGTH 64 |
257 | #define RELEASE_LENGTH 64 |
258 | #define VERSION_LENGTH 64 |
259 | #define MACHINE_LENGTH 64 |
260 | #define DOMNAME_LENGTH 64 |
261 | |
262 | struct host_system_info { |
263 | uint32_t os_type; |
264 | char sysname[SYSNAME_LENGTH]; |
265 | char nodename[NODENAME_LENGTH]; |
266 | char release[RELEASE_LENGTH]; |
267 | char version[VERSION_LENGTH]; |
268 | char machine[MACHINE_LENGTH]; |
269 | char domainname[DOMNAME_LENGTH]; |
270 | char hostdriver[VERSION_LENGTH]; |
271 | uint32_t reserved[64]; |
272 | } __packed; |
273 | |
274 | struct register_host_info { |
275 | struct host_system_info hsi; /* host system info */ |
276 | uint64_t utc; /* UTC (system time) */ |
277 | uint32_t reserved[64]; /* future additions */ |
278 | } __packed; |
279 | |
280 | |
281 | #define QLAFX00_PORT_DATA_INFO (sizeof(struct port_info_data)) |
282 | #define QLAFX00_TGT_NODE_LIST_SIZE (sizeof(uint32_t) * 32) |
283 | |
284 | struct config_info_data { |
285 | uint8_t model_num[16]; |
286 | uint8_t model_description[80]; |
287 | uint8_t reserved0[160]; |
288 | uint8_t symbolic_name[64]; |
289 | uint8_t serial_num[32]; |
290 | uint8_t hw_version[16]; |
291 | uint8_t fw_version[16]; |
292 | uint8_t uboot_version[16]; |
293 | uint8_t fru_serial_num[32]; |
294 | |
295 | uint8_t fc_port_count; |
296 | uint8_t iscsi_port_count; |
297 | uint8_t reserved1[2]; |
298 | |
299 | uint8_t mode; |
300 | uint8_t log_level; |
301 | uint8_t reserved2[2]; |
302 | |
303 | uint32_t log_size; |
304 | |
305 | uint8_t tgt_pres_mode; |
306 | uint8_t iqn_flags; |
307 | uint8_t lun_mapping; |
308 | |
309 | uint64_t adapter_id; |
310 | |
311 | uint32_t cluster_key_len; |
312 | uint8_t cluster_key[16]; |
313 | |
314 | uint64_t cluster_master_id; |
315 | uint64_t cluster_slave_id; |
316 | uint8_t cluster_flags; |
317 | uint32_t enabled_capabilities; |
318 | uint32_t nominal_temp_value; |
319 | } __packed; |
320 | |
321 | #define FXDISC_GET_CONFIG_INFO 0x01 |
322 | #define FXDISC_GET_PORT_INFO 0x02 |
323 | #define FXDISC_GET_TGT_NODE_INFO 0x80 |
324 | #define FXDISC_GET_TGT_NODE_LIST 0x81 |
325 | #define FXDISC_REG_HOST_INFO 0x99 |
326 | #define FXDISC_ABORT_IOCTL 0xff |
327 | |
328 | #define QLAFX00_HBA_ICNTRL_REG 0x20B08 |
329 | #define QLAFX00_ICR_ENB_MASK 0x80000000 |
330 | #define QLAFX00_ICR_DIS_MASK 0x7fffffff |
331 | #define QLAFX00_HST_RST_REG 0x18264 |
332 | #define QLAFX00_SOC_TEMP_REG 0x184C4 |
333 | #define QLAFX00_HST_TO_HBA_REG 0x20A04 |
334 | #define QLAFX00_HBA_TO_HOST_REG 0x21B70 |
335 | #define QLAFX00_HST_INT_STS_BITS 0x7 |
336 | #define QLAFX00_BAR1_BASE_ADDR_REG 0x40018 |
337 | #define QLAFX00_PEX0_WIN0_BASE_ADDR_REG 0x41824 |
338 | |
339 | #define QLAFX00_INTR_MB_CMPLT 0x1 |
340 | #define QLAFX00_INTR_RSP_CMPLT 0x2 |
341 | #define QLAFX00_INTR_ASYNC_CMPLT 0x4 |
342 | |
343 | #define QLAFX00_MBA_SYSTEM_ERR 0x8002 |
344 | #define QLAFX00_MBA_TEMP_OVER 0x8005 |
345 | #define QLAFX00_MBA_TEMP_NORM 0x8006 |
346 | #define QLAFX00_MBA_TEMP_CRIT 0x8007 |
347 | #define QLAFX00_MBA_LINK_UP 0x8011 |
348 | #define QLAFX00_MBA_LINK_DOWN 0x8012 |
349 | #define QLAFX00_MBA_PORT_UPDATE 0x8014 |
350 | #define QLAFX00_MBA_SHUTDOWN_RQSTD 0x8062 |
351 | |
352 | #define SOC_SW_RST_CONTROL_REG_CORE0 0x0020800 |
353 | #define SOC_FABRIC_RST_CONTROL_REG 0x0020840 |
354 | #define SOC_FABRIC_CONTROL_REG 0x0020200 |
355 | #define SOC_FABRIC_CONFIG_REG 0x0020204 |
356 | #define SOC_PWR_MANAGEMENT_PWR_DOWN_REG 0x001820C |
357 | |
358 | #define SOC_INTERRUPT_SOURCE_I_CONTROL_REG 0x0020B00 |
359 | #define SOC_CORE_TIMER_REG 0x0021850 |
360 | #define SOC_IRQ_ACK_REG 0x00218b4 |
361 | |
362 | #define CONTINUE_A64_TYPE_FX00 0x03 /* Continuation entry. */ |
363 | |
364 | #define QLAFX00_SET_HST_INTR(ha, value) \ |
365 | wrt_reg_dword((ha)->cregbase + QLAFX00_HST_TO_HBA_REG, \ |
366 | value) |
367 | |
368 | #define QLAFX00_CLR_HST_INTR(ha, value) \ |
369 | wrt_reg_dword((ha)->cregbase + QLAFX00_HBA_TO_HOST_REG, \ |
370 | ~value) |
371 | |
372 | #define QLAFX00_RD_INTR_REG(ha) \ |
373 | rd_reg_dword((ha)->cregbase + QLAFX00_HBA_TO_HOST_REG) |
374 | |
375 | #define QLAFX00_CLR_INTR_REG(ha, value) \ |
376 | wrt_reg_dword((ha)->cregbase + QLAFX00_HBA_TO_HOST_REG, \ |
377 | ~value) |
378 | |
379 | #define QLAFX00_SET_HBA_SOC_REG(ha, off, val)\ |
380 | wrt_reg_dword((ha)->cregbase + off, val) |
381 | |
382 | #define QLAFX00_GET_HBA_SOC_REG(ha, off)\ |
383 | rd_reg_dword((ha)->cregbase + off) |
384 | |
385 | #define QLAFX00_HBA_RST_REG(ha, val)\ |
386 | wrt_reg_dword((ha)->cregbase + QLAFX00_HST_RST_REG, val) |
387 | |
388 | #define QLAFX00_RD_ICNTRL_REG(ha) \ |
389 | rd_reg_dword((ha)->cregbase + QLAFX00_HBA_ICNTRL_REG) |
390 | |
391 | #define QLAFX00_ENABLE_ICNTRL_REG(ha) \ |
392 | wrt_reg_dword((ha)->cregbase + QLAFX00_HBA_ICNTRL_REG, \ |
393 | (QLAFX00_GET_HBA_SOC_REG(ha, QLAFX00_HBA_ICNTRL_REG) | \ |
394 | QLAFX00_ICR_ENB_MASK)) |
395 | |
396 | #define QLAFX00_DISABLE_ICNTRL_REG(ha) \ |
397 | wrt_reg_dword((ha)->cregbase + QLAFX00_HBA_ICNTRL_REG, \ |
398 | (QLAFX00_GET_HBA_SOC_REG(ha, QLAFX00_HBA_ICNTRL_REG) & \ |
399 | QLAFX00_ICR_DIS_MASK)) |
400 | |
401 | #define QLAFX00_RD_REG(ha, off) \ |
402 | rd_reg_dword((ha)->cregbase + off) |
403 | |
404 | #define QLAFX00_WR_REG(ha, off, val) \ |
405 | wrt_reg_dword((ha)->cregbase + off, val) |
406 | |
407 | struct qla_mt_iocb_rqst_fx00 { |
408 | __le32 reserved_0; |
409 | |
410 | __le16 func_type; |
411 | uint8_t flags; |
412 | uint8_t reserved_1; |
413 | |
414 | __le32 dataword; |
415 | |
416 | __le32 adapid; |
417 | __le32 adapid_hi; |
418 | |
419 | __le32 ; |
420 | |
421 | __le16 req_len; |
422 | __le16 reserved_2; |
423 | |
424 | __le16 rsp_len; |
425 | __le16 reserved_3; |
426 | }; |
427 | |
428 | struct qla_mt_iocb_rsp_fx00 { |
429 | uint32_t reserved_1; |
430 | |
431 | uint16_t func_type; |
432 | __le16 ioctl_flags; |
433 | |
434 | __le32 ioctl_data; |
435 | |
436 | uint32_t adapid; |
437 | uint32_t adapid_hi; |
438 | |
439 | uint32_t reserved_2; |
440 | __le32 seq_number; |
441 | |
442 | uint8_t reserved_3[20]; |
443 | |
444 | int32_t res_count; |
445 | |
446 | __le32 status; |
447 | }; |
448 | |
449 | |
450 | #define MAILBOX_REGISTER_COUNT_FX00 16 |
451 | #define AEN_MAILBOX_REGISTER_COUNT_FX00 8 |
452 | #define MAX_FIBRE_DEVICES_FX00 512 |
453 | #define MAX_LUNS_FX00 0x1024 |
454 | #define MAX_TARGETS_FX00 MAX_ISA_DEVICES |
455 | #define REQUEST_ENTRY_CNT_FX00 512 /* Number of request entries. */ |
456 | #define RESPONSE_ENTRY_CNT_FX00 256 /* Number of response entries.*/ |
457 | |
458 | /* |
459 | * Firmware state codes for QLAFX00 adapters |
460 | */ |
461 | #define FSTATE_FX00_CONFIG_WAIT 0x0000 /* Waiting for driver to issue |
462 | * Initialize FW Mbox cmd |
463 | */ |
464 | #define FSTATE_FX00_INITIALIZED 0x1000 /* FW has been initialized by |
465 | * the driver |
466 | */ |
467 | |
468 | #define FX00_DEF_RATOV 10 |
469 | |
470 | struct mr_data_fx00 { |
471 | uint8_t symbolic_name[64]; |
472 | uint8_t serial_num[32]; |
473 | uint8_t hw_version[16]; |
474 | uint8_t fw_version[16]; |
475 | uint8_t uboot_version[16]; |
476 | uint8_t fru_serial_num[32]; |
477 | fc_port_t fcport; /* fcport used for requests |
478 | * that are not linked |
479 | * to a particular target |
480 | */ |
481 | uint8_t fw_hbt_en; |
482 | uint8_t fw_hbt_cnt; |
483 | uint8_t fw_hbt_miss_cnt; |
484 | uint32_t old_fw_hbt_cnt; |
485 | uint16_t fw_reset_timer_tick; |
486 | uint8_t fw_reset_timer_exp; |
487 | uint16_t fw_critemp_timer_tick; |
488 | uint32_t old_aenmbx0_state; |
489 | uint32_t critical_temperature; |
490 | bool extended_io_enabled; |
491 | bool host_info_resend; |
492 | uint8_t hinfo_resend_timer_tick; |
493 | }; |
494 | |
495 | #define QLAFX00_EXTENDED_IO_EN_MASK 0x20 |
496 | |
497 | /* |
498 | * SoC Junction Temperature is stored in |
499 | * bits 9:1 of SoC Junction Temperature Register |
500 | * in a firmware specific format format. |
501 | * To get the temperature in Celsius degrees |
502 | * the value from this bitfiled should be converted |
503 | * using this formula: |
504 | * Temperature (degrees C) = ((3,153,000 - (10,000 * X)) / 13,825) |
505 | * where X is the bit field value |
506 | * this macro reads the register, extracts the bitfield value, |
507 | * performs the calcualtions and returns temperature in Celsius |
508 | */ |
509 | #define QLAFX00_GET_TEMPERATURE(ha) ((3153000 - (10000 * \ |
510 | ((QLAFX00_RD_REG(ha, QLAFX00_SOC_TEMP_REG) & 0x3FE) >> 1))) / 13825) |
511 | |
512 | |
513 | #define QLAFX00_LOOP_DOWN_TIME 615 /* 600 */ |
514 | #define QLAFX00_HEARTBEAT_INTERVAL 6 /* number of seconds */ |
515 | #define QLAFX00_HEARTBEAT_MISS_CNT 3 /* number of miss */ |
516 | #define QLAFX00_RESET_INTERVAL 120 /* number of seconds */ |
517 | #define QLAFX00_MAX_RESET_INTERVAL 600 /* number of seconds */ |
518 | #define QLAFX00_CRITEMP_INTERVAL 60 /* number of seconds */ |
519 | #define QLAFX00_HINFO_RESEND_INTERVAL 60 /* number of seconds */ |
520 | |
521 | #define QLAFX00_CRITEMP_THRSHLD 80 /* Celsius degrees */ |
522 | |
523 | /* Max conncurrent IOs that can be queued */ |
524 | #define QLAFX00_MAX_CANQUEUE 1024 |
525 | |
526 | /* IOCTL IOCB abort success */ |
527 | #define QLAFX00_IOCTL_ICOB_ABORT_SUCCESS 0x68 |
528 | |
529 | #endif |
530 | |