1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * QLogic iSCSI HBA Driver |
4 | * Copyright (c) 2003-2012 QLogic Corporation |
5 | */ |
6 | |
7 | #include "ql4_def.h" |
8 | #include "ql4_glbl.h" |
9 | #include "ql4_dbg.h" |
10 | #include "ql4_inline.h" |
11 | |
12 | void qla4xxx_dump_buffer(void *b, uint32_t size) |
13 | { |
14 | uint32_t cnt; |
15 | uint8_t *c = b; |
16 | |
17 | printk(" 0 1 2 3 4 5 6 7 8 9 Ah Bh Ch Dh Eh " |
18 | "Fh\n" ); |
19 | printk("------------------------------------------------------------" |
20 | "--\n" ); |
21 | for (cnt = 0; cnt < size; c++) { |
22 | printk("%02x" , *c); |
23 | if (!(++cnt % 16)) |
24 | printk("\n" ); |
25 | |
26 | else |
27 | printk(" " ); |
28 | } |
29 | printk(KERN_INFO "\n" ); |
30 | } |
31 | |
32 | void qla4xxx_dump_registers(struct scsi_qla_host *ha) |
33 | { |
34 | uint8_t i; |
35 | |
36 | if (is_qla8022(ha)) { |
37 | for (i = 1; i < MBOX_REG_COUNT; i++) |
38 | printk(KERN_INFO "mailbox[%d] = 0x%08X\n" , |
39 | i, readl(&ha->qla4_82xx_reg->mailbox_in[i])); |
40 | return; |
41 | } |
42 | |
43 | for (i = 0; i < MBOX_REG_COUNT; i++) { |
44 | printk(KERN_INFO "0x%02X mailbox[%d] = 0x%08X\n" , |
45 | (uint8_t) offsetof(struct isp_reg, mailbox[i]), i, |
46 | readw(&ha->reg->mailbox[i])); |
47 | } |
48 | |
49 | printk(KERN_INFO "0x%02X flash_address = 0x%08X\n" , |
50 | (uint8_t) offsetof(struct isp_reg, flash_address), |
51 | readw(&ha->reg->flash_address)); |
52 | printk(KERN_INFO "0x%02X flash_data = 0x%08X\n" , |
53 | (uint8_t) offsetof(struct isp_reg, flash_data), |
54 | readw(&ha->reg->flash_data)); |
55 | printk(KERN_INFO "0x%02X ctrl_status = 0x%08X\n" , |
56 | (uint8_t) offsetof(struct isp_reg, ctrl_status), |
57 | readw(&ha->reg->ctrl_status)); |
58 | |
59 | if (is_qla4010(ha)) { |
60 | printk(KERN_INFO "0x%02X nvram = 0x%08X\n" , |
61 | (uint8_t) offsetof(struct isp_reg, u1.isp4010.nvram), |
62 | readw(&ha->reg->u1.isp4010.nvram)); |
63 | } else if (is_qla4022(ha) | is_qla4032(ha)) { |
64 | printk(KERN_INFO "0x%02X intr_mask = 0x%08X\n" , |
65 | (uint8_t) offsetof(struct isp_reg, u1.isp4022.intr_mask), |
66 | readw(&ha->reg->u1.isp4022.intr_mask)); |
67 | printk(KERN_INFO "0x%02X nvram = 0x%08X\n" , |
68 | (uint8_t) offsetof(struct isp_reg, u1.isp4022.nvram), |
69 | readw(&ha->reg->u1.isp4022.nvram)); |
70 | printk(KERN_INFO "0x%02X semaphore = 0x%08X\n" , |
71 | (uint8_t) offsetof(struct isp_reg, u1.isp4022.semaphore), |
72 | readw(&ha->reg->u1.isp4022.semaphore)); |
73 | } |
74 | printk(KERN_INFO "0x%02X req_q_in = 0x%08X\n" , |
75 | (uint8_t) offsetof(struct isp_reg, req_q_in), |
76 | readw(&ha->reg->req_q_in)); |
77 | printk(KERN_INFO "0x%02X rsp_q_out = 0x%08X\n" , |
78 | (uint8_t) offsetof(struct isp_reg, rsp_q_out), |
79 | readw(&ha->reg->rsp_q_out)); |
80 | |
81 | if (is_qla4010(ha)) { |
82 | printk(KERN_INFO "0x%02X ext_hw_conf = 0x%08X\n" , |
83 | (uint8_t) offsetof(struct isp_reg, u2.isp4010.ext_hw_conf), |
84 | readw(&ha->reg->u2.isp4010.ext_hw_conf)); |
85 | printk(KERN_INFO "0x%02X port_ctrl = 0x%08X\n" , |
86 | (uint8_t) offsetof(struct isp_reg, u2.isp4010.port_ctrl), |
87 | readw(&ha->reg->u2.isp4010.port_ctrl)); |
88 | printk(KERN_INFO "0x%02X port_status = 0x%08X\n" , |
89 | (uint8_t) offsetof(struct isp_reg, u2.isp4010.port_status), |
90 | readw(&ha->reg->u2.isp4010.port_status)); |
91 | printk(KERN_INFO "0x%02X req_q_out = 0x%08X\n" , |
92 | (uint8_t) offsetof(struct isp_reg, u2.isp4010.req_q_out), |
93 | readw(&ha->reg->u2.isp4010.req_q_out)); |
94 | printk(KERN_INFO "0x%02X gp_out = 0x%08X\n" , |
95 | (uint8_t) offsetof(struct isp_reg, u2.isp4010.gp_out), |
96 | readw(&ha->reg->u2.isp4010.gp_out)); |
97 | printk(KERN_INFO "0x%02X gp_in = 0x%08X\n" , |
98 | (uint8_t) offsetof(struct isp_reg, u2.isp4010.gp_in), |
99 | readw(&ha->reg->u2.isp4010.gp_in)); |
100 | printk(KERN_INFO "0x%02X port_err_status = 0x%08X\n" , (uint8_t) |
101 | offsetof(struct isp_reg, u2.isp4010.port_err_status), |
102 | readw(&ha->reg->u2.isp4010.port_err_status)); |
103 | } else if (is_qla4022(ha) | is_qla4032(ha)) { |
104 | printk(KERN_INFO "Page 0 Registers:\n" ); |
105 | printk(KERN_INFO "0x%02X ext_hw_conf = 0x%08X\n" , (uint8_t) |
106 | offsetof(struct isp_reg, u2.isp4022.p0.ext_hw_conf), |
107 | readw(&ha->reg->u2.isp4022.p0.ext_hw_conf)); |
108 | printk(KERN_INFO "0x%02X port_ctrl = 0x%08X\n" , (uint8_t) |
109 | offsetof(struct isp_reg, u2.isp4022.p0.port_ctrl), |
110 | readw(&ha->reg->u2.isp4022.p0.port_ctrl)); |
111 | printk(KERN_INFO "0x%02X port_status = 0x%08X\n" , (uint8_t) |
112 | offsetof(struct isp_reg, u2.isp4022.p0.port_status), |
113 | readw(&ha->reg->u2.isp4022.p0.port_status)); |
114 | printk(KERN_INFO "0x%02X gp_out = 0x%08X\n" , |
115 | (uint8_t) offsetof(struct isp_reg, u2.isp4022.p0.gp_out), |
116 | readw(&ha->reg->u2.isp4022.p0.gp_out)); |
117 | printk(KERN_INFO "0x%02X gp_in = 0x%08X\n" , |
118 | (uint8_t) offsetof(struct isp_reg, u2.isp4022.p0.gp_in), |
119 | readw(&ha->reg->u2.isp4022.p0.gp_in)); |
120 | printk(KERN_INFO "0x%02X port_err_status = 0x%08X\n" , (uint8_t) |
121 | offsetof(struct isp_reg, u2.isp4022.p0.port_err_status), |
122 | readw(&ha->reg->u2.isp4022.p0.port_err_status)); |
123 | printk(KERN_INFO "Page 1 Registers:\n" ); |
124 | writel(HOST_MEM_CFG_PAGE & set_rmask(CSR_SCSI_PAGE_SELECT), |
125 | addr: &ha->reg->ctrl_status); |
126 | printk(KERN_INFO "0x%02X req_q_out = 0x%08X\n" , |
127 | (uint8_t) offsetof(struct isp_reg, u2.isp4022.p1.req_q_out), |
128 | readw(&ha->reg->u2.isp4022.p1.req_q_out)); |
129 | writel(PORT_CTRL_STAT_PAGE & set_rmask(CSR_SCSI_PAGE_SELECT), |
130 | addr: &ha->reg->ctrl_status); |
131 | } |
132 | } |
133 | |
134 | void qla4_8xxx_dump_peg_reg(struct scsi_qla_host *ha) |
135 | { |
136 | uint32_t halt_status1, halt_status2; |
137 | |
138 | halt_status1 = qla4_8xxx_rd_direct(ha, crb_reg: QLA8XXX_PEG_HALT_STATUS1); |
139 | halt_status2 = qla4_8xxx_rd_direct(ha, crb_reg: QLA8XXX_PEG_HALT_STATUS2); |
140 | |
141 | if (is_qla8022(ha)) { |
142 | ql4_printk(KERN_INFO, ha, |
143 | "scsi(%ld): %s, ISP%04x Dumping hw/fw registers:\n" |
144 | " PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,\n" |
145 | " PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,\n" |
146 | " PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,\n" |
147 | " PEG_NET_4_PC: 0x%x\n" , ha->host_no, __func__, |
148 | ha->pdev->device, halt_status1, halt_status2, |
149 | qla4_82xx_rd_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c), |
150 | qla4_82xx_rd_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c), |
151 | qla4_82xx_rd_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c), |
152 | qla4_82xx_rd_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c), |
153 | qla4_82xx_rd_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c)); |
154 | } else if (is_qla8032(ha) || is_qla8042(ha)) { |
155 | ql4_printk(KERN_INFO, ha, |
156 | "scsi(%ld): %s, ISP%04x Dumping hw/fw registers:\n" |
157 | " PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,\n" , |
158 | ha->host_no, __func__, ha->pdev->device, |
159 | halt_status1, halt_status2); |
160 | } |
161 | } |
162 | |