1	// SPDX-License-Identifier: GPL-2.0-only
2	/*
3	* QLogic iSCSI HBA Driver
4	* Copyright (c) 2003-2013 QLogic Corporation
5	*/
6
7	#include <linux/ctype.h>
8	#include "ql4_def.h"
9	#include "ql4_glbl.h"
10	#include "ql4_dbg.h"
11	#include "ql4_inline.h"
12	#include "ql4_version.h"
13
14	void qla4xxx_queue_mbox_cmd(struct scsi_qla_host *ha, uint32_t *mbx_cmd,
15	int in_count)
16	{
17	int i;
18
19	/* Load all mailbox registers, except mailbox 0. */
20	for (i = 1; i < in_count; i++)
21	writel(val: mbx_cmd[i], addr: &ha->reg->mailbox[i]);
22
23	/* Wakeup firmware */
24	writel(val: mbx_cmd[0], addr: &ha->reg->mailbox[0]);
25	readl(addr: &ha->reg->mailbox[0]);
26	writel(val: set_rmask(CSR_INTR_RISC), addr: &ha->reg->ctrl_status);
27	readl(addr: &ha->reg->ctrl_status);
28	}
29
30	void qla4xxx_process_mbox_intr(struct scsi_qla_host *ha, int out_count)
31	{
32	int intr_status;
33
34	intr_status = readl(addr: &ha->reg->ctrl_status);
35	if (intr_status & INTR_PENDING) {
36	/*
37	* Service the interrupt.
38	* The ISR will save the mailbox status registers
39	* to a temporary storage location in the adapter structure.
40	*/
41	ha->mbox_status_count = out_count;
42	ha->isp_ops->interrupt_service_routine(ha, intr_status);
43	}
44	}
45
46	/**
47	* qla4xxx_is_intr_poll_mode - Are we allowed to poll for interrupts?
48	* @ha: Pointer to host adapter structure.
49	* returns: 1=polling mode, 0=non-polling mode
50	**/
51	static int qla4xxx_is_intr_poll_mode(struct scsi_qla_host *ha)
52	{
53	int rval = 1;
54
55	if (is_qla8032(ha) || is_qla8042(ha)) {
56	if (test_bit(AF_IRQ_ATTACHED, &ha->flags) &&
57	test_bit(AF_83XX_MBOX_INTR_ON, &ha->flags))
58	rval = 0;
59	} else {
60	if (test_bit(AF_IRQ_ATTACHED, &ha->flags) &&
61	test_bit(AF_INTERRUPTS_ON, &ha->flags) &&
62	test_bit(AF_ONLINE, &ha->flags) &&
63	!test_bit(AF_HA_REMOVAL, &ha->flags))
64	rval = 0;
65	}
66
67	return rval;
68	}
69
70	/**
71	* qla4xxx_mailbox_command - issues mailbox commands
72	* @ha: Pointer to host adapter structure.
73	* @inCount: number of mailbox registers to load.
74	* @outCount: number of mailbox registers to return.
75	* @mbx_cmd: data pointer for mailbox in registers.
76	* @mbx_sts: data pointer for mailbox out registers.
77	*
78	* This routine issue mailbox commands and waits for completion.
79	* If outCount is 0, this routine completes successfully WITHOUT waiting
80	* for the mailbox command to complete.
81	**/
82	int qla4xxx_mailbox_command(struct scsi_qla_host *ha, uint8_t inCount,
83	uint8_t outCount, uint32_t *mbx_cmd,
84	uint32_t *mbx_sts)
85	{
86	int status = QLA_ERROR;
87	uint8_t i;
88	u_long wait_count;
89	unsigned long flags = 0;
90	uint32_t dev_state;
91
92	/* Make sure that pointers are valid */
93	if (!mbx_cmd || !mbx_sts) {
94	DEBUG2(printk("scsi%ld: %s: Invalid mbx_cmd or mbx_sts "
95	"pointer\n", ha->host_no, __func__));
96	return status;
97	}
98
99	if (is_qla40XX(ha)) {
100	if (test_bit(AF_HA_REMOVAL, &ha->flags)) {
101	DEBUG2(ql4_printk(KERN_WARNING, ha, "scsi%ld: %s: "
102	"prematurely completing mbx cmd as "
103	"adapter removal detected\n",
104	ha->host_no, __func__));
105	return status;
106	}
107	}
108
109	if ((is_aer_supported(ha)) &&
110	(test_bit(AF_PCI_CHANNEL_IO_PERM_FAILURE, &ha->flags))) {
111	DEBUG2(printk(KERN_WARNING "scsi%ld: %s: Perm failure on EEH, "
112	"timeout MBX Exiting.\n", ha->host_no, __func__));
113	return status;
114	}
115
116	/* Mailbox code active */
117	wait_count = MBOX_TOV * 100;
118
119	while (wait_count--) {
120	mutex_lock(&ha->mbox_sem);
121	if (!test_bit(AF_MBOX_COMMAND, &ha->flags)) {
122	set_bit(AF_MBOX_COMMAND, addr: &ha->flags);
123	mutex_unlock(lock: &ha->mbox_sem);
124	break;
125	}
126	mutex_unlock(lock: &ha->mbox_sem);
127	if (!wait_count) {
128	DEBUG2(printk("scsi%ld: %s: mbox_sem failed\n",
129	ha->host_no, __func__));
130	return status;
131	}
132	msleep(msecs: 10);
133	}
134
135	if (is_qla80XX(ha)) {
136	if (test_bit(AF_FW_RECOVERY, &ha->flags)) {
137	DEBUG2(ql4_printk(KERN_WARNING, ha,
138	"scsi%ld: %s: prematurely completing mbx cmd as firmware recovery detected\n",
139	ha->host_no, __func__));
140	goto mbox_exit;
141	}
142	/* Do not send any mbx cmd if h/w is in failed state*/
143	ha->isp_ops->idc_lock(ha);
144	dev_state = qla4_8xxx_rd_direct(ha, crb_reg: QLA8XXX_CRB_DEV_STATE);
145	ha->isp_ops->idc_unlock(ha);
146	if (dev_state == QLA8XXX_DEV_FAILED) {
147	ql4_printk(KERN_WARNING, ha,
148	"scsi%ld: %s: H/W is in failed state, do not send any mailbox commands\n",
149	ha->host_no, __func__);
150	goto mbox_exit;
151	}
152	}
153
154	spin_lock_irqsave(&ha->hardware_lock, flags);
155
156	ha->mbox_status_count = outCount;
157	for (i = 0; i < outCount; i++)
158	ha->mbox_status[i] = 0;
159
160	/* Queue the mailbox command to the firmware */
161	ha->isp_ops->queue_mailbox_command(ha, mbx_cmd, inCount);
162
163	spin_unlock_irqrestore(lock: &ha->hardware_lock, flags);
164
165	/* Wait for completion */
166
167	/*
168	* If we don't want status, don't wait for the mailbox command to
169	* complete. For example, MBOX_CMD_RESET_FW doesn't return status,
170	* you must poll the inbound Interrupt Mask for completion.
171	*/
172	if (outCount == 0) {
173	status = QLA_SUCCESS;
174	goto mbox_exit;
175	}
176
177	/*
178	* Wait for completion: Poll or completion queue
179	*/
180	if (qla4xxx_is_intr_poll_mode(ha)) {
181	/* Poll for command to complete */
182	wait_count = jiffies + MBOX_TOV * HZ;
183	while (test_bit(AF_MBOX_COMMAND_DONE, &ha->flags) == 0) {
184	if (time_after_eq(jiffies, wait_count))
185	break;
186	/*
187	* Service the interrupt.
188	* The ISR will save the mailbox status registers
189	* to a temporary storage location in the adapter
190	* structure.
191	*/
192	spin_lock_irqsave(&ha->hardware_lock, flags);
193	ha->isp_ops->process_mailbox_interrupt(ha, outCount);
194	spin_unlock_irqrestore(lock: &ha->hardware_lock, flags);
195	msleep(msecs: 10);
196	}
197	} else {
198	/* Do not poll for completion. Use completion queue */
199	set_bit(AF_MBOX_COMMAND_NOPOLL, addr: &ha->flags);
200	wait_for_completion_timeout(x: &ha->mbx_intr_comp, MBOX_TOV * HZ);
201	clear_bit(AF_MBOX_COMMAND_NOPOLL, addr: &ha->flags);
202	}
203
204	/* Check for mailbox timeout. */
205	if (!test_bit(AF_MBOX_COMMAND_DONE, &ha->flags)) {
206	if (is_qla80XX(ha) &&
207	test_bit(AF_FW_RECOVERY, &ha->flags)) {
208	DEBUG2(ql4_printk(KERN_INFO, ha,
209	"scsi%ld: %s: prematurely completing mbx cmd as "
210	"firmware recovery detected\n",
211	ha->host_no, __func__));
212	goto mbox_exit;
213	}
214	ql4_printk(KERN_WARNING, ha, "scsi%ld: Mailbox Cmd 0x%08X timed out, Scheduling Adapter Reset\n",
215	ha->host_no, mbx_cmd[0]);
216	ha->mailbox_timeout_count++;
217	mbx_sts[0] = (-1);
218	set_bit(DPC_RESET_HA, addr: &ha->dpc_flags);
219	if (is_qla8022(ha)) {
220	ql4_printk(KERN_INFO, ha,
221	"disabling pause transmit on port 0 & 1.\n");
222	qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x98,
223	CRB_NIU_XG_PAUSE_CTL_P0 |
224	CRB_NIU_XG_PAUSE_CTL_P1);
225	} else if (is_qla8032(ha) || is_qla8042(ha)) {
226	ql4_printk(KERN_INFO, ha, " %s: disabling pause transmit on port 0 & 1.\n",
227	__func__);
228	qla4_83xx_disable_pause(ha);
229	}
230	goto mbox_exit;
231	}
232
233	/*
234	* Copy the mailbox out registers to the caller's mailbox in/out
235	* structure.
236	*/
237	spin_lock_irqsave(&ha->hardware_lock, flags);
238	for (i = 0; i < outCount; i++)
239	mbx_sts[i] = ha->mbox_status[i];
240
241	/* Set return status and error flags (if applicable). */
242	switch (ha->mbox_status[0]) {
243	case MBOX_STS_COMMAND_COMPLETE:
244	status = QLA_SUCCESS;
245	break;
246
247	case MBOX_STS_INTERMEDIATE_COMPLETION:
248	status = QLA_SUCCESS;
249	break;
250
251	case MBOX_STS_BUSY:
252	ql4_printk(KERN_WARNING, ha, "scsi%ld: %s: Cmd = %08X, ISP BUSY\n",
253	ha->host_no, __func__, mbx_cmd[0]);
254	ha->mailbox_timeout_count++;
255	break;
256
257	default:
258	ql4_printk(KERN_WARNING, ha, "scsi%ld: %s: FAILED, MBOX CMD = %08X, MBOX STS = %08X %08X %08X %08X %08X %08X %08X %08X\n",
259	ha->host_no, __func__, mbx_cmd[0], mbx_sts[0],
260	mbx_sts[1], mbx_sts[2], mbx_sts[3], mbx_sts[4],
261	mbx_sts[5], mbx_sts[6], mbx_sts[7]);
262	break;
263	}
264	spin_unlock_irqrestore(lock: &ha->hardware_lock, flags);
265
266	mbox_exit:
267	mutex_lock(&ha->mbox_sem);
268	clear_bit(AF_MBOX_COMMAND, addr: &ha->flags);
269	mutex_unlock(lock: &ha->mbox_sem);
270	clear_bit(AF_MBOX_COMMAND_DONE, addr: &ha->flags);
271
272	return status;
273	}
274
275	/**
276	* qla4xxx_get_minidump_template - Get the firmware template
277	* @ha: Pointer to host adapter structure.
278	* @phys_addr: dma address for template
279	*
280	* Obtain the minidump template from firmware during initialization
281	* as it may not be available when minidump is desired.
282	**/
283	int qla4xxx_get_minidump_template(struct scsi_qla_host *ha,
284	dma_addr_t phys_addr)
285	{
286	uint32_t mbox_cmd[MBOX_REG_COUNT];
287	uint32_t mbox_sts[MBOX_REG_COUNT];
288	int status;
289
290	memset(&mbox_cmd, 0, sizeof(mbox_cmd));
291	memset(&mbox_sts, 0, sizeof(mbox_sts));
292
293	mbox_cmd[0] = MBOX_CMD_MINIDUMP;
294	mbox_cmd[1] = MINIDUMP_GET_TMPLT_SUBCOMMAND;
295	mbox_cmd[2] = LSDW(phys_addr);
296	mbox_cmd[3] = MSDW(phys_addr);
297	mbox_cmd[4] = ha->fw_dump_tmplt_size;
298	mbox_cmd[5] = 0;
299
300	status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, outCount: 2, mbx_cmd: &mbox_cmd[0],
301	mbx_sts: &mbox_sts[0]);
302	if (status != QLA_SUCCESS) {
303	DEBUG2(ql4_printk(KERN_INFO, ha,
304	"scsi%ld: %s: Cmd = %08X, mbx[0] = 0x%04x, mbx[1] = 0x%04x\n",
305	ha->host_no, __func__, mbox_cmd[0],
306	mbox_sts[0], mbox_sts[1]));
307	}
308	return status;
309	}
310
311	/**
312	* qla4xxx_req_template_size - Get minidump template size from firmware.
313	* @ha: Pointer to host adapter structure.
314	**/
315	int qla4xxx_req_template_size(struct scsi_qla_host *ha)
316	{
317	uint32_t mbox_cmd[MBOX_REG_COUNT];
318	uint32_t mbox_sts[MBOX_REG_COUNT];
319	int status;
320
321	memset(&mbox_cmd, 0, sizeof(mbox_cmd));
322	memset(&mbox_sts, 0, sizeof(mbox_sts));
323
324	mbox_cmd[0] = MBOX_CMD_MINIDUMP;
325	mbox_cmd[1] = MINIDUMP_GET_SIZE_SUBCOMMAND;
326
327	status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, outCount: 8, mbx_cmd: &mbox_cmd[0],
328	mbx_sts: &mbox_sts[0]);
329	if (status == QLA_SUCCESS) {
330	ha->fw_dump_tmplt_size = mbox_sts[1];
331	DEBUG2(ql4_printk(KERN_INFO, ha,
332	"%s: sts[0]=0x%04x, template size=0x%04x, size_cm_02=0x%04x, size_cm_04=0x%04x, size_cm_08=0x%04x, size_cm_10=0x%04x, size_cm_FF=0x%04x, version=0x%04x\n",
333	__func__, mbox_sts[0], mbox_sts[1],
334	mbox_sts[2], mbox_sts[3], mbox_sts[4],
335	mbox_sts[5], mbox_sts[6], mbox_sts[7]));
336	if (ha->fw_dump_tmplt_size == 0)
337	status = QLA_ERROR;
338	} else {
339	ql4_printk(KERN_WARNING, ha,
340	"%s: Error sts[0]=0x%04x, mbx[1]=0x%04x\n",
341	__func__, mbox_sts[0], mbox_sts[1]);
342	status = QLA_ERROR;
343	}
344
345	return status;
346	}
347
348	void qla4xxx_mailbox_premature_completion(struct scsi_qla_host *ha)
349	{
350	set_bit(AF_FW_RECOVERY, addr: &ha->flags);
351	ql4_printk(KERN_INFO, ha, "scsi%ld: %s: set FW RECOVERY!\n",
352	ha->host_no, __func__);
353
354	if (test_bit(AF_MBOX_COMMAND, &ha->flags)) {
355	if (test_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags)) {
356	complete(&ha->mbx_intr_comp);
357	ql4_printk(KERN_INFO, ha, "scsi%ld: %s: Due to fw "
358	"recovery, doing premature completion of "
359	"mbx cmd\n", ha->host_no, __func__);
360
361	} else {
362	set_bit(AF_MBOX_COMMAND_DONE, addr: &ha->flags);
363	ql4_printk(KERN_INFO, ha, "scsi%ld: %s: Due to fw "
364	"recovery, doing premature completion of "
365	"polling mbx cmd\n", ha->host_no, __func__);
366	}
367	}
368	}
369
370	static uint8_t
371	qla4xxx_set_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
372	uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma)
373	{
374	memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
375	memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
376
377	if (is_qla8022(ha))
378	qla4_82xx_wr_32(ha, ha->nx_db_wr_ptr, 0);
379
380	mbox_cmd[0] = MBOX_CMD_INITIALIZE_FIRMWARE;
381	mbox_cmd[1] = 0;
382	mbox_cmd[2] = LSDW(init_fw_cb_dma);
383	mbox_cmd[3] = MSDW(init_fw_cb_dma);
384	mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
385
386	if (qla4xxx_mailbox_command(ha, inCount: 6, outCount: 6, mbx_cmd: mbox_cmd, mbx_sts: mbox_sts) !=
387	QLA_SUCCESS) {
388	DEBUG2(printk(KERN_WARNING "scsi%ld: %s: "
389	"MBOX_CMD_INITIALIZE_FIRMWARE"
390	" failed w/ status %04X\n",
391	ha->host_no, __func__, mbox_sts[0]));
392	return QLA_ERROR;
393	}
394	return QLA_SUCCESS;
395	}
396
397	uint8_t
398	qla4xxx_get_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
399	uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma)
400	{
401	memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
402	memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
403	mbox_cmd[0] = MBOX_CMD_GET_INIT_FW_CTRL_BLOCK;
404	mbox_cmd[2] = LSDW(init_fw_cb_dma);
405	mbox_cmd[3] = MSDW(init_fw_cb_dma);
406	mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
407
408	if (qla4xxx_mailbox_command(ha, inCount: 5, outCount: 5, mbx_cmd: mbox_cmd, mbx_sts: mbox_sts) !=
409	QLA_SUCCESS) {
410	DEBUG2(printk(KERN_WARNING "scsi%ld: %s: "
411	"MBOX_CMD_GET_INIT_FW_CTRL_BLOCK"
412	" failed w/ status %04X\n",
413	ha->host_no, __func__, mbox_sts[0]));
414	return QLA_ERROR;
415	}
416	return QLA_SUCCESS;
417	}
418
419	uint8_t qla4xxx_set_ipaddr_state(uint8_t fw_ipaddr_state)
420	{
421	uint8_t ipaddr_state;
422
423	switch (fw_ipaddr_state) {
424	case IP_ADDRSTATE_UNCONFIGURED:
425	ipaddr_state = ISCSI_IPDDRESS_STATE_UNCONFIGURED;
426	break;
427	case IP_ADDRSTATE_INVALID:
428	ipaddr_state = ISCSI_IPDDRESS_STATE_INVALID;
429	break;
430	case IP_ADDRSTATE_ACQUIRING:
431	ipaddr_state = ISCSI_IPDDRESS_STATE_ACQUIRING;
432	break;
433	case IP_ADDRSTATE_TENTATIVE:
434	ipaddr_state = ISCSI_IPDDRESS_STATE_TENTATIVE;
435	break;
436	case IP_ADDRSTATE_DEPRICATED:
437	ipaddr_state = ISCSI_IPDDRESS_STATE_DEPRECATED;
438	break;
439	case IP_ADDRSTATE_PREFERRED:
440	ipaddr_state = ISCSI_IPDDRESS_STATE_VALID;
441	break;
442	case IP_ADDRSTATE_DISABLING:
443	ipaddr_state = ISCSI_IPDDRESS_STATE_DISABLING;
444	break;
445	default:
446	ipaddr_state = ISCSI_IPDDRESS_STATE_UNCONFIGURED;
447	}
448	return ipaddr_state;
449	}
450
451	static void
452	qla4xxx_update_local_ip(struct scsi_qla_host *ha,
453	struct addr_ctrl_blk *init_fw_cb)
454	{
455	ha->ip_config.tcp_options = le16_to_cpu(init_fw_cb->ipv4_tcp_opts);
456	ha->ip_config.ipv4_options = le16_to_cpu(init_fw_cb->ipv4_ip_opts);
457	ha->ip_config.ipv4_addr_state =
458	qla4xxx_set_ipaddr_state(fw_ipaddr_state: init_fw_cb->ipv4_addr_state);
459	ha->ip_config.eth_mtu_size =
460	le16_to_cpu(init_fw_cb->eth_mtu_size);
461	ha->ip_config.ipv4_port = le16_to_cpu(init_fw_cb->ipv4_port);
462
463	if (ha->acb_version == ACB_SUPPORTED) {
464	ha->ip_config.ipv6_options = le16_to_cpu(init_fw_cb->ipv6_opts);
465	ha->ip_config.ipv6_addl_options =
466	le16_to_cpu(init_fw_cb->ipv6_addtl_opts);
467	ha->ip_config.ipv6_tcp_options =
468	le16_to_cpu(init_fw_cb->ipv6_tcp_opts);
469	}
470
471	/* Save IPv4 Address Info */
472	memcpy(ha->ip_config.ip_address, init_fw_cb->ipv4_addr,
473	min(sizeof(ha->ip_config.ip_address),
474	sizeof(init_fw_cb->ipv4_addr)));
475	memcpy(ha->ip_config.subnet_mask, init_fw_cb->ipv4_subnet,
476	min(sizeof(ha->ip_config.subnet_mask),
477	sizeof(init_fw_cb->ipv4_subnet)));
478	memcpy(ha->ip_config.gateway, init_fw_cb->ipv4_gw_addr,
479	min(sizeof(ha->ip_config.gateway),
480	sizeof(init_fw_cb->ipv4_gw_addr)));
481
482	ha->ip_config.ipv4_vlan_tag = be16_to_cpu(init_fw_cb->ipv4_vlan_tag);
483	ha->ip_config.control = init_fw_cb->control;
484	ha->ip_config.tcp_wsf = init_fw_cb->ipv4_tcp_wsf;
485	ha->ip_config.ipv4_tos = init_fw_cb->ipv4_tos;
486	ha->ip_config.ipv4_cache_id = init_fw_cb->ipv4_cacheid;
487	ha->ip_config.ipv4_alt_cid_len = init_fw_cb->ipv4_dhcp_alt_cid_len;
488	memcpy(ha->ip_config.ipv4_alt_cid, init_fw_cb->ipv4_dhcp_alt_cid,
489	min(sizeof(ha->ip_config.ipv4_alt_cid),
490	sizeof(init_fw_cb->ipv4_dhcp_alt_cid)));
491	ha->ip_config.ipv4_vid_len = init_fw_cb->ipv4_dhcp_vid_len;
492	memcpy(ha->ip_config.ipv4_vid, init_fw_cb->ipv4_dhcp_vid,
493	min(sizeof(ha->ip_config.ipv4_vid),
494	sizeof(init_fw_cb->ipv4_dhcp_vid)));
495	ha->ip_config.ipv4_ttl = init_fw_cb->ipv4_ttl;
496	ha->ip_config.def_timeout = le16_to_cpu(init_fw_cb->def_timeout);
497	ha->ip_config.abort_timer = init_fw_cb->abort_timer;
498	ha->ip_config.iscsi_options = le16_to_cpu(init_fw_cb->iscsi_opts);
499	ha->ip_config.iscsi_max_pdu_size =
500	le16_to_cpu(init_fw_cb->iscsi_max_pdu_size);
501	ha->ip_config.iscsi_first_burst_len =
502	le16_to_cpu(init_fw_cb->iscsi_fburst_len);
503	ha->ip_config.iscsi_max_outstnd_r2t =
504	le16_to_cpu(init_fw_cb->iscsi_max_outstnd_r2t);
505	ha->ip_config.iscsi_max_burst_len =
506	le16_to_cpu(init_fw_cb->iscsi_max_burst_len);
507	memcpy(ha->ip_config.iscsi_name, init_fw_cb->iscsi_name,
508	min(sizeof(ha->ip_config.iscsi_name),
509	sizeof(init_fw_cb->iscsi_name)));
510
511	if (is_ipv6_enabled(ha)) {
512	/* Save IPv6 Address */
513	ha->ip_config.ipv6_link_local_state =
514	qla4xxx_set_ipaddr_state(fw_ipaddr_state: init_fw_cb->ipv6_lnk_lcl_addr_state);
515	ha->ip_config.ipv6_addr0_state =
516	qla4xxx_set_ipaddr_state(fw_ipaddr_state: init_fw_cb->ipv6_addr0_state);
517	ha->ip_config.ipv6_addr1_state =
518	qla4xxx_set_ipaddr_state(fw_ipaddr_state: init_fw_cb->ipv6_addr1_state);
519
520	switch (le16_to_cpu(init_fw_cb->ipv6_dflt_rtr_state)) {
521	case IPV6_RTRSTATE_UNKNOWN:
522	ha->ip_config.ipv6_default_router_state =
523	ISCSI_ROUTER_STATE_UNKNOWN;
524	break;
525	case IPV6_RTRSTATE_MANUAL:
526	ha->ip_config.ipv6_default_router_state =
527	ISCSI_ROUTER_STATE_MANUAL;
528	break;
529	case IPV6_RTRSTATE_ADVERTISED:
530	ha->ip_config.ipv6_default_router_state =
531	ISCSI_ROUTER_STATE_ADVERTISED;
532	break;
533	case IPV6_RTRSTATE_STALE:
534	ha->ip_config.ipv6_default_router_state =
535	ISCSI_ROUTER_STATE_STALE;
536	break;
537	default:
538	ha->ip_config.ipv6_default_router_state =
539	ISCSI_ROUTER_STATE_UNKNOWN;
540	}
541
542	ha->ip_config.ipv6_link_local_addr.in6_u.u6_addr8[0] = 0xFE;
543	ha->ip_config.ipv6_link_local_addr.in6_u.u6_addr8[1] = 0x80;
544
545	memcpy(&ha->ip_config.ipv6_link_local_addr.in6_u.u6_addr8[8],
546	init_fw_cb->ipv6_if_id,
547	min(sizeof(ha->ip_config.ipv6_link_local_addr)/2,
548	sizeof(init_fw_cb->ipv6_if_id)));
549	memcpy(&ha->ip_config.ipv6_addr0, init_fw_cb->ipv6_addr0,
550	min(sizeof(ha->ip_config.ipv6_addr0),
551	sizeof(init_fw_cb->ipv6_addr0)));
552	memcpy(&ha->ip_config.ipv6_addr1, init_fw_cb->ipv6_addr1,
553	min(sizeof(ha->ip_config.ipv6_addr1),
554	sizeof(init_fw_cb->ipv6_addr1)));
555	memcpy(&ha->ip_config.ipv6_default_router_addr,
556	init_fw_cb->ipv6_dflt_rtr_addr,
557	min(sizeof(ha->ip_config.ipv6_default_router_addr),
558	sizeof(init_fw_cb->ipv6_dflt_rtr_addr)));
559	ha->ip_config.ipv6_vlan_tag =
560	be16_to_cpu(init_fw_cb->ipv6_vlan_tag);
561	ha->ip_config.ipv6_port = le16_to_cpu(init_fw_cb->ipv6_port);
562	ha->ip_config.ipv6_cache_id = init_fw_cb->ipv6_cache_id;
563	ha->ip_config.ipv6_flow_lbl =
564	le16_to_cpu(init_fw_cb->ipv6_flow_lbl);
565	ha->ip_config.ipv6_traffic_class =
566	init_fw_cb->ipv6_traffic_class;
567	ha->ip_config.ipv6_hop_limit = init_fw_cb->ipv6_hop_limit;
568	ha->ip_config.ipv6_nd_reach_time =
569	le32_to_cpu(init_fw_cb->ipv6_nd_reach_time);
570	ha->ip_config.ipv6_nd_rexmit_timer =
571	le32_to_cpu(init_fw_cb->ipv6_nd_rexmit_timer);
572	ha->ip_config.ipv6_nd_stale_timeout =
573	le32_to_cpu(init_fw_cb->ipv6_nd_stale_timeout);
574	ha->ip_config.ipv6_dup_addr_detect_count =
575	init_fw_cb->ipv6_dup_addr_detect_count;
576	ha->ip_config.ipv6_gw_advrt_mtu =
577	le32_to_cpu(init_fw_cb->ipv6_gw_advrt_mtu);
578	ha->ip_config.ipv6_tcp_wsf = init_fw_cb->ipv6_tcp_wsf;
579	}
580	}
581
582	uint8_t
583	qla4xxx_update_local_ifcb(struct scsi_qla_host *ha,
584	uint32_t *mbox_cmd,
585	uint32_t *mbox_sts,
586	struct addr_ctrl_blk *init_fw_cb,
587	dma_addr_t init_fw_cb_dma)
588	{
589	if (qla4xxx_get_ifcb(ha, mbox_cmd, mbox_sts, init_fw_cb_dma)
590	!= QLA_SUCCESS) {
591	DEBUG2(printk(KERN_WARNING
592	"scsi%ld: %s: Failed to get init_fw_ctrl_blk\n",
593	ha->host_no, __func__));
594	return QLA_ERROR;
595	}
596
597	DEBUG2(qla4xxx_dump_buffer(init_fw_cb, sizeof(struct addr_ctrl_blk)));
598
599	/* Save some info in adapter structure. */
600	ha->acb_version = init_fw_cb->acb_version;
601	ha->firmware_options = le16_to_cpu(init_fw_cb->fw_options);
602	ha->heartbeat_interval = init_fw_cb->hb_interval;
603	memcpy(ha->name_string, init_fw_cb->iscsi_name,
604	min(sizeof(ha->name_string),
605	sizeof(init_fw_cb->iscsi_name)));
606	ha->def_timeout = le16_to_cpu(init_fw_cb->def_timeout);
607	/*memcpy(ha->alias, init_fw_cb->Alias,
608	min(sizeof(ha->alias), sizeof(init_fw_cb->Alias)));*/
609
610	qla4xxx_update_local_ip(ha, init_fw_cb);
611
612	return QLA_SUCCESS;
613	}
614
615	/**
616	* qla4xxx_initialize_fw_cb - initializes firmware control block.
617	* @ha: Pointer to host adapter structure.
618	**/
619	int qla4xxx_initialize_fw_cb(struct scsi_qla_host * ha)
620	{
621	struct addr_ctrl_blk *init_fw_cb;
622	dma_addr_t init_fw_cb_dma;
623	uint32_t mbox_cmd[MBOX_REG_COUNT];
624	uint32_t mbox_sts[MBOX_REG_COUNT];
625	int status = QLA_ERROR;
626
627	init_fw_cb = dma_alloc_coherent(dev: &ha->pdev->dev,
628	size: sizeof(struct addr_ctrl_blk),
629	dma_handle: &init_fw_cb_dma, GFP_KERNEL);
630	if (init_fw_cb == NULL) {
631	DEBUG2(printk("scsi%ld: %s: Unable to alloc init_cb\n",
632	ha->host_no, __func__));
633	goto exit_init_fw_cb_no_free;
634	}
635
636	/* Get Initialize Firmware Control Block. */
637	memset(&mbox_cmd, 0, sizeof(mbox_cmd));
638	memset(&mbox_sts, 0, sizeof(mbox_sts));
639
640	if (qla4xxx_get_ifcb(ha, mbox_cmd: &mbox_cmd[0], mbox_sts: &mbox_sts[0], init_fw_cb_dma) !=
641	QLA_SUCCESS) {
642	goto exit_init_fw_cb;
643	}
644
645	/* Fill in the request and response queue information. */
646	init_fw_cb->rqq_consumer_idx = cpu_to_le16(ha->request_out);
647	init_fw_cb->compq_producer_idx = cpu_to_le16(ha->response_in);
648	init_fw_cb->rqq_len = cpu_to_le16(REQUEST_QUEUE_DEPTH);
649	init_fw_cb->compq_len = cpu_to_le16(RESPONSE_QUEUE_DEPTH);
650	init_fw_cb->rqq_addr_lo = cpu_to_le32(LSDW(ha->request_dma));
651	init_fw_cb->rqq_addr_hi = cpu_to_le32(MSDW(ha->request_dma));
652	init_fw_cb->compq_addr_lo = cpu_to_le32(LSDW(ha->response_dma));
653	init_fw_cb->compq_addr_hi = cpu_to_le32(MSDW(ha->response_dma));
654	init_fw_cb->shdwreg_addr_lo = cpu_to_le32(LSDW(ha->shadow_regs_dma));
655	init_fw_cb->shdwreg_addr_hi = cpu_to_le32(MSDW(ha->shadow_regs_dma));
656
657	/* Set up required options. */
658	init_fw_cb->fw_options |=
659	cpu_to_le16(FWOPT_SESSION_MODE |
660	FWOPT_INITIATOR_MODE);
661
662	if (is_qla80XX(ha))
663	init_fw_cb->fw_options |=
664	cpu_to_le16(FWOPT_ENABLE_CRBDB);
665
666	init_fw_cb->fw_options &= cpu_to_le16(~FWOPT_TARGET_MODE);
667
668	init_fw_cb->add_fw_options = 0;
669	init_fw_cb->add_fw_options |=
670	cpu_to_le16(ADFWOPT_SERIALIZE_TASK_MGMT);
671	init_fw_cb->add_fw_options |=
672	cpu_to_le16(ADFWOPT_AUTOCONN_DISABLE);
673
674	if (qla4xxx_set_ifcb(ha, mbox_cmd: &mbox_cmd[0], mbox_sts: &mbox_sts[0], init_fw_cb_dma)
675	!= QLA_SUCCESS) {
676	DEBUG2(printk(KERN_WARNING
677	"scsi%ld: %s: Failed to set init_fw_ctrl_blk\n",
678	ha->host_no, __func__));
679	goto exit_init_fw_cb;
680	}
681
682	if (qla4xxx_update_local_ifcb(ha, mbox_cmd: &mbox_cmd[0], mbox_sts: &mbox_sts[0],
683	init_fw_cb, init_fw_cb_dma) != QLA_SUCCESS) {
684	DEBUG2(printk("scsi%ld: %s: Failed to update local ifcb\n",
685	ha->host_no, __func__));
686	goto exit_init_fw_cb;
687	}
688	status = QLA_SUCCESS;
689
690	exit_init_fw_cb:
691	dma_free_coherent(dev: &ha->pdev->dev, size: sizeof(struct addr_ctrl_blk),
692	cpu_addr: init_fw_cb, dma_handle: init_fw_cb_dma);
693	exit_init_fw_cb_no_free:
694	return status;
695	}
696
697	/**
698	* qla4xxx_get_dhcp_ip_address - gets HBA ip address via DHCP
699	* @ha: Pointer to host adapter structure.
700	**/
701	int qla4xxx_get_dhcp_ip_address(struct scsi_qla_host * ha)
702	{
703	struct addr_ctrl_blk *init_fw_cb;
704	dma_addr_t init_fw_cb_dma;
705	uint32_t mbox_cmd[MBOX_REG_COUNT];
706	uint32_t mbox_sts[MBOX_REG_COUNT];
707
708	init_fw_cb = dma_alloc_coherent(dev: &ha->pdev->dev,
709	size: sizeof(struct addr_ctrl_blk),
710	dma_handle: &init_fw_cb_dma, GFP_KERNEL);
711	if (init_fw_cb == NULL) {
712	printk("scsi%ld: %s: Unable to alloc init_cb\n", ha->host_no,
713	__func__);
714	return QLA_ERROR;
715	}
716
717	/* Get Initialize Firmware Control Block. */
718	if (qla4xxx_get_ifcb(ha, mbox_cmd: &mbox_cmd[0], mbox_sts: &mbox_sts[0], init_fw_cb_dma) !=
719	QLA_SUCCESS) {
720	DEBUG2(printk("scsi%ld: %s: Failed to get init_fw_ctrl_blk\n",
721	ha->host_no, __func__));
722	dma_free_coherent(dev: &ha->pdev->dev,
723	size: sizeof(struct addr_ctrl_blk),
724	cpu_addr: init_fw_cb, dma_handle: init_fw_cb_dma);
725	return QLA_ERROR;
726	}
727
728	/* Save IP Address. */
729	qla4xxx_update_local_ip(ha, init_fw_cb);
730	dma_free_coherent(dev: &ha->pdev->dev, size: sizeof(struct addr_ctrl_blk),
731	cpu_addr: init_fw_cb, dma_handle: init_fw_cb_dma);
732
733	return QLA_SUCCESS;
734	}
735
736	/**
737	* qla4xxx_get_firmware_state - gets firmware state of HBA
738	* @ha: Pointer to host adapter structure.
739	**/
740	int qla4xxx_get_firmware_state(struct scsi_qla_host * ha)
741	{
742	uint32_t mbox_cmd[MBOX_REG_COUNT];
743	uint32_t mbox_sts[MBOX_REG_COUNT];
744
745	/* Get firmware version */
746	memset(&mbox_cmd, 0, sizeof(mbox_cmd));
747	memset(&mbox_sts, 0, sizeof(mbox_sts));
748
749	mbox_cmd[0] = MBOX_CMD_GET_FW_STATE;
750
751	if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, outCount: 4, mbx_cmd: &mbox_cmd[0], mbx_sts: &mbox_sts[0]) !=
752	QLA_SUCCESS) {
753	DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_FW_STATE failed w/ "
754	"status %04X\n", ha->host_no, __func__,
755	mbox_sts[0]));
756	return QLA_ERROR;
757	}
758	ha->firmware_state = mbox_sts[1];
759	ha->board_id = mbox_sts[2];
760	ha->addl_fw_state = mbox_sts[3];
761	DEBUG2(printk("scsi%ld: %s firmware_state=0x%x\n",
762	ha->host_no, __func__, ha->firmware_state);)
763
764	return QLA_SUCCESS;
765	}
766
767	/**
768	* qla4xxx_get_firmware_status - retrieves firmware status
769	* @ha: Pointer to host adapter structure.
770	**/
771	int qla4xxx_get_firmware_status(struct scsi_qla_host * ha)
772	{
773	uint32_t mbox_cmd[MBOX_REG_COUNT];
774	uint32_t mbox_sts[MBOX_REG_COUNT];
775
776	/* Get firmware version */
777	memset(&mbox_cmd, 0, sizeof(mbox_cmd));
778	memset(&mbox_sts, 0, sizeof(mbox_sts));
779
780	mbox_cmd[0] = MBOX_CMD_GET_FW_STATUS;
781
782	if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, outCount: 3, mbx_cmd: &mbox_cmd[0], mbx_sts: &mbox_sts[0]) !=
783	QLA_SUCCESS) {
784	DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_FW_STATUS failed w/ "
785	"status %04X\n", ha->host_no, __func__,
786	mbox_sts[0]));
787	return QLA_ERROR;
788	}
789
790	/* High-water mark of IOCBs */
791	ha->iocb_hiwat = mbox_sts[2];
792	DEBUG2(ql4_printk(KERN_INFO, ha,
793	"%s: firmware IOCBs available = %d\n", __func__,
794	ha->iocb_hiwat));
795
796	if (ha->iocb_hiwat > IOCB_HIWAT_CUSHION)
797	ha->iocb_hiwat -= IOCB_HIWAT_CUSHION;
798
799	/* Ideally, we should not enter this code, as the # of firmware
800	* IOCBs is hard-coded in the firmware. We set a default
801	* iocb_hiwat here just in case */
802	if (ha->iocb_hiwat == 0) {
803	ha->iocb_hiwat = REQUEST_QUEUE_DEPTH / 4;
804	DEBUG2(ql4_printk(KERN_WARNING, ha,
805	"%s: Setting IOCB's to = %d\n", __func__,
806	ha->iocb_hiwat));
807	}
808
809	return QLA_SUCCESS;
810	}
811
812	/*
813	* qla4xxx_get_fwddb_entry - retrieves firmware ddb entry
814	* @ha: Pointer to host adapter structure.
815	* @fw_ddb_index: Firmware's device database index
816	* @fw_ddb_entry: Pointer to firmware's device database entry structure
817	* @num_valid_ddb_entries: Pointer to number of valid ddb entries
818	* @next_ddb_index: Pointer to next valid device database index
819	* @fw_ddb_device_state: Pointer to device state
820	**/
821	int qla4xxx_get_fwddb_entry(struct scsi_qla_host *ha,
822	uint16_t fw_ddb_index,
823	struct dev_db_entry *fw_ddb_entry,
824	dma_addr_t fw_ddb_entry_dma,
825	uint32_t *num_valid_ddb_entries,
826	uint32_t *next_ddb_index,
827	uint32_t *fw_ddb_device_state,
828	uint32_t *conn_err_detail,
829	uint16_t *tcp_source_port_num,
830	uint16_t *connection_id)
831	{
832	int status = QLA_ERROR;
833	uint16_t options;
834	uint32_t mbox_cmd[MBOX_REG_COUNT];
835	uint32_t mbox_sts[MBOX_REG_COUNT];
836
837	/* Make sure the device index is valid */
838	if (fw_ddb_index >= MAX_DDB_ENTRIES) {
839	DEBUG2(printk("scsi%ld: %s: ddb [%d] out of range.\n",
840	ha->host_no, __func__, fw_ddb_index));
841	goto exit_get_fwddb;
842	}
843	memset(&mbox_cmd, 0, sizeof(mbox_cmd));
844	memset(&mbox_sts, 0, sizeof(mbox_sts));
845	if (fw_ddb_entry)
846	memset(fw_ddb_entry, 0, sizeof(struct dev_db_entry));
847
848	mbox_cmd[0] = MBOX_CMD_GET_DATABASE_ENTRY;
849	mbox_cmd[1] = (uint32_t) fw_ddb_index;
850	mbox_cmd[2] = LSDW(fw_ddb_entry_dma);
851	mbox_cmd[3] = MSDW(fw_ddb_entry_dma);
852	mbox_cmd[4] = sizeof(struct dev_db_entry);
853
854	if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, outCount: 7, mbx_cmd: &mbox_cmd[0], mbx_sts: &mbox_sts[0]) ==
855	QLA_ERROR) {
856	DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_DATABASE_ENTRY failed"
857	" with status 0x%04X\n", ha->host_no, __func__,
858	mbox_sts[0]));
859	goto exit_get_fwddb;
860	}
861	if (fw_ddb_index != mbox_sts[1]) {
862	DEBUG2(printk("scsi%ld: %s: ddb mismatch [%d] != [%d].\n",
863	ha->host_no, __func__, fw_ddb_index,
864	mbox_sts[1]));
865	goto exit_get_fwddb;
866	}
867	if (fw_ddb_entry) {
868	options = le16_to_cpu(fw_ddb_entry->options);
869	if (options & DDB_OPT_IPV6_DEVICE) {
870	ql4_printk(KERN_INFO, ha, "%s: DDB[%d] MB0 %04x Tot %d "
871	"Next %d State %04x ConnErr %08x %pI6 "
872	":%04d \"%s\"\n", __func__, fw_ddb_index,
873	mbox_sts[0], mbox_sts[2], mbox_sts[3],
874	mbox_sts[4], mbox_sts[5],
875	fw_ddb_entry->ip_addr,
876	le16_to_cpu(fw_ddb_entry->port),
877	fw_ddb_entry->iscsi_name);
878	} else {
879	ql4_printk(KERN_INFO, ha, "%s: DDB[%d] MB0 %04x Tot %d "
880	"Next %d State %04x ConnErr %08x %pI4 "
881	":%04d \"%s\"\n", __func__, fw_ddb_index,
882	mbox_sts[0], mbox_sts[2], mbox_sts[3],
883	mbox_sts[4], mbox_sts[5],
884	fw_ddb_entry->ip_addr,
885	le16_to_cpu(fw_ddb_entry->port),
886	fw_ddb_entry->iscsi_name);
887	}
888	}
889	if (num_valid_ddb_entries)
890	*num_valid_ddb_entries = mbox_sts[2];
891	if (next_ddb_index)
892	*next_ddb_index = mbox_sts[3];
893	if (fw_ddb_device_state)
894	*fw_ddb_device_state = mbox_sts[4];
895
896	/*
897	* RA: This mailbox has been changed to pass connection error and
898	* details. Its true for ISP4010 as per Version E - Not sure when it
899	* was changed. Get the time2wait from the fw_dd_entry field :
900	* default_time2wait which we call it as minTime2Wait DEV_DB_ENTRY
901	* struct.
902	*/
903	if (conn_err_detail)
904	*conn_err_detail = mbox_sts[5];
905	if (tcp_source_port_num)
906	*tcp_source_port_num = (uint16_t) (mbox_sts[6] >> 16);
907	if (connection_id)
908	*connection_id = (uint16_t) mbox_sts[6] & 0x00FF;
909	status = QLA_SUCCESS;
910
911	exit_get_fwddb:
912	return status;
913	}
914
915	int qla4xxx_conn_open(struct scsi_qla_host *ha, uint16_t fw_ddb_index)
916	{
917	uint32_t mbox_cmd[MBOX_REG_COUNT];
918	uint32_t mbox_sts[MBOX_REG_COUNT];
919	int status;
920
921	memset(&mbox_cmd, 0, sizeof(mbox_cmd));
922	memset(&mbox_sts, 0, sizeof(mbox_sts));
923
924	mbox_cmd[0] = MBOX_CMD_CONN_OPEN;
925	mbox_cmd[1] = fw_ddb_index;
926
927	status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, outCount: 2, mbx_cmd: &mbox_cmd[0],
928	mbx_sts: &mbox_sts[0]);
929	DEBUG2(ql4_printk(KERN_INFO, ha,
930	"%s: status = %d mbx0 = 0x%x mbx1 = 0x%x\n",
931	__func__, status, mbox_sts[0], mbox_sts[1]));
932	return status;
933	}
934
935	/**
936	* qla4xxx_set_ddb_entry - sets a ddb entry.
937	* @ha: Pointer to host adapter structure.
938	* @fw_ddb_index: Firmware's device database index
939	* @fw_ddb_entry_dma: dma address of ddb entry
940	* @mbx_sts: mailbox 0 to be returned or NULL
941	*
942	* This routine initializes or updates the adapter's device database
943	* entry for the specified device.
944	**/
945	int qla4xxx_set_ddb_entry(struct scsi_qla_host * ha, uint16_t fw_ddb_index,
946	dma_addr_t fw_ddb_entry_dma, uint32_t *mbx_sts)
947	{
948	uint32_t mbox_cmd[MBOX_REG_COUNT];
949	uint32_t mbox_sts[MBOX_REG_COUNT];
950	int status;
951
952	/* Do not wait for completion. The firmware will send us an
953	* ASTS_DATABASE_CHANGED (0x8014) to notify us of the login status.
954	*/
955	memset(&mbox_cmd, 0, sizeof(mbox_cmd));
956	memset(&mbox_sts, 0, sizeof(mbox_sts));
957
958	mbox_cmd[0] = MBOX_CMD_SET_DATABASE_ENTRY;
959	mbox_cmd[1] = (uint32_t) fw_ddb_index;
960	mbox_cmd[2] = LSDW(fw_ddb_entry_dma);
961	mbox_cmd[3] = MSDW(fw_ddb_entry_dma);
962	mbox_cmd[4] = sizeof(struct dev_db_entry);
963
964	status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, outCount: 5, mbx_cmd: &mbox_cmd[0],
965	mbx_sts: &mbox_sts[0]);
966	if (mbx_sts)
967	*mbx_sts = mbox_sts[0];
968	DEBUG2(printk("scsi%ld: %s: status=%d mbx0=0x%x mbx4=0x%x\n",
969	ha->host_no, __func__, status, mbox_sts[0], mbox_sts[4]);)
970
971	return status;
972	}
973
974	int qla4xxx_session_logout_ddb(struct scsi_qla_host *ha,
975	struct ddb_entry *ddb_entry, int options)
976	{
977	int status;
978	uint32_t mbox_cmd[MBOX_REG_COUNT];
979	uint32_t mbox_sts[MBOX_REG_COUNT];
980
981	memset(&mbox_cmd, 0, sizeof(mbox_cmd));
982	memset(&mbox_sts, 0, sizeof(mbox_sts));
983
984	mbox_cmd[0] = MBOX_CMD_CONN_CLOSE_SESS_LOGOUT;
985	mbox_cmd[1] = ddb_entry->fw_ddb_index;
986	mbox_cmd[3] = options;
987
988	status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, outCount: 2, mbx_cmd: &mbox_cmd[0],
989	mbx_sts: &mbox_sts[0]);
990	if (status != QLA_SUCCESS) {
991	DEBUG2(ql4_printk(KERN_INFO, ha,
992	"%s: MBOX_CMD_CONN_CLOSE_SESS_LOGOUT "
993	"failed sts %04X %04X", __func__,
994	mbox_sts[0], mbox_sts[1]));
995	if ((mbox_sts[0] == MBOX_STS_COMMAND_ERROR) &&
996	(mbox_sts[1] == DDB_NOT_LOGGED_IN)) {
997	set_bit(DDB_CONN_CLOSE_FAILURE, addr: &ddb_entry->flags);
998	}
999	}
1000
1001	return status;
1002	}
1003
1004	/**
1005	* qla4xxx_get_crash_record - retrieves crash record.
1006	* @ha: Pointer to host adapter structure.
1007	*
1008	* This routine retrieves a crash record from the QLA4010 after an 8002h aen.
1009	**/
1010	void qla4xxx_get_crash_record(struct scsi_qla_host * ha)
1011	{
1012	uint32_t mbox_cmd[MBOX_REG_COUNT];
1013	uint32_t mbox_sts[MBOX_REG_COUNT];
1014	struct crash_record *crash_record = NULL;
1015	dma_addr_t crash_record_dma = 0;
1016	uint32_t crash_record_size = 0;
1017
1018	memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1019	memset(&mbox_sts, 0, sizeof(mbox_cmd));
1020
1021	/* Get size of crash record. */
1022	mbox_cmd[0] = MBOX_CMD_GET_CRASH_RECORD;
1023
1024	if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, outCount: 5, mbx_cmd: &mbox_cmd[0], mbx_sts: &mbox_sts[0]) !=
1025	QLA_SUCCESS) {
1026	DEBUG2(printk("scsi%ld: %s: ERROR: Unable to retrieve size!\n",
1027	ha->host_no, __func__));
1028	goto exit_get_crash_record;
1029	}
1030	crash_record_size = mbox_sts[4];
1031	if (crash_record_size == 0) {
1032	DEBUG2(printk("scsi%ld: %s: ERROR: Crash record size is 0!\n",
1033	ha->host_no, __func__));
1034	goto exit_get_crash_record;
1035	}
1036
1037	/* Alloc Memory for Crash Record. */
1038	crash_record = dma_alloc_coherent(dev: &ha->pdev->dev, size: crash_record_size,
1039	dma_handle: &crash_record_dma, GFP_KERNEL);
1040	if (crash_record == NULL)
1041	goto exit_get_crash_record;
1042
1043	/* Get Crash Record. */
1044	memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1045	memset(&mbox_sts, 0, sizeof(mbox_cmd));
1046
1047	mbox_cmd[0] = MBOX_CMD_GET_CRASH_RECORD;
1048	mbox_cmd[2] = LSDW(crash_record_dma);
1049	mbox_cmd[3] = MSDW(crash_record_dma);
1050	mbox_cmd[4] = crash_record_size;
1051
1052	if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, outCount: 5, mbx_cmd: &mbox_cmd[0], mbx_sts: &mbox_sts[0]) !=
1053	QLA_SUCCESS)
1054	goto exit_get_crash_record;
1055
1056	/* Dump Crash Record. */
1057
1058	exit_get_crash_record:
1059	if (crash_record)
1060	dma_free_coherent(dev: &ha->pdev->dev, size: crash_record_size,
1061	cpu_addr: crash_record, dma_handle: crash_record_dma);
1062	}
1063
1064	/**
1065	* qla4xxx_get_conn_event_log - retrieves connection event log
1066	* @ha: Pointer to host adapter structure.
1067	**/
1068	void qla4xxx_get_conn_event_log(struct scsi_qla_host * ha)
1069	{
1070	uint32_t mbox_cmd[MBOX_REG_COUNT];
1071	uint32_t mbox_sts[MBOX_REG_COUNT];
1072	struct conn_event_log_entry *event_log = NULL;
1073	dma_addr_t event_log_dma = 0;
1074	uint32_t event_log_size = 0;
1075	uint32_t num_valid_entries;
1076	uint32_t oldest_entry = 0;
1077	uint32_t max_event_log_entries;
1078	uint8_t i;
1079
1080	memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1081	memset(&mbox_sts, 0, sizeof(mbox_cmd));
1082
1083	/* Get size of crash record. */
1084	mbox_cmd[0] = MBOX_CMD_GET_CONN_EVENT_LOG;
1085
1086	if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, outCount: 5, mbx_cmd: &mbox_cmd[0], mbx_sts: &mbox_sts[0]) !=
1087	QLA_SUCCESS)
1088	goto exit_get_event_log;
1089
1090	event_log_size = mbox_sts[4];
1091	if (event_log_size == 0)
1092	goto exit_get_event_log;
1093
1094	/* Alloc Memory for Crash Record. */
1095	event_log = dma_alloc_coherent(dev: &ha->pdev->dev, size: event_log_size,
1096	dma_handle: &event_log_dma, GFP_KERNEL);
1097	if (event_log == NULL)
1098	goto exit_get_event_log;
1099
1100	/* Get Crash Record. */
1101	memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1102	memset(&mbox_sts, 0, sizeof(mbox_cmd));
1103
1104	mbox_cmd[0] = MBOX_CMD_GET_CONN_EVENT_LOG;
1105	mbox_cmd[2] = LSDW(event_log_dma);
1106	mbox_cmd[3] = MSDW(event_log_dma);
1107
1108	if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, outCount: 5, mbx_cmd: &mbox_cmd[0], mbx_sts: &mbox_sts[0]) !=
1109	QLA_SUCCESS) {
1110	DEBUG2(printk("scsi%ld: %s: ERROR: Unable to retrieve event "
1111	"log!\n", ha->host_no, __func__));
1112	goto exit_get_event_log;
1113	}
1114
1115	/* Dump Event Log. */
1116	num_valid_entries = mbox_sts[1];
1117
1118	max_event_log_entries = event_log_size /
1119	sizeof(struct conn_event_log_entry);
1120
1121	if (num_valid_entries > max_event_log_entries)
1122	oldest_entry = num_valid_entries % max_event_log_entries;
1123
1124	DEBUG3(printk("scsi%ld: Connection Event Log Dump (%d entries):\n",
1125	ha->host_no, num_valid_entries));
1126
1127	if (ql4xextended_error_logging == 3) {
1128	if (oldest_entry == 0) {
1129	/* Circular Buffer has not wrapped around */
1130	for (i=0; i < num_valid_entries; i++) {
1131	qla4xxx_dump_buffer(b: (uint8_t *)event_log+
1132	(i*sizeof(*event_log)),
1133	size: sizeof(*event_log));
1134	}
1135	}
1136	else {
1137	/* Circular Buffer has wrapped around -
1138	* display accordingly*/
1139	for (i=oldest_entry; i < max_event_log_entries; i++) {
1140	qla4xxx_dump_buffer(b: (uint8_t *)event_log+
1141	(i*sizeof(*event_log)),
1142	size: sizeof(*event_log));
1143	}
1144	for (i=0; i < oldest_entry; i++) {
1145	qla4xxx_dump_buffer(b: (uint8_t *)event_log+
1146	(i*sizeof(*event_log)),
1147	size: sizeof(*event_log));
1148	}
1149	}
1150	}
1151
1152	exit_get_event_log:
1153	if (event_log)
1154	dma_free_coherent(dev: &ha->pdev->dev, size: event_log_size, cpu_addr: event_log,
1155	dma_handle: event_log_dma);
1156	}
1157
1158	/**
1159	* qla4xxx_abort_task - issues Abort Task
1160	* @ha: Pointer to host adapter structure.
1161	* @srb: Pointer to srb entry
1162	*
1163	* This routine performs a LUN RESET on the specified target/lun.
1164	* The caller must ensure that the ddb_entry and lun_entry pointers
1165	* are valid before calling this routine.
1166	**/
1167	int qla4xxx_abort_task(struct scsi_qla_host *ha, struct srb *srb)
1168	{
1169	uint32_t mbox_cmd[MBOX_REG_COUNT];
1170	uint32_t mbox_sts[MBOX_REG_COUNT];
1171	struct scsi_cmnd *cmd = srb->cmd;
1172	int status = QLA_SUCCESS;
1173	unsigned long flags = 0;
1174	uint32_t index;
1175
1176	/*
1177	* Send abort task command to ISP, so that the ISP will return
1178	* request with ABORT status
1179	*/
1180	memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1181	memset(&mbox_sts, 0, sizeof(mbox_sts));
1182
1183	spin_lock_irqsave(&ha->hardware_lock, flags);
1184	index = (unsigned long)(unsigned char *)cmd->host_scribble;
1185	spin_unlock_irqrestore(lock: &ha->hardware_lock, flags);
1186
1187	/* Firmware already posted completion on response queue */
1188	if (index == MAX_SRBS)
1189	return status;
1190
1191	mbox_cmd[0] = MBOX_CMD_ABORT_TASK;
1192	mbox_cmd[1] = srb->ddb->fw_ddb_index;
1193	mbox_cmd[2] = index;
1194	/* Immediate Command Enable */
1195	mbox_cmd[5] = 0x01;
1196
1197	qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, outCount: 5, mbx_cmd: &mbox_cmd[0],
1198	mbx_sts: &mbox_sts[0]);
1199	if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE) {
1200	status = QLA_ERROR;
1201
1202	DEBUG2(printk(KERN_WARNING "scsi%ld:%d:%llu: abort task FAILED: "
1203	"mbx0=%04X, mb1=%04X, mb2=%04X, mb3=%04X, mb4=%04X\n",
1204	ha->host_no, cmd->device->id, cmd->device->lun, mbox_sts[0],
1205	mbox_sts[1], mbox_sts[2], mbox_sts[3], mbox_sts[4]));
1206	}
1207
1208	return status;
1209	}
1210
1211	/**
1212	* qla4xxx_reset_lun - issues LUN Reset
1213	* @ha: Pointer to host adapter structure.
1214	* @ddb_entry: Pointer to device database entry
1215	* @lun: lun number
1216	*
1217	* This routine performs a LUN RESET on the specified target/lun.
1218	* The caller must ensure that the ddb_entry and lun_entry pointers
1219	* are valid before calling this routine.
1220	**/
1221	int qla4xxx_reset_lun(struct scsi_qla_host * ha, struct ddb_entry * ddb_entry,
1222	uint64_t lun)
1223	{
1224	uint32_t mbox_cmd[MBOX_REG_COUNT];
1225	uint32_t mbox_sts[MBOX_REG_COUNT];
1226	uint32_t scsi_lun[2];
1227	int status = QLA_SUCCESS;
1228
1229	DEBUG2(printk("scsi%ld:%d:%llu: lun reset issued\n", ha->host_no,
1230	ddb_entry->fw_ddb_index, lun));
1231
1232	/*
1233	* Send lun reset command to ISP, so that the ISP will return all
1234	* outstanding requests with RESET status
1235	*/
1236	memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1237	memset(&mbox_sts, 0, sizeof(mbox_sts));
1238	int_to_scsilun(lun, (struct scsi_lun *) scsi_lun);
1239
1240	mbox_cmd[0] = MBOX_CMD_LUN_RESET;
1241	mbox_cmd[1] = ddb_entry->fw_ddb_index;
1242	/* FW expects LUN bytes 0-3 in Incoming Mailbox 2
1243	* (LUN byte 0 is LSByte, byte 3 is MSByte) */
1244	mbox_cmd[2] = cpu_to_le32(scsi_lun[0]);
1245	/* FW expects LUN bytes 4-7 in Incoming Mailbox 3
1246	* (LUN byte 4 is LSByte, byte 7 is MSByte) */
1247	mbox_cmd[3] = cpu_to_le32(scsi_lun[1]);
1248	mbox_cmd[5] = 0x01; /* Immediate Command Enable */
1249
1250	qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, outCount: 1, mbx_cmd: &mbox_cmd[0], mbx_sts: &mbox_sts[0]);
1251	if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE &&
1252	mbox_sts[0] != MBOX_STS_COMMAND_ERROR)
1253	status = QLA_ERROR;
1254
1255	return status;
1256	}
1257
1258	/**
1259	* qla4xxx_reset_target - issues target Reset
1260	* @ha: Pointer to host adapter structure.
1261	* @ddb_entry: Pointer to device database entry
1262	*
1263	* This routine performs a TARGET RESET on the specified target.
1264	* The caller must ensure that the ddb_entry pointers
1265	* are valid before calling this routine.
1266	**/
1267	int qla4xxx_reset_target(struct scsi_qla_host *ha,
1268	struct ddb_entry *ddb_entry)
1269	{
1270	uint32_t mbox_cmd[MBOX_REG_COUNT];
1271	uint32_t mbox_sts[MBOX_REG_COUNT];
1272	int status = QLA_SUCCESS;
1273
1274	DEBUG2(printk("scsi%ld:%d: target reset issued\n", ha->host_no,
1275	ddb_entry->fw_ddb_index));
1276
1277	/*
1278	* Send target reset command to ISP, so that the ISP will return all
1279	* outstanding requests with RESET status
1280	*/
1281	memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1282	memset(&mbox_sts, 0, sizeof(mbox_sts));
1283
1284	mbox_cmd[0] = MBOX_CMD_TARGET_WARM_RESET;
1285	mbox_cmd[1] = ddb_entry->fw_ddb_index;
1286	mbox_cmd[5] = 0x01; /* Immediate Command Enable */
1287
1288	qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, outCount: 1, mbx_cmd: &mbox_cmd[0],
1289	mbx_sts: &mbox_sts[0]);
1290	if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE &&
1291	mbox_sts[0] != MBOX_STS_COMMAND_ERROR)
1292	status = QLA_ERROR;
1293
1294	return status;
1295	}
1296
1297	int qla4xxx_get_flash(struct scsi_qla_host * ha, dma_addr_t dma_addr,
1298	uint32_t offset, uint32_t len)
1299	{
1300	uint32_t mbox_cmd[MBOX_REG_COUNT];
1301	uint32_t mbox_sts[MBOX_REG_COUNT];
1302
1303	memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1304	memset(&mbox_sts, 0, sizeof(mbox_sts));
1305
1306	mbox_cmd[0] = MBOX_CMD_READ_FLASH;
1307	mbox_cmd[1] = LSDW(dma_addr);
1308	mbox_cmd[2] = MSDW(dma_addr);
1309	mbox_cmd[3] = offset;
1310	mbox_cmd[4] = len;
1311
1312	if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, outCount: 2, mbx_cmd: &mbox_cmd[0], mbx_sts: &mbox_sts[0]) !=
1313	QLA_SUCCESS) {
1314	DEBUG2(printk("scsi%ld: %s: MBOX_CMD_READ_FLASH, failed w/ "
1315	"status %04X %04X, offset %08x, len %08x\n", ha->host_no,
1316	__func__, mbox_sts[0], mbox_sts[1], offset, len));
1317	return QLA_ERROR;
1318	}
1319	return QLA_SUCCESS;
1320	}
1321
1322	/**
1323	* qla4xxx_about_firmware - gets FW, iscsi draft and boot loader version
1324	* @ha: Pointer to host adapter structure.
1325	*
1326	* Retrieves the FW version, iSCSI draft version & bootloader version of HBA.
1327	* Mailboxes 2 & 3 may hold an address for data. Make sure that we write 0 to
1328	* those mailboxes, if unused.
1329	**/
1330	int qla4xxx_about_firmware(struct scsi_qla_host *ha)
1331	{
1332	struct about_fw_info *about_fw = NULL;
1333	dma_addr_t about_fw_dma;
1334	uint32_t mbox_cmd[MBOX_REG_COUNT];
1335	uint32_t mbox_sts[MBOX_REG_COUNT];
1336	int status = QLA_ERROR;
1337
1338	about_fw = dma_alloc_coherent(dev: &ha->pdev->dev,
1339	size: sizeof(struct about_fw_info),
1340	dma_handle: &about_fw_dma, GFP_KERNEL);
1341	if (!about_fw) {
1342	DEBUG2(ql4_printk(KERN_ERR, ha, "%s: Unable to alloc memory "
1343	"for about_fw\n", __func__));
1344	return status;
1345	}
1346
1347	memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1348	memset(&mbox_sts, 0, sizeof(mbox_sts));
1349
1350	mbox_cmd[0] = MBOX_CMD_ABOUT_FW;
1351	mbox_cmd[2] = LSDW(about_fw_dma);
1352	mbox_cmd[3] = MSDW(about_fw_dma);
1353	mbox_cmd[4] = sizeof(struct about_fw_info);
1354
1355	status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, MBOX_REG_COUNT,
1356	mbx_cmd: &mbox_cmd[0], mbx_sts: &mbox_sts[0]);
1357	if (status != QLA_SUCCESS) {
1358	DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_ABOUT_FW "
1359	"failed w/ status %04X\n", __func__,
1360	mbox_sts[0]));
1361	goto exit_about_fw;
1362	}
1363
1364	/* Save version information. */
1365	ha->fw_info.fw_major = le16_to_cpu(about_fw->fw_major);
1366	ha->fw_info.fw_minor = le16_to_cpu(about_fw->fw_minor);
1367	ha->fw_info.fw_patch = le16_to_cpu(about_fw->fw_patch);
1368	ha->fw_info.fw_build = le16_to_cpu(about_fw->fw_build);
1369	memcpy(ha->fw_info.fw_build_date, about_fw->fw_build_date,
1370	sizeof(about_fw->fw_build_date));
1371	memcpy(ha->fw_info.fw_build_time, about_fw->fw_build_time,
1372	sizeof(about_fw->fw_build_time));
1373	strcpy(p: (char *)ha->fw_info.fw_build_user,
1374	q: skip_spaces((char *)about_fw->fw_build_user));
1375	ha->fw_info.fw_load_source = le16_to_cpu(about_fw->fw_load_source);
1376	ha->fw_info.iscsi_major = le16_to_cpu(about_fw->iscsi_major);
1377	ha->fw_info.iscsi_minor = le16_to_cpu(about_fw->iscsi_minor);
1378	ha->fw_info.bootload_major = le16_to_cpu(about_fw->bootload_major);
1379	ha->fw_info.bootload_minor = le16_to_cpu(about_fw->bootload_minor);
1380	ha->fw_info.bootload_patch = le16_to_cpu(about_fw->bootload_patch);
1381	ha->fw_info.bootload_build = le16_to_cpu(about_fw->bootload_build);
1382	strcpy(p: (char *)ha->fw_info.extended_timestamp,
1383	q: skip_spaces((char *)about_fw->extended_timestamp));
1384
1385	ha->fw_uptime_secs = le32_to_cpu(mbox_sts[5]);
1386	ha->fw_uptime_msecs = le32_to_cpu(mbox_sts[6]);
1387	status = QLA_SUCCESS;
1388
1389	exit_about_fw:
1390	dma_free_coherent(dev: &ha->pdev->dev, size: sizeof(struct about_fw_info),
1391	cpu_addr: about_fw, dma_handle: about_fw_dma);
1392	return status;
1393	}
1394
1395	int qla4xxx_get_default_ddb(struct scsi_qla_host *ha, uint32_t options,
1396	dma_addr_t dma_addr)
1397	{
1398	uint32_t mbox_cmd[MBOX_REG_COUNT];
1399	uint32_t mbox_sts[MBOX_REG_COUNT];
1400
1401	memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1402	memset(&mbox_sts, 0, sizeof(mbox_sts));
1403
1404	mbox_cmd[0] = MBOX_CMD_GET_DATABASE_ENTRY_DEFAULTS;
1405	mbox_cmd[1] = options;
1406	mbox_cmd[2] = LSDW(dma_addr);
1407	mbox_cmd[3] = MSDW(dma_addr);
1408
1409	if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, outCount: 1, mbx_cmd: &mbox_cmd[0], mbx_sts: &mbox_sts[0]) !=
1410	QLA_SUCCESS) {
1411	DEBUG2(printk("scsi%ld: %s: failed status %04X\n",
1412	ha->host_no, __func__, mbox_sts[0]));
1413	return QLA_ERROR;
1414	}
1415	return QLA_SUCCESS;
1416	}
1417
1418	int qla4xxx_req_ddb_entry(struct scsi_qla_host *ha, uint32_t ddb_index,
1419	uint32_t *mbx_sts)
1420	{
1421	int status;
1422	uint32_t mbox_cmd[MBOX_REG_COUNT];
1423	uint32_t mbox_sts[MBOX_REG_COUNT];
1424
1425	memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1426	memset(&mbox_sts, 0, sizeof(mbox_sts));
1427
1428	mbox_cmd[0] = MBOX_CMD_REQUEST_DATABASE_ENTRY;
1429	mbox_cmd[1] = ddb_index;
1430
1431	status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, outCount: 1, mbx_cmd: &mbox_cmd[0],
1432	mbx_sts: &mbox_sts[0]);
1433	if (status != QLA_SUCCESS) {
1434	DEBUG2(ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n",
1435	__func__, mbox_sts[0]));
1436	}
1437
1438	*mbx_sts = mbox_sts[0];
1439	return status;
1440	}
1441
1442	int qla4xxx_clear_ddb_entry(struct scsi_qla_host *ha, uint32_t ddb_index)
1443	{
1444	int status;
1445	uint32_t mbox_cmd[MBOX_REG_COUNT];
1446	uint32_t mbox_sts[MBOX_REG_COUNT];
1447
1448	memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1449	memset(&mbox_sts, 0, sizeof(mbox_sts));
1450
1451	mbox_cmd[0] = MBOX_CMD_CLEAR_DATABASE_ENTRY;
1452	mbox_cmd[1] = ddb_index;
1453
1454	status = qla4xxx_mailbox_command(ha, inCount: 2, outCount: 1, mbx_cmd: &mbox_cmd[0],
1455	mbx_sts: &mbox_sts[0]);
1456	if (status != QLA_SUCCESS) {
1457	DEBUG2(ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n",
1458	__func__, mbox_sts[0]));
1459	}
1460
1461	return status;
1462	}
1463
1464	int qla4xxx_set_flash(struct scsi_qla_host *ha, dma_addr_t dma_addr,
1465	uint32_t offset, uint32_t length, uint32_t options)
1466	{
1467	uint32_t mbox_cmd[MBOX_REG_COUNT];
1468	uint32_t mbox_sts[MBOX_REG_COUNT];
1469	int status = QLA_SUCCESS;
1470
1471	memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1472	memset(&mbox_sts, 0, sizeof(mbox_sts));
1473
1474	mbox_cmd[0] = MBOX_CMD_WRITE_FLASH;
1475	mbox_cmd[1] = LSDW(dma_addr);
1476	mbox_cmd[2] = MSDW(dma_addr);
1477	mbox_cmd[3] = offset;
1478	mbox_cmd[4] = length;
1479	mbox_cmd[5] = options;
1480
1481	status = qla4xxx_mailbox_command(ha, inCount: 6, outCount: 2, mbx_cmd: &mbox_cmd[0], mbx_sts: &mbox_sts[0]);
1482	if (status != QLA_SUCCESS) {
1483	DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_WRITE_FLASH "
1484	"failed w/ status %04X, mbx1 %04X\n",
1485	__func__, mbox_sts[0], mbox_sts[1]));
1486	}
1487	return status;
1488	}
1489
1490	int qla4xxx_bootdb_by_index(struct scsi_qla_host *ha,
1491	struct dev_db_entry *fw_ddb_entry,
1492	dma_addr_t fw_ddb_entry_dma, uint16_t ddb_index)
1493	{
1494	uint32_t dev_db_start_offset = FLASH_OFFSET_DB_INFO;
1495	uint32_t dev_db_end_offset;
1496	int status = QLA_ERROR;
1497
1498	memset(fw_ddb_entry, 0, sizeof(*fw_ddb_entry));
1499
1500	dev_db_start_offset += (ddb_index * sizeof(*fw_ddb_entry));
1501	dev_db_end_offset = FLASH_OFFSET_DB_END;
1502
1503	if (dev_db_start_offset > dev_db_end_offset) {
1504	DEBUG2(ql4_printk(KERN_ERR, ha,
1505	"%s:Invalid DDB index %d", __func__,
1506	ddb_index));
1507	goto exit_bootdb_failed;
1508	}
1509
1510	if (qla4xxx_get_flash(ha, dma_addr: fw_ddb_entry_dma, offset: dev_db_start_offset,
1511	len: sizeof(*fw_ddb_entry)) != QLA_SUCCESS) {
1512	ql4_printk(KERN_ERR, ha, "scsi%ld: %s: Get Flash"
1513	"failed\n", ha->host_no, __func__);
1514	goto exit_bootdb_failed;
1515	}
1516
1517	if (fw_ddb_entry->cookie == DDB_VALID_COOKIE)
1518	status = QLA_SUCCESS;
1519
1520	exit_bootdb_failed:
1521	return status;
1522	}
1523
1524	int qla4xxx_flashdb_by_index(struct scsi_qla_host *ha,
1525	struct dev_db_entry *fw_ddb_entry,
1526	dma_addr_t fw_ddb_entry_dma, uint16_t ddb_index)
1527	{
1528	uint32_t dev_db_start_offset;
1529	uint32_t dev_db_end_offset;
1530	int status = QLA_ERROR;
1531
1532	memset(fw_ddb_entry, 0, sizeof(*fw_ddb_entry));
1533
1534	if (is_qla40XX(ha)) {
1535	dev_db_start_offset = FLASH_OFFSET_DB_INFO;
1536	dev_db_end_offset = FLASH_OFFSET_DB_END;
1537	} else {
1538	dev_db_start_offset = FLASH_RAW_ACCESS_ADDR +
1539	(ha->hw.flt_region_ddb << 2);
1540	/* flt_ddb_size is DDB table size for both ports
1541	* so divide it by 2 to calculate the offset for second port
1542	*/
1543	if (ha->port_num == 1)
1544	dev_db_start_offset += (ha->hw.flt_ddb_size / 2);
1545
1546	dev_db_end_offset = dev_db_start_offset +
1547	(ha->hw.flt_ddb_size / 2);
1548	}
1549
1550	dev_db_start_offset += (ddb_index * sizeof(*fw_ddb_entry));
1551
1552	if (dev_db_start_offset > dev_db_end_offset) {
1553	DEBUG2(ql4_printk(KERN_ERR, ha,
1554	"%s:Invalid DDB index %d", __func__,
1555	ddb_index));
1556	goto exit_fdb_failed;
1557	}
1558
1559	if (qla4xxx_get_flash(ha, dma_addr: fw_ddb_entry_dma, offset: dev_db_start_offset,
1560	len: sizeof(*fw_ddb_entry)) != QLA_SUCCESS) {
1561	ql4_printk(KERN_ERR, ha, "scsi%ld: %s: Get Flash failed\n",
1562	ha->host_no, __func__);
1563	goto exit_fdb_failed;
1564	}
1565
1566	if (fw_ddb_entry->cookie == DDB_VALID_COOKIE)
1567	status = QLA_SUCCESS;
1568
1569	exit_fdb_failed:
1570	return status;
1571	}
1572
1573	int qla4xxx_get_chap(struct scsi_qla_host *ha, char *username, char *password,
1574	uint16_t idx)
1575	{
1576	int ret = 0;
1577	int rval = QLA_ERROR;
1578	uint32_t offset = 0, chap_size;
1579	struct ql4_chap_table *chap_table;
1580	dma_addr_t chap_dma;
1581
1582	chap_table = dma_pool_zalloc(pool: ha->chap_dma_pool, GFP_KERNEL, handle: &chap_dma);
1583	if (chap_table == NULL)
1584	return -ENOMEM;
1585
1586	chap_size = sizeof(struct ql4_chap_table);
1587
1588	if (is_qla40XX(ha))
1589	offset = FLASH_CHAP_OFFSET | (idx * chap_size);
1590	else {
1591	offset = FLASH_RAW_ACCESS_ADDR + (ha->hw.flt_region_chap << 2);
1592	/* flt_chap_size is CHAP table size for both ports
1593	* so divide it by 2 to calculate the offset for second port
1594	*/
1595	if (ha->port_num == 1)
1596	offset += (ha->hw.flt_chap_size / 2);
1597	offset += (idx * chap_size);
1598	}
1599
1600	rval = qla4xxx_get_flash(ha, dma_addr: chap_dma, offset, len: chap_size);
1601	if (rval != QLA_SUCCESS) {
1602	ret = -EINVAL;
1603	goto exit_get_chap;
1604	}
1605
1606	DEBUG2(ql4_printk(KERN_INFO, ha, "Chap Cookie: x%x\n",
1607	__le16_to_cpu(chap_table->cookie)));
1608
1609	if (__le16_to_cpu(chap_table->cookie) != CHAP_VALID_COOKIE) {
1610	ql4_printk(KERN_ERR, ha, "No valid chap entry found\n");
1611	goto exit_get_chap;
1612	}
1613
1614	strscpy(p: password, q: chap_table->secret, QL4_CHAP_MAX_SECRET_LEN);
1615	strscpy(p: username, q: chap_table->name, QL4_CHAP_MAX_NAME_LEN);
1616	chap_table->cookie = cpu_to_le16(CHAP_VALID_COOKIE);
1617
1618	exit_get_chap:
1619	dma_pool_free(pool: ha->chap_dma_pool, vaddr: chap_table, addr: chap_dma);
1620	return ret;
1621	}
1622
1623	/**
1624	* qla4xxx_set_chap - Make a chap entry at the given index
1625	* @ha: pointer to adapter structure
1626	* @username: CHAP username to set
1627	* @password: CHAP password to set
1628	* @idx: CHAP index at which to make the entry
1629	* @bidi: type of chap entry (chap_in or chap_out)
1630	*
1631	* Create chap entry at the given index with the information provided.
1632	*
1633	* Note: Caller should acquire the chap lock before getting here.
1634	**/
1635	int qla4xxx_set_chap(struct scsi_qla_host *ha, char *username, char *password,
1636	uint16_t idx, int bidi)
1637	{
1638	int ret = 0;
1639	int rval = QLA_ERROR;
1640	uint32_t offset = 0;
1641	struct ql4_chap_table *chap_table;
1642	uint32_t chap_size = 0;
1643	dma_addr_t chap_dma;
1644
1645	chap_table = dma_pool_zalloc(pool: ha->chap_dma_pool, GFP_KERNEL, handle: &chap_dma);
1646	if (chap_table == NULL) {
1647	ret = -ENOMEM;
1648	goto exit_set_chap;
1649	}
1650
1651	if (bidi)
1652	chap_table->flags |= BIT_6; /* peer */
1653	else
1654	chap_table->flags |= BIT_7; /* local */
1655	chap_table->secret_len = strlen(password);
1656	strncpy(p: chap_table->secret, q: password, MAX_CHAP_SECRET_LEN - 1);
1657	strncpy(p: chap_table->name, q: username, MAX_CHAP_NAME_LEN - 1);
1658	chap_table->cookie = cpu_to_le16(CHAP_VALID_COOKIE);
1659
1660	if (is_qla40XX(ha)) {
1661	chap_size = MAX_CHAP_ENTRIES_40XX * sizeof(*chap_table);
1662	offset = FLASH_CHAP_OFFSET;
1663	} else { /* Single region contains CHAP info for both ports which is
1664	* divided into half for each port.
1665	*/
1666	chap_size = ha->hw.flt_chap_size / 2;
1667	offset = FLASH_RAW_ACCESS_ADDR + (ha->hw.flt_region_chap << 2);
1668	if (ha->port_num == 1)
1669	offset += chap_size;
1670	}
1671
1672	offset += (idx * sizeof(struct ql4_chap_table));
1673	rval = qla4xxx_set_flash(ha, dma_addr: chap_dma, offset,
1674	length: sizeof(struct ql4_chap_table),
1675	FLASH_OPT_RMW_COMMIT);
1676
1677	if (rval == QLA_SUCCESS && ha->chap_list) {
1678	/* Update ha chap_list cache */
1679	memcpy((struct ql4_chap_table *)ha->chap_list + idx,
1680	chap_table, sizeof(struct ql4_chap_table));
1681	}
1682	dma_pool_free(pool: ha->chap_dma_pool, vaddr: chap_table, addr: chap_dma);
1683	if (rval != QLA_SUCCESS)
1684	ret = -EINVAL;
1685
1686	exit_set_chap:
1687	return ret;
1688	}
1689
1690
1691	int qla4xxx_get_uni_chap_at_index(struct scsi_qla_host *ha, char *username,
1692	char *password, uint16_t chap_index)
1693	{
1694	int rval = QLA_ERROR;
1695	struct ql4_chap_table *chap_table = NULL;
1696	int max_chap_entries;
1697
1698	if (!ha->chap_list) {
1699	ql4_printk(KERN_ERR, ha, "Do not have CHAP table cache\n");
1700	rval = QLA_ERROR;
1701	goto exit_uni_chap;
1702	}
1703
1704	if (!username || !password) {
1705	ql4_printk(KERN_ERR, ha, "No memory for username & secret\n");
1706	rval = QLA_ERROR;
1707	goto exit_uni_chap;
1708	}
1709
1710	if (is_qla80XX(ha))
1711	max_chap_entries = (ha->hw.flt_chap_size / 2) /
1712	sizeof(struct ql4_chap_table);
1713	else
1714	max_chap_entries = MAX_CHAP_ENTRIES_40XX;
1715
1716	if (chap_index > max_chap_entries) {
1717	ql4_printk(KERN_ERR, ha, "Invalid Chap index\n");
1718	rval = QLA_ERROR;
1719	goto exit_uni_chap;
1720	}
1721
1722	mutex_lock(&ha->chap_sem);
1723	chap_table = (struct ql4_chap_table *)ha->chap_list + chap_index;
1724	if (chap_table->cookie != cpu_to_le16(CHAP_VALID_COOKIE)) {
1725	rval = QLA_ERROR;
1726	goto exit_unlock_uni_chap;
1727	}
1728
1729	if (!(chap_table->flags & BIT_7)) {
1730	ql4_printk(KERN_ERR, ha, "Unidirectional entry not set\n");
1731	rval = QLA_ERROR;
1732	goto exit_unlock_uni_chap;
1733	}
1734
1735	strscpy(p: password, q: chap_table->secret, MAX_CHAP_SECRET_LEN);
1736	strscpy(p: username, q: chap_table->name, MAX_CHAP_NAME_LEN);
1737
1738	rval = QLA_SUCCESS;
1739
1740	exit_unlock_uni_chap:
1741	mutex_unlock(lock: &ha->chap_sem);
1742	exit_uni_chap:
1743	return rval;
1744	}
1745
1746	/**
1747	* qla4xxx_get_chap_index - Get chap index given username and secret
1748	* @ha: pointer to adapter structure
1749	* @username: CHAP username to be searched
1750	* @password: CHAP password to be searched
1751	* @bidi: Is this a BIDI CHAP
1752	* @chap_index: CHAP index to be returned
1753	*
1754	* Match the username and password in the chap_list, return the index if a
1755	* match is found. If a match is not found then add the entry in FLASH and
1756	* return the index at which entry is written in the FLASH.
1757	**/
1758	int qla4xxx_get_chap_index(struct scsi_qla_host *ha, char *username,
1759	char *password, int bidi, uint16_t *chap_index)
1760	{
1761	int i, rval;
1762	int free_index = -1;
1763	int found_index = 0;
1764	int max_chap_entries = 0;
1765	struct ql4_chap_table *chap_table;
1766
1767	if (is_qla80XX(ha))
1768	max_chap_entries = (ha->hw.flt_chap_size / 2) /
1769	sizeof(struct ql4_chap_table);
1770	else
1771	max_chap_entries = MAX_CHAP_ENTRIES_40XX;
1772
1773	if (!ha->chap_list) {
1774	ql4_printk(KERN_ERR, ha, "Do not have CHAP table cache\n");
1775	return QLA_ERROR;
1776	}
1777
1778	if (!username || !password) {
1779	ql4_printk(KERN_ERR, ha, "Do not have username and psw\n");
1780	return QLA_ERROR;
1781	}
1782
1783	mutex_lock(&ha->chap_sem);
1784	for (i = 0; i < max_chap_entries; i++) {
1785	chap_table = (struct ql4_chap_table *)ha->chap_list + i;
1786	if (chap_table->cookie !=
1787	cpu_to_le16(CHAP_VALID_COOKIE)) {
1788	if (i > MAX_RESRV_CHAP_IDX && free_index == -1)
1789	free_index = i;
1790	continue;
1791	}
1792	if (bidi) {
1793	if (chap_table->flags & BIT_7)
1794	continue;
1795	} else {
1796	if (chap_table->flags & BIT_6)
1797	continue;
1798	}
1799	if (!strncmp(chap_table->secret, password,
1800	MAX_CHAP_SECRET_LEN) &&
1801	!strncmp(chap_table->name, username,
1802	MAX_CHAP_NAME_LEN)) {
1803	*chap_index = i;
1804	found_index = 1;
1805	break;
1806	}
1807	}
1808
1809	/* If chap entry is not present and a free index is available then
1810	* write the entry in flash
1811	*/
1812	if (!found_index && free_index != -1) {
1813	rval = qla4xxx_set_chap(ha, username, password,
1814	idx: free_index, bidi);
1815	if (!rval) {
1816	*chap_index = free_index;
1817	found_index = 1;
1818	}
1819	}
1820
1821	mutex_unlock(lock: &ha->chap_sem);
1822
1823	if (found_index)
1824	return QLA_SUCCESS;
1825	return QLA_ERROR;
1826	}
1827
1828	int qla4xxx_conn_close_sess_logout(struct scsi_qla_host *ha,
1829	uint16_t fw_ddb_index,
1830	uint16_t connection_id,
1831	uint16_t option)
1832	{
1833	uint32_t mbox_cmd[MBOX_REG_COUNT];
1834	uint32_t mbox_sts[MBOX_REG_COUNT];
1835	int status = QLA_SUCCESS;
1836
1837	memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1838	memset(&mbox_sts, 0, sizeof(mbox_sts));
1839
1840	mbox_cmd[0] = MBOX_CMD_CONN_CLOSE_SESS_LOGOUT;
1841	mbox_cmd[1] = fw_ddb_index;
1842	mbox_cmd[2] = connection_id;
1843	mbox_cmd[3] = option;
1844
1845	status = qla4xxx_mailbox_command(ha, inCount: 4, outCount: 2, mbx_cmd: &mbox_cmd[0], mbx_sts: &mbox_sts[0]);
1846	if (status != QLA_SUCCESS) {
1847	DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_CONN_CLOSE "
1848	"option %04x failed w/ status %04X %04X\n",
1849	__func__, option, mbox_sts[0], mbox_sts[1]));
1850	}
1851	return status;
1852	}
1853
1854	/**
1855	* qla4_84xx_extend_idc_tmo - Extend IDC Timeout.
1856	* @ha: Pointer to host adapter structure.
1857	* @ext_tmo: idc timeout value
1858	*
1859	* Requests firmware to extend the idc timeout value.
1860	**/
1861	static int qla4_84xx_extend_idc_tmo(struct scsi_qla_host *ha, uint32_t ext_tmo)
1862	{
1863	uint32_t mbox_cmd[MBOX_REG_COUNT];
1864	uint32_t mbox_sts[MBOX_REG_COUNT];
1865	int status;
1866
1867	memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1868	memset(&mbox_sts, 0, sizeof(mbox_sts));
1869	ext_tmo &= 0xf;
1870
1871	mbox_cmd[0] = MBOX_CMD_IDC_TIME_EXTEND;
1872	mbox_cmd[1] = ((ha->idc_info.request_desc & 0xfffff0ff) |
1873	(ext_tmo << 8)); /* new timeout */
1874	mbox_cmd[2] = ha->idc_info.info1;
1875	mbox_cmd[3] = ha->idc_info.info2;
1876	mbox_cmd[4] = ha->idc_info.info3;
1877
1878	status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, MBOX_REG_COUNT,
1879	mbx_cmd: mbox_cmd, mbx_sts: mbox_sts);
1880	if (status != QLA_SUCCESS) {
1881	DEBUG2(ql4_printk(KERN_INFO, ha,
1882	"scsi%ld: %s: failed status %04X\n",
1883	ha->host_no, __func__, mbox_sts[0]));
1884	return QLA_ERROR;
1885	} else {
1886	ql4_printk(KERN_INFO, ha, "%s: IDC timeout extended by %d secs\n",
1887	__func__, ext_tmo);
1888	}
1889
1890	return QLA_SUCCESS;
1891	}
1892
1893	int qla4xxx_disable_acb(struct scsi_qla_host *ha)
1894	{
1895	uint32_t mbox_cmd[MBOX_REG_COUNT];
1896	uint32_t mbox_sts[MBOX_REG_COUNT];
1897	int status = QLA_SUCCESS;
1898
1899	memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1900	memset(&mbox_sts, 0, sizeof(mbox_sts));
1901
1902	mbox_cmd[0] = MBOX_CMD_DISABLE_ACB;
1903
1904	status = qla4xxx_mailbox_command(ha, inCount: 8, outCount: 5, mbx_cmd: &mbox_cmd[0], mbx_sts: &mbox_sts[0]);
1905	if (status != QLA_SUCCESS) {
1906	DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_DISABLE_ACB "
1907	"failed w/ status %04X %04X %04X", __func__,
1908	mbox_sts[0], mbox_sts[1], mbox_sts[2]));
1909	} else {
1910	if (is_qla8042(ha) &&
1911	test_bit(DPC_POST_IDC_ACK, &ha->dpc_flags) &&
1912	(mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE)) {
1913	/*
1914	* Disable ACB mailbox command takes time to complete
1915	* based on the total number of targets connected.
1916	* For 512 targets, it took approximately 5 secs to
1917	* complete. Setting the timeout value to 8, with the 3
1918	* secs buffer.
1919	*/
1920	qla4_84xx_extend_idc_tmo(ha, IDC_EXTEND_TOV);
1921	if (!wait_for_completion_timeout(x: &ha->disable_acb_comp,
1922	IDC_EXTEND_TOV * HZ)) {
1923	ql4_printk(KERN_WARNING, ha, "%s: Disable ACB Completion not received\n",
1924	__func__);
1925	}
1926	}
1927	}
1928	return status;
1929	}
1930
1931	int qla4xxx_get_acb(struct scsi_qla_host *ha, dma_addr_t acb_dma,
1932	uint32_t acb_type, uint32_t len)
1933	{
1934	uint32_t mbox_cmd[MBOX_REG_COUNT];
1935	uint32_t mbox_sts[MBOX_REG_COUNT];
1936	int status = QLA_SUCCESS;
1937
1938	memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1939	memset(&mbox_sts, 0, sizeof(mbox_sts));
1940
1941	mbox_cmd[0] = MBOX_CMD_GET_ACB;
1942	mbox_cmd[1] = acb_type;
1943	mbox_cmd[2] = LSDW(acb_dma);
1944	mbox_cmd[3] = MSDW(acb_dma);
1945	mbox_cmd[4] = len;
1946
1947	status = qla4xxx_mailbox_command(ha, inCount: 5, outCount: 5, mbx_cmd: &mbox_cmd[0], mbx_sts: &mbox_sts[0]);
1948	if (status != QLA_SUCCESS) {
1949	DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_GET_ACB "
1950	"failed w/ status %04X\n", __func__,
1951	mbox_sts[0]));
1952	}
1953	return status;
1954	}
1955
1956	int qla4xxx_set_acb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
1957	uint32_t *mbox_sts, dma_addr_t acb_dma)
1958	{
1959	int status = QLA_SUCCESS;
1960
1961	memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
1962	memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
1963	mbox_cmd[0] = MBOX_CMD_SET_ACB;
1964	mbox_cmd[1] = 0; /* Primary ACB */
1965	mbox_cmd[2] = LSDW(acb_dma);
1966	mbox_cmd[3] = MSDW(acb_dma);
1967	mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
1968
1969	status = qla4xxx_mailbox_command(ha, inCount: 5, outCount: 5, mbx_cmd: &mbox_cmd[0], mbx_sts: &mbox_sts[0]);
1970	if (status != QLA_SUCCESS) {
1971	DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_SET_ACB "
1972	"failed w/ status %04X\n", __func__,
1973	mbox_sts[0]));
1974	}
1975	return status;
1976	}
1977
1978	int qla4xxx_set_param_ddbentry(struct scsi_qla_host *ha,
1979	struct ddb_entry *ddb_entry,
1980	struct iscsi_cls_conn *cls_conn,
1981	uint32_t *mbx_sts)
1982	{
1983	struct dev_db_entry *fw_ddb_entry;
1984	struct iscsi_conn *conn;
1985	struct iscsi_session *sess;
1986	struct qla_conn *qla_conn;
1987	struct sockaddr *dst_addr;
1988	dma_addr_t fw_ddb_entry_dma;
1989	int status = QLA_SUCCESS;
1990	int rval = 0;
1991	struct sockaddr_in *addr;
1992	struct sockaddr_in6 *addr6;
1993	char *ip;
1994	uint16_t iscsi_opts = 0;
1995	uint32_t options = 0;
1996	uint16_t idx, *ptid;
1997
1998	fw_ddb_entry = dma_alloc_coherent(dev: &ha->pdev->dev, size: sizeof(*fw_ddb_entry),
1999	dma_handle: &fw_ddb_entry_dma, GFP_KERNEL);
2000	if (!fw_ddb_entry) {
2001	DEBUG2(ql4_printk(KERN_ERR, ha,
2002	"%s: Unable to allocate dma buffer.\n",
2003	__func__));
2004	rval = -ENOMEM;
2005	goto exit_set_param_no_free;
2006	}
2007
2008	conn = cls_conn->dd_data;
2009	qla_conn = conn->dd_data;
2010	sess = conn->session;
2011	dst_addr = (struct sockaddr *)&qla_conn->qla_ep->dst_addr;
2012
2013	if (dst_addr->sa_family == AF_INET6)
2014	options |= IPV6_DEFAULT_DDB_ENTRY;
2015
2016	status = qla4xxx_get_default_ddb(ha, options, dma_addr: fw_ddb_entry_dma);
2017	if (status == QLA_ERROR) {
2018	rval = -EINVAL;
2019	goto exit_set_param;
2020	}
2021
2022	ptid = (uint16_t *)&fw_ddb_entry->isid[1];
2023	*ptid = cpu_to_le16((uint16_t)ddb_entry->sess->target_id);
2024
2025	DEBUG2(ql4_printk(KERN_INFO, ha, "ISID [%pmR]\n", fw_ddb_entry->isid));
2026
2027	iscsi_opts = le16_to_cpu(fw_ddb_entry->iscsi_options);
2028	memset(fw_ddb_entry->iscsi_alias, 0, sizeof(fw_ddb_entry->iscsi_alias));
2029
2030	memset(fw_ddb_entry->iscsi_name, 0, sizeof(fw_ddb_entry->iscsi_name));
2031
2032	if (sess->targetname != NULL) {
2033	memcpy(fw_ddb_entry->iscsi_name, sess->targetname,
2034	min(strlen(sess->targetname),
2035	sizeof(fw_ddb_entry->iscsi_name)));
2036	}
2037
2038	memset(fw_ddb_entry->ip_addr, 0, sizeof(fw_ddb_entry->ip_addr));
2039	memset(fw_ddb_entry->tgt_addr, 0, sizeof(fw_ddb_entry->tgt_addr));
2040
2041	fw_ddb_entry->options = DDB_OPT_TARGET | DDB_OPT_AUTO_SENDTGTS_DISABLE;
2042
2043	if (dst_addr->sa_family == AF_INET) {
2044	addr = (struct sockaddr_in *)dst_addr;
2045	ip = (char *)&addr->sin_addr;
2046	memcpy(fw_ddb_entry->ip_addr, ip, IP_ADDR_LEN);
2047	fw_ddb_entry->port = cpu_to_le16(ntohs(addr->sin_port));
2048	DEBUG2(ql4_printk(KERN_INFO, ha,
2049	"%s: Destination Address [%pI4]: index [%d]\n",
2050	__func__, fw_ddb_entry->ip_addr,
2051	ddb_entry->fw_ddb_index));
2052	} else if (dst_addr->sa_family == AF_INET6) {
2053	addr6 = (struct sockaddr_in6 *)dst_addr;
2054	ip = (char *)&addr6->sin6_addr;
2055	memcpy(fw_ddb_entry->ip_addr, ip, IPv6_ADDR_LEN);
2056	fw_ddb_entry->port = cpu_to_le16(ntohs(addr6->sin6_port));
2057	fw_ddb_entry->options |= DDB_OPT_IPV6_DEVICE;
2058	DEBUG2(ql4_printk(KERN_INFO, ha,
2059	"%s: Destination Address [%pI6]: index [%d]\n",
2060	__func__, fw_ddb_entry->ip_addr,
2061	ddb_entry->fw_ddb_index));
2062	} else {
2063	ql4_printk(KERN_ERR, ha,
2064	"%s: Failed to get IP Address\n",
2065	__func__);
2066	rval = -EINVAL;
2067	goto exit_set_param;
2068	}
2069
2070	/* CHAP */
2071	if (sess->username != NULL && sess->password != NULL) {
2072	if (strlen(sess->username) && strlen(sess->password)) {
2073	iscsi_opts |= BIT_7;
2074
2075	rval = qla4xxx_get_chap_index(ha, username: sess->username,
2076	password: sess->password,
2077	LOCAL_CHAP, chap_index: &idx);
2078	if (rval)
2079	goto exit_set_param;
2080
2081	fw_ddb_entry->chap_tbl_idx = cpu_to_le16(idx);
2082	}
2083	}
2084
2085	if (sess->username_in != NULL && sess->password_in != NULL) {
2086	/* Check if BIDI CHAP */
2087	if (strlen(sess->username_in) && strlen(sess->password_in)) {
2088	iscsi_opts |= BIT_4;
2089
2090	rval = qla4xxx_get_chap_index(ha, username: sess->username_in,
2091	password: sess->password_in,
2092	BIDI_CHAP, chap_index: &idx);
2093	if (rval)
2094	goto exit_set_param;
2095	}
2096	}
2097
2098	if (sess->initial_r2t_en)
2099	iscsi_opts |= BIT_10;
2100
2101	if (sess->imm_data_en)
2102	iscsi_opts |= BIT_11;
2103
2104	fw_ddb_entry->iscsi_options = cpu_to_le16(iscsi_opts);
2105
2106	if (conn->max_recv_dlength)
2107	fw_ddb_entry->iscsi_max_rcv_data_seg_len =
2108	cpu_to_le16((conn->max_recv_dlength / BYTE_UNITS));
2109
2110	if (sess->max_r2t)
2111	fw_ddb_entry->iscsi_max_outsnd_r2t = cpu_to_le16(sess->max_r2t);
2112
2113	if (sess->first_burst)
2114	fw_ddb_entry->iscsi_first_burst_len =
2115	cpu_to_le16((sess->first_burst / BYTE_UNITS));
2116
2117	if (sess->max_burst)
2118	fw_ddb_entry->iscsi_max_burst_len =
2119	cpu_to_le16((sess->max_burst / BYTE_UNITS));
2120
2121	if (sess->time2wait)
2122	fw_ddb_entry->iscsi_def_time2wait =
2123	cpu_to_le16(sess->time2wait);
2124
2125	if (sess->time2retain)
2126	fw_ddb_entry->iscsi_def_time2retain =
2127	cpu_to_le16(sess->time2retain);
2128
2129	status = qla4xxx_set_ddb_entry(ha, fw_ddb_index: ddb_entry->fw_ddb_index,
2130	fw_ddb_entry_dma, mbx_sts);
2131
2132	if (status != QLA_SUCCESS)
2133	rval = -EINVAL;
2134	exit_set_param:
2135	dma_free_coherent(dev: &ha->pdev->dev, size: sizeof(*fw_ddb_entry),
2136	cpu_addr: fw_ddb_entry, dma_handle: fw_ddb_entry_dma);
2137	exit_set_param_no_free:
2138	return rval;
2139	}
2140
2141	int qla4xxx_get_mgmt_data(struct scsi_qla_host *ha, uint16_t fw_ddb_index,
2142	uint16_t stats_size, dma_addr_t stats_dma)
2143	{
2144	int status = QLA_SUCCESS;
2145	uint32_t mbox_cmd[MBOX_REG_COUNT];
2146	uint32_t mbox_sts[MBOX_REG_COUNT];
2147
2148	memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
2149	memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
2150	mbox_cmd[0] = MBOX_CMD_GET_MANAGEMENT_DATA;
2151	mbox_cmd[1] = fw_ddb_index;
2152	mbox_cmd[2] = LSDW(stats_dma);
2153	mbox_cmd[3] = MSDW(stats_dma);
2154	mbox_cmd[4] = stats_size;
2155
2156	status = qla4xxx_mailbox_command(ha, inCount: 5, outCount: 1, mbx_cmd: &mbox_cmd[0], mbx_sts: &mbox_sts[0]);
2157	if (status != QLA_SUCCESS) {
2158	DEBUG2(ql4_printk(KERN_WARNING, ha,
2159	"%s: MBOX_CMD_GET_MANAGEMENT_DATA "
2160	"failed w/ status %04X\n", __func__,
2161	mbox_sts[0]));
2162	}
2163	return status;
2164	}
2165
2166	int qla4xxx_get_ip_state(struct scsi_qla_host *ha, uint32_t acb_idx,
2167	uint32_t ip_idx, uint32_t *sts)
2168	{
2169	uint32_t mbox_cmd[MBOX_REG_COUNT];
2170	uint32_t mbox_sts[MBOX_REG_COUNT];
2171	int status = QLA_SUCCESS;
2172
2173	memset(&mbox_cmd, 0, sizeof(mbox_cmd));
2174	memset(&mbox_sts, 0, sizeof(mbox_sts));
2175	mbox_cmd[0] = MBOX_CMD_GET_IP_ADDR_STATE;
2176	mbox_cmd[1] = acb_idx;
2177	mbox_cmd[2] = ip_idx;
2178
2179	status = qla4xxx_mailbox_command(ha, inCount: 3, outCount: 8, mbx_cmd: &mbox_cmd[0], mbx_sts: &mbox_sts[0]);
2180	if (status != QLA_SUCCESS) {
2181	DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: "
2182	"MBOX_CMD_GET_IP_ADDR_STATE failed w/ "
2183	"status %04X\n", __func__, mbox_sts[0]));
2184	}
2185	memcpy(sts, mbox_sts, sizeof(mbox_sts));
2186	return status;
2187	}
2188
2189	int qla4xxx_get_nvram(struct scsi_qla_host *ha, dma_addr_t nvram_dma,
2190	uint32_t offset, uint32_t size)
2191	{
2192	int status = QLA_SUCCESS;
2193	uint32_t mbox_cmd[MBOX_REG_COUNT];
2194	uint32_t mbox_sts[MBOX_REG_COUNT];
2195
2196	memset(&mbox_cmd, 0, sizeof(mbox_cmd));
2197	memset(&mbox_sts, 0, sizeof(mbox_sts));
2198
2199	mbox_cmd[0] = MBOX_CMD_GET_NVRAM;
2200	mbox_cmd[1] = LSDW(nvram_dma);
2201	mbox_cmd[2] = MSDW(nvram_dma);
2202	mbox_cmd[3] = offset;
2203	mbox_cmd[4] = size;
2204
2205	status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, outCount: 1, mbx_cmd: &mbox_cmd[0],
2206	mbx_sts: &mbox_sts[0]);
2207	if (status != QLA_SUCCESS) {
2208	DEBUG2(ql4_printk(KERN_ERR, ha, "scsi%ld: %s: failed "
2209	"status %04X\n", ha->host_no, __func__,
2210	mbox_sts[0]));
2211	}
2212	return status;
2213	}
2214
2215	int qla4xxx_set_nvram(struct scsi_qla_host *ha, dma_addr_t nvram_dma,
2216	uint32_t offset, uint32_t size)
2217	{
2218	int status = QLA_SUCCESS;
2219	uint32_t mbox_cmd[MBOX_REG_COUNT];
2220	uint32_t mbox_sts[MBOX_REG_COUNT];
2221
2222	memset(&mbox_cmd, 0, sizeof(mbox_cmd));
2223	memset(&mbox_sts, 0, sizeof(mbox_sts));
2224
2225	mbox_cmd[0] = MBOX_CMD_SET_NVRAM;
2226	mbox_cmd[1] = LSDW(nvram_dma);
2227	mbox_cmd[2] = MSDW(nvram_dma);
2228	mbox_cmd[3] = offset;
2229	mbox_cmd[4] = size;
2230
2231	status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, outCount: 1, mbx_cmd: &mbox_cmd[0],
2232	mbx_sts: &mbox_sts[0]);
2233	if (status != QLA_SUCCESS) {
2234	DEBUG2(ql4_printk(KERN_ERR, ha, "scsi%ld: %s: failed "
2235	"status %04X\n", ha->host_no, __func__,
2236	mbox_sts[0]));
2237	}
2238	return status;
2239	}
2240
2241	int qla4xxx_restore_factory_defaults(struct scsi_qla_host *ha,
2242	uint32_t region, uint32_t field0,
2243	uint32_t field1)
2244	{
2245	int status = QLA_SUCCESS;
2246	uint32_t mbox_cmd[MBOX_REG_COUNT];
2247	uint32_t mbox_sts[MBOX_REG_COUNT];
2248
2249	memset(&mbox_cmd, 0, sizeof(mbox_cmd));
2250	memset(&mbox_sts, 0, sizeof(mbox_sts));
2251
2252	mbox_cmd[0] = MBOX_CMD_RESTORE_FACTORY_DEFAULTS;
2253	mbox_cmd[3] = region;
2254	mbox_cmd[4] = field0;
2255	mbox_cmd[5] = field1;
2256
2257	status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, outCount: 3, mbx_cmd: &mbox_cmd[0],
2258	mbx_sts: &mbox_sts[0]);
2259	if (status != QLA_SUCCESS) {
2260	DEBUG2(ql4_printk(KERN_ERR, ha, "scsi%ld: %s: failed "
2261	"status %04X\n", ha->host_no, __func__,
2262	mbox_sts[0]));
2263	}
2264	return status;
2265	}
2266
2267	/**
2268	* qla4_8xxx_set_param - set driver version in firmware.
2269	* @ha: Pointer to host adapter structure.
2270	* @param: Parameter to set i.e driver version
2271	**/
2272	int qla4_8xxx_set_param(struct scsi_qla_host *ha, int param)
2273	{
2274	uint32_t mbox_cmd[MBOX_REG_COUNT];
2275	uint32_t mbox_sts[MBOX_REG_COUNT];
2276	uint32_t status;
2277
2278	memset(&mbox_cmd, 0, sizeof(mbox_cmd));
2279	memset(&mbox_sts, 0, sizeof(mbox_sts));
2280
2281	mbox_cmd[0] = MBOX_CMD_SET_PARAM;
2282	if (param == SET_DRVR_VERSION) {
2283	mbox_cmd[1] = SET_DRVR_VERSION;
2284	strncpy(p: (char *)&mbox_cmd[2], QLA4XXX_DRIVER_VERSION,
2285	MAX_DRVR_VER_LEN - 1);
2286	} else {
2287	ql4_printk(KERN_ERR, ha, "%s: invalid parameter 0x%x\n",
2288	__func__, param);
2289	status = QLA_ERROR;
2290	goto exit_set_param;
2291	}
2292
2293	status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, outCount: 2, mbx_cmd: mbox_cmd,
2294	mbx_sts: mbox_sts);
2295	if (status == QLA_ERROR)
2296	ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n",
2297	__func__, mbox_sts[0]);
2298
2299	exit_set_param:
2300	return status;
2301	}
2302
2303	/**
2304	* qla4_83xx_post_idc_ack - post IDC ACK
2305	* @ha: Pointer to host adapter structure.
2306	*
2307	* Posts IDC ACK for IDC Request Notification AEN.
2308	**/
2309	int qla4_83xx_post_idc_ack(struct scsi_qla_host *ha)
2310	{
2311	uint32_t mbox_cmd[MBOX_REG_COUNT];
2312	uint32_t mbox_sts[MBOX_REG_COUNT];
2313	int status;
2314
2315	memset(&mbox_cmd, 0, sizeof(mbox_cmd));
2316	memset(&mbox_sts, 0, sizeof(mbox_sts));
2317
2318	mbox_cmd[0] = MBOX_CMD_IDC_ACK;
2319	mbox_cmd[1] = ha->idc_info.request_desc;
2320	mbox_cmd[2] = ha->idc_info.info1;
2321	mbox_cmd[3] = ha->idc_info.info2;
2322	mbox_cmd[4] = ha->idc_info.info3;
2323
2324	status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, MBOX_REG_COUNT,
2325	mbx_cmd: mbox_cmd, mbx_sts: mbox_sts);
2326	if (status == QLA_ERROR)
2327	ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n", __func__,
2328	mbox_sts[0]);
2329	else
2330	ql4_printk(KERN_INFO, ha, "%s: IDC ACK posted\n", __func__);
2331
2332	return status;
2333	}
2334
2335	int qla4_84xx_config_acb(struct scsi_qla_host *ha, int acb_config)
2336	{
2337	uint32_t mbox_cmd[MBOX_REG_COUNT];
2338	uint32_t mbox_sts[MBOX_REG_COUNT];
2339	struct addr_ctrl_blk *acb = NULL;
2340	uint32_t acb_len = sizeof(struct addr_ctrl_blk);
2341	int rval = QLA_SUCCESS;
2342	dma_addr_t acb_dma;
2343
2344	acb = dma_alloc_coherent(dev: &ha->pdev->dev,
2345	size: sizeof(struct addr_ctrl_blk),
2346	dma_handle: &acb_dma, GFP_KERNEL);
2347	if (!acb) {
2348	ql4_printk(KERN_ERR, ha, "%s: Unable to alloc acb\n", __func__);
2349	rval = QLA_ERROR;
2350	goto exit_config_acb;
2351	}
2352	memset(acb, 0, acb_len);
2353
2354	switch (acb_config) {
2355	case ACB_CONFIG_DISABLE:
2356	rval = qla4xxx_get_acb(ha, acb_dma, acb_type: 0, len: acb_len);
2357	if (rval != QLA_SUCCESS)
2358	goto exit_free_acb;
2359
2360	rval = qla4xxx_disable_acb(ha);
2361	if (rval != QLA_SUCCESS)
2362	goto exit_free_acb;
2363
2364	if (!ha->saved_acb)
2365	ha->saved_acb = kzalloc(size: acb_len, GFP_KERNEL);
2366
2367	if (!ha->saved_acb) {
2368	ql4_printk(KERN_ERR, ha, "%s: Unable to alloc acb\n",
2369	__func__);
2370	rval = QLA_ERROR;
2371	goto exit_free_acb;
2372	}
2373	memcpy(ha->saved_acb, acb, acb_len);
2374	break;
2375	case ACB_CONFIG_SET:
2376
2377	if (!ha->saved_acb) {
2378	ql4_printk(KERN_ERR, ha, "%s: Can't set ACB, Saved ACB not available\n",
2379	__func__);
2380	rval = QLA_ERROR;
2381	goto exit_free_acb;
2382	}
2383
2384	memcpy(acb, ha->saved_acb, acb_len);
2385
2386	rval = qla4xxx_set_acb(ha, mbox_cmd: &mbox_cmd[0], mbox_sts: &mbox_sts[0], acb_dma);
2387	if (rval != QLA_SUCCESS)
2388	goto exit_free_acb;
2389
2390	break;
2391	default:
2392	ql4_printk(KERN_ERR, ha, "%s: Invalid ACB Configuration\n",
2393	__func__);
2394	}
2395
2396	exit_free_acb:
2397	dma_free_coherent(dev: &ha->pdev->dev, size: sizeof(struct addr_ctrl_blk), cpu_addr: acb,
2398	dma_handle: acb_dma);
2399	exit_config_acb:
2400	if ((acb_config == ACB_CONFIG_SET) && ha->saved_acb) {
2401	kfree(objp: ha->saved_acb);
2402	ha->saved_acb = NULL;
2403	}
2404	DEBUG2(ql4_printk(KERN_INFO, ha,
2405	"%s %s\n", __func__,
2406	rval == QLA_SUCCESS ? "SUCCEEDED" : "FAILED"));
2407	return rval;
2408	}
2409
2410	int qla4_83xx_get_port_config(struct scsi_qla_host *ha, uint32_t *config)
2411	{
2412	uint32_t mbox_cmd[MBOX_REG_COUNT];
2413	uint32_t mbox_sts[MBOX_REG_COUNT];
2414	int status;
2415
2416	memset(&mbox_cmd, 0, sizeof(mbox_cmd));
2417	memset(&mbox_sts, 0, sizeof(mbox_sts));
2418
2419	mbox_cmd[0] = MBOX_CMD_GET_PORT_CONFIG;
2420
2421	status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, MBOX_REG_COUNT,
2422	mbx_cmd: mbox_cmd, mbx_sts: mbox_sts);
2423	if (status == QLA_SUCCESS)
2424	*config = mbox_sts[1];
2425	else
2426	ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n", __func__,
2427	mbox_sts[0]);
2428
2429	return status;
2430	}
2431
2432	int qla4_83xx_set_port_config(struct scsi_qla_host *ha, uint32_t *config)
2433	{
2434	uint32_t mbox_cmd[MBOX_REG_COUNT];
2435	uint32_t mbox_sts[MBOX_REG_COUNT];
2436	int status;
2437
2438	memset(&mbox_cmd, 0, sizeof(mbox_cmd));
2439	memset(&mbox_sts, 0, sizeof(mbox_sts));
2440
2441	mbox_cmd[0] = MBOX_CMD_SET_PORT_CONFIG;
2442	mbox_cmd[1] = *config;
2443
2444	status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, MBOX_REG_COUNT,
2445	mbx_cmd: mbox_cmd, mbx_sts: mbox_sts);
2446	if (status != QLA_SUCCESS)
2447	ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n", __func__,
2448	mbox_sts[0]);
2449
2450	return status;
2451	}
2452